Capacitor short circuit detection circuit, device and capacitor testing system

Abstract

The utility model provides a capacitor short circuit detection circuit, device and capacitor test system. The capacitor short circuit detection circuit includes sampling resistance, switch circuit and isolation circuit. Sampling resistance one end ground connection, the other end connects the capacitor under test, is used for with test loop current change turns into level difference. Switch circuit control test loop is on or is disconnected, guarantees and is safe with controllable detection. Isolation circuit is arranged between second node and signal output end, unidirectional conduction when test loop opens makes second node level acts on signal output end, prevents high pressure from acting on control unit when the capacitor under test short circuit, and again forms short circuit determination signal, and control unit judges short circuit in real time accordingly, realizes the capacitor short circuit detection of automation, high efficiency, reliable.

Description

Technical Field

[0001] This utility model relates to the field of capacitance testing technology, and in particular to a capacitor short-circuit detection circuit, device and capacitance testing system. Background Technology

[0002] Capacitors are widely used in the design and manufacturing of electronic products, and their reliability directly affects the performance and quality of the entire device. In current technology, short-circuit failures in capacitors are difficult to detect in advance. Typically, only after a product has been used for a period of time and an abnormality occurs will engineers use capacitance testers, multimeters, or other manual testing methods to confirm whether the capacitor is short-circuited. Alternatively, component engineers may conduct reliability tests on capacitors during material certification and measure whether the capacitor has failed short-circuit failure after the reliability test.

[0003] Therefore, the above-mentioned manual detection method for capacitor short circuits is inefficient.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this utility model, and therefore may include information that does not constitute prior art known to those skilled in the art. Utility Model Content

[0005] In view of the problems in the prior art, the purpose of this utility model is to provide a capacitor short circuit detection circuit, device and capacitor testing system that overcomes the difficulties of the prior art and can solve the problem of low efficiency of the existing manual detection scheme for capacitor short circuits.

[0006] This disclosure provides a capacitor short-circuit detection circuit, which includes:

[0007] A sampling resistor, one end of which is coupled to the ground terminal and the other end is used to couple the measured capacitor through the first node;

[0008] A switching circuit is used to control the connection or disconnection between the first node and the second node, and to open the test circuit of the capacitor under test when the connection is made, wherein the second node is configured to be coupled to the capacitor under test;

[0009] An isolation circuit is provided, coupling the second node to the signal output terminal, which is used to couple the control unit. The isolation circuit is configured to maintain a unidirectional conduction state between the second node and the signal output terminal when the test circuit of the capacitor under test is open, so as to allow the level of the second node to act on the signal output terminal. When the capacitor under test is short-circuited, the isolation circuit blocks the level transmission of the second node to the signal output terminal, thereby switching the level state of the signal output terminal, so that the control unit can determine whether the capacitor under test is short-circuited based on the level state.

[0010] Optionally, the switching circuit includes a first switching transistor and a second switching transistor;

[0011] The control terminal of the first switch is coupled to the first control signal through the third node. The first terminal is coupled to the first node and the second terminal is coupled to the second node, which is used to control the opening or closing of the test circuit in response to the first control signal.

[0012] The control terminal of the second switch is coupled to the second control signal through the fourth node, the first terminal is coupled to the third node and the second terminal is coupled to the ground terminal, which is used to self-lock to turn off the first switch when the capacitor under test is short-circuited.

[0013] Optionally, the first switching transistor is a first MOSFET, and the second switching transistor is a second MOSFET;

[0014] The control terminal of the first switch is the gate of the first MOS transistor, and one of the first and second terminals of the first switch is the source of the first MOS transistor and the other terminal is the drain of the first MOS transistor.

[0015] The control terminal of the second switch is the gate of the second MOS transistor, and one of the first and second terminals of the second switch is the source of the second MOS transistor and the other terminal is the drain of the second MOS transistor.

[0016] Optionally, the isolation circuit includes a diode, the cathode of which is coupled to the second node and the anode of which is coupled to the signal output terminal.

[0017] Alternatively, the diode may be a germanium diode or a Schottky diode.

[0018] Optionally, the switching circuit further includes:

[0019] A first resistor is coupled to the first control signal and the third node;

[0020] The second resistor is coupled to the second control signal and the fourth node.

[0021] Optionally, the switching circuit further includes:

[0022] The first capacitor, coupled to the third node and the first node, is used to stabilize the gate level of the first MOS transistor.

[0023] The second capacitor, coupled to the fourth node and the ground terminal, is used to stabilize the gate level of the second MOS transistor.

[0024] Optionally, a third control signal is coupled to the fifth node between the isolation circuit and the signal output terminal. The third control signal is used to provide a reference level to the fifth node so that when the capacitor under test is short-circuited, the level state of the signal output terminal is switched to the reference level.

[0025] Optionally, the capacitor short-circuit detection circuit further includes at least one of the following filtering elements:

[0026] The third resistor is coupled to the third control signal and the fifth node;

[0027] The fourth resistor is coupled to the fifth node and the signal output terminal;

[0028] The third capacitor is coupled to the sixth node and the ground terminal, and the sixth node is located between the fourth resistor and the signal output terminal.

[0029] Optionally, the capacitor short-circuit detection circuit further includes:

[0030] A test fixture board is provided, on which multiple capacitor short-circuit detection circuits are mounted, and each capacitor short-circuit detection circuit is coupled to the corresponding capacitor under test through the second node.

[0031] A second aspect of this disclosure provides a capacitor short-circuit detection device, comprising:

[0032] Capacitor short-circuit detection circuit of any of the above embodiments;

[0033] The control unit has its input terminal connected to the signal output terminal, and is used to determine whether the capacitor under test is short-circuited based on the level state of the signal output terminal.

[0034] A third aspect of this disclosure provides a capacitance testing system, comprising:

[0035] The above-mentioned capacitor short-circuit detection device;

[0036] The capacitor under test has one terminal connected to the second node and the other terminal used to connect to the test excitation voltage.

[0037] The capacitor short-circuit detection circuit, device, and capacitor testing system provided in this disclosure have the following beneficial effects:

[0038] Using the capacitor short-circuit detection circuit described above, the control switch circuit connects the first node and the second node, opening the test circuit of the capacitor under test. The capacitor under test is then tested using a test excitation voltage. During the test, under normal circumstances, the capacitor under test is in a normal state, the current in its test circuit remains within a predetermined range, the second node maintains a predetermined level, the level across the sampling resistor is stable, and the isolation circuit ensures the control unit is not interfered with. However, when the capacitor under test is short-circuited, the current in its test circuit increases significantly, the level across the sampling resistor changes accordingly, and the test excitation voltage of the capacitor under test directly acts on the second node, causing the isolation circuit to switch the level state of its signal output. The control unit accurately identifies the short-circuit state based on this. The technical advantage of this embodiment is that it enables automated and real-time determination of whether the capacitor under test is short-circuited, improving the accuracy and detection efficiency of capacitor short circuits.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0040] Other features, objects, and advantages of this invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0041] Figure 1 This illustration shows an architecture diagram of a capacitor short-circuit detection circuit provided by an embodiment of the present disclosure.

[0042] Figure 2 exhibit Figure 1 The circuit topology diagram of the capacitor short-circuit detection circuit shown is as follows;

[0043] Figure 3 This invention discloses a structural diagram of a test fixture board, which is equipped with multiple capacitor short-circuit detection circuits according to an embodiment of the present invention.

[0044] Figure 4 exhibit Figure 3 The diagram shows the connection relationship between the test fixture board and the capacitor test board. Detailed Implementation

[0045] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0046] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0047] Furthermore, the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to define the order of functions performed by these devices, modules or units or their interdependencies.

[0048] Figure 1 A schematic diagram of the capacitor short-circuit detection circuit 100 provided in this embodiment is shown, such as... Figure 1 As shown, the capacitor short-circuit detection circuit 100 includes a sampling resistor R_SENSE, a switching circuit 1, and an isolation circuit 2.

[0049] One end of the sampling resistor R_SENSE is coupled to the ground terminal GND, and the other end is used to couple the capacitor under test C_DUT through the first node N1. The sampling resistor R_SENSE is used to sense the current change in the test circuit where the capacitor under test C_DUT is located during the test. When the capacitor under test C_DUT is short-circuited, the current in the test circuit increases significantly. This current change is converted into a level difference by the sampling resistor R_SENSE, providing a basis for subsequent short-circuit determination.

[0050] Switching circuit 1 is used to control the connection or disconnection between the first node N1 and the second node N2. During the testing phase of the capacitor under test, the first node N1, the second node N2, and the sampling resistor R_SENSE are connected by the control of switching circuit 1, keeping the test circuit of the capacitor under test in the open state; or, during the non-testing phase, N1 and N2 are disconnected, thus disconnecting the test circuit, thereby ensuring the controllability and safety of the testing process.

[0051] Isolation circuit 2 is disposed between the second node N2 and the signal output terminal OUT, wherein the signal output terminal OUT is coupled to the input terminal of the control unit. Isolation circuit 2 is configured to maintain the second node N2 and the signal output terminal OUT in a unidirectional conduction state when the test loop of the capacitor under test C_DUT is open, so as to allow the level of the second node N2 to act on the signal output terminal OUT, and to block the level transmission of the second node N2 to the signal output terminal OUT when the capacitor under test C_DUT is short-circuited, thereby switching the level state of the signal output terminal OUT.

[0052] In this embodiment, when the capacitor under test (C_DUT) is not short-circuited, the second node N2 is at a low level, and the isolation circuit 2 is turned on, keeping the signal output terminal OUT at a low level. However, when the capacitor under test (C_DUT) is short-circuited, the test excitation voltage on the C_DUT side directly acts on N2. At this time, the isolation circuit 2 blocks the level transmission from the second node N2 to the signal output terminal OUT. This prevents the test excitation voltage on the C_DUT side from directly acting on the control unit 3, thus avoiding electrical damage to the control unit 3. It also causes a level switch at the signal output terminal OUT.

[0053] During the testing of the capacitor under test (C_DUT), the control unit 3 receives the level signal from the signal output terminal OUT and performs logical judgments based on this level signal. When the signal output terminal OUT maintains a normal level, it indicates that the capacitor under test (C_DUT) is not short-circuited; when the level state of the signal output terminal OUT changes according to a preset switch, the control unit 3 determines that the capacitor under test (C_DUT) is short-circuited.

[0054] Through the coordinated operation of the above modules, this implementation method can achieve the following principle:

[0055] Control switch circuit 1 connects the first node N1 and the second node N2, opening the test circuit of the capacitor under test (C_DUT). The test excitation voltage is then used to test the C_DUT. During the test, under normal conditions, the C_DUT is in a normal state, the current in its test circuit remains within a predetermined range, the second node N2 maintains a predetermined level (e.g., low level), the level across the sampling resistor R_SENSE is stable, and isolation circuit 2 ensures that control unit 3 is not interfered with. However, when the C_DUT is short-circuited, the current in its test circuit increases significantly, the level across the sampling resistor R_SENSE changes accordingly, and the test excitation voltage of the C_DUT directly acts on the second node N2, causing isolation circuit 2 to switch the level of its signal output terminal OUT. Control unit 3 then accurately identifies the short-circuit state based on this.

[0056] The technical advantage of this embodiment is that it enables automated and real-time determination of whether the capacitor under test (C_DUT) is short-circuited, improving the accuracy and detection efficiency of capacitor short circuits. Simultaneously, the isolation circuit 2 effectively prevents the high voltage on the test excitation side from directly acting on the control unit 3 when the capacitor under test (C_DUT) is short-circuited, improving the reliability and safety of capacitor short-circuit detection, thereby achieving safe detection of capacitor short-circuit failures.

[0057] Optionally, the capacitor short-circuit detection circuit 100 described above can be modularly designed. Its modular structure is applicable to various capacitor testing environments and can be electrically connected with the corresponding control unit 3, thus making the capacitor short-circuit detection circuit universal.

[0058] As one way of implementation, Figure 2 exhibit Figure 1 The circuit topology diagram of the capacitor short-circuit detection circuit is shown. The switching circuit 1 includes a first switching transistor Q1 and a second switching transistor Q2.

[0059] The control terminal K0 of the first switch Q1 is coupled to the first control signal CAPRTN_EN through the third node N3. Terminal K1 is coupled to the first node N1, and terminal K2 is coupled to the second node N2. The first switch Q1 is used to control the conduction or disconnection between the first node N1 and the second node N2 in response to the state of the first control signal CAPRTN_EN. For example, during the capacitor under test (DUT) testing phase, if CAPRTN_EN is high, Q1 is on, forming a closed loop between the DUT and the sampling resistor R_SENSE; if CAPRTN_EN is low, Q1 is off, disconnecting N1 and N2. This design allows the testing process to be flexibly controlled by external signals, improving the schedulability of the test.

[0060] The control terminal M0 of the second switch Q2 is coupled to the second control signal SELF_LATCH_EN through the fourth node N4, the first terminal M1 is coupled to the third node N3, and the second terminal M2 is coupled to the ground terminal GND. The second switch Q2 is used to enter a self-locking state when the capacitor under test C_DUT is short-circuited, thereby turning off the first switch Q1. Specifically, when the short circuit of C_DUT causes abnormal potentials in N1 and N2, the SELF_LATCH_EN level triggers Q2 to conduct, N3 is pulled down to ground, causing the control terminal K0 of Q1 to lose its driving capability, Q1 automatically turns off, and the test circuit is promptly disconnected. Through this interlocking mechanism, even if the control unit 3 does not respond in time, protection can be achieved at the circuit level to avoid overcurrent damage to the sampling resistor R_SENSE and other components.

[0061] Therefore, the switching circuit 1, through the interlocking and self-locking actions of the two-stage switching transistors (the first switching transistor Q1 and the second switching transistor Q2), not only realizes the normal opening and closing of the test circuit of the capacitor under test, but also provides hardware-level protection at the moment of short circuit of the capacitor under test C_DUT, thereby improving the reliability of the test and the robustness of the circuit.

[0062] In another embodiment, such as Figure 2 As shown, the first switch Q1 is a first MOS (Metal-Oxide-Semiconductor) transistor, and the second switch Q2 is a second MOS transistor.

[0063] In this configuration, the gate G of the first MOSFET serves as the control terminal K0 of Q1, the source S serves as the first terminal K1 of Q1, and the drain D serves as the second terminal K2 of Q1. The source S is coupled to the first node N1, and the drain D is coupled to the second node N2. When CAPRTN_EN is applied to the gate G, the first MOSFET is turned on, and the test circuit is opened. If CAPRTN_EN is removed, the first MOSFET is turned off, and the test circuit is disconnected. The first MOSFET structure provides high input impedance and low on-resistance, ensuring fast switching and low loss characteristics of the test circuit.

[0064] The gate (G) of the second MOSFET serves as the control terminal (M0) of Q2, the source (S) as the first terminal (M1) of Q2, and the drain (D) as the second terminal (M2) of Q2. The source (S) is coupled to the third node (N3), and the drain (D) is coupled to ground (GND). When SELF_LATCH_EN is triggered, Q2 turns on, and the level of N3 is pulled down to GND, thereby disabling the gate (G) of Q1 and causing Q1 to turn off. Utilizing the fast switching characteristics of MOSFETs, Q2 can trigger a latch-up within a very short time after a short-circuit current occurs, immediately cutting off the overcurrent condition.

[0065] In the above embodiment, both the first MOSFET and the second MOSFET are N-channel MOSFETs. Thus, when both the first control signal CAPRTN_EN and the second control signal SELF_LATCH_EN provide a high level, the first MOSFET and the second MOSFET are turned on; otherwise, they are turned off when the high level is removed or a low level is provided.

[0066] This embodiment selects MOS devices for the first switch Q1 and the second switch Q2 to further ensure the response speed and withstand voltage capability of the capacitor under test test circuit, and is suitable for capacitor short circuit detection application scenarios with a high voltage range (e.g., 3.3V to 100V DC test excitation voltage).

[0067] Optionally, the first switch Q1 and the second switch Q2 can also be a combination of insulated gate bipolar transistors (IGBTs) to cope with test scenarios with higher power capacitors.

[0068] Optionally, the second switch Q2 can be replaced with a parallel structure of a Schottky diode and a MOSFET to achieve dual protection of fast clamping and delayed self-locking, thereby improving safety under high current surges.

[0069] Optionally, the first control signal CAPRTN_EN can be understood as a capacitor circuit enable signal, which can be provided by the control unit 3. Its function is to initialize the test circuit, control the conduction of the first MOSFET, and ensure that the test circuit operates stably during startup. The second control signal SELF_LATCH_EN can be interpreted as a latch-up enable signal, which can be provided by the control unit 3. Its function is to trigger an automatic latch-up protection state when the capacitor under test C_DUT is short-circuited, and turn off Q1 through Q2 to prevent the sampling resistor R_SENSE from being burned out.

[0070] As described above, both the first control signal CAPRTN_EN and the second control signal SELF_LATCH_EN originate from the control unit 3, but they can originate from different logic modules or programs within the control unit 3. For example, CAPRTN_EN is controlled by the software program in the control unit 3 to control the detection timing, while SELF_LATCH_EN is directly triggered by the hardware comparator in the control unit 3, thereby achieving dual-path redundancy of software judgment and hardware protection and improving the system's fault tolerance.

[0071] For example Figure 2 As shown, the switching circuit 1 also includes a resistor. For example, a first resistor R1 is coupled between the first control signal CAPRTN_EN and the third node N3, used to provide gate bias for the first MOSFET when the first control signal CAPRTN_EN is released. If the first MOSFET is an N-channel MOSFET, the third node N3 needs to be pulled down to a low level through R1 to ensure that the gate potential is lower than its source potential when there is an invalid control signal, thereby reliably turning off and preventing the test circuit from being mistakenly turned on.

[0072] The second resistor R2 is coupled between the second control signal SELF_LATCH_EN and the fourth node N4, and is used to provide gate bias for the second MOSFET when the second control signal SELF_LATCH_EN is released. If the second MOSFET is an N-channel MOSFET, the fourth node N4 should be pulled down to a low level through R2 to ensure that its gate potential is not higher than its source potential, thereby keeping it off under invalid signals and avoiding false turn-on.

[0073] With this design, regardless of the channel type of the MOSFET used, a reasonable default bias can be established through the resistor element, avoiding malfunctions caused by the gate being floating.

[0074] By introducing resistors (such as R1 and R2) between the first control signal CAPRTN_EN and the second control signal SELF_LATCH_EN and the gates of the corresponding first and second MOSFETs, transient voltage spikes can be prevented from directly impacting the gates of the first and second MOSFETs, thereby enhancing the circuit's anti-interference capability and long-term stability.

[0075] In alternative implementations, such as Figure 2 As shown, the switching circuit 1 also includes a capacitor. For example, the first capacitor C1 is connected between the third node N3 and the first node N1, and is used to filter and stabilize the gate potential of the first MOS transistor when the first control signal CAPRTN_EN switches, thereby avoiding gate oscillation caused by rapid switching.

[0076] The second capacitor C2 is connected between the fourth node N4 and the ground terminal GND. It is used to provide bypass filtering for the gate G of the second MOSFET, suppressing high-frequency noise and transient interference. By introducing C2 into the gate G, the drive signal of the second MOSFET is smoothed, reducing the possibility of malfunction and ensuring the stability and reliability of the short-circuit detection process.

[0077] In this disclosure, for example, Figure 2 As shown, isolation circuit 2 includes diode D1. The cathode K of diode D1 is coupled to the second node N2, and the anode A is connected to the signal output terminal OUT.

[0078] Under normal testing conditions, the capacitor under test C_DUT is in a non-short-circuit state, and the test circuit current is maintained within the predetermined range. At this time, the potential of the second node N2 is low, and the diode D1 is in a forward conducting state, pulling the signal output terminal OUT down to a potential close to that of the second node N2.

[0079] During the test, when the capacitor under test (C_DUT) experiences a short circuit failure, the current in the test circuit increases rapidly, causing the potential of the second node N2 to rise, and diode D1 to be reverse-biased and cut off. At this time, the signal output terminal OUT is no longer affected by the potential of the second node N2, and its level changes. Based on this, control unit 3 determines that the capacitor under test (C_DUT) has failed due to a short circuit.

[0080] In an optional implementation, diode D1 is selected as a germanium diode or a Schottky diode. This type of diode D1 has a lower forward voltage drop, enabling it to more sensitively reflect the potential drop of the second node N2 when a short circuit occurs in the capacitor under test C_DUT, thus shortening the response time and improving detection sensitivity and accuracy. Simultaneously, the lower forward voltage drop also facilitates the level state determination of control unit 3, reducing the risk of false alarms.

[0081] like Figure 2 As shown in this embodiment, a fifth node N5 is provided between the isolation circuit 2 and the signal output terminal OUT. The fifth node N5 is configured to be coupled to a third control signal CTRL, which is used to provide a reference level for the signal output terminal OUT so that when the capacitor under test C_DUT is short-circuited, the level state of the signal output terminal OUT is switched to the reference level.

[0082] During the normal testing phase, the level of the signal output terminal OUT is affected by the second node N2. The isolation circuit 2 maintains unidirectional conduction, so that the output terminal OUT is consistent with the level of the second node N2, thereby reflecting the normal working state of the capacitor under test C_DUT.

[0083] For example, the third control signal CTRL and the second control signal SELF_LATCH_EN share the same control signal, that is, the same level signal is used to simultaneously control the second switch Q2 (the second MOSFET) and provide a reference level for the signal output terminal OUT, which can simplify circuit design and reduce wiring complexity.

[0084] In another optional implementation, the third control signal CTRL can also be set independently of the second control signal SELF_LATCH_ENU. In this case, the reference level provided by the third control signal CTRL is not affected by the control logic of the second switching transistor, and the reference level of the output terminal OUT can be flexibly adjusted according to different application scenarios, thereby improving the adaptability of the capacitor short-circuit detection circuit in various power supply environments.

[0085] In this embodiment, when the capacitor under test (C_DUT) is short-circuited, the voltage level of the second node N2 increases, causing diode D1 to be reverse-biased and thus blocking the voltage level transmission from the second node N2 to the output terminal OUT. At this time, the signal output terminal OUT maintains the reference level provided by the fifth node N5, realizing the level state switching. Based on this, the control unit 3 can accurately identify the short-circuit state of the capacitor under test (C_DUT), avoiding misjudgments caused by interference or level drift during normal detection.

[0086] In this disclosure, such as Figure 2 As shown, the capacitor short-circuit detection circuit 100 also includes at least one filtering element to stabilize the reference level of the signal output terminal OUT and reduce the influence of external interference and test ripple on the short-circuit determination.

[0087] Optionally, the filtering element includes:

[0088] The third resistor R3 is coupled to the third control signal CTRL and the fifth node N5. It is used to provide the third control signal CTRL to N5 and form a low-pass filter and current limiting effect through resistance matching.

[0089] The fourth resistor R4 is coupled to the fifth node N5 and the signal output terminal OUT. It is used to limit the current flow from the fifth node N5 to the signal output terminal OUT. When the capacitor under test C_DUT is short-circuited, the level of the second node N2 rises, the diode D1 is reverse cut off, and the direct current between OUT and N2 is blocked. However, N5 still provides a reference level to OUT through R4. At this time, R4 can affect the magnitude of the current from N5 to OUT, preventing excessive transient current from interfering with the OUT terminal, thereby ensuring that OUT switches smoothly to the reference level.

[0090] The third capacitor C3 is coupled to the sixth node N6 and the ground terminal GND. The sixth node N6 is located between the fourth resistor R4 and the signal output terminal OUT. It is used to filter out high-frequency noise and test ripple superimposed on the reference level, thereby ensuring that the signal output terminal OUT can stably switch to the reference level when a short circuit occurs.

[0091] During the normal testing phase, when the capacitor under test C_DUT is not short-circuited, the level of the second node N2 is low, the diode D1 is turned on, and the level of the signal output terminal OUT is dominated by the second node N2. At the same time, the filter components such as R3, R4 and C3 smooth the reference level to ensure that the level of the signal output terminal OUT is stable and reliable.

[0092] When the capacitor under test (C_DUT) is short-circuited, the voltage level at the second node N2 increases, causing diode D1 to reverse-biased and blocking the influence of the second node N2 on the signal output terminal OUT. At this time, the signal output terminal OUT switches to the reference level provided by the third control signal CTRL. This reference level is stably output through a filtering network including R3, R4, and C3. Based on this, the control unit 3 can accurately determine the short-circuit state and avoid misjudgments caused by external interference or voltage fluctuations.

[0093] Through the above design, the fourth resistor R4, together with the third resistor R3 and the third capacitor C3, form a low-pass filter network, which can effectively suppress high-frequency noise or test ripple transmitted from the second node N2 during the opening phase of the test circuit of the capacitor under test. Specifically, any small interference voltage caused by the change of N2 will be attenuated when passing through the R4-R3-C3 network, thereby preventing these interferences from being directly reflected at the signal output terminal OUT, and ensuring the stability and reliability of the level signal received by the control unit 3.

[0094] Thus, this embodiment utilizes filtering elements to stabilize the reference level, enabling reliable identification of capacitor short-circuit states while maintaining the response sensitivity and anti-interference capability of the capacitor short-circuit detection circuit during normal operation.

[0095] In this disclosure, such as Figure 3As shown, the capacitor short-circuit detection circuit further includes a test fixture board 4. The test fixture board 4 is used to mount multiple capacitor short-circuit detection circuits 100 described above. The structure of each capacitor short-circuit detection circuit 100 is as described in the above embodiment and will not be repeated here.

[0096] The multiple capacitor short-circuit detection circuits 100 on the test fixture board 4 are set independently of each other. Accordingly, each capacitor short-circuit detection circuit 100 can be connected through the second node N2 (reference). Figure 2 The corresponding capacitor under test is coupled. In practical applications, multiple capacitor short-circuit detection circuits 100 can be used to simultaneously perform independent testing and short-circuit detection on multiple capacitors under test, achieving batch capacitor testing.

[0097] In one implementation, such as Figure 4 As shown, multiple capacitors under test (C_DUTs) are mounted on a capacitor test board 5, and the capacitor test board 5 is provided to the test fixture board 4 as described above. The test fixture board 4 and the capacitor test board 5 are electrically connected through a standard interface (e.g., pins, sockets, or solder pads), so that each capacitor under test (C_DUT) is connected to the corresponding capacitor short-circuit detection circuit 100. This ensures that each capacitor under test test circuit establishes an accurate signal transmission with the corresponding capacitor short-circuit detection circuit, and the signal is ultimately transmitted to the control unit 3 (e.g., ...). Figure 2 The determination is made as shown in the figure.

[0098] During operation, multiple capacitors under test (C_DUTs) can share a single test excitation voltage. The control unit 3 can simultaneously or sequentially control the testing process of multiple C_DUTs and the capacitor short-circuit detection circuit 100, performing capacitance testing and short-circuit detection on the multiple C_DUTs mounted on the capacitor test board 5. Each capacitor short-circuit detection circuit 100 operates independently, and the control unit 3 determines the short-circuit state of each capacitor under test, thereby achieving batch and automated capacitor short-circuit detection.

[0099] The technical advantage of this embodiment is that by integrating multiple capacitor short-circuit detection circuits 100 onto the test fixture board 4 and connecting them to multiple capacitors under test C_DUT on the capacitor test board 5, multiple capacitors under test C_DUT can be detected simultaneously or quickly, improving detection efficiency and reliability, while ensuring the independence of the test circuit of each capacitor under test and avoiding mutual interference.

[0100] Combination Figure 2 and Figure 3 The following section explains the capacitor short-circuit detection mechanism in conjunction with the testing process of the capacitor under test.

[0101] In this embodiment of the disclosure, in order to achieve batch automatic detection of short-circuit failure of multiple capacitors under test C_DUT during the test, each capacitor under test C_DUT is connected to a corresponding capacitor short-circuit detection circuit 100.

[0102] During the initial power-on phase, control unit 3 first sets the second control signal SELF_LATCH_EN to a low level to ensure that the second switching transistor Q2 (corresponding to the second MOSFET) is not turned on, thus avoiding the control unit 3 from mistakenly identifying a short circuit. Subsequently, control unit 3 sets the first control signal CAPRTN_EN to a high level to fully turn on the first MOSFET, thereby enabling the test circuit of C_DUT. Afterwards, SELF_LATCH_EN is set to a high level, at which point the capacitor test circuit is fully open, and the voltage across diode D1 (V) is... a =V F +V ds +V R_SENSE VF stands for Forward Voltage, which refers to the forward voltage across D1. ds This refers to the source-drain voltage of the first MOSFET, V. R_SENSE This is the voltage across the sampling resistor R_SENSE.

[0103] Under normal operating conditions, the capacitor under test (C_DUT) is not short-circuited. The resistance of R_SENSE is set relatively low, and the DC current in the test circuit is close to zero. Meanwhile, the resistance of R3 is relatively high (e.g., in the K-level), resulting in a voltage VR_SENSE approximately 0V superimposed on R_SENSE. Considering that the test excitation includes not only the DC voltage component but also analog ripple noise voltage superimposed on VR_SENSE, the specific superposition coefficient varies depending on the C_DUT. However, this noise is filtered out by the low-pass filter composed of R4 and R3. Although SELF_LATCH_EN is high, OUT is low because diode D1 is in the open state, and control unit 3 determines that C_DUT is normal. The second MOSFET remains off due to insufficient gate voltage, while the first MOSFET remains on, ensuring stable operation of the C_DUT test circuit.

[0104] During testing, the withstand capability of the capacitor under test (C_DUT) is examined under various test excitation conditions, including various DC voltages, superimposed ripple noise voltages, voltage change rates (dv / dt), and switching voltage surges. To obtain statistical reliability, each test typically uses multiple samples (e.g., 100 capacitors) under different environmental conditions (high and low temperatures, alternating humidity). The capacitor short-circuit detection circuit 100 can replace manual operation, enabling batch automatic determination of whether a short circuit has occurred in the C_DUT.

[0105] When the capacitor under test (C_DUT) is short-circuited, the entire test excitation voltage is applied to the first MOSFET and R_SENSE. Diode D1 is in reverse cutoff, causing the signal output terminal OUT to switch to a high level along with the SELF_LATCH_EN level. Control unit 3 can accurately identify the short-circuit state. At this time, the first MOSFET turns on, rapidly pulling down the gate-source voltage Vgs of the second MOSFET, thereby immediately turning off the second MOSFET. This avoids the risk of overheating or burnout caused by the short-circuit current on the first MOSFET and R_SENSE, achieving short-circuit self-locking protection.

[0106] As described above, this disclosure uses a sampling resistor R_SENSE to sense current changes in real time, and combines this with diode D1 to achieve high-voltage isolation. The control unit 3 can accurately identify the capacitor short-circuit state while protecting itself from high-voltage damage. This embodiment introduces a second MOSFET for short-circuit latch-up, which can quickly turn off the first MOSFET when the capacitor is short-circuited, preventing overcurrent from damaging the test circuit and circuit components of the capacitor under test.

[0107] In summary, this implementation method combines the test fixture board 4 and the capacitor test board 5 with functional modules such as sampling, isolation, and self-locking to achieve safe, reliable, and efficient short-circuit detection of a large number of capacitors C_DUTs under test.

[0108] This disclosure also provides a capacitor short-circuit detection device, which includes the capacitor short-circuit detection circuit 100 and control unit 3 of the above embodiments (e.g., Figure 1 and 2 As shown), the input terminal and signal output terminal OUT of control unit 3 (as shown) Figure 1 and 2 The connection shown is used to determine whether the capacitor under test is short-circuited based on the level state of the signal output terminal OUT.

[0109] Optionally, the capacitor short-circuit detection circuit 100 and the control unit 3 can be designed separately. The capacitor short-circuit detection circuit 100 adopts a modular design, and its modular structure can be applied to various capacitor testing environments. It can establish an electrical connection with the corresponding control unit 3, so that the capacitor short-circuit detection circuit has universality.

[0110] Alternatively, the capacitor short-circuit detection circuit 100 and the control unit 3 can be directly assembled, for example, the capacitor short-circuit detection circuit 100 is integrated into the control unit 3.

[0111] This disclosure also provides a capacitance testing system, which includes the capacitance short-circuit detection device of the above-described embodiments and a capacitor under test, wherein one terminal of the capacitor under test is connected to the second node N2 (e.g., Figure 2 (As shown) and the other pole is used to connect to the test excitation voltage.

[0112] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the utility models disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A capacitance short detection circuit, characterized by comprising: include: A sampling resistor, one end of which is coupled to the ground terminal and the other end is used to couple the measured capacitor through the first node; A switching circuit is used to control the connection or disconnection between the first node and the second node, and to open the test circuit of the capacitor under test when the connection is made, wherein the second node is configured to be coupled to the capacitor under test; An isolation circuit is provided, coupling the second node to the signal output terminal, which is used to couple to the control unit. The isolation circuit is configured to maintain a unidirectional conduction state between the second node and the signal output terminal when the test circuit of the capacitor under test is open, so as to allow the level of the second node to act on the signal output terminal. When the capacitor under test is short-circuited, the isolation circuit blocks the level transmission of the second node to the signal output terminal, thereby switching the level state of the signal output terminal, so that the control unit can determine whether the capacitor under test is short-circuited based on the level state.

2. The capacitor short-circuit detection circuit according to claim 1, characterized in that, The switching circuit includes a first switching transistor and a second switching transistor; The control terminal of the first switch is coupled to the first control signal through the third node. The first terminal is coupled to the first node and the second terminal is coupled to the second node, which is used to control the opening or closing of the test circuit in response to the first control signal. The control terminal of the second switch is coupled to the second control signal through the fourth node, the first terminal is coupled to the third node and the second terminal is coupled to the ground terminal, which is used to self-lock to turn off the first switch when the capacitor under test is short-circuited.

3. The capacitance short detection circuit according to claim 2, characterized by The first switching transistor is a first MOSFET, and the second switching transistor is a second MOSFET; The control terminal of the first switch is the gate of the first MOS transistor, and one of the first and second terminals of the first switch is the source of the first MOS transistor and the other terminal is the drain of the first MOS transistor. The control terminal of the second switch is the gate of the second MOS transistor, and one of the first and second terminals of the second switch is the source of the second MOS transistor and the other terminal is the drain of the second MOS transistor.

4. The capacitance short detection circuit according to claim 3, characterized by The isolation circuit includes a diode, the cathode of which is coupled to the second node and the anode of which is coupled to the signal output terminal.

5. The capacitance short detection circuit according to claim 4, characterized by The diode is a germanium diode or a Schottky diode.

6. The capacitance short detection circuit according to claim 3, characterized by The switching circuit also includes: A first resistor is coupled to the first control signal and the third node; The second resistor is coupled to the second control signal and the fourth node.

7. The capacitance short detection circuit according to claim 6, characterized by The switching circuit also includes: The first capacitor, coupled to the third node and the first node, is used to stabilize the gate level of the first MOS transistor; The second capacitor, coupled to the fourth node and the ground terminal, is used to stabilize the gate level of the second MOS transistor.

8. The capacitance short detection circuit according to claim 1, characterized by, A third control signal is coupled to the fifth node between the isolation circuit and the signal output terminal. The third control signal is used to provide a reference level to the fifth node so that when the capacitor under test is short-circuited, the level state of the signal output terminal is switched to the reference level.

9. The capacitance short detection circuit according to claim 8, characterized by The capacitor short-circuit detection circuit further includes at least one of the following filtering components: The third resistor is coupled to the third control signal and the fifth node; The fourth resistor is coupled to the fifth node and the signal output terminal; The third capacitor is coupled to the sixth node and the ground terminal, and the sixth node is located between the fourth resistor and the signal output terminal.

10. The capacitance short detection circuit according to claim 1, characterized by, The capacitor short-circuit detection circuit also includes: A test fixture board is provided, on which multiple capacitor short-circuit detection circuits are mounted, and each capacitor short-circuit detection circuit is coupled to the corresponding capacitor under test through the second node.

11. A capacitance short detection device, characterized by comprising: include: The capacitor short-circuit detection circuit according to any one of claims 1-10; The control unit has its input terminal connected to the signal output terminal, and is used to determine whether the capacitor under test is short-circuited based on the level state of the signal output terminal.

12. A capacitance testing system, comprising: include: The capacitor short-circuit detection device according to claim 11; The capacitor under test has one terminal connected to the second node and the other terminal used to connect to the test excitation voltage.

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