A bias current generator

Abstract

The utility model provides a kind of bias current generator, it is related to current generator technical field, comprising: one operational amplifier, its output node is connected to the gate of the output transistor, during the active operating mode of the bias current generator, the operational amplifier is configured to bias the output node according to the comparison result of feedback node voltage and reference voltage, so that the output transistor conducts bias current during the active mode;And one secondary current generator, configured to mirror the bias current as a secondary current, wherein the bias current is greater than the secondary current, and the secondary current is greater than the node bias current.The utility model can be powered off during inactivity, but can be quickly stabilized after power-on during activity, to provide stable bias current with minimum delay.

Description

Technical Field

[0001] This utility model relates to the field of current generator technology, and in particular to a bias current generator. Background Technology

[0002] Mobile devices such as tablets and smartphones typically use lithium-ion batteries with relatively high output voltages, such as 4V. While these batteries are efficient and have a long lifespan, their output voltage is too high for modern transistor process nodes. For example, digital cores often operate at supply voltages below 1V. Therefore, mobile devices typically include a buck converter to regulate the higher battery voltage to a lower supply voltage suitable for digital circuitry.

[0003] Buck converters (and other types of switching power converters) typically include a bias current generator to produce a bias current (e.g., 10 μA) for use by other converter components. Figure 1 A conventional bias current generator 100 is shown. An operational amplifier 105 drives the gate of an NMOS output transistor M1, with its control voltage responding to the difference between the source voltage of transistor M1 and a reference voltage (such as a bandgap reference voltage VBG). The source of transistor M1 is grounded through a resistor R1. Through the feedback mechanism of the operational amplifier 105, the source voltage of transistor M1 is maintained at the reference voltage VBG, so the bias current I through resistor R1 is equal to VBG / R1 according to Ohm's law. This bias current I is then mirrored through a current mirror formed by a diode-connected PMOS transistor P1, whose gate (and drain) voltage also drives the gates of PMOS transistors P2 and P3, whose sources are commonly connected to the power supply voltage VDD. Therefore, transistors P2 and P3 mirror the bias current I into a secondary current proportional to the bias current, the ratio depending on the size ratio between transistors P1, P2, and P3.

[0004] It's important to note that mobile device processors typically enter sleep mode during inactivity to conserve battery power. Ideally, the processor should wake from sleep mode and resume normal operation as quickly as possible. To achieve this rapid transition, the bias current generator 100 may run continuously during sleep mode (also known as hibernation or inactivity), but this continuous operation reduces efficiency due to the power consumption caused by bias current and secondary current. However, shutting down the bias current generator also presents problems, as the feedback mechanism of the operational amplifier 105 requires a certain amount of time to stabilize, typically several microseconds, to generate a stable bias current, which slows down the transition from sleep mode to normal mode. Utility Model Content

[0005] The purpose of this invention is to provide a bias current generator that can be powered off during inactive periods, but can quickly stabilize after power is applied during active periods, providing a stable bias current with minimal delay. The specific technical solution is as follows:

[0006] A bias current generator, comprising:

[0007] One output transistor;

[0008] An operational amplifier, the output node of which is connected to the gate of the output transistor, is configured during the active operating mode of the bias current generator to bias the output node based on a comparison between the feedback node voltage and a reference voltage, such that the output transistor conducts bias current during the active mode.

[0009] A current source is configured to conduct node bias current;

[0010] A switching network is configured to provide the node bias current from the output of the operational amplifier during a sleep mode, in which the output transistor does not conduct the bias current, wherein the bias current is greater than the node bias current; and

[0011] A secondary current generator is configured to mirror the bias current as a secondary current, wherein the bias current is greater than the secondary current and the secondary current is greater than the node bias current.

[0012] Furthermore, the operational amplifier includes a differential pair transistor, wherein during the active operation mode, the gate of the first differential pair transistor in the differential pair is charged to the feedback node voltage, and the gate of the second differential pair transistor is charged to the reference voltage.

[0013] Furthermore, the switching network includes a first switching transistor configured to be turned on during the sleep operation mode to charge the gate of the first differential pair transistor to the power supply voltage, and the first switching transistor is also configured to be turned off during the active operation mode.

[0014] Furthermore, the switching network also includes a second switching transistor configured to be turned on during the sleep operation mode to power the first differential transistor with the supply voltage, and the second switching transistor is also configured to be turned off during the active operation mode.

[0015] Furthermore, the source of the output transistor is connected to a power supply node, and the secondary current generator includes:

[0016] A first transistor, the source of which is connected to the power node and the gate of which is connected to the gate of the output transistor; and

[0017] A current mirror is connected to the drain of the first transistor via a first switch.

[0018] Furthermore, the switching network includes a first switch connected between the current source and the output node, the first switch being configured to close during the sleep operation mode and open during the active operation mode.

[0019] Furthermore, it also includes a diode-connected transistor, wherein the switching network further includes a second switch configured to close during the active operating mode to connect the current source to the diode-connected transistor, and configured to open during the sleep operating mode to isolate the current source from the diode-connected transistor.

[0020] Furthermore, the current source is configured to direct the node bias current to ground, wherein the source of the diode-connected transistor is connected to the power supply node, and the drain is connected to the second switch.

[0021] Furthermore, it also includes a compensation circuit configured to compensate the output node of the operational amplifier.

[0022] Furthermore, the compensation circuit includes a compensation capacitor connected in series with a compensation resistor.

[0023] The bias current generator provided by this utility model has the following beneficial effects:

[0024] The bias current generator of this invention provides bias to the operational amplifier nodes when it is in a static state and does not generate bias current. In the active mode where the bias current generator generates bias current, the current source does not provide bias to the operational amplifier nodes. This self-biasing of the operational amplifier nodes when the bias current generator is not operating is highly advantageous because the transition from sleep to active state is extremely rapid, requiring only nanoseconds. In contrast, the active mode transition time of conventional bias current generators is much longer. Furthermore, because the bias current of the current source to the operational amplifier nodes is much smaller than the bias current itself, this improved transition speed results in a very small increase in power consumption during inactivity. Attached Figure Description

[0025] Figure 1 This is a circuit diagram of a current bias generator using existing technology.

[0026] Figure 2 This is a schematic diagram of a bias current generator provided by the present invention.

[0027] Figure 3 A circuit diagram of an operational amplifier provided by this utility model. Detailed Implementation

[0028] The technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clearly illustrate the embodiments of this utility model.

[0029] This invention provides a bias current generator comprising a current source that provides node bias current to operational amplifier nodes via a switching network. The switching network only provides bias to the operational amplifier nodes via the node bias current when the bias current generator is in sleep mode (i.e., not generating bias current). When the bias current generator switches to active mode to generate bias current, the switching network prevents the current source from providing bias to the operational amplifier nodes. Because the operational amplifier nodes are already biased, the transition from sleep to active state is very rapid. However, since the node bias current is much smaller than the bias current, the power consumption is correspondingly reduced. For example, the bias current may be 5 to 10 microamps, while the node bias current may be only 5 to 10 nanoamps in some embodiments, resulting in very low bias power consumption for the operational amplifier nodes.

[0030] Figure 2 An exemplary bias current generator 200 is shown. During active operation, operational amplifier 205 drives the gate of PMOS output transistor P5 to control a bias current I, which flows to ground through variable resistor R2 and switch S3. Switch S3 closes in response to an assertion of an enable signal during active operation of bias current generator 200. With switch S3 closed, the feedback mechanism through operational amplifier 205 is similar to... Figure 1 As discussed earlier, the drain of the output transistor P5 (designated as the feedback node) is kept equal to the reference voltage Vref, such as the bandgap voltage. Therefore, the bias current I will be equal to Vref / R2 during active (normal) operation. Resistor R2 is a variable resistor, so its resistance value can be varied to calibrate the bias current, thus taking into account process, voltage, or temperature variations.

[0031] The feedback node is coupled to the power node supplying the supply voltage VDD via a PMOS switching transistor MPU2. An enable signal drives the gate of the switching transistor MPU2, causing the feedback node to be charged to the supply voltage during non-operating operation, when the enable signal is negated. During this non-operating operation, switch S3 opens in response to the negation of the enable signal to prevent the output transistor P5 from conducting current. The negation of the enable signal is equivalent to an assertion of the en-bar, which closes switch S2 to connect current source 210 to the output of operational amplifier 205. Switch S2 and switching transistor MPU2 form a switching network used to provide bias to the operational amplifier node. During active operation, switch S2 opens when the output transistor P5 conducts bias current. To keep current source 210 active so that it can immediately provide bias to the operational amplifier when needed, switch S1 closes in response to the assertion of the enable signal, causing current source 210 to be powered by a diode-connected PMOS transistor P4, whose source is connected to the power node. Therefore, transistor P4 will provide node bias current to current source 210 during active mode operation of bias current generator 200. Switch S1 turns on in response to the negation of the enable signal.

[0032] Bias current generator 200 includes a secondary current generator 215 that mirrors the bias current to one or more secondary currents that can be used to bias external circuitry, such as components of a switching power converter. In secondary current generator 215, the output of operational amplifier 205 drives the gate of PMOS transistor P6 and, through isolation resistor RISO, drives the gate of PMOS transistor P7. The sources of transistors P5, P6, and P7 are all connected to a power node and share a common gate voltage. Therefore, transistor P6 will conduct a secondary current proportional to the bias current, the ratio depending on the size ratio between transistors P5 and P6. Similarly, transistor P7 will source a secondary current proportional to the bias current, the ratio depending on the size ratio between transistor P7 and transistor P5. For example, if the bias current is 5 μA, the current sourced by transistor P7 might be 0.5 μA. It should be understood that the current magnitudes discussed herein are merely exemplary. To provide both sink and source secondary current, the drain of transistor P6 is connected via switch S4 to the drain of diode-connected NMOS transistor M2, which forms a current mirror configuration with NMOS transistor M3. The gate of transistor M2 is thus connected to the gate of transistor M3. The sources of both transistors M2 and M3 are connected to ground. Therefore, the drain of transistor M3 will sink a secondary current proportional to the bias current during active mode, when switch S4 is turned off in response to an assertion of an enable signal. For example, transistors M2 and M3 can be sized so that in an embodiment with a bias current of 5 μA, transistor M3 conducts a secondary current of 1 μA. To prevent transistor M3 from discharging during inactive mode operation of the bias current generator 200, the gate of transistor M3 is connected to ground via NMOS switch transistor M4, which is turned on in response to an assertion of an en-bar signal. Therefore, switch transistor M4 is turned off during active mode operation.

[0033] The biasing of the operational amplifier nodes by the node bias current enables operational amplifier 205 to quickly transition to stable operation in active mode. For example, the output node of operational amplifier 205 is biased by the node bias current. Since this output node voltage is also the gate voltage of output transistor P5, the bias of this gate voltage is very close to the gate voltage required for active operation. The transition from sleep mode to active operation therefore requires very little time to transition the gate voltage of output transistor P5 to the level required for active operation. Furthermore, the bias current may be relatively large compared to the secondary current generated by secondary current generator 215. For example, the bias current may be equal to 5 μA, while the secondary current sourced by transistor P7 is an order of magnitude smaller (0.5 μA). This relatively strong level of bias current helps operational amplifier 205 quickly reach stable operation relative to the gate of driving output transistor P5, so that the bias current is stably generated at the required level within a relatively short transition time from sleep mode to active mode operation.

[0034] The self-biasing of operational amplifier nodes by the node bias current can be achieved through a reference. Figure 3 The circuit diagram of operational amplifier 205 shown provides a better understanding. Operational amplifier 205 includes a differential pair formed by NMOS first differential pair transistor M4 and NMOS second differential pair transistor M5. The sources of transistors M4 and M5 are coupled to the drain of NMOS switching transistor M6 through their respective resistors Rs, with the source of M6 connected to ground. An assertion of an enable signal turns on switching transistor M6 during active operation so that the bias current can be controlled via feedback from operational amplifier 205, as described above.

[0035] The feedback node voltage drives the gate of transistor M4, while the reference voltage drives the gate of transistor M5. During inactive operation, the switching transistor MPU2 ( Figure 2 The circuit is turned on, allowing the feedback node to be charged to the supply voltage VDD. Simultaneously, Figure 1 Current source 210 provides node bias current from the output of operational amplifier 205 (drain of transistor M5). The drain of transistor M4 is connected to the power node via PMOS transistor P9, which turns on when the enable signal is denied. The node bias current can therefore be provided from the power node at the source of transistor P9 and flows through the channels of transistors P9 and M4 during inactive periods or operating modes. The self-bias current then continues through two resistors Rs to the source of transistor M5, where it is conducted through the body diode of transistor M5 to the output of operational amplifier 205. The output node of operational amplifier 205 is connected to the gate of output transistor P5, such that the gate of output transistor P5 is biased in sleep mode to approximate its final value reached in active mode, thereby enabling a rapid transition to active mode operation.

[0036] Once the enable signal is asserted, transistor M6 conducts, allowing transistors M4 and M5 to conduct to ground via resistor Rs and transistor M6. Transistor P9 is off, but the drain of transistor M4 is also connected to the power node via a PMOS diode connected to transistor P8, which forms a current mirror configuration with PMOS transistor P10. The sources of transistors P8 and P10 are connected to the power node. Similarly, the gate (and drain) of transistor P8 is connected to the gate of transistor P10, and its drain is connected to the drain of the second differential pair transistor M5. The feedback via differential pair transistors M4 and M5 will therefore force the feedback node voltage to be equal to the reference voltage during normal (active mode) operation. Furthermore, this feedback can be further stabilized by a compensation circuit formed by a series compensation capacitor Cc and a compensation resistor Rc, coupled from the power node to the output node of operational amplifier 205.

[0037] The bias current generator 200 is operated as follows: the method includes operations performed on the operational amplifier 205 during inactive periods. These inactive operations include opening switch S3 to prevent output transistor P5 from conducting and closing the switch formed by switching transistor MPU2 to charge the gate of the first differential pair transistor M4 to the supply voltage VDD while conducting node bias current through the channel of the first differential pair transistor M4 and through the body diode of the second differential pair transistor M5, so as to bias the gate of the output transistor with the node bias current.

[0038] The method also includes operations performed during the activity of operational amplifier 205. These operations during activity include turning off switch S3 to allow output transistor P5 to begin conducting through the output resistor, and turning off switch transistor MPU2 such that feedback through operational amplifier 205 causes output transistor P5 to conduct a bias current equal to the ratio of the reference voltage to the resistance value of the output resistor, wherein the bias current is greater than the node bias current.

[0039] Those skilled in the art should understand that this utility model can be implemented in many other specific forms without departing from the spirit and scope of this utility model. Any changes or modifications made by those skilled in the art based on the embodiments of this utility model and the above disclosure shall fall within the protection scope of the claims.

Claims

1. A bias current generator, comprising: One output transistor; An operational amplifier having its output node connected to the gate of the output transistor, characterized in that, during an active operating mode of the bias current generator, the operational amplifier is configured to bias the output node based on a comparison between a feedback node voltage and a reference voltage, such that the output transistor conducts a bias current during the active operating mode. A current source is configured to conduct node bias current; A switching network is configured to provide the node bias current from the output of the operational amplifier during a sleep operation mode, in which the output transistor does not conduct the bias current, wherein the bias current is greater than the node bias current; and A secondary current generator is configured to mirror the bias current as a secondary current, wherein the bias current is greater than the secondary current and the secondary current is greater than the node bias current.

2. The bias current generator according to claim 1, characterized in that, The operational amplifier includes a differential pair transistor, wherein during the active operation mode, the gate of the first differential pair transistor in the differential pair is charged to the feedback node voltage, and the gate of the second differential pair transistor is charged to the reference voltage.

3. The bias current generator according to claim 2, characterized in that, The switching network includes a first switching transistor configured to be turned on during the sleep operation mode to charge the gate of the first differential pair transistor to the supply voltage, and the first switching transistor is also configured to be turned off during the active operation mode.

4. The bias current generator according to claim 3, characterized in that, The switching network further includes a second switching transistor configured to be turned on during the sleep operation mode to power the first differential pair transistor with a supply voltage, and the second switching transistor is also configured to be turned off during the active operation mode.

5. The bias current generator according to claim 1, characterized in that, The source of the output transistor is connected to the power supply node, and the secondary current generator includes: A first transistor, the source of which is connected to the power node and the gate of which is connected to the gate of the output transistor; and A current mirror is connected to the drain of the first transistor via a first switch.

6. The bias current generator according to claim 1, characterized in that, The switching network includes a first switch connected between the current source and the output node, the first switch being configured to close during the sleep operation mode and open during the active operation mode.

7. The bias current generator according to claim 6, characterized in that, Also includes: A diode-connected transistor, wherein the switching network further includes a second switch configured to close during the active operating mode to connect the current source to the diode-connected transistor, and configured to open during the sleep operating mode to isolate the current source from the diode-connected transistor.

8. The bias current generator according to claim 7, characterized in that, The current source is configured to direct the node bias current to ground, wherein the source of the diode-connected transistor is connected to the power node and the drain is connected to the second switch.

9. The bias current generator according to claim 2, characterized in that, Also includes: A compensation circuit is configured to compensate the output node of the operational amplifier.

10. The bias current generator according to claim 9, characterized in that, The compensation circuit includes a compensation capacitor and a compensation resistor connected in series.

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