Power management circuit

Abstract

The utility model provides a kind of power management circuit, comprising: signal isolation module's input end is electrically connected with power supply stable output signal source;First control module is electrically connected with the first output interface of signal isolation module, and first control module generates the first control signal of control operating voltage source;Operating voltage source switch first end is electrically connected with operating voltage source, and the second end of operating voltage source switch is as load voltage source, and operating voltage source switch is controlled by first control signal;Second control module is electrically connected with the second output interface of signal isolation module, and second control module generates the second control signal of control standby voltage source;Slow start module is electrically connected with second control module;Standby voltage source switch first end is electrically connected with standby voltage source, and the second end of standby voltage source switch is as load voltage source, and standby voltage source switch is controlled by second control signal.The utility model can guarantee the voltage stability in switching process of two-way power supply system.

Description

Technical Field

[0001] This utility model relates to the field of power supply circuit technology, and in particular to a power management circuit. Background Technology

[0002] Modern computer motherboards require dual +5V power supply for low standby power consumption and fast wake-up functionality. Even after shutdown, a small portion of the computer system's circuitry (powered by the standby voltage source, VCC5SB) remains active, listening for power-on signals and network wake-up packets. If the entire motherboard's 5V supply were provided by the working voltage source, this part of the circuitry would be completely de-energized after shutdown, preventing the motherboard from responding to wake-up events. Simultaneously, the working voltage source VCC5 line is de-energized in the shutdown state and needs to be isolated from the standby voltage source VCC5SB line. Otherwise, devices powered by the standby voltage source VCC5SB might reverse-flow current through motherboard circuitry to other devices on the working voltage source VCC5 line, potentially causing unexpected device startup and, in severe cases, damage. Some devices need to operate simultaneously in both power-on and standby states, but the operating current in the power-on state is significantly greater than the current in the standby state; therefore, the standby voltage source VCC5SB is required. However, in existing dual-power supply systems, the switching between the two voltage sources is not synchronized, which can lead to excessive current flow or voltage drop, easily causing downstream equipment to reset, fail, or even be damaged. Utility Model Content

[0003] The power management circuit provided by this utility model can ensure voltage stability during the switching process of two power supply systems.

[0004] This utility model provides a power management circuit, including:

[0005] A signal isolation module, wherein the input terminal of the signal isolation module is electrically connected to a power supply stable output signal source;

[0006] A first control module is electrically connected to the first output interface of the signal isolation module. The first control module is used to generate a first control signal for controlling the output and shutdown of the operating voltage source.

[0007] A working voltage source switch, wherein the first terminal of the working voltage source switch is electrically connected to a working voltage source, the second terminal of the working voltage source switch serves as a load voltage source, and the working voltage source switch is controlled by a first control signal output by the first control module;

[0008] The second control module is electrically connected to the second output interface of the signal isolation module. The second control module is used to generate a second control signal for controlling the output and shutdown of the standby voltage source. The output speed of the second control signal for controlling the output of the standby voltage source is greater than the output speed of the first control signal for controlling the shutdown of the working voltage source, and the output speed of the second control signal for controlling the shutdown of the standby voltage source is less than the output speed of the first control signal for controlling the output of the working voltage source.

[0009] A soft-start module is electrically connected to the second control module. The soft-start module is used to reduce the output speed of the second control signal that controls the standby voltage source when the power is connected.

[0010] A standby voltage source switch, wherein the first terminal of the standby voltage source switch is electrically connected to a standby voltage source, the second terminal of the standby voltage source switch serves as a load voltage source, and the standby voltage source switch is controlled by a second control signal output by the second control module.

[0011] Optionally, the signal isolation module includes:

[0012] The first resistor, with its first end electrically connected to the power supply stable output signal source;

[0013] The first MOSFET has its gate electrically connected to the second terminal of the first resistor, and its first terminal is grounded.

[0014] The second resistor has its first end electrically connected to the standby voltage source and its second end electrically connected to the second end of the first MOSFET.

[0015] The third resistor has its first end electrically connected to the second end of the second resistor, and the second end of the third resistor serves as the second output interface of the signal isolation module.

[0016] The fourth resistor has its first end electrically connected to the second end of the second resistor, and its second end serves as the first output interface of the signal isolation module.

[0017] Optionally, the first control module includes:

[0018] The second MOSFET has its gate electrically connected to the first output interface of the signal isolation module, and its first terminal is grounded.

[0019] The fifth resistor has its first end electrically connected to the driving voltage source and its second end electrically connected to the second end of the second MOS transistor.

[0020] The sixth resistor, the first end of which is electrically connected to the second end of the fifth resistor;

[0021] The first diode has its first end electrically connected to the first end of the sixth resistor, and its second end electrically connected to the second end of the sixth resistor.

[0022] A first capacitor, the first terminal of which is electrically connected to the second terminal of the sixth resistor, the second terminal of which is grounded, and the first terminal of which is used to output a first control signal.

[0023] Optionally, the second control module includes:

[0024] The third MOS transistor has its gate electrically connected to the second output interface of the signal isolation module; the first terminal of the third MOS transistor is grounded.

[0025] The seventh resistor has its first end electrically connected to the standby voltage source and its second end electrically connected to the second end of the third MOSFET.

[0026] The fourth MOS transistor has its first terminal electrically connected to the second terminal of the seventh resistor, and its gate electrically connected to the driving voltage source.

[0027] The eighth resistor, the first end of which is electrically connected to the second end of the fourth MOS transistor;

[0028] The second capacitor has its first terminal electrically connected to the second terminal of the eighth resistor, and its second terminal electrically connected to the standby voltage source; the first terminal of the second capacitor is used to output the second control signal.

[0029] Optionally, the soft-start module includes:

[0030] The ninth resistor has its first end electrically connected to the second end of the third MOS transistor, and its second end electrically connected to the first end of the second capacitor.

[0031] Optionally, the operating voltage source switch includes:

[0032] The fifth MOS transistor has its first terminal electrically connected to the operating voltage source, its second terminal serving as the load voltage source, and its gate receiving the first control signal output by the first control module.

[0033] Optionally, it also includes:

[0034] The third capacitor has its first terminal electrically connected to the first terminal of the fifth MOS transistor, and its second terminal grounded.

[0035] Optionally, the standby voltage source switch includes:

[0036] The sixth MOS transistor has its first terminal electrically connected to the standby voltage source, its second terminal serving as the load voltage source, and its gate receiving the second control signal output by the second control module.

[0037] Optionally, it also includes:

[0038] The fourth capacitor has its first terminal electrically connected to the first terminal of the sixth MOS transistor, and its second terminal grounded.

[0039] Optionally, it also includes a filtering module, the filtering module comprising:

[0040] The fifth capacitor has its first terminal electrically connected to the load voltage source and its second terminal grounded.

[0041] The sixth capacitor has its first terminal electrically connected to the load voltage source and its second terminal grounded.

[0042] In the technical solution provided by this utility model, the working voltage source switch is controlled by the first control module, and the standby voltage source switch is controlled by the second control module and the soft start module. When the motherboard power is on, the standby voltage source output speed is slow, reducing the inrush current when the standby voltage source is powered on. When the motherboard is turned on, the working voltage source output speed is faster than the standby voltage source turn-off speed. When the motherboard is turned off, the working voltage source turn-off speed is slower than the standby voltage source output speed. Thus, the risk of voltage drop due to dead time and damage to the motherboard due to long-term through current is avoided, ensuring voltage stability. Attached Figure Description

[0043] Figure 1 This is a block diagram of a power management circuit according to an embodiment of the present invention;

[0044] Figure 2 This is a schematic diagram of a power management circuit according to another embodiment of the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0046] This utility model embodiment provides a power management circuit, such as Figure 1 As shown, it includes:

[0047] A signal isolation module, wherein the input terminal of the signal isolation module is electrically connected to the power supply stable output signal source ATX_PWROK;

[0048] A first control module is electrically connected to the first output interface of the signal isolation module. The first control module is used to generate a first control signal for controlling the output and shutdown of the working voltage source VCC5.

[0049] The working voltage source switch has a first terminal electrically connected to the working voltage source VCC5, and a second terminal serving as the load voltage source VCC5_DUAL. The working voltage source switch is controlled by a first control signal output by the first control module.

[0050] The second control module is electrically connected to the second output interface of the signal isolation module. The second control module is used to generate a second control signal for controlling the output and shutdown of the standby voltage source VCC5SB. The output speed of the second control signal controlling the output of the standby voltage source VCC5SB is greater than the output speed of the first control signal controlling the shutdown of the working voltage source VCC5, and the output speed of the second control signal controlling the shutdown of the standby voltage source VCC5SB is less than the output speed of the first control signal controlling the output of the working voltage source VCC5.

[0051] A soft-start module is electrically connected to the second control module. The soft-start module is used to reduce the output speed of the second control signal that controls the standby voltage source VCC5SB when the power is connected.

[0052] A standby voltage source switch, wherein the first terminal of the standby voltage source switch is electrically connected to the standby voltage source VCC5SB, and the second terminal of the standby voltage source switch serves as the load voltage source VCC5_DUAL. The standby voltage source switch is controlled by the second control signal output by the second control module.

[0053] In the technical solution provided by this utility model embodiment, the working voltage source switch is controlled by the first control module, and the standby voltage source switch is controlled by the second control module and the soft start module. When the motherboard power is on, the standby voltage source output speed is slow, reducing the inrush current when the standby voltage source is powered on. When the motherboard is powered on, the working voltage source output speed is 1-2ms faster than the standby voltage source turn-off speed. When the motherboard is powered off, the working voltage source turn-off speed is 1-2ms slower than the standby voltage source output speed. Thus, the risk of voltage drop due to dead time and damage to the motherboard due to long-term through current is avoided, ensuring voltage stability.

[0054] As an optional implementation method, such as Figure 2 As shown, the signal isolation module includes:

[0055] The first resistor R1 is electrically connected to the power supply stable output signal source ATX_PWROK.

[0056] The first MOSFET Q1 has its gate electrically connected to the second terminal of the first resistor R1, and its first terminal is grounded.

[0057] The second resistor R2 has its first end electrically connected to the standby voltage source VCC5SB and its second end electrically connected to the second end of the first MOSFET Q1.

[0058] The third resistor R3 has its first end electrically connected to the second end of the second resistor R2, and the second end of the third resistor R3 serves as the second output interface of the signal isolation module.

[0059] The fourth resistor R4 has its first end electrically connected to the second end of the second resistor R2, and the second end of the fourth resistor R4 serves as the first output interface of the signal isolation module.

[0060] In some embodiments, the power supply stable output signal source ATX_PWROK (3.3V power domain) signal is divided into two control signals by the first-stage MOSFET, and then the control signals are input to the second control module and the first control module through the third resistor R3 and the fourth resistor R4, respectively.

[0061] As an optional implementation method, such as Figure 2 As shown, the first control module includes:

[0062] The gate of the second MOSFET Q2 is electrically connected to the first output interface of the signal isolation module, and the first terminal of the second MOSFET Q2 is grounded.

[0063] The fifth resistor R5 has its first end electrically connected to the driving voltage source VCC12, and its second end electrically connected to the second end of the second MOSFET Q2.

[0064] The sixth resistor R6, the first end of which is electrically connected to the second end of the fifth resistor R5;

[0065] The first diode D1 has its first terminal electrically connected to the first terminal of the sixth resistor R6, and its second terminal electrically connected to the second terminal of the sixth resistor R6.

[0066] The first capacitor C1 has its first terminal electrically connected to the second terminal of the sixth resistor R6, and its second terminal is grounded. The first terminal of the first capacitor C1 is used to output a first control signal.

[0067] In some embodiments, when the motherboard is in standby mode, the standby voltage source VCC5SB provides normal power, while the drive voltage source VCC12 and the working voltage source VCC5 are not powered on. At this time, the power supply stable output signal source ATX_PWROK is at a low level, the first MOSFET Q1 is turned off, and the gate of the second MOSFET Q2 is powered by the standby voltage source VCC5SB, turning on the second MOSFET Q2. At this time, the drain of Q2 is at a low level. The fifth MOSFET Q5 is in the off state. Since the working voltage source VCC5 is not yet powered on, the body diode of the fifth MOSFET Q5 is cut off, and the working voltage source VCC5 and the load voltage source VCC5_DUAL are isolated through the fifth MOSFET Q5. When the motherboard is powered on, after the working voltage source VCC5 and the drive voltage source VCC12 are powered on, the power supply stable output signal source ATX_PWROK becomes high, the first MOSFET Q1 is turned on, the gate of the second MOSFET Q2 is at a low level, and the second MOSFET Q2 is turned off. The driving voltage source VCC12 charges the first capacitor C1 through the fifth resistor R5 and the first diode D1. The gate voltage of the fifth MOSFET Q5 gradually increases, causing Q5 to conduct. The operating voltage source VCC5 is then output to the load voltage source VCC5_DUAL. During the motherboard shutdown process, the power supply stable output signal source ATX_PWROK first drops to a low level, the first MOSFET Q1 turns off, and the second MOSFET Q2 turns on. The first capacitor C1 discharges to the ground node GND through the sixth resistor R6 and the second MOSFET Q2. The gate voltage of the fifth MOSFET Q5 gradually decreases, causing Q5 to turn off. The operating voltage source VCC5 is isolated from the load voltage source VCC5_DUAL.

[0068] As an optional implementation method, such as Figure 2 As shown, the second control module includes:

[0069] The third MOSFET Q3 has its gate electrically connected to the second output interface of the signal isolation module; the first terminal of the third MOSFET Q3 is grounded.

[0070] The seventh resistor R7 has its first end electrically connected to the standby voltage source VCC5SB, and its second end electrically connected to the second end of the third MOSFET Q3.

[0071] The fourth MOSFET Q4 is electrically connected to the second terminal of the seventh resistor R7, and its gate is electrically connected to the driving voltage source VCC12.

[0072] The eighth resistor R8, the first end of which is electrically connected to the second end of the fourth MOSFET Q4;

[0073] The second capacitor C2 has its first terminal electrically connected to the second terminal of the eighth resistor R8, and its second terminal electrically connected to the standby voltage source VCC5SB; the first terminal of the second capacitor C2 is used to output the second control signal.

[0074] As an optional implementation method, such as Figure 2 As shown, the soft-start module includes:

[0075] The ninth resistor R9 has its first end electrically connected to the second end of the third MOSFET Q3, and its second end electrically connected to the first end of the second capacitor C2.

[0076] In some embodiments, when the motherboard is in standby mode, the standby voltage source VCC5SB provides normal power, the power supply stable output signal source ATX_PWROK is at a low level, the first MOSFET Q1 is turned off, the third MOSFET Q3 is turned on, and the gate of the sixth MOSFET Q6 is at a low level, so the sixth MOSFET Q6 is in a conducting state. Therefore, the standby voltage source VCC5SB is output to the load voltage source VCC5_DUAL. When the motherboard is powered on, the working voltage source VCC5 and the drive voltage source VCC12 are powered on first, and the gate voltage of the fourth MOSFET Q4 rises to 12V. At this time, V_GS of the fourth MOSFET Q4 > V_GS(th), so the fourth MOSFET Q4 is turned on. Then the power supply stable output signal source ATX_PWROK becomes high, the first MOSFET Q1 is turned on, and the third MOSFET Q3 is turned off. The second capacitor C2 discharges through the path of the seventh resistor R7, the fourth MOSFET Q4, and the eighth resistor R8. The gate voltage of the sixth MOSFET Q6 gradually increases, causing Q6 to turn off, isolating the standby voltage source VCC5SB from the load voltage source VCC5_DUAL. During the power-off process, the power supply stable output signal source ATX_PWROK first goes low, turning off the first MOSFET Q1 and turning on the third MOSFET Q3. At this time, the working voltage source VCC5 and the drive voltage source VCC12 have not yet been completely de-energized, and the fourth MOSFET Q4 remains on. VCC5SB charges the second capacitor C2 through the path of the eighth resistor R8, the fourth MOSFET Q4, the third MOSFET Q3, and the ground node GND. The gate voltage of the sixth MOSFET Q6 gradually decreases, causing Q6 to turn on, and the standby voltage source VCC5SB is output to the load voltage source VCC5_DUAL.

[0077] At the same time, by formula It can be seen that the factors affecting the magnitude of current I include the capacitance C of the load and the slope of the voltage change. In this embodiment, by reducing To reduce the inrush current of the standby voltage source VCC5SB, the rise time of the voltage is extended while keeping the rise voltage value constant. After the ATX power supply is connected and the motherboard is operating normally, the standby voltage source VCC5SB begins to rise. At this time, the first MOSFET Q1 and the third MOSFET Q3 are turned off, and the gate voltage of the sixth MOSFET Q6 rises with the standby voltage source VCC5SB. When the standby voltage source VCC5SB rises to the conduction threshold voltage of the third MOSFET Q3, the third MOSFET Q3 turns on, and the standby voltage source VCC5SB charges the second capacitor C2 through the path of the ninth resistor R9 and the ground node GND. The gate voltage of the sixth MOSFET Q6 then decreases. Increasing the charging time of the second capacitor C2 (i.e., increasing the resistance value of the ninth resistor R9) reduces the inrush current.

[0078] As an optional implementation, the operating voltage source switch includes:

[0079] The fifth MOSFET Q5 has its first terminal electrically connected to the operating voltage source VCC5, and its second terminal serves as the load voltage source VCC5_DUAL. The gate of the fifth MOSFET Q5 receives the first control signal output by the first control module.

[0080] As an optional implementation method, such as Figure 2 As shown, it also includes:

[0081] The third capacitor C3 has its first terminal electrically connected to the first terminal of the fifth MOSFET Q5, and its second terminal grounded.

[0082] As an optional implementation method, such as Figure 2 As shown, the standby voltage source switch includes:

[0083] The sixth MOSFET Q6 has its first terminal electrically connected to the standby voltage source VCC5SB, and its second terminal serves as the load voltage source VCC5_DUAL. The gate of the sixth MOSFET Q6 receives the second control signal output by the second control module.

[0084] As an optional implementation method, such as Figure 2 As shown, it also includes:

[0085] The fourth capacitor C4 has its first terminal electrically connected to the first terminal of the sixth MOSFET Q6, and its second terminal grounded.

[0086] As an optional implementation method, such as Figure 2 As shown, it also includes a filtering module, which includes:

[0087] The fifth capacitor C5 has its first terminal electrically connected to the load voltage source VCC5_DUAL, and its second terminal grounded.

[0088] The sixth capacitor C6 has its first terminal electrically connected to the load voltage source VCC5_DUAL, and its second terminal grounded.

[0089] In the aforementioned embodiments, to avoid output voltage drops, there must be no dead time between the sixth MOSFET Q6 and the fifth MOSFET Q5, and a time margin of 1-2ms is required. Therefore, during motherboard power-on, the fifth MOSFET Q5 needs to turn on quickly, and the sixth MOSFET Q6 needs to turn off slowly; during motherboard power-off, the fifth MOSFET Q5 needs to turn off slowly, and the sixth MOSFET Q6 needs to turn on quickly. Simultaneously, to reduce the inrush current when the standby voltage source VCC5SB is powered on and to prevent the ATX power supply from entering overcurrent protection mode, the sixth MOSFET Q6 needs to turn on slowly when the motherboard ATX power supply is connected and the standby voltage source VCC5SB is powered on. To achieve this, five differentiated delay strategies are implemented as follows:

[0090] During the motherboard power-on phase, the driving voltage source VCC12 charges the first capacitor C1 through the fifth resistor R5 and the first diode D1. The gate voltage of the fifth MOSFET Q5 gradually increases, and the charging time is represented by T1.

[0091] During the motherboard power-on phase, the second capacitor C2 discharges through the seventh resistor R7, the fourth MOSFET Q4, the eighth resistor R8, and VCC5SB. The gate voltage of the sixth MOSFET Q6 gradually increases, and the charging time is represented by T2.

[0092] During the motherboard shutdown phase, the first capacitor C1 discharges to GND through the sixth resistor R6 and the second MOSFET Q2. The gate voltage of the fifth MOSFET Q5 gradually decreases, and the discharge time is represented by T3.

[0093] During the motherboard shutdown phase, the standby voltage source VCC5SB charges the second capacitor C2 through the ninth resistor R8, the fourth MOSFET Q4, the third MOSFET Q3, and the GND path. The gate voltage of the sixth MOSFET Q6 gradually decreases, and the discharge time is represented by T4.

[0094] When the motherboard ATX power supply is connected and the standby voltage source VCC5SB is powered on, the standby voltage source VCC5SB charges the second capacitor C2 through the path of the second capacitor C2, the ninth resistor R9, the third MOSFET Q3 and the ground node GND. The charging time is represented by T5.

[0095] The formula for calculating the charging and discharging time of a capacitor is as follows:

[0096]

[0097] Where V1 represents the final voltage value of the capacitor after full charging or discharging, V0 represents the initial voltage value of the capacitor before charging, and V t R represents the target voltage value for capacitor charging, R represents the path resistance, and C represents the capacitance value of the capacitor being charged and discharged.

[0098] Since the resistance of the diodes and MOSFETs in the path is extremely low when fully turned on, it can be ignored. Based on the above formula, we can obtain:

[0099]

[0100] Where V GS(th)1 V represents the turn-on threshold of the fifth MOSFET Q5. GS(th)2 This indicates the turn-on threshold of the sixth MOSFET Q6. R5, R7, R8, R6, and R9 represent the resistance values ​​of the fifth resistor R5, the seventh resistor R7, the eighth resistor R8, the sixth resistor R6, and the ninth resistor R9, respectively. C2 and C1 represent the capacitance values ​​of the second capacitor C2 and the first capacitor C1, respectively.

[0101] Based on 1ms≤T2-T1≤2ms, 1ms≤T3-T4≤2ms, and T5≥4ms, the range of values ​​for R5, R6, R7, R8, and R9 can be calculated.

[0102] Through the aforementioned implementation methods, a relatively long RC delay is used in the power-on path of the standby voltage source VCC5SB, causing the sixth MOSFET Q6 to turn on slowly. This limits the inrush current of the load voltage source VCC5_DUAL, with measured inrush current ranging from 1.2 to 1.8 A, fully complying with the ATX specification's operating current requirements for ATX power supplies. Simultaneously, by adding differentiated delay strategies to the paths of the fifth MOSFET Q5 and the sixth MOSFET Q6, precise timing control of their turn-on and turn-off is achieved, resolving voltage drops caused by dead time and ensuring that there is no prolonged short circuit between the operating voltage source VCC5 and the standby voltage source VCC5SB. Due to the use of fewer components and lower component costs, the aforementioned implementation methods offer a significant cost advantage compared to integrated circuits. Furthermore, the design of a certain dual-pass time margin improves system reliability.

[0103] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A power management circuit, characterized by, include: A signal isolation module, wherein the input terminal of the signal isolation module is electrically connected to a power supply stable output signal source; A first control module is electrically connected to the first output interface of the signal isolation module. The first control module is used to generate a first control signal for controlling the output and shutdown of the operating voltage source. A working voltage source switch, wherein the first terminal of the working voltage source switch is electrically connected to a working voltage source, the second terminal of the working voltage source switch serves as a load voltage source, and the working voltage source switch is controlled by the first control signal output by the first control module; The second control module is electrically connected to the second output interface of the signal isolation module. The second control module is used to generate a second control signal for controlling the output and shutdown of the standby voltage source. The output speed of the second control signal controlling the output of the standby voltage source is greater than the output speed of the first control signal controlling the shutdown of the working voltage source, and the output speed of the second control signal controlling the shutdown of the standby voltage source is less than the output speed of the first control signal controlling the output of the working voltage source. A soft-start module is electrically connected to the second control module. The soft-start module is used to reduce the output speed of the second control signal that controls the standby voltage source when the power is connected. A standby voltage source switch, wherein the first terminal of the standby voltage source switch is electrically connected to the standby voltage source, the second terminal of the standby voltage source switch serves as the load voltage source, and the standby voltage source switch is controlled by the second control signal output by the second control module.

2. The power management circuit of claim 1, wherein, The signal isolation module includes: The first resistor, with its first end electrically connected to the power supply stable output signal source; The first MOSFET has its gate electrically connected to the second terminal of the first resistor, and its first terminal is grounded. The second resistor has its first end electrically connected to the standby voltage source and its second end electrically connected to the second end of the first MOSFET. The third resistor has its first end electrically connected to the second end of the second resistor, and the second end of the third resistor serves as the second output interface of the signal isolation module. The fourth resistor has its first end electrically connected to the second end of the second resistor, and its second end serves as the first output interface of the signal isolation module.

3. The power management circuit of claim 1, wherein, The first control module includes: The second MOSFET has its gate electrically connected to the first output interface of the signal isolation module, and its first terminal is grounded. The fifth resistor has its first end electrically connected to the driving voltage source and its second end electrically connected to the second end of the second MOS transistor. The sixth resistor, the first end of which is electrically connected to the second end of the fifth resistor; A first diode, wherein a first terminal of the first diode is electrically connected to a first terminal of the sixth resistor, and a second terminal of the first diode is electrically connected to a second terminal of the sixth resistor; The first capacitor has its first terminal electrically connected to the second terminal of the sixth resistor, and its second terminal is grounded. The first terminal of the first capacitor is used to output the first control signal.

4. The power management circuit according to claim 1, characterized in that, The second control module includes: The third MOS transistor has its gate electrically connected to the second output interface of the signal isolation module; the first terminal of the third MOS transistor is grounded. The seventh resistor has its first end electrically connected to the standby voltage source and its second end electrically connected to the second end of the third MOSFET. The fourth MOS transistor has its first terminal electrically connected to the second terminal of the seventh resistor, and its gate electrically connected to the driving voltage source. The eighth resistor, the first end of which is electrically connected to the second end of the fourth MOS transistor; The second capacitor has its first terminal electrically connected to the second terminal of the eighth resistor, and its second terminal electrically connected to the standby voltage source; the first terminal of the second capacitor is used to output the second control signal.

5. The power management circuit of claim 4, wherein, The soft-start module includes: The ninth resistor has its first end electrically connected to the second end of the third MOS transistor, and its second end electrically connected to the first end of the second capacitor.

6. The power management circuit of claim 1, wherein, The operating voltage source switch includes: The fifth MOS transistor has its first terminal electrically connected to the operating voltage source, its second terminal serving as the load voltage source, and its gate receiving the first control signal output by the first control module.

7. The power management circuit of claim 6, wherein, Also includes: The third capacitor has its first terminal electrically connected to the first terminal of the fifth MOS transistor, and its second terminal grounded.

8. The power management circuit of claim 1, wherein, The standby voltage source switch includes: The sixth MOS transistor has its first terminal electrically connected to the standby voltage source, its second terminal serving as the load voltage source, and its gate receiving the second control signal output by the second control module.

9. The power management circuit of claim 8, wherein, Also includes: The fourth capacitor has its first terminal electrically connected to the first terminal of the sixth MOS transistor, and its second terminal grounded.

10. The power management circuit of claim 1, wherein, It also includes a filtering module, which includes: The fifth capacitor has its first terminal electrically connected to the load voltage source and its second terminal grounded. The sixth capacitor has its first terminal electrically connected to the load voltage source and its second terminal grounded.

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