control means

Abstract

The utility model embodiment provides a kind of control component, it is related to storage technical field.The control component includes power management unit, power switch and multiple circuit units;Control component is powered by mains power supply;Power switch includes first power switch and multiple second power switch;The input end of first power switch is coupled with mains power supply, and the output end of first power switch is respectively coupled with the power supply port of each circuit unit;Second power switch is set on the power supply line between each circuit unit power supply port to first power switch;Power management unit is coupled with mains power supply and power switch, and there is no power switch on the power supply line between power management unit and mains power supply;Power management unit controls power switch to open or close, to control the power supply to at least one circuit unit.The control component can realize different levels of power consumption state, and can be switched between various power consumption states.

Description

Technical Field

[0001] This utility model relates to the field of storage technology, and in particular to control components. Background Technology

[0002] Figure 1A A block diagram of the storage device is shown. (Example) Figure 1A As shown, storage device 102 includes an interface 103, a control unit 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110. Storage device 102 is coupled to a host to provide storage capabilities to the host. The host and storage device 102 can be coupled in various ways, including but not limited to using various storage protocols such as SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks to connect the host and storage device 102. The host can be an information processing device that can communicate with the storage device in the above manner, such as a personal computer, tablet computer, server, portable computer, network switch, router, cellular phone, personal digital assistant, etc.

[0003] Interface 103 is compatible with exchanging data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel. NVM chip 105 includes, for example, NAND flash memory, phase-change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc.

[0004] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110. It is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software executes to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 110 and access the data in the DRAM 110. FTL tables and / or cached I / O command data can be stored in the DRAM.

[0005] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc. The host accesses the storage device with I / O commands in accordance with the storage protocol. The control unit 104 generates one or more media interface commands based on the I / O commands from the host and provides them to the media interface controller. The media interface controller generates storage media access commands (e.g., programming commands, read commands, erase commands) in accordance with the interface protocol of the NVM chip based on the media interface commands. The control unit also tracks the completion of all media interface commands generated from an I / O command and indicates the processing results of the I / O commands to the host.

[0006] Figure 1B A block diagram showing the control components of a storage device is provided. Figure 1BAs shown, the control components include, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface receives I / O commands from the host and generates storage commands, which are then provided to the storage command processing unit. The storage command processing unit, based on the physical address provided by the storage media management unit, operates the media interface controller to issue storage media access commands to the NVM chip. The storage media management unit maintains a logical address-to-physical address translation for each storage command. For example, the storage media management unit includes an FTL table. For read commands, the storage media management unit outputs the physical address corresponding to the logical address accessed by the storage command; for write commands, the storage media management unit allocates an available physical address and records the mapping relationship between the accessed logical address and the allocated physical address. The storage media management unit also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling.

[0007] For clarity, commands sent from the host to the storage device are called I / O commands; commands sent from the host command processing unit to the storage command processing unit are called storage commands; commands sent from the storage command processing unit to the media interface controller are called media interface commands; and commands sent from the media interface controller to the NVM chip are called storage media access commands. Storage media access commands conform to the NVM chip's interface protocol.

[0008] Power management refers to the effective management of a chip's energy consumption. Managing chip power consumption helps improve chip performance and reliability. In related technologies, according to the NVMe protocol, the host sends NVMe management commands to the storage device to instruct it to enter a specified power state. The NVMe protocol defines power states, which include multiple levels, such as PS0-PS6, each corresponding to a different power consumption level for the storage device. For example, from PS0 to PS6, the power consumption of the storage device shows a decreasing trend. Utility Model Content

[0009] This utility model embodiment provides a structure for a control component to implement power management. This control component can achieve different levels of power consumption states, switch between various power consumption states, and accept power management from the host, adjusting power levels, initiating sleep mode, and waking up according to the host's instructions. The chip can operate normally under various power consumption states and during switching processes. Furthermore, the components in this storage device that interact with the outside are externally powered, and the storage device can also manage the external power supply, thereby achieving more efficient and broader functional management.

[0010] In a first aspect, the present invention provides a control component, which includes a power management unit, a power switch, and multiple circuit units; the control component is powered by a main power supply; the power switch includes a first power switch and multiple second power switches. The input terminal of the first power switch is coupled to the main power supply, and the output terminal of the first power switch is coupled to the power supply port of each circuit unit respectively. A second power switch is provided on the power supply line between the power supply port of each circuit unit and the first power switch. The power management unit is coupled to the main power supply and the power switch. There is no power switch on the power supply line between the power management unit and the main power supply. The power management unit controls the power switch to open or close in order to control the power supply to at least one circuit unit.

[0011] Optionally, in response to receiving a power management command, the power management unit controls the opening or closing of the first power switch and / or at least one second power switch according to the power management command, so as to disconnect or restore power supply to at least one circuit unit.

[0012] Optionally, the control component further includes multiple isolation units, which are coupled to the signal output path and / or signal input path of the circuit unit; Each of the isolation units is coupled to the power management unit, and each of the isolation units operates in a normal working state or an isolation state under the control of the power management unit; In the normal operating state, the isolation unit directly outputs the first signal in response to receiving the first signal; In the isolated state, the isolation unit, in response to receiving the first signal, generates a specified second signal and outputs the specified second signal.

[0013] Optionally, when the second power switch corresponding to the first circuit unit is closed, the isolation unit coupled to the first circuit unit operates in normal working condition under the control of the power management unit; or, When the second power switch corresponding to the first circuit unit is turned off, the isolation unit coupled to the first circuit unit operates in the isolation state under the control of the power management unit. The first circuit unit is any one of the plurality of circuit units.

[0014] Optionally, the power management command includes a first power management command, which instructs to cut off the power supply to the first circuit unit; In response to receiving the first power management command, the power management unit sends a first control signal to the isolation unit coupled to the first circuit unit to make the isolation unit coupled to the first circuit unit work in the isolation state, and sends a second control signal to the second power switch corresponding to the first circuit unit to control the second power switch corresponding to the first circuit unit to turn off and cut off the power supply to the first circuit unit.

[0015] Optionally, the power management command includes a second power management command, which instructs the restoration of power supply to the first circuit unit; In response to receiving the second power consumption management command, the power management unit sends a third control signal to the second power switch corresponding to the first circuit unit to control the second power switch corresponding to the first circuit unit to close, and sends a fourth control signal to the isolation unit coupled to the first circuit unit to enable the isolation unit coupled to the first circuit unit to operate in the normal working state and restore power supply to the first circuit unit.

[0016] Optionally, the power management command includes a third power management command, which instructs the control unit to enter a specified power consumption state; In response to receiving the third power management command, the power management unit generates and sends a first control signal to the isolation unit coupled to at least one circuit unit, so that the isolation unit coupled to at least one circuit unit operates in the isolation state, and generates and sends a second control signal to the second power switch corresponding to the at least one circuit unit, so as to control the second power switch corresponding to the at least one circuit unit to turn off, thereby disconnecting the power supply to the at least one circuit unit, so that the control component enters the specified power consumption state.

[0017] Optionally, the power management command includes a fourth power management command, which instructs the control unit to exit a specified power consumption state; In response to receiving the fourth power management command, the power management unit generates and sends a third control signal to the isolation unit coupled to at least one circuit unit to enable the isolation unit coupled to at least one circuit unit to operate in a working state, and generates and sends a second control signal to the second power switch corresponding to the at least one circuit unit to control the second power switch corresponding to the at least one circuit unit to close, thereby restoring power supply to the at least one circuit unit and causing the control component to exit the specified power consumption state.

[0018] Optionally, the specified power consumption state includes the power consumption state defined by the NVMe protocol.

[0019] Optionally, the plurality of isolation units include isolation units of a first type and isolation units of a second type; There is no power switch on the power supply line between the first type of isolation unit and the main power supply, and the power supply of the first type of isolation unit is not controlled by the power management unit. The second type of isolation unit is either powered off or powered on under the control of the power management unit.

[0020] Optionally, the isolation unit of the first type includes two power supply ports, one of which is connected to the main power supply.

[0021] Optionally, when the power supply to the circuit units connected to both ends of the second type of isolation unit is cut off, the power management unit controls the second type of isolation unit to disconnect from the power.

[0022] Optionally, the power management unit includes a power management sequence generation unit; In response to the power management unit receiving a power management command, the power management sequence generation unit generates a power management sequence. The power management sequence is used to control the opening of the second power switch corresponding to the specified circuit unit and to control the isolation unit corresponding to the specified circuit unit to be in an isolated state. Alternatively, the power management sequence is used to control the closing of the second power switch corresponding to the specified circuit unit and to control the isolation unit corresponding to the specified circuit unit to be in a normal working state. The specified circuit unit is the circuit unit indicated by the power management command or the circuit unit corresponding to the power state indicated by the power management command.

[0023] Optionally, in response to the power management unit receiving the first power management command, the power management sequence generation unit generates a first power management sequence, the first power management sequence including the first control signal and the second control signal; or, In response to the power management unit receiving the second power management command, the power management sequence generation unit generates a second power management sequence, which includes the third control signal and the fourth control signal.

[0024] Optionally, the power management sequence generation unit generates the second control signal after generating the first control signal at a first specified time interval; or, The power management sequence generation unit generates the fourth control signal after generating the third control signal, at a second specified time interval.

[0025] Optionally, the power management sequence generation unit controls the first control signal to remain unchanged when generating the second control signal, and controls the second control signal to remain unchanged after the second control signal is generated; or, When generating the fourth control signal, the power management sequence generation unit controls the third control signal to remain unchanged, and after the fourth control signal is generated, it controls the fourth control signal to remain unchanged.

[0026] Optionally, the power management sequence generation unit corresponds one-to-one with the circuit unit.

[0027] Optionally, the plurality of circuit units include one or more of the following: a PCIe controller, a CPU core group, an NVMe protocol processor, a media interface controller, and an inter-chip interconnect unit, wherein the CPU core group includes a plurality of CPU cores; The plurality of second power switches are respectively connected to the power supply circuits of the PCIe controller, the CPU core group, each of the CPU cores, the NVMe protocol processor, the media interface controller, and the chip interconnect unit.

[0028] Optionally, the plurality of isolation units are respectively coupled to the signal input path and / or signal output path of the PCIe controller, the CPU core group, each of the CPUs, the NVMe protocol processor, the media interface controller and the chip interconnect unit.

[0029] Optionally, the PCIe controller includes a PCIe physical layer module, which is coupled to the main power supply and the power management unit. There is no power switch on the power supply line between the PCIe physical layer module and the main power supply. The PCIe physical layer module sends a signal to the power management unit, which instructs the power management unit to wake up one or more circuit units.

[0030] Optionally, the isolation unit is coupled to the signal input path of the PCIe physical layer module.

[0031] Optionally, the CPU core group includes a first CPU core; the specified power consumption state includes the PS0 power consumption state, PS1 power consumption state and / or PS2 power consumption state defined by the NVMe protocol; The PSO power consumption status indication indicates that each CPU core in the CPU core group, the PCIe controller, the PCIe physical layer module, the NVMe protocol processor, the media interface controller, and the power management unit are all in normal working condition, and the inter-chip interconnect unit is in a power-off state. The PS1 power consumption status indicates that the first CPU core, the PCIe controller, the PCIe physical layer module, the NVMe protocol processor, and the power management unit are all in normal working condition, while each CPU core in the CPU core group except the first CPU core, the media interface controller, and the chip interconnect unit are in a power-off state. The PS2 power consumption status indicates that each CPU core in the CPU core group, the PCIe controller, the NVMe protocol processor, the media interface controller, and the chip interconnect unit are all in a power-off state; the PCIe physical layer module and the power management unit are in a normal working state.

[0032] Optionally, the PCIe physical layer module is coupled to a first external power supply, and a third power switch is provided on the line where the first external power supply supplies power to the PCIe physical layer module. The input terminal of the third power switch is coupled to the first external power supply, and the output terminal is coupled to the PCIe physical layer module. The third power switch is also coupled to the power management module. The power management unit controls the third power switch to open or close, so as to disconnect or restore the first external power supply to the PCIe physical layer module.

[0033] Optionally, the media interface controller includes a LUN controller, and the LUN controller includes an ONFI physical layer module; The ONFI physical layer module is coupled to a second external power supply. A fourth power switch is provided on the line where the second external power supply powers the ONFI physical layer module. The input terminal of the fourth power switch is coupled to the second external power supply, and the output terminal is coupled to the ONFI physical layer module. The fourth power switch is also coupled to the power management module. The power management unit controls the fourth power switch to open or close, so as to disconnect or restore the second external power supply to the ONFI physical layer module.

[0034] Optionally, the power management unit includes an NVMe power management sequence generation unit, a media interface controller power management sequence generation unit, a CPU power management sequence generation unit, and a PCIe power management sequence generation unit, which respectively generate power management sequences for power management of the NVMe protocol processor, media interface controller, CPU, and PCIe unit.

[0035] Optionally, the power management sequences generated by the NVMe power management sequence generation unit, the media interface controller power management sequence generation unit, the CPU power management sequence generation unit, and the PCIe power management sequence generation unit are the same.

[0036] Optionally, the power management sequences generated by the NVMe power management sequence generation unit, the media interface controller power management sequence generation unit, the CPU power management sequence generation unit, and the PCIe power management sequence generation unit are different.

[0037] Optionally, the first CPU core sends a first power management command to the power management unit, instructing the power supply to the NVMe protocol processor to be cut off; In response to receiving the first power management command, the power management unit starts the NVMe power management sequence generation unit to generate a first power management sequence. The first power management sequence includes a first control signal that controls the isolation unit corresponding to the NVMe protocol processor to work in an isolated state and a second control signal that controls the second power switch corresponding to the NVMe protocol processor to be turned off. The NVMe power management sequence generation unit sends the first control signal to the isolation unit corresponding to the NVMe protocol processor and the second control signal to the second power switch corresponding to the NVMe protocol processor.

[0038] Optionally, the first CPU core sends a second power management command to the power management unit, instructing the restoration of power supply to the NVMe protocol processor; In response to receiving the second power management command, the power management unit starts the NVMe power management sequence generation unit to generate a second power management sequence. The second power management sequence includes a third control signal that controls the isolation unit corresponding to the NVMe protocol processor to work in a normal working state and a fourth control signal that controls the second power switch corresponding to the NVMe protocol processor to close. The NVMe power management sequence generation unit sends the third control signal to the isolation unit corresponding to the NVMe protocol processor and the fourth control signal to the second power switch corresponding to the NVMe protocol processor.

[0039] Optionally, the first CPU core sends a first power management command to the power management unit, instructing the power supply to the NVMe protocol processor to be cut off; In response to receiving the first power management command, the power management unit starts the NVMe power management sequence generation unit to generate the first power management sequence. In response to the power supply to the NVMe protocol processor being cut off, the first CPU core sequentially sends a first power management command to the power management unit, instructing the PCIe controller, the media interface controller, and CPU cores other than the first CPU core to cut off power supply. In response to receiving a first power management command that sequentially instructs to cut off power supply to the PCIe controller, the media interface controller, and the CPU cores other than the first CPU core, the power management unit sequentially starts the PCIe power management sequence generation unit, the media interface controller power management sequence generation unit, and the CPU power management sequence generation unit to generate the first power management sequence. In response to the power supply to the PCIe controller, media interface controller, and CPU cores other than the first CPU core being cut off, the first CPU core sends a control command to the power management unit instructing the first power switch to be turned off. In response to receiving the control command, the power management unit controls the first power switch to turn off. In response to the first power switch being turned off, the control unit enters a deep sleep state.

[0040] Optionally, when the control unit is in a deep sleep state, the PCIe physical layer module, in response to receiving a wake-up signal from an external source, provides the wake-up signal to the power management unit, the wake-up signal indicating that the control unit should exit the deep sleep state.

[0041] Optionally, in response to receiving the wake-up signal, the power management unit controls the first power switch and the second power switch corresponding to the first CPU to close, and the first CPU resumes power supply. In response to the first CPU core restoring power supply, the first CPU core sequentially sends a second power management command to the power management unit, instructing the restoration of power supply to the PCIe controller, the media interface controller, and CPU cores other than the first CPU core. In response to receiving a second power management command that sequentially instructs to restore power supply to the PCIe controller, the media interface controller, and the CPU cores other than the first CPU core, the power management unit sequentially starts the CPU power management sequence generation unit, the media interface controller power management sequence generation unit, the PCIe power management sequence generation unit, and the NVMe power management sequence generation unit to generate the second power management sequence. According to the generated second power management sequences, power supply to the PCIe controller, media interface controller, and CPU cores other than the first CPU core is restored in sequence, and the deep sleep state is exited.

[0042] Optionally, the control component further includes a clock generation circuit and multiple clock gating units; The clock generation circuit generates a clock signal; The input terminal of the clock gating unit is coupled to the output terminal of the clock generation circuit, and the output terminal of the clock gating unit is coupled to the circuit unit that receives the clock signal. The clock gating unit is also coupled to the power management unit. Under the control of the power management unit, the clock gating unit transmits the clock signal generated by the clock generation circuit to the circuit unit or cuts off the clock signal provided to the circuit unit.

[0043] Optionally, in response to receiving a fifth power management command instructing a circuit unit to enter a clock-gated state, the power management unit sends a fifth control signal to the clock-gated unit corresponding to the circuit unit to control the clock-gated unit to cut off the clock signal supplied to the circuit unit; or, In response to receiving a sixth power management command instructing the restoration of clock signal supply to the circuit unit, the power management unit sends a sixth control signal to the clock gating unit corresponding to the circuit unit. The sixth control signal controls the clock gating unit to restore the clock signal supplied to the circuit unit.

[0044] Optionally, the control unit further includes a first static random access memory (SRAM), which is coupled to the main power supply. There is no power switch on the power supply line between the first SRAM and the main power supply. The first SRAM stores the state data of the control unit before it enters a deep sleep state.

[0045] Optionally, an isolation unit is coupled to the signal input path of the first static random access memory; When the control component enters a deep sleep state, the power management unit controls the isolation unit to operate in an isolated state.

[0046] Optionally, the first static random access memory includes a power management port; The power management unit sends a power management signal to the first static random access memory through the power management port to instruct the first static random access memory to enter the corresponding power consumption state.

[0047] Optionally, the control unit further includes a second static random access memory, and a second power switch is provided on the power supply line of the second static random access memory.

[0048] Optionally, the control component further includes a flash memory controller, a second power switch is provided on the power supply line of the flash memory controller, and an isolation unit is provided on the signal input path of the flash memory controller; The power management unit also includes a flash controller power management sequence generation unit.

[0049] Optionally, the flash memory controller includes a flash memory physical layer module, which is powered by a third external power supply. A fifth power switch is connected to the line through which the third external power supply powers the flash memory physical layer module. The input terminal of the fifth power switch is coupled to the third external power supply, and the output terminal is coupled to the flash memory physical layer module. The fifth power switch is also coupled to the power management module. The power management unit controls the fifth power switch to open or close, so as to disconnect or restore the third external power supply to the flash physical layer module.

[0050] Optionally, the flash physical layer module is coupled with a flash memory chip; The flash memory chip is powered by a fourth external power supply. A sixth power switch is connected to the line on which the fourth external power supply powers the flash memory chip. The input terminal of the sixth power switch is coupled to the fourth external power supply, and the output terminal is coupled to the flash memory chip. The sixth power switch is also coupled to the power management module. The power management unit controls the sixth power switch to open or close, thereby disconnecting or restoring the power supply of the fourth external power source to the flash memory chip.

[0051] Optionally, the media interface controller is coupled to an NVM chip; the NVM chip is powered by a fifth external power supply, and a seventh power switch is connected to the circuit on which the fifth external power supply powers the NVM chip. The input terminal of the seventh power switch is coupled to the fifth external power supply, and the output terminal is coupled to the NVM chip. The seventh power switch is also coupled to the power management module. The power management unit controls the seventh power switch to open or close, thereby disconnecting or restoring the power supply from the fifth external power source to the NVM chip.

[0052] Optionally, a clock gating unit may be provided on the line where clock signals are received by each CPU core, NVMe protocol processor, media interface controller, and chip interconnect unit in the CPU core group.

[0053] Optionally, the specified power consumption state includes the PS0 power consumption state, PS1 power consumption state, PS2 power consumption state and / or PS3 power consumption state defined by the NVMe protocol; The PSO power consumption status indication indicates that each CPU core in the CPU core group, the PCIe controller, the PCIe physical layer module, the NVMe protocol processor, the media interface controller, the power management unit, and the NVM chip are all in normal working condition, and the inter-chip interconnection unit is in a power-off state. The PS1 power consumption status indicates that the first CPU core, the PCIe controller, the power management unit, and the NVM chip are all in normal working condition. Each CPU core in the CPU core group except the first CPU core, the NVMe protocol processor, and the media interface controller are in clock-gated state. The inter-chip interconnect unit is in power-off state. The operating frequency of the PCIe physical layer module is a specified frequency, which is less than the normal working frequency of the PCIe physical layer module. The PS2 power consumption status indication is as follows: each CPU core in the CPU core group is in clock-gated state, the PCIe controller and the power management unit are in normal working state, the PCIe physical layer module is in L1 state, and the NVMe protocol processor, the media interface controller, the chip interconnect unit and the NVM chip are all in power-off state. The PS3 power consumption status indicates that the power management unit is in normal working condition, each CPU core in the CPU core group, the PCIe controller, the NVMe protocol processor, the media interface controller, and the NVM chip are all in a power-off state, and the PCIe physical layer module is in L1.2 state.

[0054] Optionally, the power management sequence generation unit includes a state machine; The state machine sequentially includes a waiting state, a clock gating enabled state, an isolation unit enabled state, a reset enabled state, a power switch disabled state, a power switch disabled state, a reset canceled state, an isolation unit restored state, and a clock gating restored state. The waiting state indicates that no power consumption control is applied to the multiple circuit units within the control component, and the control component is operating normally. The clock gating enabled state represents applying clock gating to the circuit unit to cut off the clock signal supplied to the circuit unit; The isolation enabled state means that the isolation unit corresponding to the circuit unit is in the isolation state. The reset enabled state means that a continuous reset signal is applied to the circuit unit, causing it to continuously reset or remain in the initialized state; The power switch being off indicates that the second power switch corresponding to the circuit unit is disconnected. The closed state of the power switch represents the second power switch corresponding to the closed circuit unit; The reset cancellation state indicates that the reset signal applied to the circuit unit has been cancelled; The isolation recovery state means that the isolation unit corresponding to the circuit unit is put into normal operation.

[0055] Optionally, the power consumption levels represented by the waiting state, the clock gating on state, the isolation unit on state, the reset on state, and the power switch off state decrease sequentially. The power consumption levels represented by the power switch closed state, the reset undo state, the isolation unit restored state, and the clock gating restored state increase sequentially.

[0056] Optionally, the power management sequence generation unit further includes a configuration register, which stores configuration information; The power management sequence generation unit determines the power consumption states that are used and the power consumption states that are disabled based on the configuration information of the configuration register. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings.

[0058] Figure 1A A block diagram of a solid-state storage device is shown. Figure 1B A block diagram of the control components in a solid-state storage device is shown; Figure 2 A schematic diagram of the structure of the control component provided in an embodiment of the present invention is shown; Figure 3 A schematic diagram of the power management unit is shown. Figure 4 A schematic diagram of the power management sequence generated by the power management unit in an embodiment of the present invention is shown; Figure 5 This invention illustrates a flowchart of power management for an NVMe protocol processor in an embodiment of the present invention. Figure 6 A flowchart illustrating the process of enabling the NVMe protocol processor according to an embodiment of this utility model is shown; Figure 7 This invention illustrates a flowchart of a process in which CPU core 0 controls the entire control unit to enter a deep sleep state according to an embodiment of the present invention. Figure 8 A flowchart illustrating the control component for waking up the host from a deep sleep state according to an embodiment of the present invention is shown. Figure 9 A schematic diagram of the structure of the control component according to another embodiment of the present invention is shown; Figure 10 A schematic diagram of the structure of the control component according to another embodiment of the present invention is shown; Figure 11 This invention illustrates a flowchart of a process in which CPU core 0 controls the entire control unit to enter a deep sleep state according to an embodiment of the present invention. Figure 12 A flowchart illustrating the control component for waking up the host from a deep sleep state according to an embodiment of the present invention is shown. Figure 13 A schematic diagram of a state machine for implementing a power management sequence generation unit according to an embodiment of the present invention is shown; Figure 14 The state machine corresponding to the power management sequence generation unit for the chip interconnect unit is shown. Detailed Implementation

[0059] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0060] Figure 2 A schematic diagram of the structure of the control component provided in an embodiment of this utility model is shown. Figure 2 As shown, the control components include a power management unit (Power Management Unit, Figure 2 (represented as PMU in Chinese) and multiple circuit units, such as a CPU core group comprising multiple CPU cores (e.g., CPU core 0, CPU core 1, CPU core 2, and CPU core 3), and a PCIe controller (the PCIe controller includes a physical layer module, in...) Figure 2 The components are represented as PCIe PHY, NVMe protocol processor, and media interface controller (the media interface controller includes a LUN controller, which in turn includes a physical layer module). Figure 2 The term "ONFI PHY" is used to represent the inter-chip interconnect unit (which also includes a physical layer module). Figure 2 This is represented by the interconnect PHY, multiple power switches (e.g., SW0, SW1, SW10, SW11, SW12, SW13, SW2, SW3, SW4, SW5), and multiple isolation units (e.g., ISO1, ISO2, ISO3, ISO4, ISO5, ISO6, ISO7, ISO8, ISO9, ISO10). Optionally, if the storage device includes a control unit, the control unit may not include the inter-chip interconnect units. Figure 2In this diagram, VDD supplies power to each circuit unit in the control component, serving as the main power supply for the control component. The VDD power supply lines to each circuit unit in the control component are represented by solid red lines. The connection lines between the power management unit and each power switch are represented by solid blue lines. The power management unit sends control signals to each power switch through these connection lines. The power management unit can also couple to the PCIe PHY in the PCIe controller, and to the CPU core group and / or the CPU cores within the CPU core group, through connection lines. The connection lines between the power management unit and the PCIe PHY / CPU core group are represented by dashed green lines; arrows on these dashed green lines indicate signals sent from the PCIe PHY to the power management unit, or from the CPU core group or a specific CPU core to the power management unit. Input or output signals of the isolation unit are represented by solid purple lines with arrows, where the arrows indicate the direction of signal transmission (from output to input).

[0061] The power management unit is coupled to various power switches in the control unit, such as SW0, SW1, SW10, SW11, SW12, SW13, SW2, SW3, SW4, and SW5, to control the opening and closing of each power switch, thereby controlling whether power is supplied to each circuit unit. For example, the power management unit receives control commands from the CPU core (e.g., CPU core 0) to control the opening and closing of each power switch, thereby controlling whether power is supplied to each circuit unit. Alternatively, the power management unit can also receive control commands from the CPU core to instruct it to cut off power to the CPU core itself.

[0062] For example, the power supply ports of the PCIe PHY and power management unit are directly connected to the main power supply VDD. There are no power switches on the power supply lines corresponding to the PCIe PHY and the power management unit. For example, there is no power switch on the power supply line from the main power supply VDD to the PCIe PHY, and there is also no power switch on the power supply line from the main power supply VDD to the power management unit. The PCIe PHY and the power management unit are directly powered by the main power supply VDD. Disconnecting any power switches in the control unit will not affect the main power supply VDD to the PCIe PHY and the power management unit.

[0063] Optionally, the power management unit (Power Management Unit) also receives signals from the PCIe PHY in response to restore power to a group of CPU cores or a specific CPU core. For example, when the control unit is in sleep mode, only the Power Management Unit and the PCIe PHY are active. The PCIe PHY provides a signal to the Power Management Unit to wake up CPU core 0 in response to a wake-up signal from an external source (e.g., the host). The Power Management Unit restores power to CPU core 0 and, based on the target power consumption state, sends control commands to the Power Management Unit to wake up the required circuitry.

[0064] Each power switch is independently opened or closed under the control of the power management unit to control whether power is supplied to the circuit unit corresponding to the power switch. For example, the input terminal of power switch SW0 is coupled to the main power supply VDD, and the output terminal of power switch SW0 is coupled to the input terminals of each circuit unit within the control unit that requires power management. For example, the output terminal of power switch SW0 is coupled to the power supply ports of the PCIe controller, NVMe protocol processor, media interface controller, inter-chip interconnect unit, CPU core group, and each CPU core within the CPU core group within the control unit. When power switch SW0 is opened, the PCIe controller, NVMe protocol processor, media interface controller, inter-chip interconnect unit, CPU core group, and each CPU core within the CPU core group within the control unit are all powered down.

[0065] A separate power switch can be installed on the power supply line of the control components for each circuit unit, so that the power supply to each circuit unit can be controlled independently. For example, power switches SW1, SW2, SW3, SW4, and SW5 can be installed.

[0066] For example, power switch SW1 is installed on the line between the output of power switch SW0 and the power supply port of the CPU core group to control the power supply to the entire CPU core group. When power switch SW0 is closed, the power management unit controls power switch SW1 to close, and the entire CPU core group is powered; when the power management unit controls power switch SW1 to open, the entire CPU core group is powered off. Alternatively, the power supply to each CPU core in the CPU core group can be controlled independently. For example, power switches SW10, SW11, SW12, and SW13 can be installed on the line between the output of power switch SW1 and the power supply port of each CPU core. Power switch SW10 is installed on the circuit supplying power to CPU core 0 to control the power supply to CPU core 0. The input of power switch SW10 is coupled to the output of power switch SW1, and the output of power switch SW10 is coupled to the power supply port of CPU core 0. Power switch SW11 is installed on the circuit supplying power to CPU core 1 to control the power supply to CPU core 1. The input terminal of power switch SW11 is coupled to the output terminal of power switch SW1, and the output terminal of power switch SW11 is coupled to the power supply port of CPU core 1. Power switch SW12 is installed in the circuit that supplies power to CPU core 2 to control the power supply to CPU core 2. The input terminal of power switch SW12 is coupled to the output terminal of power switch SW1, and the output terminal of power switch SW12 is coupled to the power supply port of CPU core 2. Power switch SW13 is installed in the circuit that supplies power to CPU core 3 to control the power supply to CPU core 3. The input terminal of power switch SW13 is coupled to the output terminal of power switch SW1, and the output terminal of power switch SW13 is coupled to the power supply port of CPU core 3. When both power switches SW0 and SW1 are closed, the power supply to each CPU core can be controlled individually through SW10, SW11, SW12, and SW13. For example, when SW10 is closed, CPU core 0 is powered; when SW10 is open, CPU core 0 is powered off; when SW11 is closed, CPU core 1 is powered; when SW11 is open, CPU core 1 is powered off; when SW12 is closed, CPU core 2 is powered; when SW12 is open, CPU core 2 is powered off; when SW13 is closed, CPU core 3 is powered; when SW13 is open, CPU core 3 is powered off.

[0067] Power switch SW2 is connected to the circuit supplying power to the PCIe controller to control whether power is supplied to the PCIe controller. The input of power switch SW2 is coupled to the output of power switch SW0, and the output of power switch SW2 is coupled to the power supply port of the PCIe controller. For example, when power switch SW0 is closed, the power management unit controls power switch SW2 to close, supplying power to the PCIe controller; when the power management unit controls power switch SW2 to open, the PCIe controller is powered off. Power switch SW3 is connected to the circuit supplying power to the NVMe protocol processor to control whether power is supplied to the NVMe protocol processor. The input of power switch SW3 is coupled to the output of power switch SW0, and the output of power switch SW3 is coupled to the power supply port of the NVMe protocol processor. For example, when power switch SW0 is closed, the power management unit controls power switch SW3 to close, supplying power to the NVMe protocol processor; when the power management unit controls power switch SW3 to open, the NVMe protocol processor is powered off. Power switch SW4 is connected to the circuit supplying power to the media interface controller to control whether power is supplied to the media interface controller. The input terminal of power switch SW4 is coupled to the output terminal of power switch SW0, and the output terminal of power switch SW4 is coupled to the power supply port of the media interface controller. For example, when power switch SW0 is closed, the power management unit controls power switch SW4 to close, supplying power to the media interface controller; when the power management unit controls power switch SW4 to open, the media interface controller is de-energized. Power switch SW5 is connected to the circuit that supplies power to the inter-chip interconnect unit to control whether power is supplied to the inter-chip interconnect unit. The input terminal of power switch SW5 is coupled to the output terminal of power switch SW0, and the output terminal of power switch SW5 is coupled to the power supply port of the inter-chip interconnect unit. For example, when power switch SW0 is closed, the power management unit controls power switch SW5 to close, supplying power to the inter-chip interconnect unit; when the power management unit controls power switch SW5 to open, the inter-chip interconnect unit is de-energized.

[0068] Since the PCIe PHY is directly powered by the main power supply VDD, the disconnection of power switches SW0 and SW2 will not affect the power supply of the main power supply VDD to the PCIe PHY. This allows the PCIe PHY to continue working even when the PCIe controller is powered off, in order to listen for and respond to wake-up signals.

[0069] The internal circuit units of the control unit are divided into two categories: circuit units not controlled by the power management unit (referred to as AON type), and circuit units controlled by the power management unit (i.e., circuit units requiring power management, referred to as non-AON type). For example, circuit units not controlled by the power management unit include the power management unit and the PCIe PHY, whose power supply ports are connected between the main power supply VDD and the input terminal of the power switch SW0, so that the power management unit and the PCIe PHY can be directly powered from the main power supply VDD regardless of whether SW0 is on or off. Circuit units controlled by the power management unit include the CPU core group and each CPU core, the PCIe controller, the NVMe protocol processor, the media interface controller, and the chip interconnect unit, whose power supply ports are connected to their respective power switches and are powered on or off under the control of the power management unit.

[0070] The PCIe PHY also receives power from external power supply V1, and the ONFI PHY also receives power from external power supply V2. Power switch SW6 is located on the circuit where external power supply V1 powers the PCIe PHY. The input of power switch SW6 is coupled to external power supply V1, and the output of power switch SW6 is coupled to the power supply port of the PCIe PHY. Power switch SW6 is also coupled to the power management unit (Power Management Unit) and is used to open or close under the control of the Power Management Unit to control whether power is supplied to the PCIe PHY through external power supply V1. SW7 is located on the circuit where external power supply V2 powers the ONFI PHY. The input of power switch SW7 is coupled to external power supply V2, and the output of power switch SW7 is coupled to the power supply port of the ONFI PHY. Power switch SW7 is coupled to the Power Management Unit (Power Management Unit) and is used to open or close under the control of the Power Management Unit to control whether power is supplied to the ONFI PHY through external power supply V2. Optionally, the Power Management Unit provides control signals to power switches SW6 and SW7 through the GPIO pins of the control component. SW6 and SW7 are located outside the control components and are not part of the control components. They are implemented by discrete components, such as those on a PCB board.

[0071] In an optional embodiment, the interconnect PHY is powered by an external power supply V3, but no power switch is used to control the power supply of power supply V3 to the interconnect PHY. The power management unit controls the power supply to the inter-chip interconnect unit via a single power switch SW5. For example, the storage device includes either a single control unit or multiple control units. With a single control unit, operation is achieved through that single control unit. With multiple control units, inter-chip interconnect units are used to enable the multiple control units to work collaboratively. When operating with a single control unit, no interconnect PHY is connected to the corresponding circuit board of the storage device, and no power is supplied to the interconnect PHY. In this case, the power management unit can prevent the inter-chip interconnect unit from consuming power by disconnecting SW6. Therefore, there is no need to control the connection between power supply V3 and the interconnect PHY. When multiple control units work collaboratively, the circuit board provides power supply V3 to power the interconnect PHY of each control unit. Although the host wakes up the control unit via the PCIe PHY, control units not directly connected to the host via the PCIe PHY need to be woken up via the interconnect PHY, thus requiring the circuit board to provide continuous power to the interconnect PHY of each control unit. Therefore, there is no need to control the connection between power supply V3 and interconnect PHY (power supply V3 is always connected to interconnect PHY).

[0072] In this embodiment of the invention, the power management unit controls whether to supply power to the corresponding circuit unit by independently controlling the opening and closing of each power switch. It can be understood that disconnecting the power supply to one or more circuit units reduces the power consumption of the control components.

[0073] As another example, isolation units can be added to the signal paths of each circuit unit. For instance, if an isolation unit is added to the signal path between circuit unit A and circuit unit B, when circuit unit A outputs a signal to circuit unit B, the output of circuit unit A is provided to the isolation unit, and the isolation unit provides the input signal to circuit unit B. The isolation unit has two operating states, referred to as the normal operating state and the isolation state. In the normal operating state, the signal provided by the circuit unit to the isolation unit is directly output. In the isolation state, the signal provided by the circuit unit to the isolation unit is blocked, and the isolation unit replaces the circuit unit in generating an output signal with a specified value. For example, if the power supply to circuit unit A is cut off, the output signal of circuit unit A will not have a definite state. The isolation unit set in the signal path between circuit unit A and circuit unit B will replace circuit unit A in generating an output signal with a specified value and provide the generated output signal with the specified value to circuit unit B, thus enabling the receiver (circuit unit B) to still receive a definite signal (such as a signal with a specified value).

[0074] like Figure 2As shown, isolation units are installed on the signal output path and / or signal input path of the circuit units within the control component. The isolation units operate in either normal operation or isolation mode according to the control signals from the power management unit. For example, when the power management unit disconnects the power switch corresponding to circuit unit A, it controls the isolation unit installed on the signal output path of circuit unit A to operate in isolation mode, isolating the output signal of that circuit unit. When the power management unit closes the power switch corresponding to circuit unit A, it controls the isolation unit installed on the signal output path of circuit unit A to operate in normal operation mode, directly outputting the output signal of circuit unit A. As another example, if the signal input to circuit unit B is uncertain under certain circumstances (for example, circuit unit B receives the output signal of circuit unit C, and the power management unit disconnects the power switch corresponding to circuit unit C, causing the output signal of circuit unit C to be uncertain), the power management unit controls the isolation unit installed on the signal input path of circuit unit B to operate in isolation mode, allowing circuit unit B to receive a definite signal. If the signal input to circuit unit B is a definite signal, the power management unit controls the isolation unit installed on the signal input path of circuit unit B to operate in normal operation mode, directly providing the signal input to the isolation unit to circuit unit B. For example, isolation units ISO1, ISO2, ISO3, and ISO4 are respectively configured on the signal output paths of CPU core 0, CPU core 1, CPU core 2, and CPU core 3. Isolation unit ISO5 is configured on the signal output path of the CPU core group, and isolation unit ISO6 is configured on the signal input path of the CPU core group. Isolation unit ISO7 is configured on the signal input path of the PCIe PHY. Isolation unit ISO8 is configured on the signal output path of the NVMe protocol processor. Isolation unit ISO9 is configured on the signal output path of the media interface controller. Isolation unit ISO10 is configured on the signal output path of the inter-chip interconnect unit. When the power management unit disconnects the power switch corresponding to CPU core 0 (e.g., disconnects SW10) and does not supply power to CPU core 0, it controls isolation unit ISO1 to operate in isolation mode, thus isolating the output signals of CPU core 0. When the power management unit closes the power switch corresponding to CPU core 0 and supplies power to CPU core 0, it controls isolation unit ISO1 to operate in normal operating mode, thus directly outputting the output signals of CPU core 0. When the power management unit disconnects the power switch corresponding to CPU core 1 (e.g., disconnects SW11) and does not supply power to CPU core 1, it controls the isolation unit ISO2 to operate in isolation mode, thus isolating the output signals of CPU core 1. When the power management unit closes the power switch corresponding to CPU core 1 and supplies power to CPU core 1, it controls the isolation unit ISO2 to operate in normal operating mode, thus allowing the isolation unit ISO2 to directly output the output signals of CPU core 1.When the power management unit disconnects the power switch corresponding to CPU core 2 (e.g., disconnects SW12) and does not supply power to CPU core 2, it controls isolation unit ISO3 to operate in isolation mode, thus isolating the output signal of CPU core 2. When the power management unit closes the power switch corresponding to CPU core 2 and supplies power to CPU core 2, it controls isolation unit ISO3 to operate in normal operating mode, thus directly outputting the output signal of CPU core 2. When the power management unit disconnects the power switch corresponding to CPU core 3 (e.g., disconnects SW13) and does not supply power to CPU core 3, it controls isolation unit ISO4 to operate in isolation mode, thus isolating the output signal of CPU core 3. When the power management unit closes the power switch corresponding to CPU core 3 and supplies power to CPU core 3, it controls isolation unit ISO4 to operate in normal operating mode, thus directly outputting the output signal of CPU core 3. When the power management unit disconnects the power switch corresponding to the CPU core group (e.g., disconnects SW1) and does not supply power to the CPU core group, it controls isolation unit ISO5 to operate in isolation mode, thus isolating the output signal of the CPU core group. When the power management unit (Power Management Unit) closes the power switch corresponding to the CPU core group to supply power, it controls isolation unit ISO5 to operate in normal working mode, allowing ISO5 to directly output the CPU core group's output signal. If the signal input to the CPU core group is uncertain, the Power Management Unit controls isolation unit ISO6 to operate in isolation mode, allowing the CPU core group to receive a definite signal. If the signal input to the CPU core group is definite, the Power Management Unit controls isolation unit ISO6 to operate in normal working mode, and the signal input to isolation unit ISO8 is directly provided to the CPU core group. If the signal input to the PCIe PHY is uncertain, the Power Management Unit controls isolation unit ISO7 to operate in isolation mode, allowing the PCIe PHY to receive a definite signal. If the signal input to the PCIe PHY is definite, the Power Management Unit controls isolation unit ISO7 to operate in normal working mode, and the signal input to isolation unit ISO7 is directly provided to the PCIe PHY. When the power management unit disconnects the power switch SW3 corresponding to the NVMe protocol processor, it controls isolation unit ISO8 to operate in isolation mode, isolating the NVMe protocol processor's output signal. When the power management unit closes the power switch corresponding to the NVMe protocol processor to supply power, it controls the isolation unit ISO8 to operate in normal working state, allowing ISO8 to directly output the output signal of the NVMe protocol processor. When the power management unit disconnects the power switch corresponding to the media interface controller (e.g., disconnects SW4) to stop supplying power to the media interface controller, it controls the isolation unit ISO9 to operate in isolation state, allowing ISO9 to isolate the output signal of the media interface controller.When the power management unit closes the power switch corresponding to the media interface controller to supply power to the media interface controller, it controls the isolation unit ISO9 to operate in normal working state, allowing ISO9 to directly output the output signal of the media interface controller. When the power management unit disconnects the power switch corresponding to the inter-chip interconnect unit (e.g., disconnects SW5) to stop supplying power to the inter-chip interconnect unit, it controls the isolation unit ISO10 to operate in isolation state, isolating the output signal of the inter-chip interconnect unit. When the power management unit closes the power switch SW5 corresponding to the inter-chip interconnect unit, it controls the isolation unit ISO10 to operate in normal working state, allowing ISO10 to directly output the output signal of the inter-chip interconnect unit.

[0075] Optionally, isolation units can be configured as needed, without requiring an isolation unit between every pair of output and input signals. For example, if signal transmission is required between circuit unit A and circuit unit B, an isolation unit can be placed on the signal transmission path between circuit unit A and circuit unit B. However, if circuit unit A and circuit unit B are always powered on and off simultaneously, no isolation unit is needed between these two circuit units. For example, if a CPU core group both outputs signals to and receives signals from other circuit units, different isolation units can be configured for different signal transmission directions, such as setting isolation unit ISO5 on the output signal path of the CPU core group and isolation unit ISO6 on the input signal path of the CPU core group.

[0076] Optionally, the power management unit is coupled to each isolation unit and independently controls the operating state of each isolation unit.

[0077] Optionally, based on the number of power ports of the isolation unit, the isolation units can be divided into AON type isolation units and non-AON type isolation units.

[0078] The AON type isolation unit has two power ports, one of which is connected between the main power supply VDD and the input of the power switch SW0. This ensures that the AON type isolation unit is not powered down due to the power management unit's power consumption control. For example, in a scenario where circuit unit A outputs a signal to circuit unit B, if the power management unit manages the power supply to circuit unit A, while circuit unit B is not controlled by the power management unit, such as when the power supply to circuit unit A is cut off but circuit unit B continues to operate, an AON type isolation unit is placed on the signal path from circuit unit A to circuit unit B. For example, if the power supply to circuit unit A is cut off, the AON type isolation unit will generate an output signal with a specified value on behalf of circuit unit A and provide this output signal to circuit unit B, enabling circuit unit B to operate. Alternatively, the specified value may be a value that circuit unit A currently does not output, preventing unit B from responding to this specified value and generating unnecessary behavior. Optionally, each isolation unit (e.g., ISO1-ISO10) may be directly powered by the main power supply VDD and not controlled by the power management unit.

[0079] Non-AON type isolation units have a single power port that is not connected between the main power supply VDD and the input of SW0. The power management unit can cut off power supply to non-AON type isolation units.

[0080] In certain power consumption states, the power supply to both circuit units connected to a non-AON type isolation unit is cut off. In this case, the power supply to the non-AON type isolation unit can also be cut off to further reduce power consumption. For example, ISO6 and ISO7 are non-AON type isolation units.

[0081] For example, the power management unit receives control commands from the CPU core to instruct the power management unit to cut off power to non-AON type isolation units.

[0082] In an optional embodiment, the power management unit includes multiple sequence generation units, each corresponding to a circuit unit in the control component that requires power management, for performing power control on the corresponding circuit unit. For example, the sequence generation unit performs power control on the circuit unit by generating a power management sequence. As another example, the power management sequence includes a power management sequence for cutting off power to the circuit unit and a power management sequence for restoring power to the circuit unit.

[0083] Figure 3 A schematic diagram of the power management unit is shown.

[0084] like Figure 3As shown, the power management unit includes an NVMe power management sequence generation unit, a media interface controller power management sequence generation unit, a CPU power management sequence generation unit, and a PCIe power management sequence generation unit. The NVMe power management sequence generation unit generates power management sequences for power control of the NVMe protocol processor; the media interface controller power management sequence generation unit generates power management sequences for power control of the media interface controller; the CPU power management sequence generation unit generates power management sequences for power control of the CPU core; and the PCIe power management sequence generation unit generates power management sequences for power control of the PCIe controller. For example, the sequence generation units use the generated power management sequences to control the power switch and isolation unit, thereby achieving power control of the circuit unit.

[0085] Optionally, the power management sequence for cutting off the power supply to the circuit unit includes, for example, generating a control signal to disconnect the power switch on the power supply line to the circuit unit when the power supply to the circuit unit is cut off, and generating a control signal to turn on the isolation unit connected to the circuit unit, so that the isolation unit operates in an isolated state. The power management sequence for restoring the power supply to the circuit unit includes, for example, generating a control signal to close the power switch on the power supply line to the circuit unit when the power supply to the circuit unit is restored, and generating a control signal to turn off the isolation unit connected to the circuit unit, so that the isolation unit operates in a normal operating state. Optionally, the power management sequence, in addition to providing control signals to the power switch and the isolation unit, also includes the interval and duration of the control signals. For example, for a certain circuit unit, when the power supply to the circuit unit is cut off, the control signal to control the power switch needs to be generated 100µs after the control signal to control the isolation unit is generated, to ensure that the isolation unit completes its operation. Still optionally, the control signals provided by the power management sequence are continuous. For example, when a control signal for the control isolation unit is generated, and then a control signal for the control power switch is generated, the control signal for the control isolation unit remains unchanged, and the control signal for the control power switch also remains unchanged after it is generated, until the power management unit generates a power management sequence to restore power supply.

[0086] Optionally, the power management sequence for cutting off power to a circuit unit and the power management sequence for restoring power to a circuit unit are logically inverses. This is not mandatory, but depends on the specific operating mode of the circuit unit being operated on.

[0087] Optionally, the power management sequences generated by each sequence generation unit of the power management unit can be the same or different to meet the needs of the controlled circuit unit. Each sequence generation unit is implemented by, for example, a state machine or a sequence generator, and can be configured to generate the desired sequence.

[0088] To facilitate understanding, the process of the power management unit generating a power management sequence will be explained using an NVMe protocol processor as an example.

[0089] Figure 4 The illustration shows a schematic diagram of how the NVMe power management sequence generation unit generates a power management sequence for cutting off power supply and a power management sequence for restoring power supply according to an embodiment of the present invention.

[0090] like Figure 4 As shown, before time T1, the NVMe protocol processor is powered. The power management unit controls the power switch SW3 corresponding to the NVMe protocol processor to close and the isolation unit ISO8 set on the signal output path of the NVMe protocol processor to be in normal working condition, so that the NVMe protocol processor is powered normally. At time T1, power management is implemented for the NVMe protocol processor. The power management unit (e.g., the NVMe power management sequence generation unit) needs to generate a power management sequence for cutting off power supply; that is, the power management sequence generation unit needs to generate a control signal to open the power switch and a control signal to control the isolation unit to operate in isolation state. At time T3, power supply to the NVMe protocol processor needs to be restored. The power management unit needs to generate a power management sequence for restoring power supply; that is, the NVMe power management sequence generation unit needs to generate a control signal to open the power switch and a signal to control the isolation unit to operate in normal working state. Figure 4 As shown, before time T1, the NVMe power management sequence generation unit generates a control signal to close the power switch SW3 and a control signal to enable the isolation unit ISO8 to operate in normal working state. At time T1, the power management unit needs a certain amount of time from receiving the instruction to disconnect the NVMe protocol processor to generating the control signal. Therefore, at time T1, the power management unit does not immediately generate the control signal to enable the isolation unit ISO to operate in isolated state. Instead, after waiting for a period of time, the NVMe power management sequence generation unit generates the control signal to enable the isolation unit ISO to operate in isolated state, and after a delay of, for example, 100µs, generates the control signal to open the power switch SW3 at time T2. At time T3, the power management unit needs a certain amount of time from receiving the instruction to restore the NVMe protocol processor to generating the control signal. Therefore, at time T3, the power management unit does not immediately generate the control signal to close the power switch SW3. Instead, after a certain period of time, the NVMe power management sequence generation unit generates the control signal to close the power switch SW3, and after a delay of a period of time, generates the control signal to enable the isolation unit ISO8 to operate in normal working state at time T4.

[0091] It should be noted that, in Figure 4In the diagram, the curve corresponding to the isolation unit represents the control signal generated by the NVMe power management sequence generation unit to control ISO8, and the curve corresponding to the power switch represents the control signal generated by the NVMe power management sequence generation unit to control the power switch SW3 to close or open.

[0092] The following example illustrates the process of power management for the control unit, using the example of CPU core 0 sending control commands to instruct the power management unit to control the power consumption of the circuit units in the control component.

[0093] For example, when managing power consumption of the control unit, CPU0 can instruct the power management unit to turn off one or more circuit units in the control unit or turn on one or more circuit units. CPU core 0 instructs the power management unit to shut down a circuit unit in the control unit. For example, as Figure 2 The control unit shown is currently in normal working condition, and all circuit units are functioning correctly. Due to the prolonged absence of I / O commands, CPU core 0 needs to disable the NVMe protocol processor to reduce the power consumption of the control unit. Figure 5 A flowchart illustrating power management for an NVMe protocol processor in an embodiment of this utility model is shown. Figure 5 As shown, the process includes: Step S501: CPU core 0 sends control command 1 to the power management unit, instructing to shut down the NVMe protocol processor.

[0094] Step S502: The power management unit receives control command 1. In response to recognizing that control command 1 instructs the NVMe protocol processor to be shut down, the NVMe power management sequence generation unit starts to generate a power management sequence for cutting off power supply. This power management sequence for cutting off power supply is, for example... Figure 4 The diagram shows the control isolation unit ISO8 (see...) Figure 2 The control signals operating in isolation and the control power switch SW3 (see...) Figure 2 The control signal is disconnected.

[0095] Step S503: The NVMe power management sequence generation unit sends control signals to the isolation unit and power switch corresponding to the NVMe protocol processor based on the generated power management sequence for cutting off power supply. For example, it sends a control signal to the isolation unit ISO8 based on the power management sequence for cutting off power supply, so that the isolation unit ISO8 switches from the normal operation state to the isolation state; and it sends a control signal to the power switch SW3 based on the power management sequence for cutting off power supply, so that the power switch SW3 changes from closed to open. When the isolation unit ISO8 operates in the isolation state under the control of the NVMe power management sequence generation unit, the power switch SW3 is opened under the control of the NVMe power management sequence generation unit. At this point, the NVMe protocol processor is shut down, and the control unit enters a low-power state.

[0096] For example, if the PCIe controller indicates that a new I / O command has been received, CPU core 0 needs to enable the NVMe protocol processor to handle the I / O command. Figure 6 A flowchart illustrating the activation of the NVMe protocol processor according to an embodiment of this utility model is shown. Figure 6 As shown, the process includes: Step S601: CPU core 0 sends control command 2 to the power management unit, instructing to enable the NVMe protocol processor.

[0097] Step S602: The power management unit receives control command 2. In response to recognizing that control command 2 instructs the NVMe protocol processor to be enabled, it starts the NVMe power management sequence generation unit to generate a power management sequence for power restoration. This power management sequence for power restoration includes controlling the power switch SW3 (see reference). Figure 2 The control signal for closing the control isolation unit ISO8 (as shown in the embodiment) and the control isolation unit ISO8 (reference) Figure 2 The control signal shown in the embodiment operates in the normal working state.

[0098] Step S603: The NVMe power management sequence generation unit sends control signals to the isolation unit and power switch corresponding to the NVMe protocol processor based on the power management sequence for power restoration. For example, it sends a control signal to the isolation unit ISO8 based on the power management sequence for power restoration to switch the isolation unit ISO8 from the isolation state to the normal operation state; and it sends a control signal to the control power switch SW3 based on the power management sequence for power restoration to change the power switch SW3 from open to closed.

[0099] When power switch SW3 is closed under the control of the NVMe power management sequence generation unit, isolation unit ISO8 operates in normal working condition under the control of the NVMe power management sequence generation unit. At this point, the NVMe protocol processor is powered on, and the control components are currently in normal working condition.

[0100] CPU0 instructs the power management unit to shut down multiple circuit units in the control unit. For example, CPU0 instructs the power management unit to shut down multiple circuit units in the control unit, causing the control unit to enter a deep sleep state. Deep sleep state refers to the operating state of the control unit with the lowest power consumption, where only AON-type circuit units are powered on (e.g., the power management unit and PCIe PHY), and power to other circuit units is cut off. For example, the PCIe controller, NVMe protocol processor, media interface controller, and CPU core group are all powered off.

[0101] Figure 7 This diagram illustrates a flowchart of an embodiment of the present invention showing how CPU core 0 controls the entire control unit to enter a deep sleep state. (See attached flowchart.) Figure 7 As shown, the process includes: Step S701: CPU core 0 sends a control command to the power management unit, instructing it to shut down the NVMe protocol processor.

[0102] Step S702: In response to recognizing a control command instructing the NVMe protocol processor to shut down, the power management unit initiates the NVMe power management sequence generation unit to generate a power management sequence for cutting off power supply, thereby shutting down the NVMe protocol processor. The process by which the NVMe power management sequence generation unit generates the power management sequence for cutting off power supply to shut down the NVMe protocol processor is described below. Figure 5 This will not be elaborated upon here.

[0103] Step S703: In response to the NVMe protocol processor being shut down, CPU core 0 sequentially sends control commands to the power management unit to instruct the PCIe controller, media interface controller, and CPU cores 1-3 to be shut down.

[0104] Step S704: In response to the identified control command indicating the shutdown of the PCIe controller, the media interface controller, and CPU cores 1-3, the power management unit sequentially activates the PCIe power management sequence generation unit, the media interface controller power management sequence generation unit, and the CPU power management sequence generation unit to generate a power management sequence for cutting off power supply, thereby shutting down the PCIe controller, the media interface controller, and CPU cores 1-3. The process of shutting down the PCIe controller, the media interface controller, and CPU cores 1-3 is similar to the process of shutting down the NVMe protocol processor, and will not be described further here.

[0105] Step S705: CPU core 0 sends a control command to the power management unit, instructing to turn off the power switch SW0 to shut down all turn-off circuit units (including CPU core 0 itself).

[0106] Step S706: The power management unit sends a control signal to the power switch SW0 to turn off the power switch SW0. At this point, the PCIe controller, NVMe protocol processor, media interface controller, and CPU core group are all disconnected from power, and only the power management unit and PCIe PHY are powered.

[0107] Figure 8 A flowchart illustrating a host waking up a control component in deep sleep mode according to an embodiment of this invention is shown. In the control component in deep sleep mode, only AON-type circuit units (e.g., power management unit and PCIe PHY) are active. Figure 8 As shown, the process includes: Step S801: In response to receiving a wake-up signal sent by the host through the PCIe link, the PCIe PHY transmits a wake-up signal to the power management unit.

[0108] Step S802: In response to receiving the wake-up signal, the power management unit sends a control signal to the power switch SW0 to close the power switch SW0 and restore power supply to the CPU core 0.

[0109] Step S803: In response to recognizing that the host wants to wake up the control unit, CPU core 0 sends control commands to the power management unit in sequence to instruct CPU cores 1-3, PCIe controller, NVMe protocol processor and media interface controller to be turned on.

[0110] Step S804: In response to the received control command indicating that CPU cores 1-3, the PCIe controller, the NVMe protocol processor, and the media interface controller are to be enabled, the power management unit sequentially starts the CPU power management sequence generation unit, the media interface controller power management sequence generation unit, the PCIe power management sequence generation unit, and the NVMe power management sequence generation unit to generate a power management sequence for restoring power supply, thereby enabling CPU cores 1-3, the media interface controller, the PCIe controller, and the NVMe protocol processor. The process of enabling CPU cores 1-3, the PCIe controller, the NVMe protocol processor, and the media interface controller is similar to... Figure 6 Similarly, I will not go into details here.

[0111] Optionally, this embodiment of the invention defines multiple power consumption states (e.g., PS0-PS2) for the control component. This facilitates correspondence with power consumption states defined by industry standards such as NVMe or PCIe, and also allows users to perceive, estimate, and manage the power consumption level of the control component. Table 1 shows the operating state of each circuit unit of the control component under each power consumption state. The CPU core 0 and the power management unit can... Figures 5-8The processes shown work together to ensure the control unit operates in the desired state. Optionally, the host can instruct the control unit to switch to a specific power consumption state via management commands or custom commands. For example, the host may want the control unit to enter PS2 state. In response, CPU core 0 and the power management unit work together to execute actions such as... Figure 8 The process shown will shut down multiple circuit units, causing the control unit to be in the PS2 state.

[0112] Table 1:

[0113] In one implementation, each row of Table 1 represents a circuit unit as a power domain, and circuit units in different rows are designated as different power domains. The power management unit provides a corresponding power management sequence generation unit for each power domain, used to generate a power management sequence for that power domain. Optionally, each row of Table 1 may further include multiple power domains. A power domain refers to a circuit area in an integrated circuit that is powered by the same power supply. These areas are physically or logically separated so that the switching of the power supply, voltage levels, etc., can be controlled independently.

[0114] In an optional embodiment, the power management unit also manages the power consumption of the circuit unit using clock gating technology. Specifically, the power management unit controls whether to cut off the clock signal supplied to the circuit unit, so that the circuit unit stops receiving the clock signal when it is not needed, thereby reducing the power consumption caused by the internal state switching of the circuit unit due to the clock signal. Even when the clock signal supplied to the circuit unit is cut off (hereinafter referred to as the clock-gated state), power supply to the circuit unit may still exist, and therefore the circuit unit will still generate static power consumption. Thus, through clock gating, the managed circuit unit can be in a power consumption level between the normal operating state and the power-off state.

[0115] Figure 9 A schematic diagram of the structure of a control component according to another embodiment of the present invention is shown. Figure 8 The storage device shown also includes a clock generation circuit. Figure 9 (represented as CLK) and multiple clock gating units ( Figure 9 (represented as CG in Chinese). Figure 9 middle( Figure 9 The connection cables between the power management unit and each power switch are not shown. Refer to the connection cable diagram between the power management unit and each power switch. Figure 2The connection lines between the clock generation circuit and each clock gating unit are represented by solid black lines, indicating the clock signal provided by the clock generation circuit. The connection lines between the power management unit and each clock gating unit are represented by dashed orange lines, indicating the control signals from the power management unit to each clock gating unit. The power management unit can independently control the control signals provided to each clock gating unit. The clock generation circuit generates the clock signal. The clock gating unit is located between the clock generation circuit and the circuit unit receiving the clock signal. The input port of the clock gating unit is coupled to the clock generation circuit, and the output port is coupled to the circuit unit receiving the clock signal. The clock gating unit is used to cut off the clock signal provided to each circuit unit according to the control signal generated by the power management unit, putting each circuit unit in a clock-gated state. For example, the circuit units within the control unit that need to receive clock signals include CPU cores 0-3, the NVMe protocol processor, the media interface controller, and the inter-chip interconnect unit. Clock gating units are set between the clock generation circuit and CPU cores 0-3, the NVMe protocol processor, and the media interface controller. No clock gating units are set on the path between the inter-chip interconnect unit and the clock generation circuit; clock gating is not used, and the power supply is only controlled to turn on or off. No clock gating units are set on the path between the PCIe controller and the clock generation circuit, and clock gating is not used; instead, it has its own power management scheme. For example, the PCIe protocol defines several manageable low-power states (such as L1, L1.1, L1.2, etc.), and power consumption can also be reduced by lowering the frequency. The power management unit controls the power consumption level of the PCIe controller according to the power management scheme supported by the PCIe controller itself. For example, the PCIe controller provides a power management port (…). Figure 9 The power management unit (PM) provides control signals to the power management port of the PCIe controller to instruct the PCIe controller to enter a specific power level.

[0116] Table 2 shows the operating status of each circuit unit of the control component under each power consumption state in another embodiment of this utility model.

[0117] Table 2:

[0118] Optionally, the control signals provided by the power management unit to the clock gating unit and / or power management port are also part of the power management sequence. For example, when the control unit transitions from the PS0 power state to the PS1 power state, taking an NVMe protocol processor as an example, the NVMe power management sequence generation unit of the power management unit generates a control signal for the clock gating unit of the NVMe protocol processor to cut off the clock supplied to the NVMe protocol processor and keep the control signal for the clock gating unit of the NVMe protocol processor valid until it exits from the PS1 power state to the PS0 power state.

[0119] Figure 10 A schematic diagram of the control component according to another embodiment of the present invention is shown. Figure 10 As shown, the control component includes a power management unit (PMU). Figure 10 The components are represented as PMU, CPU core group (including multiple CPU cores, such as CPU core 0, CPU core 1, CPU core 2 and CPU core 3), PCIe controller (including PCIe PHY), NVMe protocol processor, media interface controller, chip interconnect unit (including interconnect PHY), multiple power switches (e.g. SW0, SW1, SW10, SW11, SW12, SW13, SW2, SW3, SW4, SW5, SW6, SW7), multiple isolation units (e.g. ISO1, ISO2, ISO3, ISO4, ISO5, ISO6, ISO7, ISO8, ISO9, ISO10), clock generation circuit ( Figure 10 (represented as CLK), multiple clock gating units ( Figure 10 (represented as CG), it also includes SRAM0 memory, an isolation cell (ISO11) coupled to SRAM0, SRAM1 memory, and a power switch connected to the power supply circuit of SRAM1 (such as... Figure 2 SW8 shown), flash memory controller ( Figure 10 The components are DDR controller, power switch (SW9) connected to the flash controller power supply circuit, and clock gating unit and isolation unit (ISO11) coupled to the flash controller. Figure 10 The NVM chip and flash memory chip, located outside the control unit and connected to the control unit, are also shown. Figure 10 (This is represented as a DDR chip).

[0120] The power supply port of SRAM0 is connected between the main power supply VDD and the input terminal of the power switch SW0. The power supply of SRAM0 is not controlled by the power management unit. SRAM0 is an AON type circuit unit; therefore, SRAM0 does not lose power when the control unit enters a deep sleep state. SRAM0 is used to save the state data before sleep when the control unit is in deep sleep. The state data saved in SRAM0 allows the control unit to quickly restore its main circuit units (such as the CPU core group) to their state before sleep when waking from deep sleep, thus shortening the wake-up time. For the scheme of saving deep sleep state data using SRAM0 and the rapid wake-up, please refer to Chinese patents CN2022117334108 and CN2022117334837, the contents of which are incorporated herein by reference. Further details are omitted here.

[0121] The input port of SRAM0 is coupled to isolation unit ISO11, which is located on the signal input path of SRAM0. During normal operation of the control unit, isolation unit ISO11 operates normally under the control of the power management unit. When the control unit is in deep sleep mode, the power management unit controls isolation unit ISO11 to operate in an isolated state. Isolation unit ISO11 outputs a definite signal to SRAM0, ensuring that the input port of SRAM0 receives the definite signal, thus preventing erroneous operation of SRAM0 by the control unit during sleep mode and avoiding damage to the state data stored in SRAM0.

[0122] Optionally, SRAM0 provides a power management port ( Figure 10 The power management unit (PM) provides control signals to the power management port of SRAM0 to instruct SRAM0 to enter a specific power level.

[0123] The input port of power switch SW8 is coupled to the output port of power switch SW0, and the output port of power switch SW8 is coupled to the power supply port of SRAM1. Power switch SW8 is opened or closed under the control of the power management unit to control whether power is supplied to SRAM1. The power supply to SRAM1 can be cut off by the power management unit to further reduce the power consumption of the control components.

[0124] The input port of power switch SW9 is coupled to the output port of power switch SW0, and the output port of power switch SW9 is coupled to the power supply port of the flash memory controller. Power switch SW9 is opened or closed under the control of the power management unit to control whether power is supplied to the flash memory controller. Isolation unit ISO11 is located on the signal output path of the flash memory controller. Isolation unit ISO11 operates in normal operation or isolation mode under the control of the power management unit. When the flash memory controller is off, the power management unit controls power switch SW9 to open and controls isolation unit ISO11 to operate in isolation mode. When the flash memory controller is on, the power management unit controls power switch SW9 to close and controls isolation unit ISO11 to operate in normal operation. The flash memory controller is also coupled to a clock gating unit. The input port of this clock gating unit is coupled to a clock generation circuit, and the output port is coupled to the flash memory controller. This clock gating unit is used to cut off the clock signal supplied to the flash memory controller according to the control signal of the power management unit, so that the flash memory controller is in clock-gated mode.

[0125] The power management unit includes a flash controller power management sequence generation unit. This unit generates power management sequences to manage the power consumption of the flash controller, including sequences for cutting off power supply, restoring power supply, and implementing clock gating. The flash controller includes a physical layer module (denoted as DDR PHY). The DDR PHY is powered externally to the control unit, for example, by an external power supply V5. The DDR PHY is coupled to a power switch SW10; the input port of power switch SW10 is coupled to the external power supply V5, and the output port is coupled to the DDR PHY. Power switch SW10 is opened or closed under the control of the power management unit to control whether power is supplied to the DDR PHY. Power switch SW10 is located externally to the control unit.

[0126] Figure 10 The system also showcases an NVM chip coupled to a media interface controller and a flash memory chip coupled to a DDR PHY. The NVM chip is powered externally to the control unit, for example, by an external power supply V6. The flash memory chip is powered externally to the control unit, for example, by an external power supply V7. A power management unit (PMU) can also manage the power consumption levels of the NVM chip and the flash memory chip. For example, the PMU controls whether power is supplied to the NVM chip by controlling the opening and closing of power switch SW11. The input port of power switch SW11 is coupled to external power supply V6, and the output port is coupled to the NVM chip. Power switch SW11 is located externally to the control unit. The PMU controls whether power is supplied to the flash memory chip by controlling the opening and closing of power switch SW12. The input port of power switch SW12 is coupled to external power supply V7, and the output port is coupled to the flash memory chip. Power switch SW12 is located externally to the control unit.

[0127] Similar to PCIe controllers, flash memory chips also have their own power management schemes. For example, flash memory chips offer a self-refresh operating mode. In self-refresh mode, the flash memory chip does not respond to read / write requests, but it can retain the stored data without loss. The flash memory chip can only respond to read / write requests after exiting self-refresh mode. Self-refresh mode has lower power consumption compared to normal operation. For simplicity, Figure 10 The image shows the power management port of the flash memory chip (in...). Figure 10 The power management unit (PM) controls the flash memory chip to enter or exit self-refresh mode by sending control signals to the power management port PM. Optionally, the power management port of the flash memory chip shares some or all of its pins with the address port, data port, and control port of the flash memory chip.

[0128] Optionally, the power management unit provides power switches to the external control components and / or control signals to the power management ports of external chips, which are also part of the power management sequence.

[0129] Table 3 shows the operating status of each circuit unit of the control component under each power consumption state in another embodiment of this utility model.

[0130] Table 3:

[0131] In one implementation, each row of Table 3 above represents a circuit unit as a power domain, and circuit units in different rows are set as different power domains. The power management unit provides a corresponding power management sequence generation unit for each power domain, used to generate a power management sequence for its corresponding power domain.

[0132] Figure 11 This diagram illustrates a flowchart of an embodiment of the present invention showing how CPU core 0 controls the entire control unit to enter a deep sleep state. (See attached flowchart.) Figure 11 As shown, the process includes: Step S1101: CPU core 0 sends a control command to the power management unit, instructing to shut down the NVMe protocol processor.

[0133] Step S1102: In response to recognizing a control command instructing the NVMe protocol processor to shut down, the power management unit initiates the NVMe power management sequence generation unit to generate a power management sequence for cutting off power supply, thereby shutting down the NVMe protocol processor. The process by which the NVMe power management sequence generation unit generates the power management sequence for cutting off power supply to shut down the NVMe protocol processor is described below. Figure 5 This will not be elaborated upon here.

[0134] Step S1103: In response to the NVMe protocol processor being shut down, CPU core 0 sends control commands to the power management unit in sequence, instructing the PCIe controller, the media interface controller, and the flash memory controller to be shut down.

[0135] Step S1104: The power management unit sequentially activates the PCIe power management sequence generation unit, the media interface controller power management sequence generation unit, and the flash controller power management sequence generation unit to generate a power management sequence for cutting off power supply, thereby shutting down the PCIe controller, the media interface controller, and the flash controller. The process of shutting down the PCIe controller, the media interface controller, and the flash controller is similar to the process of shutting down the NVMe protocol processor, and will not be described further here.

[0136] Step S1105: CPU core 0 sends a control command to the power management unit, instructing to turn off the power switch SW8 to shut down SRAM1.

[0137] Step S1116: The power management unit sends a control signal to the power switch SW8 to turn off the power switch SW8.

[0138] Step S1107: CPU core 0 saves its own runtime environment in SRAM0. Optionally, CPU core 0 instructs CPU cores 1-3 to save their own runtime environment in SRAM0.

[0139] Step S1107: CPU core 0 sends a control command to the power management unit to instruct CPU cores 1-3 to be shut down.

[0140] Step S1109: The power management unit responds sequentially to the recognition of the control command instruction to shut down CPU cores 1-3, and starts the CPU power management sequence generation unit to generate a power management sequence for cutting off power supply to shut down CPU cores 1-3.

[0141] Step S1110: CPU core 0 sends a control command to the power management unit, instructing to turn off the power switch SW0 to shut down all turn-off circuit units (including CPU core 0 itself).

[0142] Step S1111: The power management unit sends a control signal to the power switch SW0 to turn off the power switch SW0.

[0143] Figure 12 A flowchart illustrating a host waking up a control component in deep sleep mode according to an embodiment of this invention is shown. In the control component in deep sleep mode, only AON-type circuit units (e.g., power management unit and PCIe PHY) are active. Figure 12 As shown, the process includes: Step S1201: In response to receiving a wake-up signal sent by the host through the PCIe link, the PCIe PHY transmits a wake-up signal to the power management unit.

[0144] Step S1202: In response to receiving the wake-up signal, the power management unit sends a control signal to the power switch SW0 to close the power switch SW0 and restore power supply to the CPU core 0.

[0145] Step S1203: In response to recognizing that the host wants to wake up the control unit, CPU core 0 sends control commands to the power management unit in sequence to instruct CPU cores 1-3 to be turned on.

[0146] Step S1204: In response to recognizing the received control command indicating that CPU core 1-3 should be enabled, the power management unit initiates the CPU power management sequence generation unit to generate a power management sequence for restoring power supply, thereby enabling CPU core 1-3. The process of enabling CPU core 1-3 is described in reference [reference needed]. Figure 6 This will not be elaborated further here. In response to power-on, CPU cores 1-3 restore the working state before hibernation using the running state saved in SRAM0.

[0147] Step S1205: In response to recognizing that the host wants to wake up the control unit, CPU core 0 sends a control command to the power management unit, instructing the PCIe controller, NVMe protocol processor, media interface controller and flash memory controller to be turned on.

[0148] Step S1206: In response to the received control command indicating that the PCIe controller, NVMe protocol processor, media interface controller, and flash memory controller are to be enabled, the power management unit sequentially starts the PCIe power management sequence generation unit, NVMe power management sequence generation unit, media interface controller power management sequence generation unit, and flash memory controller power management sequence generation unit to generate a power management sequence for restoring power supply, thereby enabling the PCIe controller, NVMe protocol processor, media interface controller, and flash memory controller. The process of enabling the PCIe controller, NVMe protocol processor, media interface controller, and flash memory controller is described in reference [reference needed]. Figure 6 This will not be elaborated upon here.

[0149] Figure 13 A schematic diagram of a state machine for implementing a power management sequence generation unit according to an embodiment of the present invention is shown.

[0150] like Figure 13 As shown, the state machine includes a wait state and a clock-gated open state. Figure 13 (Indicated by GC enabled), isolation enabled ( Figure 13 The text indicates that ISO is enabled, reset is enabled, and power switch is off. Figure 13The middle indicates that SW is open, and the power switch is closed. Figure 13 (represented as SW closure), reset undo, isolation recovery ( Figure 13 (represented as ISO recovery) and clock gating recovery Figure 13 The state is represented in the middle (e.g., GC recovery).

[0151] The waiting state represents not applying additional power control to the managed circuit unit to allow it to operate normally, at which point the circuit unit has the maximum power consumption.

[0152] The clock gating enabled state indicates that clock gating is applied to the managed circuit unit to cut off the clock signal supplied to that circuit unit.

[0153] The isolation enabled state means that the isolation unit of the managed circuit unit is enabled, so that the isolation unit works in the isolation state, isolating the output / output of the circuit unit.

[0154] The reset enabled state means that a continuous reset signal is applied to the managed circuit unit, causing it to continuously reset or remain in the initialized state without operating. Figure 2 , Figure 9 and Figure 10 The hardware block diagram shown does not display the reset port of the circuit unit, nor does it show the reset signal provided by the power management unit, but those skilled in the art can understand its meaning, as well as the circuit structure and principle.

[0155] The power switch being in the off state means that the power switch is turned off, thus cutting off the power supply to the managed circuit unit.

[0156] The closed state of the power switch indicates that the power switch is closed to supply power to the managed circuit unit.

[0157] The reset cancel status indicates that the reset signal applied to the circuit unit has been canceled.

[0158] The isolation recovery state means that the isolation unit of the managed circuit unit is switched to the normal operating state, thereby no longer isolating the output / output of the circuit unit.

[0159] The clock gating recovery state indicates that the clock gating is turned off, and the clock signal is resumed to the circuit unit.

[0160] exist Figure 13 In the diagram, the arrows represent the state transitions. The waiting states in the first row and the waiting states in the second row represent the same state. Figure 13The first row represents the state transition process of a circuit unit switching from a relatively high power consumption level to a low power consumption level. In the multiple states in the first row, the further to the right, the lower the power consumption level. The rightmost state, SW (Switch Off), cuts off the power supply to the corresponding power domain of the circuit unit, minimizing its power consumption. The second row represents the state transition process of a circuit unit switching from a relatively low power consumption level to a high power consumption level. In the multiple states in the second row, the further to the right, the higher the power consumption level. The rightmost state returns to the standby state, which is the power consumption level at which the corresponding circuit unit operates normally.

[0161] Therefore, according to Figure 13 As shown in the state machine of this embodiment, when a circuit unit needs to enter the isolation enabled state, it cannot be directly switched from the waiting state to the clock-gated enabled state. Instead, it needs to be switched from the waiting state to the clock-gated enabled state first, and then to the isolation enabled state. Correspondingly, in the clock-gated enabled state, the sequence generation unit of the power management unit enables the clock gating unit for the managed circuit unit to cut off the clock supplied to the circuit unit, and then sets the isolation unit of the circuit unit to the isolated state. Furthermore, the clock gating unit remains enabled at this time. Similarly, in the reset enabled state, both the clock gating unit and the isolation unit remain enabled.

[0162] Therefore, in Figure 13 In this configuration, a control signal continuously generated from a certain state (e.g., clock gating enabled) will only be canceled by the subsequent corresponding state (clock gating resumed), and will not be canceled by switching to another state. Similarly, a control signal canceled from a certain state (e.g., reset canceled) will only be enabled by the subsequent corresponding state (reset enabled), and will not be enabled by switching to another state. This facilitates faster switching between different power consumption states controlled by the power management unit.

[0163] For example, during the process of the power consumption state of the control unit switching from PS0 to PS1, and then further to PS2 and PS3. Taking the NVMe protocol processor as an example, firstly, the control command received by the power management unit instructs the NVMe protocol processor to be clock-gated (entering the PS1 power consumption state). At this time, the state machine corresponding to the NVMe power management sequence generation unit is in a waiting state, and in response to the control command, it switches to the clock-gated on state.

[0164] Then, the power management unit receives a command to power down the NVMe protocol processor (entering the PS2 power state). At this time, the state machine corresponding to the NVMe power management sequence generation unit switches sequentially to the clock gating enabled, reset enabled, and power switch off states. Throughout this process, clock gating of the NVMe protocol processor remains active.

[0165] Finally, the control unit needs to enter the PS3 state. Since the NVMe protocol processor is powered down in both PS2 and PS3 states, no additional power management is required, and therefore the CPU does not need to issue power control commands to the power management unit (PMU) for the NVMe protocol processor. Alternatively, the CPU issues a power-down command to the PMU to power down the NVMe protocol processor, and the PMU, based on the NVMe power management sequence, generates a state machine corresponding to the power management unit that is already in the off state without performing any additional operations.

[0166] Optionally, the control unit can remain in a certain power consumption state, such as the PS1 state, for an extended period. Accordingly, the state machine of the NVMe power management sequence generation unit remains in the clock gating enabled state and maintains the output control signal to enable the clock gating unit.

[0167] Optionally, some power management sequence generation units require additional states in their state machines. For example, the PCIe power management sequence generation unit requires additional states to utilize the power management scheme of the PCIe controller, and the DDR power management sequence generation unit requires additional states to utilize the power management scheme of the flash memory chip, as well as to manage the power switches of the flash memory controller and the flash memory chip respectively.

[0168] In an optional embodiment, the state machine of the power management sequence generation unit can be configured to provide multiple power management sequence generation units for different power domains using multiple instances of the same state machine circuit. For example, Figure 13 The demonstrated state machine is applicable to controlling the power consumption of the NVMe protocol processor and the inter-chip interconnect units. The NVMe protocol processor and the inter-chip interconnect units belong to different power domains. The power management unit provides different power management sequence generation units to control the power consumption of these power domains, and these power management sequence generation units can have the same state machine hardware.

[0169] Optionally, the power management unit configures the used states of each power management sequence generation unit, and skips unused states during state transitions. Each power management sequence generation unit also has a configuration register for configuring the used states and skipped states in the state machine of the sequence generation unit.

[0170] exist Figure 13 In the process, each state in the state machine is used, and the configuration information of its corresponding configuration register is shown in Table 4 below.

[0171] Table 4:

[0172] Figure 14The state machine corresponding to the power management sequence generation unit for inter-chip interconnect units is shown. Figure 14 In the state machine, the CG on state, reset on state, reset off state, and CG recovery state are skipped, while the wait state, ISO on state, SW off state, SW closed state, and ISO recovery state are all used. The configuration information of their corresponding configuration registers is shown in Table 5 below.

[0173] Table 5:

[0174] In Tables 4 and 5, "1" indicates that a state is used, and "0" indicates that a state is skipped.

[0175] In the state machine of the power management sequence generation unit for inter-chip interconnect units, the configuration register indicates that states other than GC enabled, reset enabled, reset revoked, and GC resumed are enabled. In this state machine, a direct switch from a wait state to an ISO enabled state can be made, skipping the GC enabled state. Similarly, a direct switch from an ISO enabled state to a SW disabled state can be made, skipping the reset enabled state. In each state, the control signals generated by the sequence generation unit are consistent with those in the previous embodiment. Therefore, without changing the state machine hardware of the sequence generation unit, the configuration register generates sequence generation units for controlling different power domains. Furthermore, this change can occur during the operation of the control unit and / or at the user site without redesigning or manufacturing the chip.

[0176] Understandably, for example, the state machine corresponding to the PCIe power management sequence generation unit needs more states to utilize the PCIe controller's own power management scheme. Figure 13 , Figure 14 The state machine shown cannot be directly applied to providing a PCIe power management sequence generation unit.

[0177] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the present invention. Clearly, those skilled in the art can make various alterations and modifications to the present invention without departing from its spirit and scope. Thus, if such modifications and modifications fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include such modifications and modifications.

Claims

1. A control component, characterized in that, The control component includes a power management unit, a power switch, and multiple circuit units; the control component is powered by a main power supply; the power switch includes a first power switch and multiple second power switches. The input terminal of the first power switch is coupled to the main power supply, and the output terminal of the first power switch is coupled to the power supply port of each circuit unit respectively. A second power switch is provided on the power supply line between the power supply port of each circuit unit and the first power switch. The power management unit is coupled to the main power supply and the power switch, and there is no power switch on the power supply line between the power management unit and the main power supply. The power management unit controls the power switch to open or close to control the power supply to at least one circuit unit.

2. The control component according to claim 1, characterized in that, The control component also includes multiple isolation units, which are coupled to the signal output path and / or signal input path of the circuit unit; Each of the isolation units is coupled to the power management unit, and each of the isolation units operates in a normal working state or an isolation state under the control of the power management unit; Under normal operating conditions, the isolation unit directly outputs the first signal in response to receiving the first signal; In the isolated state, the isolation unit, in response to receiving the first signal, generates a specified second signal and outputs the specified second signal.

3. The control component according to claim 1 or 2, characterized in that, The power management unit includes a power management sequence generation unit; In response to the power management unit receiving a power management command, the power management sequence generation unit generates a power management sequence. The power management sequence is used to control the opening of the second power switch corresponding to the specified circuit unit and to control the isolation unit corresponding to the specified circuit unit to be in an isolated state; or, the power management sequence is used to control the closing of the second power switch corresponding to the specified circuit unit and to control the isolation unit corresponding to the specified circuit unit to be in a normal operating state. The specified circuit unit is the circuit unit indicated by the power management command or the circuit unit corresponding to the power state indicated by the power management command.

4. The control component according to any one of claims 1-3, characterized in that, The plurality of circuit units include one or more of the following: a PCIe controller, a CPU core group, an NVMe protocol processor, a media interface controller, and an inter-chip interconnect unit; the CPU core group includes a plurality of CPU cores, and the plurality of CPU cores includes a first CPU core. The plurality of second power switches are respectively connected to the power supply circuits of the PCIe controller, the CPU core group, each of the CPU cores, the NVMe protocol processor, the media interface controller, and the chip interconnect unit.

5. The control component according to claim 4, characterized in that, The power management unit includes an NVMe power management sequence generation unit, which is used to generate a power management sequence for implementing power management on the NVMe protocol processor. The first CPU core sends a first power management command to the power management unit, instructing the power supply to the NVMe protocol processor to be cut off; In response to receiving the first power management command, the power management unit starts the NVMe power management sequence generation unit to generate a first power management sequence. The first power management sequence includes a first control signal that controls the isolation unit corresponding to the NVMe protocol processor to work in an isolated state and a second control signal that controls the second power switch corresponding to the NVMe protocol processor to be turned off. The NVMe power management sequence generation unit sends the first control signal to the isolation unit corresponding to the NVMe protocol processor and the second control signal to the second power switch corresponding to the NVMe protocol processor.

6. The control component according to claim 5, characterized in that, The first CPU core sends a second power management command to the power management unit, instructing the power supply to the NVMe protocol processor to be restored; In response to receiving the second power management command, the power management unit starts the NVMe power management sequence generation unit to generate a second power management sequence. The second power management sequence includes a third control signal that controls the isolation unit corresponding to the NVMe protocol processor to work in a normal working state and a fourth control signal that controls the second power switch corresponding to the NVMe protocol processor to close. The NVMe power management sequence generation unit sends the third control signal to the isolation unit corresponding to the NVMe protocol processor and the fourth control signal to the second power switch corresponding to the NVMe protocol processor.

7. The control component according to any one of claims 4-6, characterized in that, The first CPU core sends a first power management command to the power management unit, instructing the power supply to the NVMe protocol processor to be cut off; In response to receiving the first power management command, the power management unit starts the NVMe power management sequence generation unit to generate the first power management sequence. In response to the power supply to the NVMe protocol processor being cut off, the first CPU core sequentially sends a first power management command to the power management unit, instructing the PCIe controller, the media interface controller, and CPU cores other than the first CPU core to cut off power supply. In response to receiving a first power management command that sequentially instructs to cut off power supply to the PCIe controller, the media interface controller, and the CPU cores other than the first CPU core, the power management unit sequentially starts the PCIe power management sequence generation unit, the media interface controller power management sequence generation unit, and the CPU power management sequence generation unit to generate the first power management sequence. In response to the power supply to the PCIe controller, media interface controller, and CPU cores other than the first CPU core being cut off, the first CPU core sends a control command to the power management unit instructing the first power switch to be turned off. In response to receiving the control command, the power management unit controls the first power switch to turn off. In response to the first power switch being turned off, the control unit enters a deep sleep state.

8. The control component according to claim 7, characterized in that, In response to receiving a wake-up signal, the power management unit controls the first power switch and the second power switch corresponding to the first CPU core to close, and the first CPU core resumes power supply. In response to the first CPU core restoring power supply, the first CPU core sequentially sends a second power management command to the power management unit, instructing the restoration of power supply to the PCIe controller, the media interface controller, and CPU cores other than the first CPU core. In response to receiving a second power management command that sequentially instructs to restore power supply to the PCIe controller, the media interface controller, and the CPU cores other than the first CPU core, the power management unit sequentially starts the CPU power management sequence generation unit, the media interface controller power management sequence generation unit, the PCIe power management sequence generation unit, and the NVMe power management sequence generation unit to generate the second power management sequence. According to the generated second power management sequences, power supply to the PCIe controller, media interface controller, and CPU cores other than the first CPU core is restored in sequence, and the deep sleep state is exited.

9. The control component according to claim 3, characterized in that, The control component also includes a clock generation circuit and multiple clock gating units; The clock generation circuit generates a clock signal; The input terminal of the clock gating unit is coupled to the output terminal of the clock generation circuit, and the output terminal of the clock gating unit is coupled to the circuit unit that receives the clock signal. The clock gating unit is also coupled to the power management unit. Under the control of the power management unit, the clock gating unit transmits the clock signal generated by the clock generation circuit to the circuit unit or cuts off the clock signal provided to the circuit unit.

10. The control component according to claim 9, characterized in that, The power management sequence generation unit includes a state machine; The state machine sequentially includes a waiting state, a clock gating enabled state, an isolation unit enabled state, a reset enabled state, a power switch disabled state, a power switch disabled state, a reset canceled state, an isolation unit restored state, and a clock gating restored state. The waiting state indicates that no power consumption control is applied to the multiple circuit units within the control component, and the control component is operating normally. The clock gating enabled state represents applying clock gating to the circuit unit to cut off the clock signal supplied to the circuit unit; The isolation unit being enabled indicates that the isolation unit corresponding to the circuit unit is in an isolated state. The reset enabled state means that a continuous reset signal is applied to the circuit unit, causing it to continuously reset or remain in the initialized state; The power switch being off indicates that the second power switch corresponding to the circuit unit is disconnected. The closed state of the power switch represents the second power switch corresponding to the closed circuit unit; The reset cancellation state indicates that the reset signal applied to the circuit unit has been cancelled; The isolation unit recovery state means that the isolation unit corresponding to the circuit unit is put into normal working state.

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