OTP module with adjustable structure and integrated circuit chip

Abstract

The utility model provides a kind of OTP module and integrated circuit chip of adjustable structure.The OTP module of adjustable structure includes at least one with first storage area and second storage area at least two storage areas of OTP and read logic operation part;Read logic operation part includes selection area and logic operation area;Logic operation area includes first level logic layer and second level logic layer at least two levels of logic layer, the input port of first level logic layer is connected with the output port of first storage area and second storage area, and the output port of first level logic layer is connected with the input port of second level logic layer;The output port of second level logic layer and the output port of first storage area are as the input port of selection area, and read logic operation part is connected first enable signal.The utility model can improve the reliability of OTP storage unit read-write data, improve product test yield and reliability before OTP storage unit is not optimized to complete in process development stage.

Description

Technical Field

[0001] This utility model relates to the field of memory technology, and in particular to an OTP module with adjustable structure and an integrated circuit chip. Background Technology

[0002] One-Time Programmable (OTP) memory is a type of non-volatile memory with advantages such as high-speed read speed, low power consumption, and high reliability. It has been widely used in various electronic devices (such as mobile phones and tablets), smart cards, security authentication, and ID identification. However, during the process development phase, in order to ensure the smooth testing and verification of other functional modules that rely on OTP, a significant amount of time and resources are often required to first perform functional and reliability verification on the OTP memory cells.

[0003] Furthermore, OTPs are commonly used in chips as IP (Intellectual Property) cores provided by chip manufacturers, often for storing reliable and retrievable data. For example, OTPs (such as eFuses) are used to store boot programs, encryption keys, and analog device configuration parameters. For an example of an eFuse, please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a magnified diagram of an OTP memory cell before and after programming in one specific example. From Figure 1 It can be seen that because the resistance of the OTP memory cell differs significantly before and after programming, it is easy to obtain the stored data through reverse engineering, resulting in poor confidentiality.

[0004] It should be noted that the information disclosed in the background section of this utility model is intended only to enhance the understanding of the general background of this utility model, and should not be regarded as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0005] The purpose of this invention is to provide an OTP module and integrated circuit chip with an adjustable structure. This invention can improve the reliability of reading and writing data in the OTP storage unit, thereby improving the product testing yield and reliability during the process development stage and before the OTP storage unit has been optimized, accelerating the mass production schedule, and significantly saving manpower and material costs. Furthermore, this invention can also effectively improve the confidentiality of the product.

[0006] To achieve the above objectives, this utility model provides the following technical solution: an adjustable OTP module, comprising at least one OTP and a read logic operation section; the OTP includes at least two storage areas: a first storage area and a second storage area; the read logic operation section includes a selection area and a logic operation area; the logic operation area includes at least two logic layers: a first-level logic layer and a second-level logic layer, wherein the input port of the first-level logic layer is connected to the output ports of the first storage area and the second storage area, the output port of the first-level logic layer is connected to the input port of the second-level logic layer, and the number of logic gates contained in the second-level logic layer is at least 1 / 2 of the number of logic gates contained in the first-level logic layer; the output port of the second-level logic layer and the output port of the first storage area serve as the input ports of the selection area, and the read logic operation section is connected to a first enable signal.

[0007] Optionally, the first logic layer includes several AND gates, and one input of each of the AND gates is connected to the first enable signal.

[0008] Optionally, the second-level logic layer includes several OR gates, and the two inputs of the OR gates are respectively connected to the outputs of the AND gates corresponding to the first storage area and the second storage area.

[0009] Optionally, the OTP module further includes a data encryption logic section, which is located between the second storage area and the first-level logic layer.

[0010] Optionally, the data encryption logic section includes several inverting logic gates, and one input of each of the inverting logic gates is connected to a second enable signal.

[0011] Optionally, the OTP module is an efuse type OTP.

[0012] To achieve the above objectives, the present invention also provides an integrated circuit chip, which includes the OTP module described in any of the preceding claims.

[0013] Compared with the prior art, the adjustable OTP module and integrated circuit chip provided by this utility model have the following advantages: The adjustable OTP module provided by this utility model includes at least one OTP and a read logic operation section; the OTP includes at least two storage areas: a first storage area and a second storage area; the read logic operation section includes a selection area and a logic operation area; the read logic operation area includes at least two logic layers: a first logic layer and a second logic layer, the input port of the first logic layer is connected to the output ports of the first storage area and the second storage area, the output port of the first logic layer is connected to the input port of the second logic layer, the number of logic gates contained in the second logic layer is at least 1 / 2 of the number of logic gates contained in the first logic layer; the output port of the second logic layer and the output port of the first storage area serve as the input ports of the selection area, and the read logic operation section is connected to a first enable signal. Therefore, the adjustable OTP module provided by this invention can operate in either a normal read operation state or an optimized data reliability state depending on the state of the first enable signal (e.g., operating in normal read operation state when the first enable signal is a disable instruction; operating in optimized data reliability state when the first enable signal is an enable instruction). When the OTP module operates in normal read operation state, the storage capacity of the OTP is equal to the number of OTP storage units, enabling normal read operations. When the OTP module operates in optimized data reliability state, the logic operation area can receive readback data from the first storage area and the second storage area, and output the readback data after processing by the selection area. Thus, the adjustable OTP module provided by this invention can optimize data read reliability through the first and second storage areas, thereby improving product testing yield and reliability during the process development stage, before the OTP storage units are optimized, accelerating mass production timelines, and significantly saving manpower and material costs.

[0014] Furthermore, the OTP module also includes a data encryption logic section, which is located between the second storage area and the first-level logic layer. Therefore, the data encryption logic section can encrypt or not encrypt the read-back data from the second storage area based on the state of the second enable signal (e.g., encrypting when the second enable signal is an enable instruction; not encrypting when the second enable signal is a disable instruction), thereby effectively improving the confidentiality and security of electronic devices (such as mobile phones) equipped with the adjustable OTP module provided by this invention.

[0015] In summary, the state of the first enable signal (e.g., enabled or disabled) can be set as needed, thereby allowing the adjustable OTP module provided by this invention to operate in either normal read / write mode or optimized data reliability mode, thus achieving the adjustability of the OTP's structure and functional attributes. Furthermore, the state of the second enable signal (e.g., disabled or enabled) can also be set as needed, allowing the adjustable OTP module provided by this invention to perform encryption operations on readback data or not. Therefore, the adjustable OTP module provided by this invention also has good applicability.

[0016] Since the integrated circuit chip provided by this utility model and the adjustable OTP module provided by this utility model belong to the same utility model concept, the integrated circuit chip provided by this utility model has at least all the advantages of the adjustable OTP module provided by this utility model. For details on the beneficial effects of the integrated circuit chip provided by this utility model, please refer to the above description of the beneficial effects of the adjustable OTP module provided by this utility model. It will not be repeated here. Attached Figure Description

[0017] Figure 1 This is an enlarged schematic diagram of an OTP memory cell before and after programming in one specific example;

[0018] Figure 2 A block diagram of the adjustable structure OTP module provided in the first embodiment of this utility model;

[0019] Figure 3 A schematic diagram of the circuit topology of a specific example of the adjustable OTP module provided in the first embodiment of this utility model.

[0020] Figure 4 for Figure 3 A schematic diagram of one specific example of the selection area of ​​the adjustable OTP module shown;

[0021] The reference numerals in the attached figures are as follows:

[0022] First storage area -110, second storage area -120;

[0023] Read logic operation section - 200, selection area - 210, CMOS modules - 2111, 2112, 2113, 2114, first CMOS unit - 2111a, 2112a, 2113a, 2114a, second CMOS unit - 2111b, 2112b, 2113b, 2114b, NOT gate - 212; logic operation area - 220, first level logic layer - 221, AND gate - 2211, 2212, 2213, 2214, 2215, 2216, 2217, 2218; second level logic layer - 222, OR gate - 2221, 2222, 2223, 2224;

[0024] Output ports - IO0, IO1, IO2, IO3, IO4, IO5, IO6, IO7, SA11, SA12, SA13, SA14, SA21, SA22, SA23, SA24;

[0025] Data encryption logic section -300, inverting logic gates -310, 320, 330, 340;

[0026] First enable signal - TestMode1, second enable signal - TestMode2. Detailed Implementation

[0027] The following detailed description, in conjunction with the accompanying drawings, further illustrates the adjustable structure OTP module and integrated circuit chip proposed in this utility model. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clearly illustrate the embodiments of this utility model. Please refer to the drawings to make the objectives, features, and advantages of this utility model more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes and to enable those skilled in the art to understand and read them, and are not intended to limit the implementation conditions of this utility model. Any modifications to the structure, changes in proportions, or adjustments to the size, provided they produce the same or similar effects and achieve the same objectives as this utility model, should still fall within the scope of the technical content disclosed in this utility model. Specific design features of this utility model disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures. Additionally, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which these steps can be performed, some described steps may be omitted and / or other steps not described herein may be added to the method.

[0028] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms “a,” “an,” and “the” include plural objects. The term “or” is generally used to mean “and / or,” the term “several” is generally used to mean “at least one,” and the term “at least two” is generally used to mean “two or more.” Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0029] It should be understood that when a component is referred to as "connected," "connected to," or "coupled to" other components, it may be directly connected to other components, or there may be intermediary components. Conversely, when a component is referred to as "directly connected" or "directly connected to" other components, there are no intermediary components.

[0030] The core idea of ​​this utility model is to provide an OTP module and integrated circuit chip with adjustable structure. This utility model can improve the reliability of reading and writing data in the OTP storage unit, thereby improving the product testing yield and reliability during the process development stage and before the OTP storage unit has been optimized, accelerating the mass production schedule, and significantly saving manpower and material costs. Furthermore, this utility model can also effectively improve the confidentiality of the product.

[0031] To achieve the above-mentioned goals, a first embodiment of this utility model provides an OTP module with an adjustable structure. For example, please refer to... Figure 2 , Figure 2 This is a block diagram illustrating the adjustable structure of the OTP module provided in this embodiment. From... Figure 2It can be seen that the adjustable OTP module provided by this utility model includes an OTP (One-Time Programmable Memory) and a read logic operation section 200; the OTP includes at least two storage areas: a first storage area 110 and a second storage area 120; the read logic operation section 200 includes a selection area 210 and a logic operation area 220; the logic operation area 200 includes at least two logic layers: a first logic layer 221 and a second logic layer 222, the input port of the first logic layer 221 is connected to the output ports of the first storage area 110 and the second storage area 120 (…). Figure 2 In the diagram, SA11, SA12, SA13, and SA14 represent the output ports of the first storage area 110, and SA21, SA22, SA23, and SA24 represent the output ports of the second storage area 120. The output ports of the first logic layer 221 (…) are connected… Figure 2 (Not shown in the text) and the input port of the second-level logic layer 222 ( Figure 2 (Not shown in the text) The second-level logic layer 222 contains at least half the number of logic gates contained in the first-level logic layer 221; the output port of the second-level logic layer 222 and the output port of the first storage area 110 serve as the input ports of the selection area, and the read logic operation section 200 is connected to the first enable signal TestMode1.

[0032] With this configuration, the adjustable OTP module provided by this utility model can operate in either a normal read operation state or an optimized data reliability state depending on the state of the first enable signal TestMode1 (for example, when the first enable signal TestMode1 is a disable instruction, it operates in the normal read operation state; for example, TestMode1 is low and has a value of "0"; when the first enable signal TestMode1 is an enable instruction, it operates in the optimized data reliability state; for example, TestMode1 is high and has a value of "1"). When the OTP module operates in the normal read operation state, the storage capacity of the OTP is equal to the number of OTP storage units, enabling the normal read operation of the OTP. When the OTP module operates in the optimized data reliability state, the logic operation area 220 can receive readback data from the first storage area 110 and the second storage area 120, and output the readback data after processing by the selection area 210. Therefore, the adjustable OTP module provided by this utility model can optimize the read reliability of data through the first storage area 110 and the second storage area 120, thereby improving the product test yield and reliability, accelerating the mass production schedule, and significantly saving manpower and material costs during the process development stage and before the OTP storage unit has been optimized.

[0033] It should be noted that those skilled in the art should understand that the present invention does not impose excessive limitations on the size of the first storage area 110 and the second storage area 120. For example, the first storage area 110 and the second storage area 120 can be storage arrays with identical structures, formed by M×N OTP storage cells. Furthermore, the values ​​of M and N can be the same or different, and the present invention does not impose any limitations on the values ​​of M and N.

[0034] Exemplary examples show that, in some exemplary embodiments, the OTP can be, but is not limited to, an eFuse memory and an electrically programmable ROM (EEPROM). Therefore, by employing an eFuse memory design, the applicability of the adjustable OTP module provided by this invention can be further enhanced. It is understood that this invention does not limit the specific type of the OTP.

[0035] It should also be noted that those skilled in the art should understand that, preferably, the first storage area 110 and / or the second storage area 120 should have been written with data before the read operation. Since the specific value of the first enable signal TestMode1 can be flexibly set by the electronic device (such as a mobile phone APP) using the adjustable structure OTP module provided by this utility model, data should be written to the first storage area 110 and / or the second storage area 120 according to actual needs during the write operation. For example, if the adjustable OTP module is to be operated in normal read / write mode (i.e., the first enable signal TestMode1 is set to disable instruction during read), data can be written to the first storage area 110, the second storage area 120, or the first storage area 110 and the second storage area 120. If the adjustable OTP module is to be operated in optimized data reliability mode (i.e., the first enable signal TestMode1 is set to enable instruction during read), the same data to be written should be written to the corresponding positions of the first storage area 110 and the second storage area 120 respectively, so as to improve the reliability of reading data during read operations.

[0036] For example, please continue to see Figure 2 ,like Figure 2As shown, in some exemplary embodiments, the OTP module has eight output ports IO0, IO1, IO2, IO3, IO4, IO5, IO6, and IO7, each of which is used to output one bit of data. It should be noted that, as those skilled in the art will understand, the adjustable OTP module provided by this invention does not impose excessive limitations on the specific number of output ports of the read logic operation section 200. For example, in some embodiments, the read logic operation section 200 may include sixteen output ports; in other embodiments, the read logic operation section 200 may include thirty-two output ports, and so on. For ease of reading, understanding, and explanation of this invention, this document uses an OTP module with eight output ports IO0, IO1, IO2, IO3, IO4, IO5, IO6, and IO7 as an example.

[0037] For example, please see Figure 3 , Figure 3 This is a schematic diagram of the circuit topology of a specific example of the adjustable OTP module provided in this embodiment. From Figure 3 It can be seen that, in some preferred embodiments, the first-level logic layer 221 includes several logic AND gates. Figure 3 (Examples include logic AND gates 2211, 2212, 2213, 2214, 2215, 2216, 2217, and 2218). One input of several of the logic AND gates 2211, 2212, 2213, 2214, 2215, 2216, 2217, and 2218 is connected to the first enable signal TestMode1.

[0038] Therefore, the present invention employs a design method that uses several AND gates to implement the first-level logic layer 221, which is not only simple in logic and low in cost; moreover, one input terminal of the AND gates 2211, 2212, 2213, 2214, 2215, 2216, 2217 and 2218 is connected to the first enable signal TestMode1, so that the adjustable OTP module provided by the present invention can work in normal read and write state when the first enable signal TestMode1 is a disable instruction, and work in optimized data reliability state when the first enable signal TestMode1 is an enable instruction.

[0039] from Figure 3As can be seen, the other input of the plurality of logic AND gates 2211, 2212, 2213, 2214, 2215, 2216, 2217 and 2218 is connected to the output ports SA11, SA12, SA13 and SA14 of the first storage area 110 and the output ports SA21, SA22, SA23 and SA24 of the second storage area 120 to receive readback data.

[0040] For example, such as Figure 3 As shown, the plurality of AND gates 2211, 2212, 2213, 2214, 2215, 2216, 2217 and 2218 are divided into two groups. The other input of the AND gates 2211, 2212, 2213 and 2214 in the first group is connected to the output ports SA11, SA12, SA13 and SA14 of the first storage area 110. The other input of the AND gates 2215, 2216, 2217 and 2218 in the second group is connected to the output ports SA21, SA22, SA23 and SA24 of the second storage area 120.

[0041] For example, please continue to see Figure 3 ,like Figure 3 As shown, in some exemplary embodiments, the second-level logic layer 222 includes several logic OR gates. Figure 3 (Examples are logic OR gates 2221, 2222, 2223, and 2224). The two inputs of the logic OR gates 2221, 2222, 2223, and 2224 are respectively connected to the outputs of the logic AND gates corresponding to the first storage area 110 and the second storage area 120.

[0042] For example, please continue to see Figure 2 and Figure 3 ,from Figure 2 and Figure 3 As can be seen, in some exemplary embodiments, the OTP module further includes a data encryption logic section 300, which is disposed between the second storage area 120 and the first level logic layer 221.

[0043] The OTP module provided by this utility model further includes a data encryption logic section 300, which is disposed between the second storage area 120 and the first-level logic layer 221. Therefore, the data encryption logic section 300 can perform encryption or non-encryption operations on the readback data of the second storage area 120 according to the state of the second enable signal TestMode2 (for example, encryption is performed when the second enable signal TestMode2 is an enable instruction, exemplarily TestMode2 is high level with a value of "1"; no encryption is performed when the second enable signal TestMode2 is a disable instruction, exemplarily TestMode2 is low level with a value of "0"), thereby effectively improving the confidentiality and security of electronic devices (such as mobile phones) equipped with the adjustable structure OTP module provided by this utility model.

[0044] Furthermore, the data encryption logic section 300 includes several inverting logic gates. Figure 3 (Illustrated with inverting logic gates 310, 320, 330, and 340), with one input of each of the inverting logic gates connected to a second enable signal TestMode2. Thus, by employing inverting logic gates 310, 320, 330, and 340 to implement the data encryption logic section 300, it becomes impossible to infer the correlation between the actual stored data based on reverse engineering observations of the stored data in the second storage area 120 (for example, a certain OTP storage cell observed through reverse engineering stores "1," but the data read back from that OTP storage cell after passing through the data encryption logic section 300 is "0," and the readback data "0" is the actual data to be stored). This achieves data confidentiality, and the logic is simple and easy to implement.

[0045] More specifically, such as Figure 3 As shown, the outputs of the inverting logic gates 310, 320, 330, and 340 are respectively connected to one of the inputs of the AND gates 2215, 2216, 2217, and 2218 of the corresponding first-level logic layer 221, and the outputs of the inverting logic gates 310, 320, 330, and 340 also serve as one of the output ports of the OTP module. Figure 3 and Figure 4 (Examples are provided for output ports IO4, IO5, IO6, and IO7), thus laying a solid foundation for implementing the normal working mode of the OTP module.

[0046] It should be specifically noted that those skilled in the art should understand that the adjustable OTP module provided by this utility model does not limit the functions and structure related to performing write operations. For example, during a write operation, the data encryption logic part 300 of the adjustable OTP module provided by this utility model can be used to encrypt the written data before performing the write operation, or the data encryption logic part 300 described herein can be omitted and the written data can be directly written to the OTP storage unit. For details on how to perform write operations, please refer to the relevant technical adaptations for OTP write operations known to those skilled in the art; due to space limitations, these details are not elaborated here.

[0047] It should also be noted that although this article uses the example of the data encryption logic part 300 being located between the first logic layer 221 and the second storage area 120, it is clear that this is not a limitation of this utility model. This utility model does not impose any limitation on the number of bits (bits) of data that the data encryption logic part 300 can encrypt. For example, in some embodiments, the data encryption logic section 300 may also be located between the first level logic layer 221 and the first storage area 110; in other embodiments, the data encryption logic section 300 may also encrypt a portion of the readback data returned by the first storage area 110 and a portion of the readback data returned by the second storage area 120. That is, the data encryption logic section 300 may also be located between a portion of the output ports of the first storage area 110 (exemplarily, such as output ports SA11 and SA12), a portion of the output ports of the second storage area 120 (exemplarily, such as output ports SA21 and SA22) and the first level logic layer 221, so that the data encryption logic section 300 can encrypt the readback data returned by the data encryption logic section 300 through the output ports SA11 and SA12 of the first storage area 110 and through the output ports SA21 and SA22 of the second storage area 120.

[0048] For example, please continue to see Figure 3 and Figure 4 ,in, Figure 4 for Figure 3 This is a schematic diagram of one specific example of the selection area of ​​an adjustable OTP module. (See diagram for example.) Figure 3 and Figure 4 As shown, in some exemplary embodiments, the selection area 21 includes a plurality of CMOS modules ( Figure 3 Examples of CMOS modules 2111, 2112, 2113, and 2114 are provided, each of which includes a first CMOS unit and a second CMOS unit. Figure 4The CMOS module 2111 includes a first CMOS unit 2111a and a second CMOS unit 2111b; the CMOS module 2112 includes a first CMOS unit 2112a and a second CMOS unit 2112b; the CMOS module 2113 includes a first CMOS unit 2113a and a second CMOS unit 21123; and the CMOS module 2114 includes a first CMOS unit 2114a and a second CMOS unit 2114b (example). Taking the CMOS module 2111 as an example, the first port of the first CMOS unit 2111a (… Figure 4 (Not shown) The output port SA11 of the first storage area 110 is connected; the first port of the second CMOS unit 2111b is connected to the output of the logic OR gate 2221; the second port of the first CMOS unit 2111a and the second port of the second CMOS unit 2111b are connected in parallel to serve as the output port IO0 of the OTP module; the gate of the PMOS transistor P1 of the first CMOS unit 2111a is connected to the gate of the NMOS transistor N2 of the second CMOS unit 2111b to receive the first enable signal TestMode1; the gate of the NMOS transistor N1 of the first CMOS unit 2111a and the gate of the PMOS transistor P2 of the second CMOS unit receive the inverted signal of the first enable signal TestMode1.

[0049] Therefore, the selection area 21 employs several CMOS modules (exemplarily, such as...). Figure 3 and Figure 4 As shown, the selection area 21 includes four CMOS modules 2111, 2112, 2113, and 2114. The first and second CMOS units of each CMOS module (e.g., CMOS module 2111 includes first CMOS unit 2111a and second CMOS unit 2111b) are designed with parallel-connected PMOS and NMOS transistors. This not only further improves the reliability of the adjustable OTP module provided by this invention, but also makes the logic simple and easy to implement.

[0050] Furthermore, according to Figure 4It can be seen that during the read operation, the first CMOS units 2111a, 2112a, 2113a and 2114a are turned on when the first enable signal TestMode1 is disabled and turned off when the first enable signal TestMode1 is enabled; the second CMOS units 2111b, 2112b, 2113b and 2114b are turned off when the first enable signal TestMode1 is disabled and turned on when the first enable signal TestMode1 is enabled. Therefore, by controlling the on and off states of the first CMOS units 2111a, 2112a, 2113a, 2114a and the second CMOS units 2111b, 2112b, 2113b in the selection area 210, the first output terminals IO0, IO1, IO2 and IO3 can output the readback data of the first storage area 110 when the OTP module is working in the normal read / write state, and output the combined readback data of the first storage area 110 and the second storage area 120 when the OTP module is working in the optimized data reliability state. This achieves the tunability of the structural and functional attributes of the OTP.

[0051] For example, please continue to see Figure 3 and Figure 4 ,like Figure 3 As shown, in some exemplary embodiments, the selection area 210 further includes a NOT gate 212, the input of which receives the first enable signal TestMode1, and the output of which is connected to the NMOS transistors of the first CMOS cells 2111a, 2112a, 2113a, and 2114a. Figure 4 Only the gate of the NMOS transistor N1 of the first CMOS cell 211a and the gates of the PMOS transistors of the second CMOS cells 2111b, 2112b, 2113b, and 2114b are shown. Figure 4 Only the PMOS transistor P2 of the second CMOS cell 2111b is shown in the diagram.

[0052] It should be noted that, as those skilled in the art will understand, the specific implementation methods of the AND gates 2211, 2212, 2213, 2214, 2215, 2216, 2217, and 2218 of the first-level logic layer 221, the OR gates 2221, 2222, 2223, and 2224 of the second-level logic layer 222, the NOT gate 212, and the inverting logic gates 310, 320, 330, and 340 of the data encryption logic part 300 are not limited in too much. Taking the AND gates 2211, 2212, 2213, 2214, 2215, 2216, 2217, and 2218 of the first-level logic layer 221 as examples, these AND gates 2211, 2212, 2213, 2214, 2215, 2216, 2217, and / or 2218 can also be implemented using two diodes and resistors. For more detailed information, please refer to the adaptation understanding of logic gate circuits known to those skilled in the art; this will not be elaborated upon herein.

[0053] To better understand this utility model, combined with Figure 3 and Figure 4 The application scenarios of the adjustable OTP module provided by this utility model are briefly described below:

[0054] For example, in an application scenario where the OTP module operates in an optimized data reliability state, firstly, "1" is written (burned) into a specific OTP storage cell corresponding to the first storage area 110 and the second storage area 120, respectively. Then, when reading data, the first enable signal TestMode1 is set to the enable instruction, and the OTP storage cells corresponding to the first storage area 110 and the second storage area 120 are read to obtain the readback data of the first storage area 110 and the second storage area 120, respectively. Then, an OR operation is performed on the readback data of the first storage area 110 and the second storage area 120 to obtain the final readback result, as shown in Table 1 below:

[0055] Table 1:

[0056] 0 0 0 1 1 1 0 1 1 1 1 1

[0057] Therefore, since the probability of failure of the final OTP memory cell (such as eFuse) is the product of the failure probabilities of the two OTP memory cells, this invention can significantly improve yield and reliability.

[0058] For example, as shown in Table 2 below:

[0059] (1) In an application scenario where the second enable signal TestMode2 of the OTP module is a disable instruction (in Table 2, TestMode2 is represented by a value of "0"), if "0" is written into a certain OTP storage unit, during readback, the readback data directly output by the OTP storage unit (in Table 2, represented by SA output) will be "0", and the readback data output after passing through the data encryption logic part 300 (in Table 2, represented by "IO output") will also be "0". If "1" is written into the OTP storage unit, during readback, the readback data output by the OTP storage unit will be "1", and the data output after passing through the data encryption logic part 300 will also be "1".

[0060] (2) In an application scenario where the second enable signal TestMode2 of the OTP module is an enable instruction (in Table 2, TestMode2 is shown as "1"), if "0" is written into a certain OTP storage unit, during readback, the readback data directly output by the OTP storage unit (in Table 2, shown as SA output) is "0", and the readback data output by the data encryption logic part 300 (in Table 2, shown as "IO output") is "1". If "1" is written into a certain OTP storage unit, during readback, the readback data directly output by the OTP storage unit (in Table 2, shown as SA output) is "1", and the readback data output by the data encryption logic part 300 (in Table 2, shown as "IO output") is "0".

[0061] Table 2:

[0062]

[0063] Therefore, by controlling the value of the second enable signal TestMode2, the relationship between the final read data and the stored data can be changed, thereby altering the inference of the correlation between the results observed by the reverse structure and the stored data, and thus achieving the purpose of increasing data confidentiality.

[0064] Based on the same inventive concept, a second embodiment of this utility model provides an integrated circuit chip, which includes an OTP module with a moduloable structure as described in any of the above embodiments.

[0065] Since the integrated circuit chip provided by this utility model and the adjustable OTP module provided by this utility model belong to the same utility model concept, the integrated circuit chip provided by this utility model has at least all the advantages of the adjustable OTP module provided by this utility model. For details on the beneficial effects of the integrated circuit chip provided by this utility model, please refer to the above description of the beneficial effects of the adjustable OTP module provided by this utility model. It will not be repeated here.

[0066] The OTP module and integrated circuit chip with adjustable structure provided by this utility model have the following advantages:

[0067] (1) The adjustable OTP module provided by this utility model can operate in either a normal read operation state or an optimized data reliability state depending on the state of the first enable signal (e.g., operating in a normal read operation state when the first enable signal is a disable instruction; operating in an optimized data reliability state when the first enable signal is an enable instruction). When the OTP module operates in a normal read operation state, the storage capacity of the OTP is equal to the number of OTP storage units, enabling normal read operations of the OTP. When the OTP module operates in an optimized data reliability state, the logic operation area can receive readback data from the first storage area and the second storage area, and output the readback data after processing by the selection area. Thus, the adjustable OTP module provided by this utility model can optimize data read reliability through the first and second storage areas, thereby improving product test yield and reliability during the process development stage and before the OTP storage units are optimized, accelerating the mass production schedule, and significantly saving manpower and material costs.

[0068] (2) The OTP module further includes a data encryption logic section, which is located between the second storage area and the first-level logic layer. Therefore, the data encryption logic section can encrypt or not encrypt the read-back data from the second storage area based on the state of the second enable signal (e.g., encrypting when the second enable signal is an enable instruction; not encrypting when the second enable signal is a disable instruction), thereby effectively improving the confidentiality and security of electronic devices (such as mobile phones) equipped with the adjustable OTP module provided by this utility model.

[0069] In summary, the state of the first enable signal (e.g., enabled or disabled) can be set as needed, thereby allowing the adjustable OTP module provided by this invention to operate in either normal read / write mode or optimized data reliability mode, thus achieving the adjustability of the OTP's structure and functional attributes. Furthermore, the state of the second enable signal (e.g., disabled or enabled) can also be set as needed, allowing the adjustable OTP module provided by this invention to perform encryption operations on readback data or not. Therefore, the adjustable OTP module provided by this invention also has good applicability.

[0070] It should be noted that the apparatus and methods disclosed in the embodiments herein can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments herein. In this regard, each block in a flowchart or block diagram may represent a module, program, or part of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system to perform the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0071] In addition, the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0072] The above description is merely a preferred embodiment of the adjustable OTP module and integrated circuit chip provided by this utility model, and is not intended to limit the scope of this utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of this utility model. Obviously, those skilled in the art can make various modifications and variations to this utility model without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of this utility model and its equivalents, this utility model also intends to include these modifications and variations.

Claims

1. An OTP module with a variable structure, characterized in that, It includes at least one OTP and a read logic operation section; the OTP includes at least two storage areas: a first storage area and a second storage area; the read logic operation section includes a selection area and a logic operation area; the logic operation area includes at least two logic layers: a first-level logic layer and a second-level logic layer, the input port of the first-level logic layer is connected to the output ports of the first storage area and the second storage area, the output port of the first-level logic layer is connected to the input port of the second-level logic layer, the number of logic gates contained in the second-level logic layer is at least 1 / 2 of the number of logic gates contained in the first-level logic layer; the output port of the second-level logic layer and the output port of the first storage area serve as the input ports of the selection area, and the read logic operation section is connected to a first enable signal.

2. The OTP module of claim 1, wherein, The first-level logic layer includes several AND gates, and one input of each of the AND gates is connected to the first enable signal.

3. The OTP module of claim 2, wherein, The second-level logic layer includes several OR gates, and the two inputs of the OR gates are respectively connected to the outputs of the AND gates corresponding to the first memory area and the second memory area.

4. The OTP module of claim 1, wherein, It also includes a data encryption logic section, which is located between the second storage area and the first-level logic layer.

5. The OTP module of claim 4, wherein, The data encryption logic section includes several inverted logic gates, and one input of each of the inverted logic gates is connected to a second enable signal.

6. The OTP module of claim 1, wherein, The OTP module is an efuse type OTP.

7. An integrated circuit chip, characterized by The integrated circuit chip includes the OTP module as described in any one of claims 1 to 6.

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