Test device and test system for cxl memory

Abstract

The application relates to a CXL memory testing device and a testing system, wherein the testing device comprises a microcontroller, a multi-way switch module and a testing module; the microcontroller is in communication connection with the multi-way switch module through an SMBus; the multi-way switch module is in communication connection with a plurality of testing modules or a plurality of CXL memories through the SMBus; and the testing module is used for simulating a testing environment and / or acquiring testing data of the CXL memory based on a control instruction of the microcontroller. The CXL memory testing device and the testing system can reduce the dependence on a server, and thus the testing cost can be reduced.

Description

Technical Field

[0001] This application relates to the field of reliability testing technology, and in particular to a testing device and system for CXL memory. Background Technology

[0002] CXL (Compute Express Link) memory is a new type of memory technology based on a high-speed interconnect protocol. It aims to achieve efficient communication between the CPU and devices through the PCIe physical layer, supporting advanced features such as memory pooling and cache coherency. It is widely used in servers, data centers, and other fields to meet the demands of high-performance computing and large-scale data processing. However, testing CXL memory faces significant cost challenges, primarily in terms of hardware investment, environment configuration, operational energy consumption, resource consumption, test fixture reliability, and the cost of trial and error with new technologies.

[0003] In related technologies, CXL memory testing typically relies on high-performance servers and customized fixtures. However, the relevant software and hardware ecosystem is not yet fully mature, resulting in high operation and maintenance, energy consumption, and trial and error costs when using servers for testing. Utility Model Content

[0004] In view of the above, it is necessary to provide a testing device and system for CXL memory, which can reduce dependence on servers and thus reduce testing costs.

[0005] This application first provides a testing device for CXL memory, including a microcontroller, a multiplexer module, and a testing module. The microcontroller and the multiplexer module are connected via SMBus communication. The multiplexer module is connected via SMBus communication with multiple testing modules or multiple CXL memory modules. The testing module is used to simulate the test environment based on the control instructions of the microcontroller and / or acquire test data of the CXL memory.

[0006] In some embodiments, the test environment includes at least one of heating, humidification, or applying a bias voltage.

[0007] In some embodiments, the test data includes at least one of temperature data, humidity data, ECC error correction counts, or retraining trigger frequency.

[0008] In some embodiments, the testing apparatus further includes a storage module connected to the microcontroller for storing test data.

[0009] In some embodiments, the testing apparatus further includes a display module connected to a microcontroller, the display module being used to display parameters of the testing environment and / or test data.

[0010] In some embodiments, the testing apparatus further includes a button module connected to a microcontroller, the button module being used to manually control the start and stop of the testing apparatus or to manually set a configuration file for batch testing.

[0011] In some embodiments, the multiplexer module includes an I2C-based bidirectional multiplexer. The master control interface of the bidirectional multiplexer is connected to the microcontroller via SMBus. The output of the bidirectional multiplexer is connected to the slave addresses of multiple test modules in a star topology. The multiplexer module integrates dynamic address allocation function, supports polling access to multiple CXL memory in a single test task, and manages the transmission timing of different test instructions through a priority queue.

[0012] In some embodiments, the testing apparatus further includes an FPGA protocol processing module, which is connected to the microcontroller via SMBus and to a multiplexer module via a CXL link. The FPGA protocol processing module is used to parse control commands and data packets in the CXL protocol and dynamically adjust the communication timing or protocol conversion logic according to the microcontroller's instructions.

[0013] In some embodiments, the testing apparatus further includes a remote management module connected to the microcontroller. The remote management module is connected to the server via an Ethernet interface, and the remote management module uploads test data to the server and / or receives configuration files for batch testing from the server via Ethernet.

[0014] This application also provides a testing system for CXL memory. The testing system includes a testing device and a server for CXL memory as described in any embodiment of this application. The testing device is connected to the server via Ethernet.

[0015] In the testing apparatus and system of this application, a microcontroller combined with a multiplexer module and testing modules is used to centrally control and manage multiple testing modules or CXL memory via an SMBus bus. The microcontroller sends control commands via SMBus, and the multiplexer module switches the connected testing modules or CXL memory according to the commands. The testing modules then simulate the test environment or directly retrieve test data from the CXL memory. This reduces reliance on servers, allowing the testing process to be completed independently, thus reducing the consumption of expensive server resources and lowering testing costs. Simultaneously, the efficient communication of SMBus improves the real-time performance and accuracy of the test data. Attached Figure Description

[0016] Figure 1 This is a structural block diagram of the test apparatus according to the first embodiment of this application.

[0017] Figure 2 This is a structural block diagram of the test apparatus according to the second embodiment of this application.

[0018] Figure 3 This is a structural block diagram of the test apparatus according to the third embodiment of this application.

[0019] Figure 4 This is a structural block diagram of the test apparatus according to the fourth embodiment of this application.

[0020] Figure 5 This is a schematic diagram of the structure of the test system according to an embodiment of this application.

[0021] Explanation of main component symbols: 1. Testing device; 2. CXL memory; 3. Server; 11. Microcontroller; 12. Multiplexer module; 13. Testing module; 14. Storage module; 15. Display module; 16. Button module; 17. FPGA protocol processing module; 18. Remote management module.

[0022] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0023] In the description of the embodiments in this application, the words "exemplary," "or," and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplary," "or," and "for example" is intended to present the relevant concepts in a specific manner.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. It should be understood that, unless otherwise stated, " / " in this application means "or". For example, A / B can mean A or B. "And / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. "At least one" refers to one or more. "More than one" refers to two or more. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, and a, b, and c (seven cases).

[0025] It should also be noted that the terms "first" and "second" in the specification, claims and drawings of this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0026] CXL (Compute Express Link) memory is a new type of memory technology based on a high-speed interconnect protocol. It aims to achieve efficient communication between the CPU and devices through the PCIe physical layer, supporting advanced features such as memory pooling and cache coherency. It is widely used in servers, data centers, and other fields to meet the demands of high-performance computing and large-scale data processing. However, testing CXL memory faces significant cost challenges, primarily in terms of hardware investment, environment configuration, operational energy consumption, resource consumption, test fixture reliability, and the cost of trial and error with new technologies.

[0027] First, the procurement cost of high-performance servers supporting the CXL protocol and their supporting infrastructure (such as PCIe 5.0 interfaces and high-bandwidth networks) is significantly higher than that of traditional equipment. Second, the CXL protocol stack is still immature, requiring customized drivers, firmware, and BIOS support, as well as verification of compatibility with equipment from different manufacturers, which increases the development and testing cycle. Finally, the high power consumption and heat dissipation requirements of test servers, as well as the labor costs of professional operation and maintenance personnel, drive up operation and maintenance expenses.

[0028] It is evident that CXL memory testing typically relies on high-performance servers and customized fixtures, but the relevant software and hardware ecosystem is not yet fully mature, resulting in high maintenance, energy consumption, and trial-and-error costs when using servers for testing.

[0029] Therefore, this application provides a testing apparatus and system for CXL memory, which can reduce reliance on servers and thus lower testing costs. Some embodiments will be described below with reference to the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0030] Figure 1 This is a structural block diagram of the test device 1 according to the first embodiment of this application. Figure 2 This is a structural block diagram of the test device 1 according to the second embodiment of this application.

[0031] This application first provides a test device 1 for CXL memory 2, which can be used for THB (Temperature and Humidity Bias Test) of CXL memory 2. The THB (Temperature-Humidity-Bias Test) of CXL memory 2 aims to evaluate its reliability under high temperature, high humidity and voltage load, and usually adopts accelerated aging to simulate environmental stress during long-term use. The specific procedures and standards for THB testing may include: setting the temperature range to 85°C ± 2°C and the humidity to 85%RH ± 5%; applying the rated operating voltage (e.g., 1.2V) to the CXL memory module 2, with some tests potentially incorporating periodic high and low voltage cycles (e.g., ±10% fluctuation) to simulate dynamic load; running high-bandwidth data transmission tasks on the test host to continuously monitor error rates (e.g., ECC error correction counts, retransmission rate) and signal integrity (e.g., eye diagram, timing jitter); using a protocol analyzer to capture link layer data and verify protocol integrity; testing interface signal quality (e.g., rise time, noise margin) with an oscilloscope and observing changes in leakage current caused by humidity; and monitoring for functional failures (e.g., inability to read or write), performance degradation (e.g., latency increase exceeding 10%), and physical damage (e.g., corrosion or delamination).

[0032] Please see Figure 1 The test device 1 may include a microcontroller unit (MCU), a multiplexer module 12, and a test module 13. The microcontroller unit 11 and the multiplexer module 12 are connected via SMBus. The multiplexer module 12 is connected via SMBus to multiple test modules 13 or multiple CXL memory 2 (e.g., when the CXL memory 2 integrates a temperature sensor, the multiplexer module 12 can directly read the temperature data of the CXL memory 2 via SMBus). The test module 13 is used to simulate the test environment and / or acquire test data of the CXL memory 2 based on the control instructions of the microcontroller unit 11.

[0033] Please see Figure 2 In some embodiments, the test module 13 may not be necessary. For example, when the CXL memory 2 integrates a temperature sensor, the microcontroller 11 can control the CXL memory 2 to operate under overpressure and heat up through the multiplexer module 12, and directly read the temperature data of the CXL memory 2 through the multiplexer module 12.

[0034] In the embodiments of this application, the microcontroller 11 implements digital control of the multiplexer module 12 via the SMBus bus protocol, utilizing the two-wire serial characteristics of SMBus to achieve a low-cost and easily expandable topology. After receiving parameterized instructions from the microcontroller 11, the test module 13 can simulate physical layer anomalies such as voltage fluctuations and timing deviations, or generate various test scenarios (such as high temperature and high humidity). The test device 1 of this application can reduce dependence on the server 3, and the test process can be completed independently, reducing the consumption of expensive server 3 resources and thus lowering test costs.

[0035] In some embodiments, the microcontroller 11 can be used to simulate the main control functions of the server 3. For example, the microcontroller 11 can generate instructions (such as read / write requests, cache consistency operations) through the CXL protocol stack (such as FPGA (Field Programmable Gate Array) or firmware implementation) and parse the response data of the CXL memory 2; or, the microcontroller 11 can use the SMBus bus to read the memory information, temperature sensor data and ECC error log of the CXL memory 2, monitor the device status in real time, and dynamically adjust the operating mode of the CXL memory 2 (such as voltage / frequency configuration) through the SMBus bus to trigger specific test scenarios (such as high voltage / high temperature sensitivity test).

[0036] In some embodiments, the multiplexer module 12 may include an I2C-based bidirectional multiplexer. The master control interface of the bidirectional multiplexer is connected to the microcontroller 11 via SMBus, and the output of the bidirectional multiplexer is connected to the slave addresses of multiple test modules 13 in a star topology. Furthermore, the multiplexer module 12 may integrate dynamic address allocation functionality, supporting polling access to multiple CXL memory modules 2 in a single test task, and managing the transmission timing of different test instructions through a priority queue. In this case, the multiplexer module 12 can simultaneously support multiple CXL memory modules 2 for synchronous testing through one-to-many channel switching, and, combined with asynchronous task scheduling, can shorten the test cycle.

[0037] In some embodiments, the multiplexer module 12 may have n output terminals, where n is a positive integer and n is greater than 2. The number of output terminals of the multiplexer module 12 may be set according to the number of test modules 13 or CXL memory 2. For example, when the number of test modules 13 or CXL memory 2 is 6, the number of output terminals of the multiplexer module 12 may be 6.

[0038] In some embodiments, the multiplexer module 12 can adopt a matrix switching architecture, dynamically reconstructing the hardware link through digital strobe signals. In this case, a single SMBus bus can be time-division multiplexed to connect multiple test modules 13 and CXL memory 2, forming a bus-type test network.

[0039] In some embodiments, test module 13 may integrate a PID temperature control unit and a steam generator. Correspondingly, the test environment (i.e., test scenario) may include at least one of heating or humidification. The heating element of the PID temperature control unit is mounted on the bottom of the CXL memory 2DIMM slot to adjust the temperature in real time, and the humidity control of the steam generator can adopt a closed-loop feedback system to prevent condensation short circuits.

[0040] In other embodiments, test module 13 may incorporate a programmable load circuit and a protocol parser, thereby enabling the application of a bias voltage to the CXL memory 2 to simulate overvoltage testing. That is, the test environment may also include the application of a bias voltage.

[0041] It is understandable that, for the corresponding testing environment, the test data may include at least one of the following: temperature data, humidity data, ECC error correction counts, or retraining trigger frequency. In addition, the test data may also include CXL link layer retransmission count statistics and error type classification data, memory access latency distribution histogram and bandwidth fluctuation curve, and PCIe-PHY layer eye diagram quality indicators (amplitude, jitter), etc.

[0042] In some embodiments, please refer to Figure 1 or Figure 2 The test device 1 may also include a storage module 14 connected to the microcontroller 11, which stores the aforementioned test data. Furthermore, the storage module 14 may employ a non-volatile MRAM memory. The storage module 14 can store, in time sequence, all register read / write history records of the CXL memory 2, corresponding microcontroller 11 operation instructions, complete bus data snapshots (e.g., 50ms before and after abnormal events such as CRC errors and timeout retries), and persistent backups of the test progress state machine. The storage module 14 can automatically resume unfinished test items after power failure recovery.

[0043] In some embodiments, please refer to Figure 1 or Figure 2 The test apparatus 1 may also include a display module 15 connected to the microcontroller 11. The display module 15 is used to display the parameters of the test environment and / or the test data. Furthermore, the display module 15 can integrate an interactive topology view, dynamically displaying the currently active channel of the multiplexer module 12 and the corresponding UID identifier of the tested CXL memory 2, a bar chart of the DMA buffer occupancy rate of the FPGA protocol processing module 17, and a heatmap showing the power consumption-performance ratio distribution of each CXL memory 2. The display module 15 can also provide a fault location wizard function; when an anomaly is detected in a certain channel, it can automatically zoom in to display the associated timing waveforms and protocol state machine transition paths.

[0044] In some embodiments, please refer to Figure 1 or Figure 2 The test device 1 may also include a button module 16 connected to the microcontroller 11. The button module 16 is used to manually control the start and stop of the test device 1 or manually set the configuration file for batch testing. The button module 16 may include an emergency stop switch, a multi-rotary encoder, and a combination key. The emergency stop switch is directly connected to the power control pin of the multiplexer module 12. After being triggered, it immediately cuts off the power supply to all tested CXL memory 2. The rotary encoder supports pressure sensing function. The pressure applied determines the parameter adjustment step size. The combination key is used to enter the underlying firmware debugging mode, where customized SMBus data packets can be manually injected.

[0045] Figure 3 This is a structural block diagram of the test device 1 according to the third embodiment of this application.

[0046] In some embodiments, please refer to Figure 3 The test device 1 may also include an FPGA protocol processing module 17, which is connected to the microcontroller 11 via SMBus and to a multiplexer module 12 via a CXL link. The FPGA protocol processing module 17 is used to parse control commands and data packets in the CXL protocol and dynamically adjust communication timing or protocol conversion logic according to the instructions of the microcontroller 11. In this case, a heterogeneous architecture design of MCU+FPGA can achieve low cost, high reliability, and parallel testing capabilities. The FPGA, as the core of protocol processing, provides hardware-level high-speed signal processing capabilities, while the MCU focuses on system management and coordination. The programmable characteristics of the FPGA can adapt to the complexity and flexibility of the CXL protocol, and combined with the MCU's SMBus control layer, the intelligence level of the testing process can be further improved.

[0047] Figure 4 This is a structural block diagram of the test device 1 according to the fourth embodiment of this application.

[0048] In some embodiments, please refer to Figure 4 The testing device 1 may also include a remote management module 18 connected to the microcontroller 11. The remote management module 18 is connected to the server 3 via an Ethernet interface, and the remote management module 18 uploads test data to the server 3 and / or receives configuration files for batch testing from the server 3 via Ethernet. This allows for pre-configuration via the server 3, reducing the problem of insufficient computing power of the microcontroller 11.

[0049] Figure 5 This is a schematic diagram of the structure of the test system according to an embodiment of this application.

[0050] Please see Figure 5This application also provides a testing system for CXL memory 2. The testing system includes a testing device 1 and a server 3 for CXL memory 2 as described in any embodiment of this application. The testing device 1 is connected to the server 3 via Ethernet.

[0051] In other embodiments, the test device 1 is also connected to the server 3 via a local area network.

[0052] In summary, in the test apparatus 1 and test system of this application, a microcontroller 11, combined with a multiplexer module 12 and a test module 13, is used to centrally control and manage multiple test modules 13 or CXL memory 2 via an SMBus bus. The microcontroller 11 sends control commands via SMBus, and the multiplexer module 12 switches the connected test modules 13 or CXL memory 2 according to the commands. The test modules 13 then simulate the test environment or directly obtain test data from the CXL memory 2. In this configuration, dependence on the server 3 can be reduced, the test process can be completed independently, and the consumption of expensive server 3 resources can be reduced, thereby lowering test costs. Simultaneously, the efficient communication of SMBus can improve the real-time performance and accuracy of test data.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.

Claims

1. A testing device for CXL memory, characterized in that, The device includes a microcontroller, a multiplexer module, and a test module. The microcontroller and the multiplexer module are connected via SMBus communication. The multiplexer module is connected via SMBus communication with multiple test modules or multiple CXL memory modules. The test module is used to simulate a test environment and / or acquire test data of the CXL memory based on the control instructions of the microcontroller. The test environment includes at least one of heating, humidification, or applying a bias voltage.

2. The testing apparatus for CXL memory according to claim 1, characterized in that, The test data includes at least one of temperature data, humidity data, ECC error correction count, or retraining trigger frequency.

3. The testing apparatus for CXL memory according to claim 1, characterized in that, It also includes a storage module connected to the microcontroller, the storage module being used to store the test data.

4. The testing apparatus for CXL memory according to claim 1, characterized in that, It also includes a display module connected to the microcontroller, the display module being used to display the parameters of the test environment and / or the test data.

5. The testing apparatus for CXL memory according to claim 1, characterized in that, It also includes a button module connected to the microcontroller, which is used to manually control the start and stop of the test device or to manually set a configuration file for batch testing.

6. The testing apparatus for CXL memory according to claim 1, characterized in that, It also includes a remote management module connected to the microcontroller, the remote management module being connected to the server via an Ethernet interface, and the remote management module uploading the test data to the server and / or receiving configuration files for batch testing from the server via the Ethernet.

7. A testing system for CXL memory, characterized in that, The testing system includes a testing device and a server for CXL memory as described in any one of claims 1 to 6, wherein the testing device is connected to the server via Ethernet.

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