A super capacitor charging and discharging circuit and a power utilization device

Abstract

The application provides a super capacitor charging and discharging circuit and a power utilization device. The charging and discharging circuit comprises a charging circuit and a discharging circuit. The charging circuit comprises an ideal diode controller, a first field effect transistor, a filter circuit, a super capacitor and a current limiting element. The discharging circuit comprises a voltage dividing circuit, a second field effect transistor and a third field effect transistor. The ideal diode controller, the first field effect transistor, the filter circuit, the current limiting element and an external power source are interconnected. The super capacitor, the current limiting element, the voltage dividing circuit, the second field effect transistor and the third field effect transistor are interconnected. In this way, the ideal diode controller is used in the charging circuit to control the opening and closing of the field effect transistor, to prevent backflow and reduce loss and pressure difference. The field effect transistor is also used as a conduction switch in the discharging circuit, to reduce loss and improve system operation stability.

Description

Technical Field

[0001] This application relates to the field of charging and discharging circuit technology, and in particular to a charging and discharging circuit and electrical equipment for a supercapacitor. Background Technology

[0002] To meet the demands of high-temperature operation inside vehicles, the use of supercapacitors as backup power has become the mainstream design for in-vehicle dashcams. Compared to batteries, supercapacitors are more resistant to high temperatures, have a longer lifespan, and offer larger charging and discharging currents. At the same time, the charging and discharging design of supercapacitors has become a key aspect of dashcam circuit design.

[0003] Currently, most dashcam products from various brands use diodes to prevent reverse current in the charging and discharging of supercapacitors. During charging, the diodes generate voltage drops and losses, reducing the voltage difference between the input power supply and the supercapacitor. This results in the supercapacitor not being fully charged (to the same voltage as the input voltage) or taking longer to fully charge. During discharging, the diodes also generate large voltage drops, leading to ineffective losses. Furthermore, when switching to supercapacitor power supply at the moment of external power failure, the system power supply will experience large fluctuations and jumps, which may affect system stability. Utility Model Content

[0004] In view of this, the purpose of this application is to provide a charging and discharging circuit and electrical device for a supercapacitor. By using an ideal diode controller to control the switching of the field-effect transistor in the charging circuit, reverse current is prevented and losses and voltage drop are reduced. In the discharging circuit, a field-effect transistor is also used as a switching switch, which can reduce losses and improve the stability of system operation.

[0005] This application provides a charging and discharging circuit for a supercapacitor, which includes a charging circuit and a discharging circuit. The charging circuit includes an ideal diode controller, a first field-effect transistor, a filter circuit, a supercapacitor, and a current-limiting element; the discharging circuit includes a voltage divider circuit, a second field-effect transistor, and a third field-effect transistor. The first terminal of the ideal diode controller, the drain of the first field-effect transistor, the first terminal of the filter circuit, and the output terminal of the external power supply are interconnected; the second terminal of the ideal diode controller is connected to the gate of the first field-effect transistor; the third terminal of the ideal diode controller, the source of the first field-effect transistor, the second terminal of the filter circuit, the first terminal of the current-limiting element, and the power input terminal of the target system are interconnected; the fourth terminal of the ideal diode controller is grounded; the second terminal of the current-limiting element, the positive terminal of the supercapacitor, and the drain of the second field-effect transistor are connected; the third terminal of the filter circuit is grounded; the negative terminal of the supercapacitor is grounded. The first terminal of the voltage divider circuit, the gate of the second field-effect transistor, and the drain of the third field-effect transistor are interconnected; the second terminal of the voltage divider circuit is grounded; the third terminal of the voltage divider circuit is connected to the output terminal of an external power supply; the source of the second field-effect transistor is connected to the power input terminal of the target system; the gate of the third field-effect transistor is connected to the signal output terminal of the controller; and the source of the third field-effect transistor is grounded.

[0006] Optionally, the ideal diode controller includes: a controller chip, a first resistor, and a second resistor; The first pin of the controller chip is connected to the first end of the first resistor, and the second end of the first resistor is grounded. The third pin of the controller chip, the gate of the first field-effect transistor, and the first end of the second resistor are interconnected, and the second end of the second resistor is grounded. The fourth pin of the controller chip, the source of the first field-effect transistor, the second terminal of the filter circuit, the first terminal of the current limiting element, and the power input terminal of the target system are interconnected. The sixth pin of the controller chip, the drain of the first field-effect transistor, the first terminal of the filter circuit, and the output terminal of the external power supply are interconnected.

[0007] Optionally, the filtering circuit includes: a first capacitor and a second capacitor; The positive terminal of the first capacitor, the first terminal of the ideal diode controller, the drain of the first field-effect transistor, and the output terminal of the external power supply are interconnected, and the negative terminal of the first capacitor is grounded. The positive terminal of the second capacitor, the third terminal of the ideal diode controller, the source of the first field-effect transistor, the first terminal of the current limiting element, and the power input terminal of the target system are interconnected, and the negative terminal of the second capacitor is grounded.

[0008] Optionally, the current-limiting element is a third resistor.

[0009] Optionally, the voltage divider circuit includes a fourth resistor and a fifth resistor; The first terminal of the fourth resistor, the first terminal of the fifth resistor, the gate of the second field-effect transistor, and the drain of the third field-effect transistor are interconnected; The second end of the fourth resistor is grounded, and the second end of the fifth resistor is connected to the output terminal of an external power supply.

[0010] Optionally, the discharge circuit further includes a sixth resistor; The first terminal of the sixth resistor, the gate of the third field-effect transistor, and the signal output terminal of the controller are interconnected; the second terminal of the sixth resistor is grounded.

[0011] Optionally, the discharge circuit further includes a diode; The anode of the diode, the second terminal of the current limiting element, the positive terminal of the supercapacitor, and the drain of the second field-effect transistor are interconnected; The cathode of the diode, the source of the second field-effect transistor, and the power input terminal of the target system are interconnected.

[0012] Optionally, the diode is a Schottky diode.

[0013] Optionally, the first pin of the controller chip is the NC pin; the third pin of the controller chip is the BIAS pin; the fourth pin of the controller chip is the SOURCE pin; and the sixth pin of the controller chip is the DRAIN pin.

[0014] This application also provides an electrical device including any of the above-described charging and discharging circuits.

[0015] This application provides a charging and discharging circuit for a supercapacitor and an electrical device thereof. The charging and discharging circuit includes a charging circuit and a discharging circuit. The charging circuit includes an ideal diode controller, a first field-effect transistor (FET), a filter circuit, a supercapacitor, and a current-limiting element. The discharging circuit includes a voltage divider circuit, a second FET, and a third FET. The first terminal of the ideal diode controller, the drain of the first FET, the first terminal of the filter circuit, and the output terminal of an external power supply are interconnected. The second terminal of the ideal diode controller is connected to the gate of the first FET. The third terminal of the ideal diode controller, the source of the first FET, the second terminal of the filter circuit, and the current-limiting element are connected. The first terminal of the component is interconnected with the power input terminal of the target system; the fourth terminal of the ideal diode controller is grounded; the second terminal of the current limiting component, the positive terminal of the supercapacitor, and the drain of the second field-effect transistor are connected; the third terminal of the filter circuit is grounded; the negative terminal of the supercapacitor is grounded; the first terminal of the voltage divider circuit, the gate of the second field-effect transistor, and the drain of the third field-effect transistor are interconnected; the second terminal of the voltage divider circuit is grounded; the third terminal of the voltage divider circuit is connected to the output terminal of the external power supply; the source of the second field-effect transistor is connected to the power input terminal of the target system; the gate of the third field-effect transistor is connected to the signal output terminal of the controller; the source of the third field-effect transistor is grounded.

[0016] In this design, an ideal diode controller is used at the power input terminal to automatically turn the input power on and off via the MOSFET, preventing reverse power flow. The MOSFET's on-resistance is extremely low, significantly reducing losses and voltage drop, thus improving the supercapacitor's charging speed and capacity. The discharge circuit also uses a MOSFET as the discharge switch, enabling automatic power switching and incorporating a control circuit. When the supercapacitor reaches a certain charge, the system outputs a control signal to directly turn on the corresponding MOSFET, allowing for rapid charging. Since the supercapacitor is connected to the main power supply circuit, it can also act as a filter, greatly optimizing the ripple of the main power circuit and improving system stability. Furthermore, when switching from external power failure to supercapacitor discharge, the corresponding MOSFET is already turned on, allowing the supercapacitor to directly supply power to the system, preventing level jumps and losses during power switching and improving system power supply stability. Simultaneously, the ideal diode controller automatically detects reverse current and turns off the power input MOSFET to prevent current backflow to the input terminal. To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the schematic diagrams of a charging and discharging circuit for a supercapacitor provided in an embodiment of this application; Figure 2 This is a second schematic diagram of the charging and discharging circuit of a supercapacitor provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a charging circuit for a supercapacitor provided in an embodiment of this application; Figure 4 This is a schematic diagram of the discharge circuit of a supercapacitor provided in an embodiment of this application.

[0019] In the diagram: 1-Charging circuit; 2-Discharging circuit; 11-Ideal diode controller; Q1-First field-effect transistor; 12-Filter circuit; P1-Supercapacitor; 13-Current limiting element; 21-Voltage divider circuit; Q2-Second field-effect transistor; Q3-Third field-effect transistor; U1-Controller chip; R1-First resistor; R2-Second resistor; C1-First capacitor; C2-Second capacitor; R3-Third resistor; R4-Fourth resistor; R5-Fifth resistor; R6-Sixth resistor; D1-Diode. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] In the description of the embodiments of this application, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the utility model product is in use. They are only for the convenience of describing the utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the utility model. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0023] In the description of the embodiments of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "connect" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0024] As used herein, the term “and / or” includes any one of the relevant items listed and any combination of any two or more items.

[0025] For ease of description, spatial relation terms such as “above,” “upper,” “below,” and “lower” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. Such spatial relation terms are intended to include not only the orientation depicted in the drawings but also the different orientations of the device during use or operation.

[0026] The terminology used herein is for the purpose of describing various examples only and is not intended to limit this disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms “comprising,” “including,” and “having” enumerate the stated features, quantities, operations, components, elements, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0027] Variations in the shapes shown in the accompanying drawings may occur due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the accompanying drawings, but include changes in shape that may occur during manufacturing.

[0028] The features of the examples described herein can be combined in various ways that will be apparent upon understanding the disclosure of this application. Furthermore, although the examples described herein have various constructions, other constructions are possible, as will be apparent upon understanding the disclosure of this application. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis that they can be implemented by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0029] To meet the demands of high-temperature operation inside vehicles, the use of supercapacitors as backup power has become the mainstream design for in-vehicle dashcams. Compared to batteries, supercapacitors are more resistant to high temperatures, have a longer lifespan, and offer larger charging and discharging currents. At the same time, the charging and discharging design of supercapacitors has become a key aspect of dashcam circuit design.

[0030] Currently, most dashcam products from various brands use diodes to prevent reverse current in the charging and discharging of supercapacitors. During charging, the diodes generate voltage drops and losses, reducing the voltage difference between the input power supply and the supercapacitor. This results in the supercapacitor not being fully charged (to the same voltage as the input voltage) or taking longer to fully charge. During discharging, the diodes also generate large voltage drops, leading to ineffective losses. Furthermore, when switching to supercapacitor power supply at the moment of external power failure, the system power supply will experience large fluctuations and jumps, which may affect system stability.

[0031] Based on this, the present application provides a charging and discharging circuit for a supercapacitor. By using an ideal diode controller to control the switching of the field-effect transistor in the charging circuit, reverse current is prevented and losses and voltage drop are reduced. In the discharging circuit, a field-effect transistor is also used as a switching switch, which can reduce losses and improve the stability of system operation.

[0032] Please see Figures 1 to 4 , Figure 1 This is one of the schematic diagrams of a charging and discharging circuit for a supercapacitor provided in an embodiment of this application; Figure 2 This is a second schematic diagram of the charging and discharging circuit of a supercapacitor provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a charging circuit for a supercapacitor provided in an embodiment of this application; Figure 4 This is a schematic diagram of the discharge circuit of a supercapacitor provided in an embodiment of this application.

[0033] like Figure 1 As shown, the charging and discharging circuit includes a charging circuit 1 and a discharging circuit 2; the charging circuit 1 includes an ideal diode controller 11, a first field-effect transistor Q1, a filter circuit 12, a supercapacitor P1, and a current-limiting element 13; the discharging circuit 2 includes a voltage divider circuit 21, a second field-effect transistor Q2, and a third field-effect transistor Q3; The first terminal of the ideal diode controller 11, the drain of the first field-effect transistor Q1, the first terminal of the filter circuit 12, and the output terminal of the external power supply are interconnected; the second terminal of the ideal diode controller 11 is connected to the gate of the first field-effect transistor Q1; the third terminal of the ideal diode controller 11, the source of the first field-effect transistor Q1, the second terminal of the filter circuit 12, the first terminal of the current-limiting element 13, and the power input terminal of the target system are interconnected; the fourth terminal of the ideal diode controller 11 is grounded; the second terminal of the current-limiting element 13, the positive terminal of the supercapacitor P1, and the drain of the second field-effect transistor Q2 are connected; the third terminal of the filter circuit 12 is grounded; the negative terminal of the supercapacitor P1 is grounded. The first terminal of the voltage divider circuit 21, the gate of the second field-effect transistor Q2, and the drain of the third field-effect transistor Q3 are interconnected; the second terminal of the voltage divider circuit 21 is grounded; the third terminal of the voltage divider circuit 21 is connected to the output terminal of the external power supply; the source of the second field-effect transistor Q2 is connected to the power input terminal of the target system; the gate of the third field-effect transistor Q3 is connected to the signal output terminal of the controller; and the source of the third field-effect transistor Q3 is grounded.

[0034] Furthermore, such as Figure 2 As shown, the discharge circuit 2 further includes a sixth resistor R6; the first end of the sixth resistor R6, the gate of the third field-effect transistor Q3, and the signal output terminal of the controller are interconnected; the second end of the sixth resistor R6 is grounded.

[0035] The discharge circuit 2 further includes a diode D1; the anode of the diode D1, the second terminal of the current limiting element 13, the positive terminal of the supercapacitor P1, and the drain of the second field-effect transistor Q2 are interconnected; the cathode of the diode D1, the source of the second field-effect transistor Q2, and the power input terminal of the target system are interconnected. The diode D1 is a Schottky diode.

[0036] Among them, the Schottky diode is formed by the contact between a metal and an N-type semiconductor to form a metal-semiconductor junction.

[0037] like Figure 3As shown, the ideal diode controller 11 includes: a controller chip U1, a first resistor R1, and a second resistor R2; the first pin of the controller chip U1 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is grounded; the third pin of the controller chip U1, the gate of the first field-effect transistor Q1, and the first end of the second resistor R2 are interconnected, and the second end of the second resistor R2 is grounded; the fourth pin of the controller chip U1, the source of the first field-effect transistor Q1, the second end of the filter circuit 12, the first end of the current limiting element 13, and the power input terminal of the target system are interconnected; the sixth pin of the controller chip U1, the drain of the first field-effect transistor Q1, the first end of the filter circuit 12, and the output terminal of the external power supply are interconnected.

[0038] The first pin of the controller chip U1 is the NC pin; the third pin of the controller chip U1 is the BIAS pin; the fourth pin of the controller chip U1 is the SOURCE pin; the sixth pin of the controller chip U1 is the DRAIN pin; the second pin of the controller chip U1 is the REF pin; and the fifth pin of the controller chip U1 is the NC pin.

[0039] The filter circuit 12 includes: a first capacitor C1 and a second capacitor C2; the positive terminal of the first capacitor C1, the first terminal of the ideal diode controller 11, the drain of the first field-effect transistor Q1, and the output terminal of the external power supply are interconnected, and the negative terminal of the first capacitor C1 is grounded; the positive terminal of the second capacitor C2, the third terminal of the ideal diode controller 11, the source of the first field-effect transistor Q1, the first terminal of the current limiting element 13, and the power input terminal of the target system are interconnected, and the negative terminal of the second capacitor C2 is grounded. The current limiting element 13 is a third resistor.

[0040] Continue to refer to Figure 3 The first pin of the controller chip U1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is grounded. The third pin of the controller chip U1, the gate of the first field-effect transistor Q1, and the first terminal of the second resistor R2 are interconnected, and the second terminal of the second resistor R2 is grounded. The fourth pin of the controller chip U1, the source of the first field-effect transistor Q1, the positive terminal of the second capacitor C2, the first terminal of the third resistor R3, and the power input terminal of the target system are interconnected. The sixth pin of the controller chip U1, the drain of the first field-effect transistor Q1, the positive terminal of the first capacitor C1, and the output terminal of the external power supply are interconnected. The negative terminal of the first capacitor C1 is grounded; the negative terminal of the second capacitor C2 is grounded; the second terminal of the third resistor R3, the positive terminal of the supercapacitor P1, and the drain of the second field-effect transistor Q2 are connected; the negative terminal of the supercapacitor P1 is grounded. like Figure 4 As shown, the voltage divider circuit 21 includes a fourth resistor R4 and a fifth resistor R5; the first end of the fourth resistor R4, the first end of the fifth resistor R5, the gate of the second field-effect transistor Q2, and the drain of the third field-effect transistor Q3 are interconnected; the second end of the fourth resistor R4 is grounded, and the second end of the fifth resistor R5 is connected to the output terminal of an external power supply.

[0041] like Figures 1 to 4 R1 and R2 are resistors matched to the ideal diode controller 11, and their resistance values ​​can be changed to adjust the switching speed of U1. Q1 is a PMOS device at the input terminal. VBAT represents the supercapacitor voltage; R3 is the current-limiting resistor for the supercapacitor, and its resistance value can be changed to adjust the maximum charging current of the supercapacitor; Q2 is a PMOS device capable of handling large currents, and Q3 is a conventional NPN transistor or NMOS; R4 and R5 are used together to control the on / off state of Q2; R6 is the grounding resistor for Q3.

[0042] Therefore, when VIN is input, Q1 automatically turns on, switching to the main power supply VSYS for the system. Capacitors C1 and C2 filter the power supply. VSYS charges the supercapacitor P1 with current limiting through the third resistor R3. Simultaneously, the input power supply VIN and the supercapacitor voltage VBAT are sampled and detected by the ADC of the main control chip. The charging circuit has no voltage drop loss, and the supercapacitor can be fully charged (until VBAT level is the same as VSYS).

[0043] Since the supercapacitor P1 is charged via a voltage difference (the difference between the input voltage and the voltage across the capacitor), when the capacitor reaches a certain charge level, the charging voltage difference decreases, and the supercapacitor P1 charges very slowly. At this point, when the main controller detects that the voltage difference between VIN and VBAT has decreased to a certain range, it outputs a high-level VBAT_CTRL signal to pull the gate (G) of NMOS transistor Q3 high, turning Q3 on. If VIN and VBAT do not meet the judgment condition, Q3 is pulled low through the sixth resistor R6 (or pulled low by the main controller) to turn it off. When Q3 is on, the gate (G) of Q2 is pulled low, Q2 meets the conduction condition, and VBAT is conducted to VSYS through Q2. The supercapacitor is then rapidly charged, and the VBAT voltage reaches VSYS. When the capacitor is fully charged and the external power is off, VBAT is directly output to VSYS for discharge (according to Ohm's law, Q2 has a smaller on-resistance and will not go through the R3 circuit during discharge), so there will be no level jump during power supply switching that would affect system stability; at the same time, when connected to VSYS, the supercapacitor P1 can also act as a filter (the power supply cable at the front end of the recorder is very long - it is wrapped inside the car, and there will be a lot of ripple when the power supply reaches the machine), optimizing the VSYS power supply ripple and improving system stability.

[0044] When the capacitor is not fully charged and VIN is in position, Q3 is not controlled to conduct, and Q2 does not meet the conduction condition. When VIN is de-energized, VBAT is converted to VSYS through the body diode of Q2 and the Schottky diode D1 (D1 can be added when the load current is large, and the theoretical conduction impedance of the diode is smaller than that of R3, so it will not discharge through R3). Since VIN is divided by resistors R5 and R4, the voltage to the G terminal of Q2 is reduced (under normal operation, the voltage division voltage from VIN to the G terminal of Q2 will not meet the conduction condition of Q2). When the supercapacitor voltage VBAT conducts to VSYS, it is easier to meet the conduction condition of Q2, realize fast power supply switching, and reduce the VSYS jump at the moment of power switching.

[0045] In this design, an ideal diode controller is used at the power input terminal to automatically turn the input power on and off via the MOSFET, preventing reverse power flow. The MOSFET's on-resistance is extremely low, significantly reducing losses and voltage drop, thus improving the supercapacitor's charging speed and capacity. The discharge circuit also uses a MOSFET as the discharge switch, enabling automatic power switching and incorporating a control circuit. When the supercapacitor reaches a certain charge, the system outputs a control signal to directly turn on the corresponding MOSFET, allowing for rapid charging. Since the supercapacitor is connected to the main power supply circuit, it can also act as a filter, greatly optimizing the ripple of the main power circuit and improving system stability. Furthermore, when switching from external power failure to supercapacitor discharge, the corresponding MOSFET is already turned on, allowing the supercapacitor to directly supply power to the system, preventing level jumps and losses during power switching and improving system power supply stability. Simultaneously, the ideal diode controller automatically detects reverse current and turns off the power input MOSFET to prevent current backflow to the input terminal.

[0046] In summary, using low-impedance MOS devices as switches for power input and discharge output significantly reduces the voltage drop from the input power supply to the system power supply, improving the charging voltage and speed of the supercapacitor. Furthermore, the addition of control switch circuitry and logic further enhances the speed at which the supercapacitor charges to full voltage. This circuit also avoids losses and jumps during power switching, allowing the supercapacitor to directly supply power to the system and act as a filter, thus optimizing the stability of the input power supply. This design not only prevents reverse power supply but also improves the charging speed and voltage of the supercapacitor, as well as the power supply stability during discharge. It also optimizes the input power supply as a filtering device.

[0047] Furthermore, embodiments of this application also provide an electrical device including any of the above-described charging and discharging circuits.

[0048] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A charge-discharge circuit of a super capacitor, characterized by comprising: The charging and discharging circuit includes a charging circuit and a discharging circuit. The charging circuit includes an ideal diode controller, a first field-effect transistor, a filter circuit, a supercapacitor, and a current-limiting element; the discharging circuit includes a voltage divider circuit, a second field-effect transistor, and a third field-effect transistor. The first terminal of the ideal diode controller, the drain of the first field-effect transistor, the first terminal of the filter circuit, and the output terminal of the external power supply are interconnected; the second terminal of the ideal diode controller is connected to the gate of the first field-effect transistor; the third terminal of the ideal diode controller, the source of the first field-effect transistor, the second terminal of the filter circuit, the first terminal of the current-limiting element, and the power input terminal of the target system are interconnected; the fourth terminal of the ideal diode controller is grounded; the second terminal of the current-limiting element, the positive terminal of the supercapacitor, and the drain of the second field-effect transistor are connected; the third terminal of the filter circuit is grounded; the negative terminal of the supercapacitor is grounded. The first terminal of the voltage divider circuit, the gate of the second field-effect transistor, and the drain of the third field-effect transistor are interconnected; the second terminal of the voltage divider circuit is grounded; the third terminal of the voltage divider circuit is connected to the output terminal of an external power supply; the source of the second field-effect transistor is connected to the power input terminal of the target system; the gate of the third field-effect transistor is connected to the signal output terminal of the controller; and the source of the third field-effect transistor is grounded.

2. The charge and discharge circuit according to claim 1, characterized by, The ideal diode controller includes: a controller chip, a first resistor, and a second resistor; The first pin of the controller chip is connected to the first end of the first resistor, and the second end of the first resistor is grounded. The third pin of the controller chip, the gate of the first field-effect transistor, and the first end of the second resistor are interconnected, and the second end of the second resistor is grounded. The fourth pin of the controller chip, the source of the first field-effect transistor, the second terminal of the filter circuit, the first terminal of the current limiting element, and the power input terminal of the target system are interconnected. The sixth pin of the controller chip, the drain of the first field-effect transistor, the first terminal of the filter circuit, and the output terminal of the external power supply are interconnected.

3. The charge and discharge circuit according to claim 1, wherein The filter circuit includes: a first capacitor and a second capacitor; The positive terminal of the first capacitor, the first terminal of the ideal diode controller, the drain of the first field-effect transistor, and the output terminal of the external power supply are interconnected, and the negative terminal of the first capacitor is grounded. The positive terminal of the second capacitor, the third terminal of the ideal diode controller, the source of the first field-effect transistor, the first terminal of the current limiting element, and the power input terminal of the target system are interconnected, and the negative terminal of the second capacitor is grounded.

4. The charge and discharge circuit according to claim 1, wherein The current-limiting element is a third resistor.

5. The charge and discharge circuit according to claim 1, wherein The voltage divider circuit includes a fourth resistor and a fifth resistor; The first terminal of the fourth resistor, the first terminal of the fifth resistor, the gate of the second field-effect transistor, and the drain of the third field-effect transistor are interconnected; The second end of the fourth resistor is grounded, and the second end of the fifth resistor is connected to the output terminal of an external power supply.

6. The charge and discharge circuit according to claim 1, wherein The discharge circuit also includes a sixth resistor; The first terminal of the sixth resistor, the gate of the third field-effect transistor, and the signal output terminal of the controller are interconnected; the second terminal of the sixth resistor is grounded.

7. The charge and discharge circuit according to claim 1, wherein The discharge circuit also includes diodes; The anode of the diode, the second terminal of the current limiting element, the positive terminal of the supercapacitor, and the drain of the second field-effect transistor are interconnected; The cathode of the diode, the source of the second field-effect transistor, and the power input terminal of the target system are interconnected.

8. The charge and discharge circuit according to claim 7, wherein The diode is a Schottky diode.

9. The charge and discharge circuit according to claim 2, wherein The first pin of the controller chip is the NC pin; the third pin of the controller chip is the BIAS pin; the fourth pin of the controller chip is the SOURCE pin; and the sixth pin of the controller chip is the DRAIN pin.

10. An electric device, characterized by Includes the charging and discharging circuit according to any one of claims 1-9.

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