Integrated gaN power device comprising a pfc and qr flyback controller

Abstract

An electronic assembly. The electronic assembly includes a base, a first semiconductor device attached to the base and having a first gallium nitride (GaN)-based switch having a first gate arranged to control a current flow between a first source and a first drain, a second GaN-based switch having a second source, a second gate coupled to the first gate, and a second drain coupled to the first drain. In one aspect, the electronic assembly further includes a second semiconductor device attached to the base and having a logic circuit coupled to the second source and arranged to detect a magnitude of the current flow, and a drive circuit coupled to the first gate and the second gate, the drive circuit arranged to control on and off states of the first GaN-based switch and the second GaN-based switch.

Description

[0001] Cross-references to related applications

[0002] This application claims U.S. Provisional Patent Application No. 63 / 608,792, filed December 11, 2023, concerning a power factor correction controller circuit and an integrated GaN power device; Chinese Provisional Patent Application No. 202311698842.4, filed December 11, 2023, concerning a package for a high-voltage power device and a package for a high-voltage power device and controller co-package; and Chinese Provisional Patent Application No. 202311698842.4, filed November 11, 2024, concerning a QR flyback controller switch in a DPAK-4L package. Priority is claimed in Chinese Provisional Patent Application No. 202411603967.9, entitled “PACKAGE”, the contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] The described embodiments generally relate to power converters, and more specifically, embodiments of the present invention relate to integrated gallium nitride (GaN) power devices comprising a power factor correction (PFC) controller and / or a quasi-resonant (QR) flyback controller. Background Technology

[0004] Electronic devices (such as computers, servers, and televisions) employ one or more power conversion circuits to convert one form of electrical energy into another. Some power conversion circuits use circuit topologies called DC-DC converters to convert high (or low) DC voltages to lower (or higher) DC voltages. Because many electronic devices are sensitive to the size and efficiency of power conversion circuits, new power converters can offer relatively high efficiency and small size for new electronic devices. Summary of the Invention

[0005] In some embodiments, an electronic component is disclosed. The electronic component includes: a base; a first semiconductor device attached to the base and having: a first gallium nitride (GaN)-based switch having a first gate, a first source, and a first drain, wherein the first gate is arranged to control current flow between the first source and the first drain; a second GaN-based switch having a second source, a second gate, and a second drain, wherein the second gate is coupled to the first gate, and the second drain is coupled to the first drain; a second semiconductor device attached to the base and having: logic circuitry coupled to the second source and arranged to detect the magnitude of the current flow; and driving circuitry coupled to the first gate and the second gate, the driving circuitry being arranged to control the on and off states of the first GaN-based switch and the second GaN-based switch; and an electrically insulating encapsulation that at least partially encapsulates the base, the first semiconductor device, and the second semiconductor device.

[0006] In some implementations, the electronic component further includes a first external terminal coupled to the first drain, a second external terminal coupled to the first source, and a third external terminal coupled to the logic circuit, the third external terminal being arranged to transmit a signal corresponding to the amplitude of the detected current flow.

[0007] In some implementations, the electronic component further includes a resistor coupled to the second source, and wherein the logic circuitry detects a voltage drop across the resistor that is proportional to the magnitude of the current flow.

[0008] In some implementations, the resistor is disposed within the second semiconductor device.

[0009] In some implementations, the driving circuit synchronously controls the on and off states of the first GaN-based switch and the second GaN-based switch.

[0010] In some implementations, the electronic component further includes a fourth external terminal coupled to the logic circuit, wherein the fourth external terminal is arranged to receive a pulse width modulation signal.

[0011] In some implementations, the electronic component further includes a fifth external terminal arranged to receive a power supply.

[0012] In some embodiments, an electronic component is disclosed. The electronic component includes: a first semiconductor device comprising: a first gallium nitride (GaN)-based switch having a first gate, a first source, and a first drain, wherein the first gate is arranged to control current flow between the first source and the first drain; a second GaN-based switch having a second source, a second gate, and a second drain, wherein the second gate is coupled to the first gate, and the second drain is coupled to the first drain; and a second semiconductor device comprising: a driving circuit coupled to the first gate and the second gate, the driving circuit being arranged to control the first GaN-based switch and the second GaN-based switch. The electronic component includes: on and off states of a base switch; logic circuitry arranged to: detect the magnitude of the current flow via a first signal received from the second source; and control the drive circuitry to turn off the first GaN base switch and the second GaN base switch when the detected magnitude of the current flow exceeds a threshold current value; an electrically insulating encapsulation that at least partially encapsulates the first semiconductor device and the second semiconductor device; a first external terminal disposed on the outer surface of the electronic component and coupled to the first drain; and a second external terminal disposed on the outer surface of the electronic component and coupled to the first source.

[0013] In some embodiments, a method of operating an electronic component is disclosed. The method includes: receiving an input signal at a first external terminal; transmitting the input signal to a drive circuit disposed on a first semiconductor device disposed within the electronic component, wherein the drive circuit transmits a first drive signal and a second drive signal in response to receiving the input signal; causing a first gallium nitride (GaN)-based switch to transition between a first on state and a first off state in response to receiving the first drive signal, wherein the first GaN-based switch is disposed on a second semiconductor device disposed within the electronic component, and wherein the first GaN-based switch controls the flow of current between a second external terminal and a third external terminal of the electronic component; causing a second gallium nitride (GaN)-based switch to transition between a second on state and a second off state in response to receiving the second drive signal, wherein the second GaN-based switch is disposed on the second semiconductor device; detecting the amplitude of the current via a detection circuit disposed on the second semiconductor device, wherein the detection circuit is coupled to the second GaN-based switch; and generating an output signal at a fourth external terminal, wherein the output signal corresponds to the amplitude of the current.

[0014] In some implementations, the detection circuit includes a resistor disposed within the first semiconductor device, the resistor being coupled to the fourth external terminal.

[0015] In some implementations, the method further includes detecting the direction of the current via the detection circuit.

[0016] In some implementations, the generated output signal corresponds to the amplitude and direction of the current. Attached Figure Description

[0017] Figure 1A A schematic diagram of a PFC converter using a controller IC with reduced pin count is shown according to some implementation schemes;

[0018] Figure 1B A schematic diagram of an integrated GaN power device including a PFC controller IC and a GaN switch is shown according to some embodiments;

[0019] Figure 2A The following are illustrated according to some implementation schemes. Figure 1A A schematic diagram of the internal circuitry of the PFC controller IC;

[0020] Figure 2B A schematic diagram of the internal circuitry of a PFC controller IC according to certain embodiments is shown;

[0021] Figure 3 This illustrates a method with certain component values ​​according to certain implementation schemes. Figure 1A A schematic diagram similar to that of a PFC converter;

[0022] Figure 4 A schematic diagram of a PFC converter using a controller IC with reduced pin count and employing a capacitive sensing scheme is shown according to some implementation schemes;

[0023] Figure 5 The use of equations is illustrated. Figure 4 Simulation results of PFC operation;

[0024] Figure 6 This illustrates the operation according to some implementation schemes. Figure 1A A simplified flowchart of the method for PFC converter;

[0025] Figure 7 This illustrates the operation according to some implementation schemes. Figure 4 A simplified flowchart of the method for PFC converter;

[0026] Figure 8A An integrated GaN power device 800 according to an embodiment of the present disclosure is shown. Figure 8B An integrated GaN power device in a four-terminal DPAK package according to an embodiment of the present disclosure is shown. Figure 8C An integrated GaN power device 850 according to an embodiment of this disclosure is shown;

[0027] Figures 9A-9C An external view of a surface-mount semiconductor package including a controller and a power switch is shown according to some embodiments;

[0028] Figure 9D-9F An external view of a surface-mount semiconductor package with a high-voltage pin on the right side, according to some embodiments, is shown, the surface-mount semiconductor package containing a controller and a power switch;

[0029] Figure 9G-9I An external view of a surface-mount semiconductor package with top cooling, comprising a controller and a power switch, is shown according to some embodiments.

[0030] Figures 10A-10C An external view of a through-hole semiconductor package including a controller and a power switch is shown according to some embodiments;

[0031] Figure 10D-10F An external view of a through-hole semiconductor package with an encapsulated back pad is shown according to some embodiments, the package including a controller and a power switch;

[0032] Figure 10G-10I An external view of a through-hole semiconductor package with a high-voltage pin on the right side, according to some embodiments, is shown, the package containing a controller and a power switch;

[0033] Figure 11A-11B An external view of a slotted surface-mount semiconductor package according to some embodiments is shown, the package including a controller and a power switch;

[0034] Figure 11C-11D An external view of a slotted surface-mount semiconductor package with a high-voltage pin on the right side, according to some embodiments, is shown, the package containing a controller and a power switch;

[0035] Figure 12A-12B An external view of a slotted through-hole semiconductor package according to some embodiments is shown, the package including a controller and a power switch;

[0036] Figure 12C-12D An external view of a slotted and back-enclosed through-hole semiconductor package according to some embodiments is shown, the package comprising a controller and a power switch;

[0037] Figure 12E-12F An external view of a slotted through-hole semiconductor package with a high-voltage pin on the right side, according to some embodiments, is shown, the package containing a controller and a power switch;

[0038] Figure 13AAn internal view of a surface-mount package containing a controller and a power switch, according to some embodiments, is shown. Figure 13B A schematic diagram of an integrated GaN power device including a drive circuit and a GaN switch is shown according to some embodiments. Figure 13C The following are illustrated according to some implementation schemes. Figure 13B A schematic diagram of an integrated GaN power device and controller. Figure 13D The following are illustrated according to some implementation schemes. Figure 13A The package shown is a top view of the package.

[0039] Figure 14 An internal view of a through-hole semiconductor package with a controller and a power switch is shown according to some embodiments;

[0040] Figure 15 An internal view of a surface-mount semiconductor package having a QR flyback controller and a power switch according to some embodiments is shown;

[0041] Figure 16 An internal view of a through-hole semiconductor package with a QR flyback controller and a power switch according to some embodiments is shown;

[0042] Figures 17A-17C An external view of a surface-mount semiconductor package including a controller and a power switch, according to some embodiments, is shown;

[0043] Figures 18A-18B An external view of a slotted surface-mount semiconductor package according to some embodiments is shown, the surface-mount semiconductor package including a controller and a power switch;

[0044] Figure 19 A schematic diagram of a QR flyback converter using a semiconductor package to house a GaN power switch, according to some embodiments, is shown.

[0045] Figure 20 A schematic diagram of a PFC converter using a semiconductor package to house a GaN power switch, according to some embodiments, is shown.

[0046] Figure 21 A schematic diagram of a PFC converter using a semiconductor package to house a GaN power switch with a PFC controller, according to some embodiments, is shown.

[0047] Figure 22 A schematic diagram of a QR flyback converter that uses an integrated GaN power device in a semiconductor package to co-package a first semiconductor device and a second semiconductor device, according to some embodiments, is shown.

[0048] Figure 23Schematic diagrams and circuit techniques are shown, according to some embodiments, for determining the current sensing resistor value and overvoltage / undervoltage operating conditions using a multi-functional external terminal; and

[0049] Figure 24 A schematic diagram of an integrated GaN power device comprising a flyback controller IC and a GaN-based die, according to some embodiments, is shown. Detailed Implementation

[0050] The circuits, devices, and related technologies disclosed herein generally relate to power converters. More specifically, the circuits, devices, and related technologies disclosed herein relate to integrated gallium nitride (GaN) power devices that include a PFC controller, a QR flyback controller, and / or a primary / secondary side controller used in the power converter. In some embodiments, a PFC controller circuit with reduced pin count is disclosed. The PFC controller circuits and technologies disclosed herein may include a sensing method in which a sensed voltage at the drain terminal of the PFC switch is multiplexed to a feedback pin of the PFC controller IC, thereby enabling a reduction in the pin count of the controller IC. Based on the sensed drain terminal voltage, embodiments of this disclosure can extract information about the input voltage (Vin) of the PFC converter, the output voltage (Vout) of the PFC converter, and the zero-current moment when the PFC inductor current becomes zero. Furthermore, the valley during quasi-resonant ringing can be sensed using the disclosed multiplexing scheme. Therefore, embodiments of this disclosure can multiplex all these functions to the feedback (FB) pin of the controller IC, thereby reducing the pin count and saving space.

[0051] In some implementations, a capacitive coupling scheme can be used to sense the drain voltage of the PFC switch, where the drain voltage of the PFC switch can be transmitted and multiplexed to the feedback (FB) pin of the controller IC. In various implementations, an inductive coupling scheme can be used, where an auxiliary winding is coupled to a boost inductor, and the auxiliary winding injects an AC signal from the boost inductor across the feedback (FB) pin voltage. In some implementations, the controller IC may include various protection detection circuitry to keep the power converter in its safe operating region, as summarized herein and described in more detail below.

[0052] In some embodiments, the PFC controller IC can be co-packaged with a GaN power switch in a semiconductor package to form an integrated GaN power device, wherein the integrated GaN power device can reduce the pin count and can be used in PFC converter circuitry. In various embodiments, the integrated GaN power device can have, for example, five terminals. In some embodiments, circuitry and methods for operating a PFC converter utilizing gallium nitride (GaN) and / or silicon carbide (SiC) power switches are disclosed, wherein the PFC converter can have a relatively high operating frequency. In various embodiments, the controller IC can be formed from silicon, silicon carbide, GaN, or any other suitable semiconductor material. In various embodiments, the integrated GaN power device can be used in high-current and / or high-voltage power conversion applications, such as, but not limited to, AC-to-DC converters, and applications such as solar energy conversion, automotive, and battery charging applications.

[0053] In some implementations, the integrated GaN power device may include a primary-side controller and a GaN-based main switch, wherein the integrated GaN power device can be used on the primary side of a flyback converter and / or for a quasi-resonant (QR) flyback converter. The circuitry and techniques disclosed herein enable the co-packaging of a QR flyback controller IC and a GaN-based switch in a pin-reduced semiconductor package, such as, but not limited to, the DPAK-4L package. In some implementations, circuitry on the silicon die can be arranged to detect gate drive signals, current sensing information, temperature, and various other operating parameters, and to generate protection signals for the GaN-based power switch. Furthermore, the silicon die can be electrically coupled to low-voltage signal pins via wire bonding and / or clips to obtain power supply, gate drive signals, current sensing information, overcurrent and overtemperature protection, enable signals, or various other signals.

[0054] In various implementations, the integrated GaN power device can include a secondary-side controller and a synchronous rectifier GaN-based switch, wherein the integrated GaN power device can be used on the secondary side of a flyback converter and / or a quasi-resonant (QR) flyback converter. The integrated GaN power device can use a semiconductor package to co-package the GaN-based switch and controller, where the package can be relatively simpler, with fewer pins and fewer external components. Thermal performance can be better than comparable quad flat no-lead (QFN) packages. Furthermore, the disclosed integrated GaN power device can be used in power conversion applications with a relatively wide power range. Additionally, the disclosed integrated GaN power device package is suitable for wave soldering processes.

[0055] In some implementations, integrated GaN power devices can include current sensing and various protection features within the semiconductor package. Integrated GaN power devices can reduce the size of printed circuit boards (PCBs) and improve the efficiency of power converters. In current methods using QFN or similar packages, external pins are used for current sensing, gate drive, and power supply pins. Furthermore, external pins can be used for internal voltage regulator outputs and / or switching speed adjustment. Therefore, the packaging cost in current methods can be relatively high. Additionally, reflow soldering processes may be used in current methods, but these are relatively expensive, increasing system manufacturing costs.

[0056] In some embodiments, the semiconductor package may be a surface-mount package, which may include a high-voltage pin, one or more low-voltage pins, and metal die pads exposed on the back of the package. The high-voltage pin and the metal die pads on the back of the package may be power supply pins, and the low-voltage pins may be signal pins. The function of the signal pins may be, but is not limited to, power supply, gate drive, current sensing, overcurrent protection, overtemperature protection, and / or enable. In various embodiments, a minimum gap of 1 mm may be used between the high-voltage pin and the adjacent low-voltage pin.

[0057] In some embodiments, the disclosed semiconductor package may be a through-hole package, which may include a high-voltage power supply pin, a low-voltage power supply pin, and one or more low-voltage signal pins. The metal die pads on the back of the package may be exposed or encapsulated with encapsulating material. In various embodiments, a minimum gap of 1 mm may be used between the high-voltage pin and the adjacent low-voltage pin. The function of the signal pin may be, but is not limited to, power supply, gate drive, current sensing, overcurrent protection, overtemperature protection, and / or enable. In some embodiments, a slot may be added between the high-voltage pin and the low-voltage pin to increase the high-voltage creepage distance.

[0058] In various implementations, a semiconductor package can be used to integrate one or more dies with a high-voltage power switch and one or more silicon dies with protection features and control circuitry. The drain terminal of the high-voltage power switch can be electrically coupled to a high-voltage pin of the semiconductor package via one or more wire bonds and / or clips, and the source terminal can be electrically coupled to a metal die pad or a low-voltage pin via one or more wire bonds or clips. The silicon die can be electrically coupled to the die of a high-voltage power device via wire bonds and / or clips. The circuitry on the silicon die can detect gate drive signals, current sensing information, temperature, and various other operating parameters, and generate protection signals for the high-voltage power switch. Furthermore, the silicon die can be electrically coupled to low-voltage signal pins via wire bonds and / or clips to obtain power supply, gate drive signals, current sensing information, overcurrent and overtemperature protection, enable signals, or various other signals.

[0059] The embodiments disclosed herein can be used in a co-package of a high-voltage power switch and a controller IC. The semiconductor package can integrate one or more dies with high-voltage power devices and a silicon controller die, such as a quasi-resonant (QR) flyback converter controller IC. The drain terminal of the high-voltage power switch can be electrically coupled to a high-voltage pin of the semiconductor package via one or more wire bonds or clips, and the source terminal can be electrically coupled to a metal die pad or a low-voltage power supply pin via one or more wire bonds and / or clips. The silicon controller die can be electrically coupled to the die of the high-voltage power switch via multiple wire bonds, thereby enabling sensing / detection of gate drive signals, current sensing signals, temperature, and various other operating parameters. Furthermore, the silicon controller IC die can be electrically coupled to a low-voltage signal pin via wire bonds to obtain power supply, feedback signals, auxiliary winding signals, current sensing, and various other signals.

[0060] In various implementations, semiconductor packages can be used to provide encapsulation for GaN-based switches with a reduced number of terminals. In some implementations, the package may include a high-voltage drain terminal, a low-voltage input signal terminal, a low-voltage current sensing terminal, and a low-voltage power supply terminal. Metal die pads may be used as source terminals.

[0061] In some embodiments, the disclosed semiconductor package can have a relatively small thickness, for example, less than 2 mm. In this way, the semiconductor package may not be the thickest component on the board and may not limit the size of the enclosure. Various inventive embodiments are described herein, including methods, processes, systems, apparatus, etc.

[0062] Several exemplary embodiments are now described with respect to the accompanying drawings, which form part of the embodiments. The following description provides embodiments only and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of the embodiments will provide those skilled in the art with a description of what is possible for implementing one or more embodiments. It should be understood that various changes may be made in terms of the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for illustrative purposes to provide a thorough understanding of certain embodiments of the invention. However, it will be apparent, however, that various embodiments may be practiced without these specific details. The drawings and description are not intended to be limiting. The words “example” or “exemplary” are used herein to mean “serves as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” or “example” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0063] Figure 1A A schematic diagram of a PFC converter 100 using a controller IC with reduced pin count, according to some embodiments, is shown. Figure 1AIn this circuit, an auxiliary inductor can be used to sense various currents and voltages. In some implementations, the PFC converter can be a PFC boost converter. The PFC converter 100 may include a controller IC 102. The controller IC 102 may have six pins, including a Vcc pin 104, a GND pin 106, a COMP pin 108, a DRV pin 114, a CS pin 112, and an FB / ZCD / Vin pin 110. The PFC converter 100 may also include a switch 116 having a drain terminal 118, a gate terminal 120, and a source terminal 122. The DRV pin 114 may be coupled to the gate terminal 120 and arranged to provide a drive signal to the gate of the switch 116 to control the on state of the switch 116. The CS pin 112 may be coupled to the source terminal 122, wherein the source terminal 122 may be coupled to a current sensing resistor 124. The CS pin 112 may be arranged to receive a signal corresponding to the current flowing through the switch 116. The GND pin can be coupled to ground node 126.

[0064] Vcc pin 104 can be coupled to capacitor 128. COMP pin 108 can be coupled to compensation network 158, which may include resistor 162 coupled in series with capacitor 164, wherein resistor 162 and capacitor 164 are connected in series and the combination is coupled in parallel with capacitor 166. FB / ZCD / Vin pin 110 can be coupled to node 130 and can be arranged to receive a feedback signal indicating the drain voltage at drain terminal 118, a zero-current detection signal indicating when the current flowing through boost inductor 142 becomes zero, and a Vin voltage indicating the input voltage at node 148. These signals are multiplexed to FB / ZCD / Vin pin 110, thus reducing the number of pins on controller IC 102. Output terminal 146 can be connected to feedback circuit 154. In some embodiments, feedback circuit 154 may be a resistor divider that includes a first feedback resistor Rfb1 connected to a second feedback resistor Rfb2. Feedback circuit 154 can be used to sense the voltage Vout at output terminal 146 and generate a corresponding voltage at node 130, wherein the corresponding voltage at node 130 can be fed back to controller IC 102 through FB / ZCD / Vin pins.

[0065] The PFC converter 100 may also include an auxiliary inductor 140 magnetically coupled to the boost inductor 142, wherein the auxiliary inductor 140 may be arranged to sense and generate a signal at node 130 corresponding to the value of the Vin voltage at node 148. The auxiliary inductor 140 may also generate a signal corresponding to the direction of the current flowing through the boost inductor 142. The auxiliary inductor 140 may also sense the voltage at the drain terminal 118 and provide the sensed drain terminal voltage to node 130. All this information can be fed back to the controller IC 102 via the FB / ZCD / Vin pin 110.

[0066] The PFC converter 100 may also include a rectifier circuit 152. The rectifier circuit 152 may be coupled between the input AC line voltage and node 148. The rectifier circuit 152 may be arranged to provide a filtered full-wave rectified voltage Vin between the power supply AC line and node 148. The rectifier circuit 152 may provide I through the boost inductor 142, switch 116, and current sensing resistor 124. L During operation, switch 116 can reduce the drain terminal voltage to ground, and boost inductor 142 can adjust according to I... L It establishes its magnetic field and stores energy.

[0067] During operation, alternating current can generate a varying magnetic flux in the boost inductor 142, which can cause a change in the alternating voltage across the boost inductor 142. During the on-time, the controller IC 102 can provide a positive drive voltage on the gate terminal 120 of the switch 116. Therefore, the switch 116 can be turned on and provide a low-impedance current path for the boost inductor 142. The rectifier circuit 152 can provide Io through the boost inductor 142, the switch 116, and the current sensing resistor 124. L In this way, switch 116 can reduce the voltage at drain terminal 118 to ground, and boost inductor 142 can adjust according to I... L It establishes its magnetic field and stores energy.

[0068] During the on-time, the current-sensing resistor 124 can provide a voltage at node 170, which is proportional to the current flowing through switch 116. When controller IC 102 turns on switch 116, the drain-source voltage of switch 116 may be relatively small. The voltage on CS pin 112 can be equal to the voltage across the current-sensing resistor 124. The internal processing circuitry of controller IC 102 can compare the voltage on CS pin 112 with an overcurrent protection threshold. If the voltage on CS pin 112 exceeds the overcurrent protection threshold, controller IC 102 can turn off switch 116.

[0069] During the off-time, controller IC 102 can turn off switch 116, which provides a high-impedance current path at node 149. In response, boost inductor 142 can resist I0. L The voltage at node 149 can be adjusted and operated to increase the voltage at node 149. Diode 144 can be switched on and supply I to output terminal 146. L The large-capacity capacitor 174 can store charge to smooth the output voltage across the load and filter high-frequency voltage transitions across the load.

[0070] The FB / ZCD / Vin pin 110 can be configured to operate as a multi-functional input terminal to sense various voltages and currents, including a feedback signal indicating the drain voltage at drain terminal 118, a zero-current detection signal indicating when the current flowing through boost inductor 142 becomes zero, and a Vin voltage indicating the input voltage at node 148. An auxiliary inductor 140 can be magnetically coupled to boost inductor 142, wherein the auxiliary inductor 140 can be configured to inject an AC signal above the voltages at FB / ZCD / Vin. The controller IC 102 can use these voltages and currents to detect various conditions, including overcurrent, demagnetization phase, power-down, and overvoltage, and adjusts its operation accordingly when the current flowing through boost inductor 142 becomes zero (ZCD). Details of how the internal circuitry of controller IC 102 extracts various voltage and current information from the FB / ZCD / Vin pins will be provided in [reference needed]. Figure 2A A more detailed description follows. By using the FB / ZCD / Vin pins as multi-function pins (pins can also be referred to as terminals), the number of pins can be reduced to implement the controller IC 102. Therefore, the PFC converter 100 can reduce costs.

[0071] Feedback circuit 154 can receive the output voltage Vout and can provide a portion of Vout to the FB / ZCD / Vin pin 110. This portion can be determined by the ratio of resistors Rfb1 and Rfb2. Controller IC 102 can use the voltage on the FB / ZCD / Vin pin 110 to adjust the duty cycle of the gate drive signal at the DRV pin 114. Furthermore, controller IC 102 can compare the voltage at the FB / ZCD / Vin pin 110 with a threshold voltage. When the voltage at the FB / ZCD / Vin pin 110 exceeds this threshold, controller IC 102 can detect the overvoltage condition and turn off the drive signal to the gate terminal 120.

[0072] The controller IC 102 can use the signal at the FB / ZCD / Vin pin 110 to adjust the duty cycle of the DRV signal at the DRV pin 114. The compensation network 158 can be used to adjust the modulation bandwidth to regulate the DRV signal at the DRV pin 114. In some implementations, vL = Ldi / dt.

[0073] Figure 1B A schematic diagram of an integrated GaN power device comprising a PFC controller IC and a GaN switch, according to some embodiments, is shown. In the illustrated embodiment, a semiconductor package 180 may be used to integrate a GaN-based switch 184 and a silicon-based PFC controller IC 182. The silicon-based PFC controller IC 182 may be similar to... Figure 1A The controller IC 102 is included. In some embodiments, the GaN-based switch 184 may be a silicon-based switch or a silicon carbide-based switch. The semiconductor package 180 may include a source lead 181 coupled to the source terminal of the GaN-based switch 184 and a drain lead 183 coupled to the drain terminal of the GaN-based switch 184. The PFC IC 182 may have a gate drive terminal 186 (DRV) that can be coupled to the gate terminal of the GaN-based switch 184. The ground node 188 of the PFC IC 182 may be coupled to the source terminal of the GaN-based switch 184. The semiconductor package 180 may also include a power supply lead 190 (Vcc) coupled to the power supply terminal of the PFC controller IC. In addition, the semiconductor package 180 may include a multi-function lead 192 that can be coupled to the multi-function terminal (FB / ZCD / Vin) of the PFC IC. The semiconductor package 180 may also include a lead 194 coupled to the COMP terminal of the PFC controller. The PFC controller IC may have an SNSFET terminal 196 that is coupled to the current sensing terminal of a GaN-based switch.

[0074] The SNSFET terminal 196 of the PFC controller IC can be arranged to receive a signal from the GaN-based switch 184 indicating the magnitude and / or direction of the current flowing through the GaN-based switch 184. In some embodiments, the PFC controller IC may include a current sensing (CS) pin. In various embodiments, the CS pin may remain floating, while in alternative embodiments, the CS may be coupled to the GaN-based switch to detect the current flowing through the GaN-based switch.

[0075] The controller IC 182 can be electrically coupled to the die of the GaN-based switch 184 via wire bonding and / or clips. The circuitry on the silicon die can detect gate drive signals, current sensing information, temperature, and various other operating parameters, and generate protection signals for high-voltage power switches. Furthermore, the silicon die can be electrically coupled to low-voltage signal pins via wire bonding and / or clips to obtain power supply, gate drive signals, current sensing information, overcurrent and overtemperature protection, enable signals, or various other signals.

[0076] Figure 2A A schematic diagram of the internal circuitry of a controller IC 102 according to some embodiments is shown. In some embodiments, the controller IC 102 may include processing circuitry. Figure 2A The circuitry and techniques for extracting various information from signals multiplexed to FB / ZCD / Vin pin 110 are illustrated. For example... Figure 2A As shown, the FB / ZCD / Vin pin 110 can be coupled to an averaging circuit 202 and a sampling circuit 204. In some embodiments, the sampling circuit 204 may include a sample-and-hold circuit. Both the sampling circuit 204 and the averaging circuit 202 can be coupled to a summing circuit 210. The output of the summing circuit 210 can be coupled to node 212. The averaging circuit 202 can provide a voltage at node 208 corresponding to the average value of the voltages on the FB / ZCD / Vin pin. During the on-time (T-on), the sampling circuit 204 can sample the voltage at the FB / ZCD / Vin pin 110 to obtain a voltage corresponding to Vin and provide the sampled voltage value at node 206. Subsequently, the actual value of the Vin voltage can be obtained by subtracting the sampled value at node 206 from the voltage value at node 208 using the summing circuit 210. The actual value of Vin is provided at node 212.

[0077] Using the FB / ZCD / Vin pin 110, a zero-current detection (ZCD) method can be implemented to detect current I. L When does it become zero? For example... Figure 2AAs shown, the FB / ZCD / Vin pins can also be coupled to delay circuit 214 and to the first input of comparator 216. In some embodiments, the delay circuit may include resistor 232 coupled to capacitor 234. The output of delay circuit 214 may be coupled to the second input of comparator 216. Comparator 216 may have an output terminal coupled to node 218. To determine when the boost inductor current becomes zero, comparator 216 can be used to compare the voltage at FB / ZCD / Vin pin 110 with a delayed (or slowed) version of the voltage at FB / ZCD / Vin pin 110 to determine when the pin voltage deviates from its delayed version. The time when comparator 216 determines that the voltage has sufficiently deviated can be used as the moment when the inductor current has reached zero or substantially zero.

[0078] Pin 110 of the FB / ZCD / Vin series can also be used to detect overvoltage conditions on the output voltage. For example... Figure 2A As shown, the output of the averaging circuit 202 can also be coupled to comparator 240. Comparator 240 can be arranged to compare the output of the averaging circuit 202 with a first reference voltage and provide a soft overvoltage protection signal. The output of the averaging circuit 202 can also be coupled to comparator 242. Comparator 242 can be arranged to compare the output of the averaging circuit 202 with a second reference voltage and provide a fast overvoltage protection signal. In some embodiments, the values ​​of the first reference voltage and the second reference voltage can be substantially the same. The output of the summing circuit 210 can be coupled to comparator 244. Comparator 244 can be arranged to compare the output of the summing circuit with a third reference voltage and provide a power-down signal. In various embodiments, the value of the third reference voltage can be the same as the first reference voltage and / or the second reference voltage. The FB / ZCD / Vin pin 110 can also be coupled to comparator 246. Comparator 246 can be arranged to compare the voltage at the FB / ZCD / Vin pin 110 with a fourth reference voltage to provide a power-down signal. A power-down condition may occur when the input voltage of the power converter drops below a predetermined threshold voltage.

[0079] The advantage of the embodiments disclosed herein is the absence of transients associated with RC charging. Furthermore, the embodiments disclosed herein enable PFC converters with lower operating power losses. Voltage sampled from the auxiliary winding provides real-time information and can significantly reduce calculation errors.

[0080] Figure 2BA schematic diagram of the internal circuitry of a controller IC 102 according to certain embodiments is shown. In this embodiment, the controller IC 102 may include a multifunction input terminal FB / ZCD / Vin 250, a COMP input terminal 253, a CS input terminal 255, an SNSFET input terminal 259, a DRV output terminal 261, a GND terminal 265, and a V... cc Terminal 267. In some implementations, the controller IC 102 may only include the multifunction input terminal FB / ZCD / Vin 250, COMP input terminal 253, CS input terminal 255, DRV output terminal 261, GND terminal 265, and V. cc Terminal 267. In various embodiments, the controller IC 102 can be used as a standalone IC with a PFC converter. In some embodiments, the controller IC 102 can be formed by all input and output terminals; however, when the controller is used alone in a PFC circuit, some terminals, such as the SNSFET input terminal 259, can remain floating. In some embodiments, the controller IC 102 can be co-packaged with a power switch in a semiconductor package. In various embodiments, the power switch can be GaN-based, silicon-based, or silicon carbide-based. When the controller and power switch are co-packaged in a semiconductor package, the CS input terminal can remain floating. In some embodiments, whether the input and output terminals remain floating can depend on the specific application and can be changed according to user settings.

[0081] The FB / ZCD / Vin input terminal 250 can be coupled to the error amplifier 252, the feedback (FB) generator circuit 254, the Vin generator circuit 256, and the V... out Sampler circuit 258, zero-current detection (ZCD) circuit 260, and adaptive valley detection circuit 262. In some implementations, V out Sampler circuit 258 may include sample-and-hold circuitry. The COMP input terminal 253 and the output node of error amplifier 252 may be coupled to summing circuit 270. The output node of summing circuit 270 may be coupled to the input node of comparator 272. In some embodiments, comparator 272 may be an amplifier circuit. COMP input terminal 253 may also be coupled to frequency foldback circuit 274.

[0082] The output node of frequency foldback circuit 274 can be coupled to PWM logic circuit 276. The output node of comparator 272 can be coupled to PWM logic circuit 276. The output node of clock generation circuit 278 can also be coupled to PWM logic circuit 276. CS input terminal 255 and SNSFET input terminal 259 can be coupled to circuit 282 (GaNSense), which can be arranged to generate overcurrent protection (VOCP), overstress protection (OSP), and saturation protection (SAT) signals. These signals can be used to protect the power switch and ensure that the power switch operates within its safe operating area (SOA). The output node of circuit 282 can be coupled to protection logic circuit 284, where the output node of protection logic circuit 284 can be coupled to PWM logic circuit 276. The output node of PWM logic circuit 276 can be coupled to drive circuit 286. The output node of drive circuit 286 can be coupled to DRV output terminal 261. DRV output terminal 261 can be coupled to the gate terminal of the power switch.

[0083] The Vin generator circuit 256 may include a delay circuit, a sampling circuit, and a summing circuit. The FB generator circuit 254 may include an averaging circuit. The averaging circuit can be used to extract Vout information. The averaging circuit can provide the Vin generator circuit 256 with a signal corresponding to the average value of the voltage at the FB / ZCD / Vin input terminals 250. During the on-time (T-on), the sampling circuit can sample the voltage at the FB / ZCD / Vin input pins 250 to obtain the voltage corresponding to Vin. Subsequently, the actual value of the Vin voltage can be obtained by subtracting the sampled value from the signal provided by the Vin generator circuit 256. The actual value of Vin is provided at node VIN_INT.

[0084] Using the FB / ZCD / Vin input terminal 250, the zero-current detection (ZCD) method can be used to detect current I. L When does it become zero? The FB / ZCD / Vin input terminal 250 can also be coupled to a ZCD circuit 260. The ZCD circuit may include a delay circuit and a comparator circuit. The ZCD circuit 260 can be arranged to determine when the boost inductor current becomes zero. In some embodiments, the ZCD circuit can be arranged to compare the voltage at the FB / ZCD / Vin input terminal 250 with a delayed (or slowed) version of the voltage at the FB / ZCD / Vin input terminal 250 to determine when the input voltage deviates from its delayed version. The time when the ZCD circuit determines that the voltage has sufficiently deviated can be used as the moment when the inductor current has reached zero or substantially zero.

[0085] The FB / ZCD / Vin input terminal 250 can also be used to detect overvoltage conditions on the output voltage. An FB generator circuit 254 can be arranged to generate an FB_INT signal 259, which can be based on a feedback (FB) signal received at the multifunction terminal 250. The FB_INT signal 259 can be transmitted to a protection logic circuit 284, and used by the protection logic circuit 284 to generate various protections, such as overvoltage protection (soft overvoltage, fast overvoltage) as well as power-down and boost protection. The output of the protection logic circuit 284 can be transmitted to a PWM logic circuit 276 for processing, and a drive signal is generated accordingly. A Dynamic Response Enhancement (DRE) circuit 287 can be arranged to receive the FB_INT signal 259 (generated by the FB generator circuit), which can be based on the feedback (FB) signal received at the multifunction terminal 250. The Dynamic Response Enhancement (DRE) circuit 287 can be arranged to generate a DRE signal 289, which can be used by a compensation circuit (COMP) to enhance the charging speed of a compensation network arranged as a compensation loop.

[0086] The PWM logic circuit 276 can be arranged to receive various signals from various circuits within the controller IC 102. The PWM logic circuit 276 can be arranged to provide a drive signal in response to receiving a first voltage that represents a voltage proportional to the output voltage of the power converter circuit at the FB / ZCD / Vin input terminals 250 and in response to receiving a second voltage that represents a current proportional to the current flowing through the auxiliary inductor 140.

[0087] Figure 3 This illustrates a method with certain component values ​​according to certain implementation schemes. Figure 1A A similar schematic diagram is shown. In the illustrated implementation, the following equations can be used to derive VFB_ZCD:

[0088]

[0089] During the switching cycle, the average voltage of VFB_ZCD can be VFB, which can be used as feedback for the output voltage Vout. During the PWM on-time, the input voltage VIN can be extracted by subtracting the VFB voltage from VFB_ZCD. The embodiments of this disclosure can use the VFB voltage level and VFB_ZCD to perform the valley switching action.

[0090] During the cutoff period, the VFB_ZCD voltage provides a snapshot of the VOUT voltage, which can be sampled and extracted in the same way as Vin. In some cases, this information can be used for another type of overvoltage protection. This information is not delayed by the average information delay, and therefore can be used for fast-response Vout overvoltage protection scenarios.

[0091] Figure 4 A schematic diagram of a PFC converter 400 using a controller IC with reduced pin count and employing a capacitive sensing scheme is shown according to some implementation schemes. Figure 4 and Figure 1A Similarly, but instead of using an auxiliary winding, a sensing capacitor 402 can be used to sense the voltage at the drain terminal of switch 116 and transmit the sensed voltage to the FB / ZCD / Vin pin 110. In the illustrated embodiment, the value of VFB_ZCD can be determined using the following equation:

[0092]

[0093] vDS AC =vDS-VIN <vDS AC >=0

[0094] vDS AC | PWMON =0-VIN=-VIN

[0095] Figure 5 The simulation results using the above equations are shown. The blue waveform shows the waveform at the FB_ZCD node, while the red waveform shows the voltage across the drain of switch 116. The average voltage of the blue waveform is marked by a blue dashed line centered at 2.5V. During the on-time, the green double arrows indicate the drop in the blue waveform, and the increment of the average value shows that the amplitude is proportional to Vin.

[0096] Figure 6 This is a simplified flowchart illustrating a method 600 for operating a PFC converter 100 having a controller IC 102 according to some embodiments. Refer to Figures 1-2 and... Figure 6Method 600 includes a controller IC (610) providing terminals with multiplexed FB / ZCD / Vin signals. The method also includes an auxiliary inductor (620) magnetically coupled to a boost inductor of a PFC converter. The method further includes sensing a voltage at the drain terminal of a switch of the PFC converter using the auxiliary inductor and transmitting the sensed voltage to the FB / CD / Vin terminal of the controller IC (630). The method also includes sensing the output voltage (Vout) of the PFC converter and transmitting the sensed voltage to the FB / ZCD / Vin terminal (640). The method further includes multiplexing the sensed output voltage and the signal from the auxiliary inductor at the FB / ZCD / Vin terminal of the controller IC (650). Furthermore, the method includes sampling the sensed signal from the auxiliary inductor using a sample-and-hold circuit (660). The method also includes averaging the sensed signal from the auxiliary inductor using an averaging circuit (670). The method further includes determining the actual value of Vin by subtracting the sampled value from the average value (680). The method further includes using a delay circuit to delay the signal at the FB / ZCD / Vin terminals and transmitting the delayed signal to a first comparator (690). The method further includes using the first comparator and the delayed signal to detect the presence of zero current (ZCD) in the boost inductor (692). The method further includes using a second comparator to detect overvoltage conditions (694). The method further includes using a third comparator to detect power-down conditions (696). The method further includes using a fourth comparator to detect boost conditions (698).

[0097] It should be understood that Figure 6 The specific steps shown provide a concrete method for operating a PFC converter circuit with a controller IC according to an embodiment of this disclosure. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of this disclosure may perform the steps outlined above in a different order. Furthermore, Figure 6 The steps shown may contain multiple sub-steps, which may be performed in various orders as needed by each step. Furthermore, depending on the specific application, other steps may be added or removed. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0098] Figure 7This is a simplified flowchart illustrating a method 700 for operating a PFC converter 400 having a controller IC 102 according to some embodiments. Referring to Figures 2 and 4, method 700 includes providing a controller IC (710) with terminals having multiplexed FB / ZCD / Vin signals. The method also includes providing a sensing capacitor (720) coupled to the drain terminal of a PFC switch of the PFC converter. The method further includes sensing the voltage at the drain terminal of the switch of the PFC converter using the sensing capacitor and transmitting the sensed voltage to the FB / CD / Vin terminal of the controller IC (730). The method also includes sensing the output voltage (Vout) of the PFC converter and transmitting the sensed voltage to the FB / ZCD / Vin terminal (740). The method further includes multiplexing the sensed output voltage and a signal from an auxiliary inductor at the FB / ZCD / Vin terminal of the controller IC (750). Furthermore, the method includes sampling the signal sensed from the auxiliary inductor using a sample-and-hold circuit (760). The method further includes averaging the signal sensed from the auxiliary inductor using an averaging circuit (770). The method further includes determining the actual value of Vin by subtracting the sampled value from the average value (780). The method further includes delaying the signal at the FB / ZCD / Vin terminals using a delay circuit and transmitting the delayed signal to a first comparator (790). The method further includes detecting the presence of zero current (ZCD) in the boost inductor using the first comparator and the delayed signal (792). The method further includes detecting overvoltage conditions using a second comparator (794). The method further includes detecting power-down conditions using a third comparator (796). The method further includes detecting boost conditions using a fourth comparator (798).

[0099] It should be understood that Figure 7 The specific steps shown provide a concrete method for operating a PFC converter circuit with a controller IC according to an embodiment of this disclosure. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of this disclosure may perform the steps outlined above in a different order. Furthermore, Figure 7 The steps shown may contain multiple sub-steps, which may be performed in various orders as needed by each step. Furthermore, depending on the specific application, other steps may be added or removed. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0100] PFC controller co-packaged with power switch

[0101] Figure 8A An integrated GaN power device 800 according to an embodiment of this disclosure is shown. Figure 8AAs shown, the integrated GaN power device 800 can include a GaN power transistor 814 and a controller IC 812 within a semiconductor package 828. By integrating the GaN power transistor 814 and the controller IC 812 into the semiconductor package 828, the pin count can be reduced, and most package parasitic components can be eliminated, thereby allowing the use of the integrated GaN power device 800 in high-current and high-power applications. Furthermore, the integrated GaN power device in the semiconductor package saves PCB area and can reduce system costs. In some embodiments, the semiconductor package can be, for example, but not limited to, DPACK4.

[0102] The integrated GaN power device 800 may include a drain terminal 802, a source terminal 804, a Vcc terminal 806, a COMP terminal 808, and an FB terminal 810. In some embodiments, the ground node may be a backplane of a semiconductor package. The source terminal of the GaN power transistor 814 may be coupled to the source backplane via multiple wire bonds 818. The drain terminal of the GaN power transistor 814 may be coupled to the drain terminal 802 of the semiconductor package via multiple wire bonds 816. The gate terminal of the GaN power transistor 814 may be coupled to the controller IC 812 via a wire bond 820. Wire bonds 820, 840, and the intermediate wire bond may be used to drive the gate terminal of a GaN power switch, or to drive a power-off FET that can keep the gate terminal of the GaN switch low during the off-time, or to obtain a signal from the gate terminal of the GaN switch during the off-time, and may have a signal from the GaN die providing a current signal proportional to the current in the main GaN switch to perform a "current limiting" function. In various implementations, the order and / or use of these connections can vary depending on the configuration of the GaN die. The ground node of the controller IC 812 can be connected to the same L-shaped pad on the top of the package to which the source bond line is connected. This connection may be exposed at the upper right of the package.

[0103] The Vcc pin of controller IC 812 can be coupled to Vcc terminal 806 via lead bond 846. The COMP pin of controller IC 812 can be coupled to COMP terminal 808 via lead bond 844. The FB pin of controller IC 812 can be coupled to FB terminal 810 via lead bond 842. The ground of controller IC 812 can be coupled to package ground via lead bond 848. In the illustrated embodiment, current sensing (CS) functionality can be built into the integrated GaN power device 800 (with a fine-tuning option), and the current sensing threshold is pre-adjusted on the controller. In some embodiments, lead bond 824 can be another connection from the GaN die to the source / GND node. In various embodiments, lead bond 824 can be used or not, depending on the configuration of the GaN die used. In some embodiments, lead bond 824 can be used as a ground connection for any auxiliary circuitry system, such as a "power-off" circuitry system in the GaN die. In various implementations, wire bonding 824 may not be used. In various implementations, alternative attachment techniques may be used instead of wire bonding.

[0104] In some embodiments, controller IC 812 may be identical to controller IC 102 previously described. In various embodiments, controller IC 812 can control and drive GaN power transistor 814. Furthermore, controller IC 812 may include various features for driving GaN power transistor 814 and features for keeping GaN power transistor 814 within its safe operating region. Those skilled in the art will understand that controller IC 812 can be used to drive GaN high electron mobility transistors (HEMTs) and other power transistors, such as, but not limited to, silicon carbide transistors, isolated gate bipolar transistors (IGBTs), and silicon MOSFETs. Figure 8B An integrated GaN power device in a four-terminal DPAK package according to an embodiment of the present disclosure is shown.

[0105] Figure 8CAn integrated GaN power device 850 according to an embodiment of this disclosure is shown. The integrated GaN power device 850 may include a drain terminal 852, a source terminal 854, a Vcc terminal 856, a COMP terminal 858, and an FB / ZCD terminal 860. The integrated GaN power device 850 is similar to the integrated GaN power device 800, but with different pin functions. In the integrated GaN power device 850, the controller IC and the GaN power device can be angled within the semiconductor package. In this manner, the connection wire bonds can be shorter, thereby reducing parasitic inductance and capacitance that may be associated with the wire bonds. Therefore, the integrated GaN power device 850 can operate at higher operating frequencies and with relatively reduced ringing. In various embodiments, the connection wire bonds can be replaced by other attachment techniques, such as, but not limited to, copper strips and / or copper clips.

[0106] Integrated GaN power devices

[0107] Figures 9A-9C An external view of a surface-mount semiconductor package including a controller and power switches is shown according to some embodiments. In some embodiments, the package may include one or more power switches. Figures 9A-9C The front, side, and bottom views of the surface mount package are shown respectively. In this embodiment, pin 1 may be a high-voltage pin, pins 2, 3, and 4 may be three low-voltage pins, and the back of the package may have exposed metal die pads 5. Pin 1 and the metal pads 5 on the back may be power pins, and low-voltage pins 2, 3, and 4 may be signal pins. In some embodiments, the spacing 902 between the high-voltage pin 1 and the low-voltage pin 2 may be greater than, for example, 1 mm. In some embodiments, the spacing 902 may be, for example, 1.2 mm, while in other embodiments, the spacing 902 may be between 0.8 mm and 1.1 mm, and in yet another embodiment, the spacing may be between 0.9 mm and 1.05 mm. As will be understood by those skilled in the art who benefit from this disclosure, the spacing 902 may be set to any suitable value.

[0108] Figure 9D-9F An external view of a surface-mount semiconductor package with a high-voltage pin on the right side, according to some embodiments, is shown. The surface-mount semiconductor package includes a controller and a power switch. In some embodiments, the package may include one or more power switches.

[0109] Figure 9G-9I An external view of a surface-mount semiconductor package with top cooling, comprising a controller and power switches, is shown according to some embodiments. In some embodiments, the package may contain one or more power switches.

[0110] Figures 10A-10C An external view of a through-hole semiconductor package including a controller and power switches is shown according to some embodiments. In some embodiments, the package may include one or more power switches. Figures 10A-10C The front, side, and bottom views of the package are shown respectively. In this embodiment, pin 1 may be a high-voltage pin, and pins 2, 3, and 4 may be three low-voltage pins. A metal die pad 5 may be present on the back of the package. In some embodiments, the metal pad 5 may be exposed. In various embodiments, the metal pad 5 may be encapsulated with some encapsulating material. High-voltage pin 1 and low-voltage pin 2 may be power supply pins, and low-voltage pins 3 and 4 may be signal pins. In some embodiments, the spacing 902 between high-voltage pin 1 and low-voltage pin 2 may be greater than, for example, 1 mm. In some embodiments, the spacing 902 may be, for example, 1.2 mm, while in other embodiments, the spacing 902 may be between 0.8 mm and 1.1 mm, and in yet another embodiment, the spacing may be between 0.9 mm and 1.05 mm. As will be understood by those skilled in the art who benefit from this disclosure, the spacing 902 may be set to any suitable value.

[0111] Figure 10D-10F An external view of a through-hole semiconductor package with encapsulated back pads is shown according to some embodiments, the package including a controller and a power switch. In some embodiments, the package may include one or more power switches.

[0112] Figure 10G-10I An external view of a through-hole semiconductor package with a high-voltage pin on the right side is shown according to some embodiments. The package includes a controller and a power switch. In some embodiments, the package may include one or more power switches.

[0113] Figure 11A-11B An external view of a slot-mount semiconductor package is shown according to some embodiments, the package including a controller and a power switch. In some embodiments, the package may include one or more power switches. Figure 11A-11B The front and bottom views of a surface-mount package with a slot are shown respectively. This package is... Figures 9A-9C The package is similar, but a slot 1110 with a width of a and a depth of b is added between the high-voltage pin 1 and the low-voltage pin 2. This slot (or recess) can increase the high-voltage creepage distance between the high-voltage pin and the low-voltage pin.

[0114] Figure 11C-11DAn external view of a slotted surface-mount semiconductor package with a high-voltage pin on the right side is shown according to some embodiments. The package includes a controller and a power switch. In some embodiments, the package may include one or more power switches.

[0115] Figure 12A-12B An external view of a slotted through-hole semiconductor package is shown according to some embodiments, the package including a controller and a power switch. In some embodiments, the package may include one or more power switches. Figure 12A-12B The front and bottom views of the package are shown respectively. This package is related to... Figures 10A-10B The package is similar, but a slot 1210 with a width of a and a depth of b is added between the high-voltage pin 1 and the low-voltage pin 2. This slot (or recess) can increase the high-voltage creepage distance between the high-voltage pin and the low-voltage pin.

[0116] Figure 12C-12D An external view of a slotted and back-enclosed through-hole semiconductor package according to some embodiments is shown, the package comprising a controller and a power switch. In some embodiments, the package may include one or more power switches.

[0117] Figure 12E-12F An external view of a slotted through-hole semiconductor package with a high-voltage pin on the right side is shown according to some embodiments. The package includes a controller and a power switch. In some embodiments, the package may include one or more power switches.

[0118] Figure 13AAn internal view of a surface-mount package including a controller and a power switch is shown according to some embodiments. In some embodiments, the package may include one or more power switches. In the illustrated embodiment, an integrated high-voltage power switch disposed on a first semiconductor device 1302 is co-packaged with a second semiconductor device 1304 having controller circuitry using a semiconductor package. In some embodiments, the first semiconductor device 1302 may include a high-voltage gallium nitride (GaN)-based switch, while the second semiconductor device 1304 may be silicon-based. In some embodiments, the controller circuitry may include drive circuitry. The controller circuitry may integrate sampling / detection and protection functions. The first semiconductor device 1302 with the GaN-based switch can be mounted on a relatively large die pad 5 using, for example, conductive adhesive. The second semiconductor device 1304 can be mounted to the die pad 5, for example, using non-conductive or conductive adhesive. The drain terminal of the high-voltage GaN-based switch can be coupled to a high-voltage external pin 1 via one or more wire bonds 1306 or clips. The source terminals of the high-voltage GaN-based switch can be coupled to pads 1308 and 1314 via one or more wire bonds 1310 and 1312 or clips, which can be plated on die pad 5. In some embodiments, pads 1308 and 1314 may be silver-plated. Low-voltage external terminal 2 can be used for Vcc, low-voltage external terminal 3 can be used for PWM, and low-voltage external terminal 4 can be used for current sensing (CS) connection.

[0119] Figure 13B A schematic diagram of an integrated GaN power device including a driver circuit and a GaN switch is shown according to some embodiments. In the illustrated embodiments, a semiconductor package 1380 may be used to integrate a first semiconductor device 1384 and a second semiconductor device 1382. In some embodiments, the first semiconductor device 1384 may be a GaN-based die. In various embodiments, the second semiconductor device 1382 may be a silicon-based die having a driver IC 1398. The first semiconductor device 1384 may include a first GaN-based switch 1372 having a first source, a first gate, and a first drain, and a second GaN-based switch 1374 having a second source, a second gate, and a second drain. In some embodiments, the first gate may be coupled to the second gate, and the first drain may be coupled to the second drain. In various embodiments, the first GaN-based switch may be a first transistor, and the second GaN-based switch may be a second transistor.

[0120] Semiconductor package 1380 may include an external source terminal 1381, an external drain terminal 1383, a current source (CS) terminal 1396, an external PWM terminal 1392, and an external power supply (VDD) terminal 1390. A first source terminal may be coupled to the external source terminal 1381. A first drain terminal and a second drain terminal may be coupled to the external drain terminal 1383. Driver IC 1398 may have a gate drive terminal 1386 (DRV) that may be coupled to the first gate terminal and the second gate terminal. Ground node 1388 may be coupled to the external source terminal 1381. External power supply terminal 1390 may be coupled to the power supply terminal of driver IC 1398. Driver IC 1398 may have a current sensing (CS) terminal 1396 coupled to the second source terminal. Driver IC 1398 may include an over-temperature protection circuit 1369, a green mode circuit 1367, and an EMI management control circuit 1365. In some implementations, the ground node of the driver IC can be connected to the die pad.

[0121] The CS terminal 1396 can be arranged to receive a signal from the second GaN-based switch 1374 indicating the amplitude and / or direction of the current flowing through the first GaN-based switch 1372. In some embodiments, the driver IC 1398 may include an amplifier 1397 coupled to the CS terminal. In various embodiments, a current-sensing resistor 1389 may be coupled between the input of the amplifier 1397 and ground. In some embodiments, the amplifier 1397 may be a comparator. The output of the amplifier 1397 may be coupled to logic circuitry 1399, which is arranged to control signals entering the driver circuitry 1395. The driver circuitry may be coupled to a first gate and a second gate. In some embodiments, the CS amplifier 1397 may sense the current from the FET 1374 and accordingly generate a proportionally amplified current that can flow out of the CS external terminal 1396.

[0122] The first semiconductor device 1384 can be coupled to the second semiconductor device 1382 via wire bonding and / or clips. In some embodiments, circuitry on the second semiconductor device can be arranged to detect gate drive signals, current sensing information, temperature, and various other operating parameters, and to generate protection signals for high-voltage power switches. The second semiconductor device can be electrically coupled to low-voltage signal pins via wire bonding and / or clips.

[0123] The second semiconductor device 1304 can be coupled to the first semiconductor device 1302 via one or more wire bonds 1316, 1318, and 1326 or clips. Controller circuitry on the second semiconductor device 1304 can be arranged to detect the current flowing through the GaN-based switch. In some embodiments, the controller circuitry can be arranged to detect the operating temperature or other operating parameters of the GaN-based switch. In various embodiments, the controller circuitry can be arranged to transmit power supply voltage, gate drive signal, over-temperature protection signal, over-current protection signal, and / or enable signal to the GaN-based switch on the first semiconductor device 1302. The second semiconductor device 1304 can be coupled to three low-voltage external pins 2, 3, and 4 via wire bonds 1324, 1322, and 1320 or via clips. External power supply voltage, gate drive signal, current sensing information, or other signals can be transmitted to the first semiconductor device 1302 via these three pins. Each of the first semiconductor device 1302 and the second semiconductor device 1304, as well as all wire bonds, can be at least partially encapsulated with an electrically insulating encapsulant. In some implementations, the back side of the die pad 5 may be exposed.

[0124] Figure 13C The following are illustrated according to some implementation schemes. Figure 13B A schematic diagram of an integrated GaN power device and its controller is shown. In the illustrated embodiment, the controller circuit 1363 can be arranged to send a PWM signal to the integrated GaN power device 1361.

[0125] Figure 13D The following are illustrated according to some implementation schemes. Figure 13A The package shown is a top view of the package.

[0126] Figure 14An internal view of a through-hole semiconductor package with a controller and a power switch is shown according to some embodiments. In some embodiments, the package may contain one or more power switches. In the illustrated embodiment, an integrated high-voltage power switch disposed on a first die 1402 is co-packaged with controller circuitry disposed on a second die 1404 using a semiconductor package. In some embodiments, die 1402 may contain a high-voltage gallium nitride (GaN)-based switch, while die 1404 may be silicon-based. The controller circuitry may integrate sampling / detection and protection functions. Die 1402 with the high-voltage GaN-based switch can be mounted to a relatively large die pad 5 using, for example, conductive adhesive, and die 1404 can be mounted to die pad 5, for example, using non-conductive or conductive adhesive. The drain terminal of the high-voltage GaN-based switch can be electrically coupled to a high-voltage pin 1 via one or more wire bonds 1406 or clips. The source terminal of the high-voltage GaN-based switch can be electrically coupled to silver pads 1408 and 1414 via one or more wire bonds 1410 and 1412 or clips, which can be plated on die pad 5. In some embodiments, the low-voltage power supply pin 2 can be directly connected to die pad 5. Die 1404 and the GaN-based switch can be electrically coupled via one or more wire bonds 1416, 1418, and 1426 or via clips. Controller circuitry on silicon die 1404 can be arranged to detect the current, temperature, or other operating parameters of the GaN-based switch via these wire bonds and to transmit power supply voltage, gate drive signal, over-temperature protection signal, over-current protection signal, and / or enable signal to the GaN-based switch on die 1402. Die 1404 can be electrically coupled to two low-voltage pins 3 and 4 via wire bonds 1422 and 1420, respectively. External power supply voltage, gate drive signal, current sensing information, or other signals can be transmitted to die 1404 via these three pins. Die 1402, die 1404, and all wire bonds may be encapsulated, at least partially, with an electrical insulating encapsulant.

[0127] Figure 15An internal view of a surface-mount semiconductor package with a QR flyback controller and a power switch is shown according to some embodiments. In some embodiments, the package may contain one or more power switches. In the illustrated embodiment, an integrated high-voltage power switch disposed on a first die 1502 is co-packaged with a QR flyback controller circuit disposed on a second die 1504 using a semiconductor package. In some embodiments, die 1502 may contain a high-voltage gallium nitride (GaN)-based switch, while die 1504 may be silicon-based. The controller circuit may integrate sampling / detection and protection functions. Die 1502 with the high-voltage GaN-based switch can be mounted to a relatively large die pad 5 using, for example, conductive adhesive, and die 1504 can be mounted to die pad 5, for example, using non-conductive or conductive adhesive. The drain terminal of the high-voltage GaN-based switch can be electrically coupled to a high-voltage pin 1 via one or more wire bonds 1506 or clips. The source of the GaN-based switch can be electrically coupled to a silver pad 1508, which can be plated onto the die pad 5 via one or more wire bonds 1510 or clips. In some embodiments, dies 1504 and 1502 can be electrically coupled via a number of single wire bonds 1512, 1526, 1518, and 1516 or via clips. Die 1504 can be arranged to detect current, temperature, or other operating parameters of the GaN-based switch via these wire bonds and to transmit power supply voltage, gate drive signal, protection signal, or enable signal to the GaN-based switch. Die 1504 can be electrically coupled to three low-voltage pins 2, 3, and 4 via wire bonds 1524, 1522, and 1520 or via clips, respectively. External power supply voltage, current sensing information, feedback signal, auxiliary winding voltage, or other signals can be transmitted to die 1504 via these three pins. Die 1502, die 1504, and all wire bonds may be encapsulated, at least partially, with an electrical insulating encapsulant.

[0128] Figure 16An internal view of a through-hole semiconductor package with a QR flyback controller and a power switch is shown according to some embodiments. In some embodiments, the package may contain one or more power switches. In the illustrated embodiment, an integrated high-voltage power switch disposed on a first die 1602 is co-packaged with QR flyback controller circuitry disposed on a second die 1604 using a semiconductor package. In some embodiments, die 1602 may contain a high-voltage gallium nitride (GaN)-based switch, while die 1604 may be silicon-based. The controller circuitry may integrate sampling / detection and protection functions. Die 1602 with the high-voltage GaN-based switch can be mounted to a relatively large die pad 5 using, for example, conductive adhesive, and die 1604 can be mounted to die pad 5, for example, using non-conductive or conductive adhesive. The drain terminal of the high-voltage GaN-based switch can be electrically coupled to a high-voltage pin 1 via one or more wire bonds 1606 or clips. The source of the GaN-based switch can be electrically coupled to a silver pad 1608, which can be plated onto the die pad 5 via one or more wire bonds 1610 or clips. In some embodiments, the low-voltage power supply pin 2 can be directly connected to the die pad 5. The die 1604 and the GaN-based switch can be electrically coupled via one or more wire bonds 1612, 1626, 1618, and 1616 or via clips. Controller circuitry on the silicon die 1604 can be arranged to detect the current, temperature, or other operating parameters of the GaN-based switch via these wire bonds and to transmit power supply voltage, gate drive signal, over-temperature protection signal, over-current protection signal, and / or enable signal to the GaN-based switch on the die 1602. The die 1604 can be electrically coupled to two low-voltage pins 3 and 4 via wire bonds 1622 and 1620, respectively. External power supply voltage, gate drive signal, current sensing information, or other signals can be transmitted to the die 1604 via these three pins. Die 1602, die 1604, and all wire bonds may be encapsulated, at least partially, with an electrical insulating encapsulant.

[0129] Figures 17A-17C An external view of a surface-mount semiconductor package including a controller and power switches is shown according to some embodiments. In some embodiments, the package may include one or more power switches. Figures 17A-17CThe front, side, and bottom views of the surface mount package are shown respectively. In this embodiment, pin 1 may be a high-voltage pin, pins 2, 3, and 4 may be three low-voltage pins, and the back of the package may have exposed metal die pads 5. Pin 1 and the metal pads 5 on the back may be power pins, and low-voltage pins 2, 3, and 4 may be signal pins. In some embodiments, the spacing 1702 between the high-voltage pin 1 and the low-voltage pin 2 may be greater than, for example, 1 mm. In some embodiments, the spacing 1702 may be, for example, 1.2 mm, while in other embodiments, the spacing 1702 may be between 0.8 mm and 1.1 mm, and in yet another embodiment, the spacing may be between 0.9 mm and 1.05 mm. As will be understood by those skilled in the art who benefit from this disclosure, the spacing 1702 may be set to any suitable value.

[0130] Figures 18A-18B An external view of a slotted surface-mount semiconductor package according to some embodiments is shown, the package including a controller and a power switch. In some embodiments, the package may include one or more power switches. Figures 18A-18B The front and bottom views of the surface mount package are shown respectively. In the illustrated embodiment, a slot (or recess) 1810 with a width of a and a depth of b may be included between the high-voltage pin 1 and the low-voltage pin 2. In this way, the creepage distance between the high-voltage pin and the low-voltage pin can be increased.

[0131] Figure 19 A schematic diagram of a QR flyback converter using a semiconductor package to house a GaN power switch is shown according to some embodiments. In the illustrated embodiment, semiconductor package 1905 may include a GaN switch, wherein semiconductor package 1905 may have a low-voltage pin current sensing (CS), an input pin that can be arranged as a pulse width modulation (PWM) signal, a low-voltage power supply, a high-voltage drain pin, and a package back side for coupling the source terminal to ground. Furthermore, an integrated GaN device 1915 connected to the secondary side may include the GaN switch and an SR controller. The GaN switch can be used as a synchronous rectifier switch on the secondary side.

[0132] Figure 20A schematic diagram of a PFC converter using a semiconductor package to house a GaN power switch is shown according to some embodiments. In the illustrated embodiment, the semiconductor package 2005 may contain a GaN switch serving as the PFC switch, wherein the semiconductor package 2005 may have a low-voltage pin current sensing (CS), an input pin that can be arranged as a pulse width modulation (PWM) signal, a low-voltage power supply, a high-voltage drain pin, and a back side of the package for coupling the source terminal to ground. A controller 2010, similar to controller 102, may be coupled to the semiconductor package 2005, wherein the controller 2010 may be arranged to control the on / off state of the GaN switch.

[0133] Figure 21 A schematic diagram of a PFC converter using a semiconductor package to house a GaN power switch with a PFC controller is shown according to some embodiments. In the illustrated embodiment, the semiconductor package 2120 may include a GaN switch serving as a PFC switch and a PFC controller, wherein the semiconductor package 2120 may have low-voltage pins VDD, COMP, and FB / VIN / ZCD (as described in the PFC controller section), a high-voltage drain pin, and a back side of the package for coupling the source terminal to ground.

[0134] QR flyback controller packaged with power switch

[0135] Figure 22A schematic diagram is shown of a QR flyback converter that uses an integrated GaN power device in a semiconductor package to co-package a first semiconductor device and a second semiconductor device, according to some embodiments. According to some embodiments, semiconductor package 2220 may include a first semiconductor device having a first GaN-based switch and a second GaN-based switch, and a second semiconductor device having a silicon-based controller IC. In the QR flyback converter circuit 2200, semiconductor package 2220 may include a GaN-based die and controller circuitry. In some embodiments, the controller circuitry may include over-temperature protection circuitry, over-current protection circuitry, over-voltage / under-voltage protection circuitry, and GaN main switch current sensing circuitry. Semiconductor package 2220 may have a low-voltage pin 2234 (labeled "VDD") for power supply, a low-voltage pin 2232 (labeled "DMAG") serving as a multi-function pin, a low-voltage pin 2240 (labeled "FB") for feedback, a high-voltage drain pin 2236, and a package backside 2238 for coupling the source terminal to ground. In some implementations, the semiconductor package 2220 may include exposed / extended thermal pads for the source terminals and / or ground. The VDD pin 2234 can be used for power supply to the controller IC, the FB pin 2240 can be used for CV loop feedback via a parallel regulator, and the DMAG pin 2232 can be used for valley switch detection, as well as for indirect Vin (input voltage) and Vo (output voltage) detection and protection, and can also be used to determine the built-in current sensing resistor (R). CS The value of ). In this way, compared with using a separate controller circuit and a separate power switch, the semiconductor package 2220 can reduce the number of pins used for operation, thereby achieving system savings, improved reliability and increased power density of the power converter.

[0136] The circuitry and techniques disclosed herein determine the value of a built-in current-sensing resistor within a semiconductor package 2220, where this value can be used to determine the amplitude and / or direction of the current flowing through a first GaN-based switch. The amplitude and / or direction of the current flow can be used to determine the appropriate gate drive for the gate terminal of the first GaN-based switch. A controller IC may have a current-sensing (CS) terminal that can be coupled to a second GaN-based switch. The sensed amplitude and / or direction of the current flow through the first GaN-based switch can be used to adjust the drive signal entering the gate of the first GaN-based switch and for peak current control. The controller circuitry may also include a DRV terminal coupled to the gates of both the first and second GaN-based switches. The gate drive voltage at the DRV terminal can be adjusted based on the sensed current of the first GaN-based switch and used to optimize the gate drive voltage via a built-in EMI control circuitry system (EMI optimizer).

[0137] By co-packaging the GaN power switch with the controller IC, the semiconductor package 2220 can reduce pin count and the number of external components used in the system. Reducing external components can lower system cost, decrease system size, increase power density, and improve reliability. In some implementations, the semiconductor package can be the DPAK 4L, which offers improved thermal performance compared to QFN. In various implementations, the DPAK semiconductor package can reduce the operating temperature by 5-10°C.

[0138] The QR flyback converter circuit 2200 may include resistors 2224 and 2226 coupled between the auxiliary winding 2230 and ground 2239. The QR flyback converter circuit 2200 may also include a diode 2222 coupled to a first terminal of resistor 2228, wherein the anode of diode 2222 may be coupled to the auxiliary winding 2230. The second terminal of resistor 2228 may be coupled to node 2241. Node 2241 may be coupled to the multifunction DMAG pin 2232. The anode of diode 2222 may be coupled to the VDD pin 2234 via diode 2248. Resistors 2224, 2228, and diode 2222 may increase the secondary path from the DMAG pin 2232 to the auxiliary winding 2230.

[0139] The QR flyback converter circuit 2200 can be configured to use the DMAG pin to detect the Vin voltage. For Vin voltage detection, the voltage at the DMAG pin can be clamped to zero by the controller IC. When the PWM is on, current can be forced from the DMAG pin 2232 to resistors 2228 and 2224 to detect Vin, where the amplitude of Vin can be determined by I... DMAG*Z21 is given. Z21 is the impedance of resistors 2228, 2224, and diode 2222 as seen from node 2241 towards node 2258. The QR flyback converter circuit 2200 can also be arranged to detect Vout by determining the voltage (VDMAG) at the DMAG pin. When the PWM is off and during the current discharge cycle, VDMAG can be given by Vaux*Z12 / (Z12+R2)=Vo*Na / Ns*Na / Np. Vaux is the voltage at node 2258, Z12 is the impedance of diode 2222, resistor 2224, and resistor 2228 as seen from node 2258 towards node 2241, Na is the number of turns in the auxiliary winding, and Ns is the number of turns in the secondary winding. The QR flyback converter circuit 2200 can use the detected Vin and Vout to provide overvoltage or undervoltage protection for the power converter and shut down the GaN main switch in the event of an overvoltage / undervoltage condition. In some implementations, the controller can force current out of the DMAG pin (IDMAG) and can measure the effective impedance Rdmag_EFF at the DMAG pin. Once Rdmag_EFF is determined, the value of the internal current sensing resistor Rcs can be determined using a lookup table.

[0140] In some implementations, the resistance value of the built-in current sensing resistor Rcs can be determined using diode 2222, resistor 2228, and the DMAG pin. To determine the built-in Rcs value, the value of Z21 can be determined using Z21 = (2224 / / 2226). This can be achieved by forcing current out of the DMAG pin 2232. Based on the effective resistance detected at the DMAG pin, the value of Rcs can be determined using a lookup table according to the value of Z21. In some implementations, determining Vin may involve: node 2258 = -|Vaux1|, VDMAG = 0V, and the current forced out of the DMAG pin can flow through resistor 2224. The magnitude of this current can be given by |Vaux1| / resistor 2224. This current can correspond to the Vin voltage. In various implementations, determining Vout may involve: the voltage at node 2258 = +|Vaux2|, where VDMAG is a resistor divider between Z12 and resistor 2226, representing the output voltage.

[0141] In some implementations, the user can select the values ​​of resistors 2224 and 2226 to set the threshold setpoint for overcurrent protection (OCP). During startup, current source 2414 can increase the current delivered to the DMAG pin until the voltage at comparator 2416 reaches the Vref voltage. Comparator 2416 can then transmit a signal to Rcs determination circuit 2428. Rcs determination circuit can receive the signal from current source 2414 (i.e., the Rcs determination circuit can receive a signal that comparator 2416 has tripped) and the voltage at the DMAG pin, and can accordingly determine the value of the equivalent parallel resistors (Z21 and / or Z12). Rcs determination circuit can use a lookup table with the determined value of the equivalent parallel resistors to determine the value of current sensing Rcs resistor 2424. The determined Rcs resistor value can be used in the overcurrent protection (OCP) circuit to set the OCP threshold, for example, 8A. The logic circuit can then adjust the value of resistor 2424 (Rcs) to an appropriate resistance value so that when the current through GaN-based switch 2402 reaches a threshold (e.g., 8A), the current-sensing comparator trips and shuts off the DRV signal. In this way, controller 2498 can fine-tune the OCP threshold using a defined effective resistance value at the DMAG pin.

[0142] Example:

[0143] DMAG resistor settings for R1, R2, and R3

[0144]

[0145] In some implementations, the method for determining the built-in value of the current sensing resistor Rcs may include: 1) For each power cycle, sensing the effective impedance Rdmag_EFF at the DMAG pin once. Rdmag_EFF can be used to determine the value of the current sensing resistor Rcs. Current can be forced out of the DMAG pin, and the voltage at node 2241 can be measured. Next, cycle-by-cycle operation may include steps 2A and 2B: 2A) When the PWM is on, the voltage at node 2241 is forced to zero, and current is forced out of the DMAG pin and measured to determine the voltage value (Vaux) at node V2258. 2B) When the PWM is off, current is forced out of the DMAG pin. The current value can be increased by a known value, such as 100μA, 150μA, 200μA, 250μA, etc. When the voltage at the input is greater than the Vref value (e.g., 0.5V), the effective impedance at the DMAG pin is recorded.

[0146] In some implementations, a secondary-side semiconductor package 2225 may be used, wherein the semiconductor package 2225 may contain a GaN switch, which serves as a synchronous rectifier switch and is co-packaged with the synchronous rectifier controller circuitry.

[0147] Figure 23 Alternative schematic diagrams illustrating the determination of the Rdmag_EFF value according to some implementation schemes are shown. Figure 23 In this QR flyback converter, an auxiliary winding 2330, resistors 2324 (R1), 2326 (R2), 2328 (R3), and diode 2322 may be included. In this embodiment, the method for determining the Rdmag_EFF value includes: 1) forcing current out of the DMAG pin when the IC is powered on and before the power converter begins switching. The value of the built-in Rcs can be determined based on the effective impedance at the DMAG pin. The value of Rcs is maintained during power-on; 2) when the primary side is off and in reverse time, VDMAG can sense secondary voltage information to determine OVP.

[0148] Figure 24 A schematic diagram of an integrated GaN power device comprising a flyback controller IC and a GaN switch according to some embodiments is shown. In the illustrated embodiments, a semiconductor package 2480 may be used to integrate a first semiconductor device 2484 and a second semiconductor device 2482. In some embodiments, the first semiconductor device 2484 may be a GaN-based die. In various embodiments, the second semiconductor device 2482 may be a silicon-based die having a flyback controller IC 2498. In some embodiments, the flyback controller IC may be a QR flyback controller IC. The first semiconductor device 2484 may include a first GaN-based switch 2402 having a first source, a first gate, and a first drain, and a second GaN-based switch 2404 having a second source, a second gate, and a second drain. In some embodiments, the first gate may be coupled to the second gate, and the first drain may be coupled to the second drain. In various embodiments, the first GaN-based switch may be a first transistor, and the second GaN-based switch may be a second transistor.

[0149] Semiconductor package 2480 may include an external source terminal 2481, an external drain terminal 2483, an external feedback (FB) terminal 2494, an external multifunction (DMAG) terminal 2492, and an external power supply (VDD) terminal 2490. A first source terminal may be coupled to the external source terminal 2481. A first drain terminal and a second drain terminal may be coupled to the external drain terminal 2483. Flyback controller IC 2498 may have a gate drive terminal 2486 (DRV) that may be coupled to a first gate and a second gate. In some embodiments, electromagnetic interference (EMI) control management circuitry may be coupled to the DRV terminal. Ground node 2488 of flyback controller IC 2498 may be coupled to the external source terminal 2481. External power supply VDD terminal 2490 may be coupled to the power supply terminal of flyback controller IC 2498. DMAG terminal 2492 may be coupled to the multifunction terminal of flyback controller IC 2498. The flyback controller IC 2498 may have a current sensing (CS) terminal 2496 coupled to a second source.

[0150] The CS terminal 2496 can be arranged to receive a signal from the second GaN-based switch 2404 indicating the amplitude and / or direction of the current flowing through the first GaN-based switch 2402. In some embodiments, the flyback controller IC 2498 may include an amplifier 2422 coupled to the CS terminal 2496 and a resistor 2420 coupled to the CS terminal 2496. In some embodiments, the amplifier 2422 may be a comparator. The amplifier 2422 may generate a current at its output. The output of the amplifier 2422 may be coupled to a current-sensing resistor 2424 (Rcs).

[0151] The value of the current sensing resistor 2424 (Rcs) can be determined by the Rcs determining circuit 2428 based on the effective impedance at the DMAG pin. The determined value of the current sensing resistor 2424 (Rcs) can be used to determine the magnitude of the current flowing through the switch 2402. The PWM control circuit 2426 can transmit a PWM signal to the drive circuit 2408 based on the magnitude of the current flowing through the switch 2402. In some embodiments, the direction of the current flowing through the switch 2402 can be determined. The PWM control circuit 2426 can transmit the PWM signal based at least on the magnitude or direction of the current flowing through the switch 2402. The flyback controller 2498 may also include a Vin / Vout detection circuit 2430. The flyback controller 2498 may also include a drive circuit 2408 coupled to a first gate and a second gate. The flyback controller 2498 may include a current source 2414 coupled to the DMAG terminal 2492. In some implementations, the PWM control circuit 2426 may include overcurrent protection circuitry, EMI optimizer circuitry, and overvoltage / undervoltage protection circuitry.

[0152] The flyback controller 2498 may also include a comparator 2416, with a first terminal coupled to the DMAG terminal 2492 and a second terminal coupled to a reference voltage Vref 2418. In some embodiments, the reference voltage may be, for example, 0.5V. Current flowing through the current source 2414 can be forced out of the DMAG pin, and the voltage at the DMAG pin can be compared to Vref. In some embodiments, the current source 2414 may comprise multiple individual current sources with values ​​such as 100μA, 50μA, 200μA, and 250μA. Each current source may be forced out of the DMAG pin until the voltage at the DMAG pin is greater than Vref. When the comparator 2416 trips, a corresponding signal can be transmitted to the Rcs determination circuit 2428. Based on the transmitted signal, a lookup table can be used to select the value of the current sensing resistor 2424.

[0153] The first semiconductor device 2484 can be coupled to the second semiconductor device 2482 via wire bonding and / or clips. In some embodiments, circuitry on the second semiconductor device can be arranged to detect gate drive signals, current sensing information, temperature, and various other operating parameters, and to generate protection signals for high-voltage power switches, such as overcurrent protection, overvoltage / undervoltage protection signals, and overtemperature protection signals. The second semiconductor device can be electrically coupled to low-voltage signal pins via wire bonding and / or clips.

[0154] In some embodiments, combinations of the circuits, packages, and methods disclosed herein can be used to provide power factor correction controller ICs, QR flyback controller ICs, and integrated GaN power devices. While this document describes and illustrates circuits and methods for several specific configurations of PFC converter circuits and QR flyback converter circuits, and for specific semiconductor packages, embodiments of this disclosure are also applicable to other power converter topologies, such as, but not limited to, power converters, such as, but not limited to, AHB converters utilizing silicon power switches, GaN power switches, or silicon carbide power switches. Furthermore, embodiments of this disclosure are applicable to other semiconductor packages, such as, but not limited to, flat leadless packages.

[0155] In the foregoing description, numerous specific details have been described with reference to embodiments of this disclosure, which may vary in different specific implementations. Therefore, the description and drawings should be considered illustrative rather than restrictive. The unique and exclusive indication of the scope of this disclosure, and what the applicant wishes to define as the scope of this disclosure, is the literal and equivalent scope of the claims published in this application, taking the specific form published by those claims, including any subsequent amendments. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of embodiments of this disclosure.

[0156] Furthermore, spatially relative terms, such as “bottom” or “top,” may be used to describe the relationship of one element and / or feature to another element and / or feature, as illustrated in the figure. It should be understood that spatially relative terms are intended to cover different orientations of the device in use and / or operation than those depicted in the figure. For example, if the device in the figure is flipped, the element described as the “bottom” surface may then be oriented “above” other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or otherwise) and may be interpreted accordingly by the spatially relative descriptors used herein.

[0157] As used herein, the terms “and,” “or,” and “and / or” can have a variety of meanings, which are also expected to depend at least in part on the context in which these terms are used. Generally, “or,” when used in a list of associations (such as A, B, or C), is intended to mean A, B, and C (used herein in an inclusive sense) and A, B, or C (used herein in an exclusive sense). Furthermore, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in the singular form, or can be used to describe some combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example and the claimed subject matter is not limited to the examples described. Additionally, the term “at least one of” when used in a list of associations (e.g., A, B, or C) can be interpreted as meaning any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0158] Throughout this specification, references to “an example,” “example,” “some examples,” or “exemplary embodiment” mean that a particular feature, structure, or characteristic described in conjunction with a feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Therefore, the phrases “in an example,” “example,” “in some examples,” “in some embodiments,” or other similar phrases appearing throughout this specification do not necessarily refer to the same feature, example, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined to form one or more examples and / or features.

[0159] In the foregoing detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill in the art have not been described in detail to avoid obscuring the claimed subject matter. Therefore, the claimed subject matter is not limited to the specific examples disclosed, but rather can encompass all aspects falling within the scope of the appended claims and their equivalents.

[0160] In some implementations, the electronic system may include the following:

[0161] 1. An electronic component comprising:

[0162] Base;

[0163] A first semiconductor device, attached to the base and comprising:

[0164] A first gallium nitride (GaN)-based switch has a first gate, a first source, and a first drain, wherein the first gate is arranged to control the current flow between the first source and the first drain;

[0165] A second GaN-based switch has a second source, a second gate, and a second drain, wherein the second gate is coupled to the first gate, and the second drain is coupled to the first drain;

[0166] A second semiconductor device, attached to the base and comprising:

[0167] A driving circuit coupled to the first gate and the second gate, the driving circuit being arranged to control the on and off states of the first GaN-based switch and the second GaN-based switch;

[0168] The logic circuit is arranged as follows:

[0169] The amplitude of the current flow is detected via a first signal received from the second source; and

[0170] When the detected current flow amplitude exceeds a threshold current value, the driving circuit is controlled to turn off the first GaN-based switch and the second GaN-based switch; and

[0171] An electrically insulating encapsulation that at least partially encapsulates the base, the first semiconductor device, and the second semiconductor device.

[0172] 2. The electronic component according to technical solution 1, wherein the logic circuit is coupled to an external circuit, and wherein the threshold current value is determined at least in part by the external circuit.

[0173] 3. The electronic component according to claim 2, wherein the external circuitry includes a resistor, and wherein the threshold current value is at least partially based on the resistance of the resistor.

[0174] 4. The electronic component according to technical solution 1, wherein the logic circuit includes an adjustable resistor, and the threshold current value is at least partially based on the resistance of the adjustable resistor.

[0175] 5. The electronic component according to technical solution 1 further includes a sensing resistor coupled to the second source, wherein the voltage at the sensing resistor corresponds to the first signal.

[0176] 6. The electronic component according to technical solution 5, wherein the sensing resistor is disposed on the second semiconductor device.

[0177] 7. The electronic component according to technical solution 1, wherein the driver synchronously controls the on and off states of the first GaN-based switch and the second GaN-based switch.

[0178] 8. An electronic component comprising:

[0179] A first semiconductor device, comprising:

[0180] A first gallium nitride (GaN)-based switch has a first gate, a first source, and a first drain, wherein the first gate is arranged to control the current flow between the first source and the first drain;

[0181] A second GaN-based switch has a second source, a second gate, and a second drain, wherein the second gate is coupled to the first gate, and the second drain is coupled to the first drain;

[0182] A second semiconductor device, comprising:

[0183] A driving circuit coupled to the first gate and the second gate, the driving circuit being arranged to control the on and off states of the first GaN-based switch and the second GaN-based switch;

[0184] The logic circuit is arranged as follows:

[0185] The amplitude of the current flow is detected via a first signal received from the second source; and

[0186] When the detected current flow amplitude exceeds a threshold current value, the driving circuit is controlled to turn off the first GaN-based switch and the second GaN-based switch; and

[0187] An electrically insulating encapsulation that at least partially encapsulates the first semiconductor device and the second semiconductor device;

[0188] A first external terminal is disposed on the outer surface of the electronic component and coupled to the first drain; and

[0189] A second external terminal is disposed on the outer surface of the electronic component and coupled to the first source electrode.

[0190] 9. The electronic component according to claim 8, wherein the logic circuit is coupled to an external circuit via a third external terminal, and wherein the threshold current value is determined at least in part by the external circuit.

[0191] 10. The electronic component according to claim 9, wherein the external circuitry includes a resistor, and wherein the threshold current value is at least partially based on the resistance of the resistor.

[0192] 11. The electronic component according to technical solution 9, wherein the first external terminal is coupled to the primary winding of the transformer, and wherein the third external terminal is coupled to the secondary winding of the transformer.

[0193] 12. The electronic component according to claim 11, wherein the logic circuit detects the input voltage at the primary winding of the transformer via the third external terminal.

[0194] 13. The electronic component according to claim 11, wherein the secondary winding is the primary winding, and wherein the logic circuit detects the output voltage at the secondary winding of the transformer via the third external terminal.

[0195] 14. The electronic component according to claim 8, wherein the logic circuit includes an adjustable resistor, and wherein the logic circuit controls the drive circuit to turn off the first GaN-based switch and the second GaN-based switch at least in part based on the resistance of the adjustable resistor.

[0196] 15. The electronic component according to claim 8 further includes a sensing resistor coupled to the second source, and wherein the logic circuit detects the magnitude of the current flow via a voltage at the sensing resistor.

[0197] 16. The electronic component according to claim 15, wherein the sensing resistor is disposed on the second semiconductor device.

[0198] 17. A method of operating an electronic component, the method comprising:

[0199] The external circuit at the first external terminal is sensed, wherein the first external terminal is located on the outer surface of the electronic component;

[0200] The value of a variable resistor is adjusted in response to the sensing of the external circuit, wherein the variable resistor is disposed within the electronic component;

[0201] Current is conducted between a second external terminal and a third external terminal via a first gallium nitride (GaN)-based transistor, wherein the first GaN-based transistor is disposed within the electronic component, and the second external terminal and the third external terminal are located on the outer surface of the electronic component;

[0202] The conduction current is sensed via a second GaN-based transistor disposed within the electronic component; and

[0203] The first GaN-based transistor is switched to the off state based at least on the value of the variable resistor and the sensed conduction current.

[0204] 18. The method according to claim 17, wherein the external circuit includes a resistor, and wherein the sensing includes sensing the resistance value of the resistor.

[0205] 19. The method according to technical solution 17, wherein the first GaN-based switch includes a first gate, a first source and a first drain, and wherein the second GaN-based switch includes a second source, a second gate and a second drain, wherein the second gate is coupled to the first gate and the second drain is coupled to the first drain.

[0206] 20. The method according to technical solution 17 further includes sensing the voltage of the transformer winding via the first external terminal.

[0207] 21. A power converter circuit, comprising:

[0208] A power factor controller includes:

[0209] The input terminal is arranged to detect a first voltage representing the output voltage of the power converter circuit and to detect a second voltage proportional to the input voltage of the power converter circuit.

[0210] The drive terminal is used to transmit drive signals to the gate of the switch;

[0211] A logic circuit is arranged to add the first voltage and the second voltage to generate a first signal during the on-time of the power converter circuit;

[0212] A delay circuit, configured to generate a zero-current detection (ZCD) signal based on the first voltage and the second voltage at the input terminals; and

[0213] A controller circuit is arranged to generate the drive signal in response to the first signal and the ZCD signal.

[0214] 22. The power converter circuit according to technical solution 21, wherein the second voltage is detected by determining the voltage drop across the first transformer winding, wherein the first transformer winding is magnetically coupled to the second transformer winding and the second transformer winding is coupled to the input node of the power converter circuit.

[0215] 23. The power converter circuit according to technical solution 22, wherein the power factor controller further includes a power-down protection circuit, the power-down protection circuit being arranged to use the first signal to generate a power-down signal.

[0216] 24. The power converter circuit according to technical solution 23, wherein the power factor controller further includes an overvoltage protection circuit, the overvoltage protection circuit being arranged to generate an overvoltage signal using the average value of the first voltage.

[0217] 25. A method of operating a power converter circuit, the method comprising:

[0218] A power factor controller is provided having input terminals, drive terminals, logic circuitry, delay circuitry, and controller circuitry, wherein the drive terminals are arranged to transmit drive signals to the gate of a switch.

[0219] A first voltage representing the output voltage of the power converter circuit is detected at the input terminal;

[0220] A second voltage proportional to the input voltage of the power converter circuit is detected at the input terminal;

[0221] The logic circuit adds the first voltage and the second voltage during the on-time of the power converter circuit to generate a first signal;

[0222] The delay circuit generates a zero-current detection (ZCD) signal based on the first voltage and the second voltage at the input terminal; and

[0223] The controller circuit generates the drive signal in response to the first signal and the ZCD signal.

Claims

1. An electronic component, characterized in that... include: Base; A first semiconductor device, attached to the base and comprising: A first gallium nitride (GaN)-based switch has a first gate, a first source, and a first drain, wherein the first gate is arranged to control the current flow between the first source and the first drain. A second GaN-based switch has a second source, a second gate, and a second drain, wherein the second gate is coupled to the first gate, and the second drain is coupled to the first drain; A second semiconductor device, attached to the base and comprising: A logic circuit coupled to the second source and arranged to detect the magnitude of the current flow; as well as A driving circuit coupled to the first gate and the second gate, the driving circuit being arranged to control the on and off states of the first GaN-based switch and the second GaN-based switch; as well as An electrically insulating encapsulation that at least partially encapsulates the base, the first semiconductor device, and the second semiconductor device.

2. The electronic component of claim 1, further comprising a first external terminal coupled to the first drain, a second external terminal coupled to the first source, and a third external terminal coupled to the logic circuit, the third external terminal being arranged to transmit a signal corresponding to the amplitude of the detected current flow.

3. The electronic component of claim 1, further comprising a resistor coupled to the second source, wherein the logic circuit detects a voltage drop across the resistor that is proportional to the magnitude of the current flow.

4. The electronic component of claim 3, wherein the resistor is disposed within the second semiconductor device.

5. The electronic component according to claim 1, wherein the driving circuit synchronously controls the on and off states of the first GaN-based switch and the second GaN-based switch.

6. The electronic component of claim 2, wherein the electronic component further comprises a fourth external terminal coupled to the logic circuit, wherein the fourth external terminal is arranged to receive a pulse width modulation signal.

7. The electronic component of claim 6 further includes a fifth external terminal, the fifth external terminal being arranged to receive a power supply.

8. An electronic component, characterized in that... include: A first semiconductor device, comprising: A first gallium nitride (GaN)-based switch has a first gate, a first source, and a first drain, wherein the first gate is arranged to control the current flow between the first source and the first drain. A second GaN-based switch has a second source, a second gate, and a second drain, wherein the second gate is coupled to the first gate, and the second drain is coupled to the first drain; A second semiconductor device, comprising: A driving circuit coupled to the first gate and the second gate, the driving circuit being arranged to control the on and off states of the first GaN-based switch and the second GaN-based switch; The logic circuit is arranged as follows: The amplitude of the current flow is detected via a first signal received from the second source; and When the detected current flow amplitude exceeds the threshold current value, the driving circuit is controlled to turn off the first GaN-based switch and the second GaN-based switch. as well as An electrically insulating encapsulation that at least partially encapsulates the first semiconductor device and the second semiconductor device; A first external terminal is disposed on the outer surface of the electronic component and coupled to the first drain electrode; as well as A second external terminal is disposed on the outer surface of the electronic component and coupled to the first source electrode.

9. The electronic component of claim 8, wherein the electronic component further comprises a third external terminal coupled to the logic circuit, the third external terminal being arranged to transmit a signal corresponding to the amplitude of the detected current flow.

10. The electronic component of claim 8, further comprising a resistor coupled to the second source, wherein the logic circuit detects a voltage drop across the resistor that is proportional to the magnitude of the current flow.

11. The electronic component of claim 10, wherein the resistor is disposed within the second semiconductor device.

12. The electronic component of claim 8, wherein the driving circuit synchronously controls the on and off states of the first GaN-based switch and the second GaN-based switch.

13. The electronic component of claim 9, further comprising a fourth external terminal coupled to the logic circuit, wherein the fourth external terminal is arranged to receive a pulse width modulation signal.

14. The electronic component of claim 13, further comprising a fifth external terminal arranged to receive a power supply.

15. The electronic component of claim 14, wherein the electronic component has a thickness of less than 2 mm.

16. The electronic component of claim 15, wherein the second external terminal is a metal pad on the bottom surface of the electronic component.

17. The electronic component of claim 16, wherein the distance between the first external terminal and any one of the third external terminal, the fourth external terminal, or the fifth external terminal is greater than 1 mm.

18. The electronic component of claim 17, wherein the electronic component includes a die pad.

19. The electronic component of claim 18, wherein the first source is coupled to the die pad via wire bonding.

20. The electronic component of claim 19, wherein the die pad is coupled to the metal pad.

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