Detection device applied to inverter and photovoltaic grid-connected inverter with current-limiting function

Abstract

Embodiments of the present disclosure provide a detection device applied to an inverter and a photovoltaic grid-connected inverter with current limiting function. In a specific embodiment, the device has a current sampling unit for collecting output current of an inverter unit, obtaining and outputting a sampling current to a differential amplification conditioning circuit; the differential amplification conditioning circuit performs level shifting and amplitude adjustment on the sampling current collected by the current sampling unit, obtains a processing current and outputs the processing current to an overcurrent comparison circuit; the overcurrent comparison circuit performs threshold comparison on the processing current, and if the processing current is greater than a first preset threshold and / or the processing current is less than a second preset threshold, outputs an overcurrent trigger signal to an input end of a first controller, so that the first controller outputs an interrupt interface to a second controller through hardware pass-through logic mapping. This embodiment adopts hardware protection and has fast response speed.

Description

Technical Field

[0001] This disclosure relates to the field of inverter units. More specifically, it relates to a detection device for inverters and a photovoltaic grid-connected inverter with current limiting function. Background Technology

[0002] With the rapid development of photovoltaic power generation, the reliability and safety of string photovoltaic grid-connected inverter units are of paramount importance. During high-voltage or low-voltage power grid rides, the internal current of the inverter unit is prone to drastic fluctuations or even instantaneous overcurrent, leading to equipment damage or system instability. Traditional current limiting methods rely heavily on software protection, which has limited response speed and cannot provide timely and effective protection for the inverter unit. Utility Model Content

[0003] The purpose of this disclosure is to provide a detection device for inverters with hardware protection and fast response speed, and a photovoltaic grid-connected inverter with current limiting function, so as to solve at least one of the problems existing in the prior art.

[0004] To achieve the above objectives, the present disclosure adopts the following technical solution: The first aspect of this disclosure provides a detection device for an inverter, comprising: The circuit includes a current sampling unit, a differential amplifier conditioning circuit, an overcurrent comparator circuit, and a first controller. The current sampling unit is used to collect the output current of the inverter unit, obtain and output the sampled current to the differential amplifier conditioning circuit; The differential amplifier conditioning circuit is used to perform level shifting and amplitude adjustment on the sampled current collected by the current sampling unit to obtain the processed current and output it to the overcurrent comparison circuit. The overcurrent comparison circuit is used to perform a threshold comparison on the processing current. If the processing current is greater than a first preset threshold and / or the processing current is less than a second preset threshold, an overcurrent trigger signal is output to the input terminal of the first controller, so that the first controller outputs to the interrupt interface of the second controller through hardware pass-through logic mapping.

[0005] Furthermore, the current sampling unit includes at least one Hall current sensor respectively fitted into each output circuit of the inverter unit.

[0006] Furthermore, the Hall current sensor includes a magnetically balanced Hall current sensor.

[0007] Furthermore, the differential amplification conditioning circuit includes at least one conditioning sub-circuit corresponding to the Hall current sensor; The conditioning sub-circuit includes: A first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The inverting input terminal of the first amplifier, one end of the first resistor, one end of the second capacitor, one end of the fourth resistor, and one end of the fourth capacitor are coupled to the first node; The non-inverting input terminal of the first amplifier, one end of the first capacitor, one end of the third capacitor, one end of the second resistor, and one end of the third resistor are coupled to the second node; The output terminal of the first amplifier, the other end of the fourth capacitor, and the other end of the fourth resistor are coupled to the third node; The first end of the Hall current sensor is connected to the other end of the first resistor, and the second end is connected to the other end of the second resistor. The other end of the third resistor and the other end of the first capacitor are connected to the first reference voltage terminal; The other end of the second capacitor and the other end of the third capacitor are grounded.

[0008] Furthermore, the overcurrent comparator circuit includes: Fifth resistor, sixth resistor, seventh resistor, eighth resistor, ninth resistor, tenth resistor, eleventh resistor, twelfth resistor, fifth capacitor, sixth capacitor, seventh capacitor, eighth capacitor, ninth capacitor, second amplifier, and third amplifier; The inverting input terminal of the second amplifier, one end of the fifth resistor, and one end of the fifth capacitor are coupled to the fourth node; the non-inverting input terminal of the second amplifier, one end of the ninth resistor, and one end of the sixth capacitor are coupled to the fifth node. The inverting input terminal of the third amplifier, one end of the eleventh resistor, one end of the twelfth resistor, and one end of the seventh capacitor are coupled to the sixth node; the non-inverting input terminal of the third amplifier, one end of the sixth resistor, and one end of the eighth capacitor are coupled to the seventh node. The output terminals of the second amplifier, the third amplifier, one end of the seventh resistor, and one end of the eighth resistor are coupled to the eighth node; the other end of the seventh resistor and one end of the ninth capacitor are coupled to the ninth node. The other end of the ninth resistor and the other end of the eleventh resistor are connected to the second reference voltage terminal; the other end of the tenth resistor, the other end of the twelfth resistor, the other end of the fifth capacitor, the other end of the sixth capacitor, the other end of the seventh capacitor, the other end of the eighth capacitor, and the other end of the ninth capacitor are grounded. The other end of the fifth resistor and the other end of the sixth resistor are coupled to the third node; the other end of the eighth resistor is connected to the first drive voltage output terminal.

[0009] Furthermore, the input of the first controller is coupled to the ninth node.

[0010] Furthermore, the first controller is a complex programmable logic device controller.

[0011] A second aspect of this disclosure provides a photovoltaic grid-connected inverter with current-limiting function, comprising: Inverter unit, second controller, driver, and detection device as described in any one of the first aspects; The output terminal of the second controller is connected to the input terminal of the driver, and the output terminal of the driver is connected to the output current adjustment terminal of the inverter unit; The current sampling unit of the detection device is connected to the output circuit of the inverter unit.

[0012] Furthermore, the inverter unit includes a boost unit and an active neutral-point clamped three-level topology inverter unit; The output of the boost unit is connected to the input of the neutral-point clamped three-level topology inverter unit; The output terminal of the driver is connected to the output current adjustment terminal of the neutral point clamped three-level topology inverter unit; The current sampling unit of the detection device is connected to the output circuit of the neutral-point clamped three-level topology inverter unit.

[0013] Furthermore, the second controller is a digital signal processor.

[0014] The beneficial effects of this disclosure are as follows: This invention identifies and triggers overcurrent signals of high voltage or low voltage ride-through through hardware circuitry. The current is sampled by a current sampling unit to obtain the sampled current. However, the sampled current signal is a periodic signal, such as a sine wave signal. Within one period of the sampled signal, the signal values ​​of two adjacent half-wave signals in the signal have opposite signs. Therefore, on the one hand, the acquired current signal cannot be used by the overcurrent comparison circuit. Thus, a differential amplifier conditioning circuit is needed to add a bias and proportional scaling to the current output from the current sampling unit to perform level shifting and amplitude adjustment on the output current, thereby converting the sampled current into a non-negative value to obtain the processed signal. On the other hand, this embodiment needs to perform overcurrent detection on both the positive and negative signals of the sine wave signal. This can be achieved by comparing the processed signal with a first preset threshold and a second preset threshold using an overcurrent comparison circuit.

[0015] Furthermore, traditional controllers use internal software logic to receive input signals and output trigger signals, while this disclosure uses hardware pass-through logic to map the output to the interrupt interface of the second controller, without the involvement of CPU instructions, thus resulting in a fast response speed. Attached Figure Description

[0016] The specific embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0017] Figure 1 A schematic diagram of the detection device of this disclosure is shown.

[0018] Figure 2 A circuit diagram of the differential amplifier conditioning circuit of this disclosure is shown.

[0019] Figure 3 A circuit diagram of the overcurrent comparator circuit of this disclosure is shown.

[0020] Figure 4 A schematic diagram of the structure of the first embodiment of the photovoltaic grid-connected inverter disclosed herein is shown.

[0021] Figure 5 A schematic diagram of the structure of a second embodiment of the photovoltaic grid-connected inverter disclosed herein is shown.

[0022] Figure 6 The circuit diagram of the follower of this disclosure is shown.

[0023] Figure 7 A circuit diagram of the voltage sampling unit of this disclosure is shown. Detailed Implementation

[0024] To more clearly illustrate this disclosure, the following description, in conjunction with embodiments and accompanying drawings, provides further insight. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0025] like Figure 1 As shown, one embodiment of this disclosure provides a detection device for an inverter, comprising: The circuit includes a current sampling unit, a differential amplifier conditioning circuit, an overcurrent comparator circuit, and a first controller. The current sampling unit is used to collect the output current of the inverter unit, obtain and output the sampled current to the differential amplifier conditioning circuit; The differential amplifier conditioning circuit is used to perform level shifting and amplitude adjustment on the sampled current collected by the current sampling unit to obtain the processed current and output it to the overcurrent comparison circuit. The overcurrent comparison circuit is used to perform a threshold comparison on the processing current. If the processing current is greater than a first preset threshold and / or the processing current is less than a second preset threshold, an overcurrent trigger signal is output to the input terminal of the first controller, so that the first controller outputs to the interrupt interface of the second controller through hardware pass-through logic mapping.

[0026] This invention identifies and triggers overcurrent signals of high voltage or low voltage ride-through through hardware circuitry. The current is sampled by a current sampling unit to obtain the sampled current. However, the sampled current signal is a periodic signal, such as a sine wave signal. Within one period of the sampled signal, the signal values ​​of two adjacent half-wave signals in the signal have opposite signs. Therefore, on the one hand, the acquired current signal cannot be used by the overcurrent comparison circuit. Thus, a differential amplifier conditioning circuit is needed to add a bias and proportional scaling to the current output from the current sampling unit to perform level shifting and amplitude adjustment on the output current, thereby converting the sampled current into a non-negative value to obtain the processed signal. On the other hand, this embodiment needs to perform overcurrent detection on both the positive and negative signals of the sine wave signal. This can be achieved by comparing the processed signal with a first preset threshold and a second preset threshold using an overcurrent comparison circuit.

[0027] Furthermore, traditional controllers use internal software logic to receive input signals and output trigger signals, while this disclosure uses hardware pass-through logic to map the output to the interrupt interface of the second controller, without the involvement of CPU instructions, thus resulting in a fast response speed.

[0028] It should be noted that in this embodiment, the first preset threshold is greater than the second preset threshold.

[0029] In one possible implementation, the current sampling unit includes at least one Hall current sensor respectively fitted into each output circuit of the inverter unit.

[0030] This embodiment uses a Hall current sensor with a 200kHz bandwidth matching high-frequency switching topology, which can eliminate the threshold drift problem of traditional CT in high-temperature environments. It has high isolation characteristics and a closed magnetic core structure, which can suppress external magnetic field interference.

[0031] In one possible implementation, the Hall current sensor includes a magnetically balanced Hall current sensor. The core of this embodiment lies in replacing traditional closed-loop Hall current sensors, such as the LEM LAH series, with a magnetically balanced Hall current sensor. This closed-loop Hall current sensor has a bandwidth of less than 50kHz and a temperature drift greater than ±0.05% / ℃; thus completely solving the overcurrent detection delay and protection threshold drift problems caused by insufficient bandwidth and excessive temperature drift in traditional current transformers. In this embodiment, the SIB-300LA magnetic balance Hall current sensor is preferred. With its high bandwidth of 200kHz at -3dB and ±0.4% full-range accuracy, the SIB-300LA magnetic balance Hall current sensor can accurately capture transient currents in drivers such as IGBT switches in real time, significantly improving the overcurrent protection reliability of active neutral point clamped (ANPC) inverters at switching frequencies above 10kHz.

[0032] In one possible implementation, such as Figure 2 As shown, the differential amplifier conditioning circuit includes at least one conditioning sub-circuit corresponding to the Hall current sensor; The conditioning sub-circuit includes: The first amplifier U1, the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4; The inverting input terminal of the first amplifier U1, one end of the first resistor R1, one end of the second capacitor C2, one end of the fourth resistor R4, and one end of the fourth capacitor C4 are coupled to the first node TP1. The non-inverting input terminal of the first amplifier U1, one end of the first capacitor C1, one end of the third capacitor C3, one end of the second resistor R2, and one end of the third resistor R3 are coupled to the second node TP2. The output terminal of the first amplifier U1, the other end of the fourth capacitor C4, and the other end of the fourth resistor R4 are coupled to the third node TP3; The first end of the Hall current sensor is connected to the other end of the first resistor R1, and the second end is connected to the other end of the second resistor R2. The other end of the third resistor R3 and the other end of the first capacitor C1 are connected to the first reference voltage VREF1 terminal; The other end of the second capacitor C2 and the other end of the third capacitor C3 are grounded.

[0033] This invention achieves level shifting and amplitude adjustment of the sampled current through a conditioning sub-circuit, resulting in a simple structure and fast response speed.

[0034] In one possible implementation, such as Figure 3 As shown, the overcurrent comparator circuit includes: Fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8, ninth resistor R9, tenth resistor R10, eleventh resistor R11, twelfth resistor R12, fifth capacitor C5, sixth capacitor C6, seventh capacitor C7, eighth capacitor C8, ninth capacitor C9, second amplifier U2 and third amplifier U3. The inverting input terminal of the second amplifier U2, one end of the fifth resistor R5, and one end of the fifth capacitor C5 are coupled to the fourth node TP4; the non-inverting input terminal of the second amplifier U2, one end of the ninth resistor R9, and one end of the sixth capacitor C6 are coupled to the fifth node TP5. The inverting input terminal of the third amplifier U3, one end of the eleventh resistor R11, one end of the twelfth resistor R12, and one end of the seventh capacitor C7 are coupled to the sixth node TP6, and the non-inverting input terminal of the third amplifier U3, one end of the sixth resistor R6, and one end of the eighth capacitor C8 are coupled to the seventh node TP7. The output terminals of the second amplifier U2, the third amplifier U3, one end of the seventh resistor R7, and one end of the eighth resistor R8 are coupled to the eighth node TP8; the other end of the seventh resistor R7 and one end of the ninth capacitor C9 are coupled to the ninth node TP9. The other end of the ninth resistor R9 and the other end of the eleventh resistor R11 are connected to the second reference voltage VREF2 terminal; the other end of the tenth resistor R10, the other end of the twelfth resistor R12, the other end of the fifth capacitor C5, the other end of the sixth capacitor C6, the other end of the seventh capacitor C7, the other end of the eighth capacitor C8, and the other end of the ninth capacitor C9 are grounded. The other end of the fifth resistor R5 and the other end of the sixth resistor R6 are coupled to the third node TP3; the other end of the eighth resistor R8 is connected to the first drive voltage output terminal.

[0035] In a specific example, such as Figure 3 As shown, the overcurrent comparator circuit also includes a tenth capacitor C10 and an eleventh capacitor C11 for filtering, respectively. One end of the tenth capacitor C10 is connected to the other end of the ninth resistor R9, and the other end is connected to the other end of the tenth resistor R10. One end of the eleventh capacitor C11 is connected to the other end of the eleventh resistor R11, and the other end is connected to the other end of the twelfth resistor R12.

[0036] In one possible implementation, the input of the first controller is coupled to the ninth node TP9.

[0037] In one possible implementation, the first controller is a complex programmable logic device controller.

[0038] like Figure 4 As shown, the second embodiment of this utility model provides a photovoltaic grid-connected inverter with current limiting function, including: Inverter unit, second controller, driver, and detection device as described in the above embodiments; The output terminal of the second controller is connected to the input terminal of the driver, and the output terminal of the driver is connected to the output current adjustment terminal of the inverter unit; The current sampling unit of the detection device is connected to the output circuit of the inverter unit; The output of the first controller of the detection device is connected to the interrupt interface of the second controller.

[0039] In one possible implementation, such as Figure 5 As shown, in this embodiment, the first controller is a Complex Programmable Logic Device (CPLD) controller; the second controller is a Digital Signal Processor (DSP). The CPLD architecture aims to achieve optimal division of labor: the DSP provides sufficient computing power to run complex control algorithms such as SPWM and closed-loop control; while the CPLD, with its nanosecond-level hardware logic speed, is responsible for handling the rapid blocking of through signals, fault state latching, and key protection logic for system safety, ensuring that it can achieve microsecond or even nanosecond-level response when overcurrent occurs, providing a crucial hardware-level protection barrier for ANPC systems under high-frequency switching.

[0040] In one possible implementation, the inverter unit includes a boost unit and an active neutral-point clamped three-level topology inverter unit; The output of the boost unit is connected to the input of the neutral-point clamped three-level topology inverter unit; The output terminal of the driver is connected to the output current adjustment terminal of the neutral point clamped three-level topology inverter unit; The current sampling unit of the detection device is connected to the output circuit of the neutral-point clamped three-level topology inverter unit.

[0041] In a specific example, such as Figure 5In this scheme, the inverter adopts a two-stage inverter unit topology. The latter stage is an inverter unit, specifically, the inverter unit can be an active neutral point clamped three-level topology inverter unit (ANPC inverter unit), while the former stage adopts a DC-DC boost converter (Boost circuit). The input terminal of the boost circuit is connected to the photovoltaic module PV.

[0042] Following the example above, such as Figure 5 The design focus of this embodiment is on the inverter unit at the downstream stage. The inverter unit disclosed herein includes an inverter unit, a second controller, a driver, and a detection device as described in any one of the first embodiments. In one possible implementation, such as Figure 7 As shown, the inverter also includes a voltage sampling unit located on the DC bus bridge arm side and / or the grid side of the inverter, which are used for voltage verification of the switching contactor, respectively. In this embodiment, the voltage acquisition of the voltage sampling unit is achieved through voltage division, which will not be elaborated further in this embodiment.

[0043] The system employs hardware to identify instantaneous overcurrent phenomena during high-voltage or low-voltage ride-throughs, providing a fast response and effectively preventing hardware damage and operational instability of the inverter caused by excessive current.

[0044] In a specific example, such as Figure 6 As shown, the inverter also includes a follower, which includes a thirteenth resistor R13, a fourteenth resistor R14, a fourth amplifier U4, and a twelfth capacitor C12; The non-inverting input of the fourth amplifier U4, one end of the thirteenth resistor R13, and one end of the twelfth capacitor C12 are coupled to the tenth node TP10; The inverting input terminal of the fourth amplifier U4 is connected to the output terminal of the fourth amplifier U4 and one end of the fourteenth resistor R14, respectively. The other end of the thirteenth resistor R13 is coupled to the third node TP3; the other end of the twelfth capacitor C12 is grounded; the other end of the fourteenth resistor R14 is connected to the signal acquisition terminal of the second controller to acquire the processed current after being processed by the differential amplification and conditioning circuit; specifically, the other end of the fourteenth resistor R14 is connected to the signal acquisition terminal of the DSP.

[0045] In a specific example, the overall working principle of this disclosure is as follows: the inverter unit outputs three-phase current, and the three-phase current signals are respectively acquired by corresponding Hall current sensors to obtain sampled currents. The Hall current sensors output a voltage signal. Since the voltage amplitude allowed at the terminals of the control chip DSP and CPLD is between 0-3.3V, and the voltage signal output by the Hall sensors has positive and negative values, a bias and proportional scaling need to be added to the acquired current signal. Therefore, the sampled current acquired by the Hall current sensors enters the differential amplification and conditioning circuit, specifically: The sampled current is filtered by an RC low-pass filter network composed of the first capacitor C1 and the third resistor R3 and output to the non-inverting input of the first amplifier U1. The inverting input of the first amplifier U1 is connected to a first reference voltage VREF1 with a voltage value of 2.5V. The process is to perform level shifting and amplitude adjustment on the current acquisition signal of the processed Hall sensor to obtain the processed current. Reference Figure 3 and Figure 5 As shown, the processed current is passed to the subsequent overcurrent comparison circuit: specifically, the processed current is input in parallel to the inverting input of the second amplifier U2 and the non-inverting input of the third amplifier U3; the second reference voltage VREF2 with a voltage value of 3.3V is divided by the ninth resistor R9 and the tenth resistor R10 at the fifth node TP5 to output a first preset threshold of 3V, which is connected to the non-inverting input of the second amplifier U2; the second reference voltage VREF2 is divided by the eleventh resistor R11 and the twelfth resistor R12 at the sixth node TP6 to output a second preset threshold of 0.264V, which is connected to the inverting input of the third amplifier U3. In this embodiment, the processed current is a sinusoidal signal, where the wavefront and trough are both peak points. It is necessary to compare that the maximum and minimum values ​​cannot exceed the threshold. The second amplifier U2 is used for the maximum wavefront. The value comparison and the third amplifier U3 are used for trough minimum value comparison. If the processing current is between the first preset threshold and the second preset threshold, the second amplifier U2 or the third amplifier U3 outputs a high-level signal. At this time, the CPLD will not be triggered. If the processing current exceeds the threshold, the second amplifier U2 or the third amplifier U3 outputs a low level (i.e., a trigger signal) to the CPLD input pin, which is mapped to the CPLD output pin through the internal hardware pass-through logic and is equivalent to being directly connected to the GPIO pin of the DSP. The DSP limits the PWM duty cycle of the current cycle in real time according to this, and controls the on and off of the IGBT in the inverter unit through the drive circuit. The IGBT in the inverter unit refers to the circuit of the ANPC inverter unit. Each switching transistor corresponds to one IGBT. The DSP needs to output each corresponding drive signal to finally realize the wave-by-wave current limiting protection of the main circuit.

[0046] It should be noted that, in this embodiment, hardware pass-through logic mapping refers to configuring the pure combinational logic functions of the second controller and the CPLD hardware design into the combinational logic unit (LUT) of the CPLD macrocell using the CPLD development tools, and making its output bypass the registers inside the macrocell, directly connecting to the output port or interconnect through the hardware logic unit. Its core purpose is to achieve the lowest possible transmission delay on a specific signal path, so that the delay is only limited by the physical transmission time, which is suitable for combinational logic application scenarios that are extremely sensitive to delay.

[0047] In addition, the CPLD can filter out glitches and interference signals, output the filtered signal to the DSP, and also quickly and temporarily disable PWM output.

[0048] It should be noted that in this embodiment, the first amplifier U1, the second amplifier U2, the third amplifier U3, and the fourth amplifier U4 can be operational amplifiers of model OPA4348AIPWT; Following the example above, the resistance of the first resistor R1 in the RC filter is 1kΩ, and the capacitance of the third capacitor C3 is 100nF; in the op-amp bias, the first amplifier U1 has a gain of 10.

[0049] Following the example above, the three-phase currents are processed by their respective overcurrent comparators, and the trigger signals output by the three overcurrent comparator circuits are connected to the CPLD pins PD0 to PD2. Similarly, the three output interfaces of the CPLD are mapped through hardware pass-through logic to output current limiting trigger signals to the DSP's interrupt pins GPIO12 to GPIO15, thereby triggering the DSP's hardware current limiting interrupt INT1, which has the highest priority.

[0050] Preferably, the CPLD model is EPM1270T144C5N, and the preferred DSP model is DSP28374s. The DSP responds to the corresponding current-limiting trigger signal by directly modifying its ePWM register. This modifies the initial PWM value, overwriting the original value, and outputs a PWM signal. The driver adjusts the duty cycle appropriately to effectively suppress the current output of the inverter unit. The driver uses an optocoupler-isolated TLP5754.

[0051] Following the example above, under normal operating conditions, the inverter current control is normal, and the detection device is in monitoring standby mode. When a high / low voltage ride occurs in the grid, the current fluctuates drastically. The overcurrent comparator circuit of the detection device immediately detects an overcurrent exceeding the limit, triggering a wave-by-wave current limiting mechanism. By continuously tracking the current changes through the follower circuit DSP, the current limiting state is gradually lifted and normal operation resumes once the current returns to a safe range.

[0052] In one specific example, the second controller and / or the first controller are also connected to a host computer for debugging.

[0053] In the description of this disclosure, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, or integral connections; they can be mechanical connections or electrical connections; they can be direct connections or indirect connections through an intermediate medium; they can be internal connections between two elements. For those skilled in the art, the specific meaning of the above terms in this disclosure can be understood according to the specific circumstances.

[0054] It should also be noted that, in the description of this disclosure, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0055] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A detection device for inverters, characterized in that, include: The circuit includes a current sampling unit, a differential amplifier conditioning circuit, an overcurrent comparator circuit, and a first controller. The current sampling unit is used to collect the output current of the inverter unit, obtain and output the sampled current to the differential amplifier conditioning circuit; The differential amplifier conditioning circuit is used to perform level shifting and amplitude adjustment on the sampled current collected by the current sampling unit to obtain the processed current and output it to the overcurrent comparison circuit. The overcurrent comparison circuit is used to perform a threshold comparison on the processing current. If the processing current is greater than a first preset threshold and / or the processing current is less than a second preset threshold, an overcurrent trigger signal is output to the input terminal of the first controller, so that the first controller outputs to the interrupt interface of the second controller through hardware pass-through logic mapping.

2. The detection device according to claim 1, characterized in that, The current sampling unit includes at least one Hall current sensor respectively fitted into each output circuit of the inverter unit.

3. The detection device according to claim 2, characterized in that, The Hall current sensor includes a magnetically balanced Hall current sensor.

4. The detection device according to claim 2, characterized in that, The differential amplification conditioning circuit includes at least one conditioning sub-circuit corresponding to the Hall current sensor; The conditioning sub-circuit includes: A first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The inverting input terminal of the first amplifier, one end of the first resistor, one end of the second capacitor, one end of the fourth resistor, and one end of the fourth capacitor are coupled to the first node; The non-inverting input terminal of the first amplifier, one end of the first capacitor, one end of the third capacitor, one end of the second resistor, and one end of the third resistor are coupled to the second node; The output terminal of the first amplifier, the other end of the fourth capacitor, and the other end of the fourth resistor are coupled to the third node; The first end of the Hall current sensor is connected to the other end of the first resistor, and the second end is connected to the other end of the second resistor. The other end of the third resistor and the other end of the first capacitor are connected to the first reference voltage terminal; The other end of the second capacitor and the other end of the third capacitor are grounded.

5. The detection device according to claim 4, characterized in that, The overcurrent comparator circuit includes: Fifth resistor, sixth resistor, seventh resistor, eighth resistor, ninth resistor, tenth resistor, eleventh resistor, twelfth resistor, fifth capacitor, sixth capacitor, seventh capacitor, eighth capacitor, ninth capacitor, second amplifier, and third amplifier; The inverting input terminal of the second amplifier, one end of the fifth resistor, and one end of the fifth capacitor are coupled to the fourth node; the non-inverting input terminal of the second amplifier, one end of the ninth resistor, one end of the tenth resistor, and one end of the sixth capacitor are coupled to the fifth node. The inverting input terminal of the third amplifier, one end of the eleventh resistor, one end of the twelfth resistor, and one end of the seventh capacitor are coupled to the sixth node; the non-inverting input terminal of the third amplifier, one end of the sixth resistor, and one end of the eighth capacitor are coupled to the seventh node. The output terminals of the second amplifier, the third amplifier, one end of the seventh resistor, and one end of the eighth resistor are coupled to the eighth node; the other end of the seventh resistor and one end of the ninth capacitor are coupled to the ninth node. The other end of the ninth resistor and the other end of the eleventh resistor are connected to the second reference voltage terminal; the other end of the tenth resistor, the other end of the twelfth resistor, the other end of the fifth capacitor, the other end of the sixth capacitor, the other end of the seventh capacitor, the other end of the eighth capacitor, and the other end of the ninth capacitor are grounded. The other end of the fifth resistor and the other end of the sixth resistor are coupled to the third node; the other end of the eighth resistor is connected to the first drive voltage output terminal.

6. The detection device according to claim 5, characterized in that, The input of the first controller is coupled to the ninth node.

7. The detection device according to claim 1 or 6, characterized in that, The first controller is a complex programmable logic device controller.

8. A photovoltaic grid-connected inverter with current limiting function, characterized in that, include: Inverter unit, second controller, driver, and detection device as described in any one of claims 1-7; The output terminal of the second controller is connected to the input terminal of the driver, and the output terminal of the driver is connected to the output current adjustment terminal of the inverter unit; The current sampling unit of the detection device is connected to the output circuit of the inverter unit; The output of the first controller of the detection device is connected to the interrupt interface of the second controller.

9. The inverter according to claim 8, characterized in that, The inverter unit includes a boost unit and an active neutral-point clamped three-level topology inverter unit; The output of the boost unit is connected to the input of the neutral-point clamped three-level topology inverter unit; The output terminal of the driver is connected to the output current adjustment terminal of the neutral point clamped three-level topology inverter unit; The current sampling unit of the detection device is connected to the output circuit of the neutral-point clamped three-level topology inverter unit.

10. The inverter according to claim 8, characterized in that, The second controller is a digital signal processor.

Images