Control circuit and power converter circuit

Abstract

The utility model discloses a control circuit and power converter circuit, control circuit is used for a power converter circuit, contains a comparison circuit, is used for comparing a first ramp signal and a second ramp signal, and is according to with control a power stage circuit, a ramp generation circuit, is used for a first signal of a switch node, generates the first ramp signal, an error amplifier circuit, is used for comparing a reference voltage signal and an output voltage to generate an error signal, a compensation circuit and an adjusting circuit, are used for generating an adjusting current according to the second signal of the switch node, and the adjusting current is affected the error signal through the compensation circuit and generates the second ramp signal, wherein the change trend of the adjusting current is opposite with the change trend of the first ramp signal.

Description

Technical Field

[0001] This utility model relates to a control circuit and a power converter circuit, and more particularly to a control circuit and a power converter circuit that can improve stability and reliability. Background Technology

[0002] In existing technologies, the Constant On-Time (COT) control architecture is widely used in buck converters. The COT control architecture typically uses a comparator to compare a ramp signal and an error signal to control the on / off state of the power stage circuit, thereby regulating the output voltage. The ramp signal is generated by a ramp signal generator based on the voltage between the power stage circuit and the inductor, while the error signal is generated by an error amplifier comparing the output voltage with a reference voltage. However, due to the bandwidth limitations of the error amplifier, its output error signal often lags behind the ramp signal, potentially causing a control delay and failing to reflect changes in the output voltage in real time. Furthermore, under certain operating conditions, the error signal and the ramp signal may change in the same direction, further reducing the accuracy of the comparison judgment.

[0003] Secondly, because the error signal lags behind the ramp signal and its trend may be in the same direction as the ramp signal, the comparator may generate two or more control pulses within a single pulse cycle, i.e., a double-pulse or multi-pulse phenomenon. This phenomenon will cause abnormal switching timing of the power stage circuit and result in abnormal disturbances or oscillations in the output voltage, leading to unexpected jitter. Furthermore, when the system is subjected to external interference, the lack of sufficient phase separation between the error signal and the ramp signal can easily cause false triggering of the comparator, further affecting the stability of the output voltage.

[0004] Therefore, overcoming the aforementioned control signal delay, insufficient noise immunity, and avoiding the generation of double or multiple pulses remain urgent issues to be addressed in this field. Utility Model Content

[0005] Therefore, the main objective of this invention is to provide a control circuit and a power converter circuit to overcome the shortcomings of the prior art.

[0006] This utility model embodiment provides a control circuit for a power converter circuit, wherein the power converter circuit includes a power stage circuit and generates an output voltage via an inductor. The control circuit includes a control node; a comparator circuit including a negative input terminal for receiving a first ramp signal and a positive input terminal for receiving a second ramp signal from the control node, the comparator circuit being used to compare the first ramp signal and the second ramp signal, and thereby control the power stage circuit; and a ramp generation circuit coupled to the negative input terminal of the comparator circuit and a switching node between the power stage circuit and the inductor, for controlling the output voltage based on the first ramp signal and the second ramp signal. A first signal from a switching node generates a first ramp signal; an error amplifier circuit, coupled to the control node, compares a reference voltage signal and the output voltage to generate an error signal to the control node; a compensation circuit is coupled between the control node and a ground terminal; and an adjustment circuit, coupled to the control node and the switching node, generates an adjustment current to the control node based on a second signal from the switching node. This adjustment current, through the compensation circuit, influences the error signal to generate the second ramp signal at the control node; wherein the trend of the adjustment current is opposite to the trend of the first ramp signal.

[0007] Specifically, when the comparator circuit controls the power stage circuit to charge the inductor, the adjustment current decreases to reduce the voltage of the second ramp signal, thereby increasing the separation between the second ramp signal and the first ramp signal; and when the comparator circuit controls the power stage circuit not to charge the inductor, the adjustment current increases to help increase the voltage of the second ramp signal to cross the first ramp signal.

[0008] Wherein, the first signal is the voltage of the switching node, and the second signal is the same as the first signal. The adjustment circuit includes: a filter circuit coupled to the ramp generation circuit for filtering the first ramp signal to generate a filter signal; and a voltage-to-current amplifier coupled to the ramp generation circuit, the filter circuit and the control node for comparing the filter signal with the first ramp signal and generating the adjustment current based on the difference between the filter signal and the first ramp signal.

[0009] The first ramp signal is close to a triangular waveform, and the filtered signal is close to a sine wave signal or a DC signal.

[0010] The ramp generation circuit includes a first low-pass filter and a second low-pass filter. The first low-pass filter performs low-pass filtering on the pair of first signals to generate a first ramp signal, and the second low-pass filter performs low-pass filtering on the pair of first ramp signals to generate the filtered signal.

[0011] Wherein, the first signal is the voltage of the switching node, and the second signal is an inductor current from the switching node to the inductor. The adjustment circuit includes: a current sensor coupled between the switching node and the inductor for sensing the inductor current to generate an inductor current sensing signal; and a current sensing amplifier coupled between the current sensor and the control node for generating the adjustment current based on the inductor current sensing signal to adjust the voltage of the second ramp signal through the compensation circuit.

[0012] The compensation circuit includes a resistor and a capacitor connected in series between the positive input terminal and the ground terminal of the comparator circuit.

[0013] The comparison circuit triggers all switching circuits of the power converter circuit to control the power stage circuit to operate according to a preset on-time when the comparison result indicates that the second ramp signal continues to exceed the first ramp signal, thereby increasing the current of the output voltage.

[0014] This utility model embodiment further provides a power converter circuit for converting an input voltage into an output voltage, comprising: a switching node; an output terminal for outputting the output voltage; an inductor coupled between the switching node and the output terminal; a power stage circuit coupled to the input voltage and the switching node; a switching circuit coupled to the power stage circuit for controlling the power stage circuit to switch the input voltage according to a control signal; a control circuit including a control node; a comparator circuit including a negative input terminal for receiving a first ramp signal, a positive input terminal for receiving a second ramp signal from the control node, and a control terminal coupled to the switching circuit. The comparator circuit is used to compare the first ramp signal and the second ramp signal, and accordingly control the switching node to switch the input voltage. The control circuit outputs the control signal to the switching circuit; a ramp generation circuit, coupled to the negative input terminal of the comparator circuit and the switching node, is used to generate the first ramp signal based on a first signal from the switching node; an error amplifier circuit, coupled to the control node, is used to compare a reference voltage signal and the output voltage to generate an error signal to the control node; a compensation circuit is coupled between the control node and a ground terminal; and an adjustment circuit, coupled to the control node and the switching node, is used to generate an adjustment current to the control node based on a second signal from the switching node. The adjustment current affects the error signal through the compensation circuit and generates the second ramp signal at the control node; wherein the trend of the adjustment current is opposite to the trend of the first ramp signal.

[0015] Wherein, the first signal is the voltage of the switching node, and the second signal is the same as the first signal. The adjustment circuit includes: a filter circuit coupled to the ramp generation circuit for filtering the first ramp signal to generate a filter signal; and a voltage-to-current amplifier coupled to the ramp generation circuit, the filter circuit and the control node for comparing the filter signal with the first ramp signal and generating the adjustment current based on the difference between the filter signal and the first ramp signal. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a power converter circuit according to an embodiment of the present invention.

[0017] Figure 2 This is a schematic diagram of a ramp wave generating circuit according to an embodiment of the present invention.

[0018] Figure 3 This is a schematic diagram of an adjustment circuit according to an embodiment of the present invention.

[0019] Figure 4 for Figure 1 A schematic diagram of the relevant signals of the power converter circuit.

[0020] Figure 5 This is a schematic diagram of an adjustment circuit according to an embodiment of the present invention.

[0021] Figure 6 for Figure 1 A schematic diagram of the relevant signals of the power converter circuit.

[0022] Figure 7 This is a schematic diagram of a conduction time generation circuit according to an embodiment of the present invention.

[0023] Figure 8 This is a schematic diagram of a control flow according to an embodiment of the present utility model.

[0024] Figure Label Explanation: 10-Power converter circuit; VIN-Input voltage; VOUT-Output voltage; NP-Switching node; L-Inductor; 100-Output terminal; COUT-Output capacitor; 12-Power stage circuit; UG-Upper bridge switch; LG-Lower bridge switch; 14-Switching circuit; 16-Control circuit; CTRL-Control signal; IL-Inductor current; 140-On-time generation circuit; 142-SR latch; S, R, Q, QB-Terminals; 144-Switch driver; PWM-Pulse Width Modulation (PWM) signal; PWMB-Inverting signal; TON-On-time signal; NX-Control node; 160-Comparator circuit; +-Positive input terminal; ---Negative input terminal; CT-Control terminal; RMP1-First ramp signal; RMP2-Second ramp signal; 162-Ramp generation circuit; S1-First signal; 164-Error amplifier circuit; VREF-Reference voltage signal; ER- Error signal; 166 - Compensation circuit; RC - Resistor; CC - Capacitor; GND - Ground; 168 - Adjustment circuit; S2 - Second signal; Icomp - Adjustment current; 20 - Ramp generation circuit; 200 - Resistor; 202 - Capacitor; 30 - Adjustment circuit; 32 - Ramp generation circuit; 320 - Resistor; 322 - Capacitor; RX1 - Ramp signal; 34 - Filter circuit; 340 - Resistor; 342 - Capacitor; RX2 - Filter signal; 36 - Voltage to current amplifier; 400~414, 600~608 - Curves; 50 - Adjustment circuit; 500 - Current sensor; ILsen - Inductor current sensing signal; 502 - Current sensing amplifier; 70 - On-time generation circuit; N - Node; 700 - Current source; ICH - Charging current; 702 - Capacitor; VCH - Charging voltage; 704 - Switch; 706 - Comparator; 80 - Control flow; 800~810 - Steps. Detailed Implementation

[0025] Please refer to Figure 1 , Figure 1This is a schematic diagram of a power converter circuit 10 according to an embodiment of the present invention. The power converter circuit 10 converts an input voltage VIN into an output voltage VOUT. It includes a switching node NP, an inductor L, an output terminal 100, a power stage circuit 12, a switching circuit 14, and a control circuit 16. The power stage circuit 12 includes an upper bridge switch UG and a lower bridge switch LG. The upper bridge switch UG is coupled between the input voltage VIN and the switching node NP, and the lower bridge switch LG is coupled between the lower bridge switch LG and a ground terminal GND. The inductor L is coupled between the switching node NP and the output terminal 100, and the output terminal 100 is coupled to an output capacitor COUT. The switching circuit 14 controls the on and off states of the upper bridge switch UG and the lower bridge switch LG according to a control signal CTRL generated by the control circuit 16, thereby switching the charging and discharging operation of the inductor L by the input voltage VIN. The input voltage VIN charges and discharges the inductor L, generating an inductor current IL, which in turn generates an output voltage VOUT of appropriate magnitude through the output capacitor COUT.

[0026] Specifically, the switching circuit 14 includes an on-time generation circuit 140, an SR latch 142, and a switch driver 144. The on-time generation circuit 140 receives the input voltage VIN, the output voltage VOUT, and the inverted signal PWMB of a pulse-width modulation (PWM) signal (hereinafter referred to as the PWM signal), and outputs an on-time signal TON accordingly. The SR latch 142 receives the control signal CTRL at its S terminal, the on-time signal TON at its R terminal, outputs the PWM signal PWM to the switch driver 144 at its Q terminal, and outputs the inverted signal PWMB to the on-time generation circuit 140 at its QB terminal. Therefore, the SR latch 142 can set the PWM signal PWM according to the control signal CTRL and reset the PWM signal PWM according to the on-time signal TON. The switch driver 144 is coupled to the SR latch 142 and the power stage circuit 12, and is used to control the power stage circuit 12 according to the PWM signal PWM.

[0027] In the power converter circuit 10, the control circuit 16 includes a control node NX, a comparator circuit 160, a ramp generation circuit 162, an error amplifier circuit 164, a compensation circuit 166, and an adjustment circuit 168. The comparator circuit 160 is implemented via an operational amplifier and includes a negative input terminal (in... Figure 1 Marked as "-"), a positive input terminal (in) Figure 1The circuit is labeled "+" and has a control terminal CT. The negative input terminal (-) is used to receive a first ramp signal RMP1 generated by the ramp generation circuit 162, and the positive input terminal (+) is used to receive a second ramp signal RMP2 by the control node NX. The control terminal CT is coupled to the switching circuit 14. The comparator circuit 160 compares the first ramp signal RMP1 and the second ramp signal RMP2, and outputs a control signal CTRL to the switching circuit 14 through the control terminal CT based on the comparison result of the first ramp signal RMP1 and the second ramp signal RMP2. That is, when the second ramp signal RMP2 continuously exceeds the first ramp signal RMP1 (i.e., RMP2≥RMP1), the control signal CTRL output by the comparator circuit 160 can trigger the switching circuit 14 to control the power stage circuit 12 to operate according to a preset conduction time, thereby increasing the inductor current IL and increasing the output voltage VOUT. Conversely, when the second ramp signal RMP2 is lower than the first ramp signal RMP1 (i.e., RMP2 < RMP1), the control signal CTRL output by the comparator circuit 160 controls the power stage circuit 12 to reduce the inductor current IL, thereby reducing the output voltage VOUT.

[0028] The ramp generation circuit 162 is coupled to the negative input terminal (-) of the comparator circuit 160 and the switching node NP, and is used to generate a first ramp signal RMP1 based on a first signal S1 from the switching node NP. Preferably, the first signal S1 is the voltage of the switching node NP, and the first ramp signal RMP1 generally presents a triangular waveform, with its rising phase corresponding to the charging of inductor L by the power stage circuit 12 (when the upper bridge switch UG is turned on), and its falling phase corresponding to the discharging phase of inductor L (when the lower bridge switch LG is turned on).

[0029] An error amplifier circuit 164 is coupled to the control node NX and the output terminal 100. It is used to compare a reference voltage signal VREF and the output voltage VOUT to generate an error signal ER to the control node NX. That is, the error signal ER is related to the difference (VREF-VOUT) between the reference voltage signal VREF and the output voltage VOUT. When the power stage circuit 12 charges the inductor L, the output voltage VOUT rises, causing the difference between the reference voltage signal VREF and the output voltage VOUT to decrease, thus the error signal ER shows a decreasing trend. When the inductor L discharges (when the inductor L is not charged), the output voltage VOUT decreases, causing the difference between the reference voltage signal VREF and the output voltage VOUT to increase, thus the error signal ER shows an increasing trend. Furthermore, the error signal ER can be of current or voltage type, and can be appropriately adjusted according to different system requirements.

[0030] In other words, when the power stage circuit 12 charges the inductor L (controlled by the switching circuit 14 according to the control signal CTRL), the first ramp signal RMP1 shows an upward trend, while the error signal ER shows a downward trend; when the inductor L discharges, the first ramp signal RMP1 shows a downward trend, while the error signal ER shows an upward trend.

[0031] The compensation circuit 166 includes a resistor RC and a capacitor CC, which are connected in series between the control node NX and the ground GND to maintain the stability of the closed-loop bandwidth of the system and control the phase edge of the loop to avoid system instability caused by changes in input voltage VIN, output voltage VOUT or load current.

[0032] The adjustment circuit 168 is coupled to the control node NX and the switching node NP, and is used to generate an adjustment current Icomp to the control node NX based on a second signal S2 from the switching node NP. The adjustment current Icomp and the error signal ER are injected into the compensation circuit 166 at the control node NX, so that the adjustment current Icomp can influence (pull up or pull down) the error signal ER, thereby generating a second ramp signal RMP2 at the control node NX. The trend of the adjustment current Icomp is opposite to the trend of the first ramp signal RMP1, thus assisting in adjusting the crossing and separation states of the first ramp signal RMP1 and the second ramp signal RMP2. This avoids the generation of double pulses or multi-pulses, thereby improving the stability of the output voltage VOUT and enhancing noise immunity.

[0033] In detail, since the comparator circuit 160 is implemented via an operational amplifier, its input impedance is ideally infinite. Therefore, the comparator circuit 160 typically does not allow current to flow into its positive input terminal (+). Assuming the error signal ER output by the error amplifier circuit 164 is current-type, the error signal ER and the adjustment current Icomp will sequentially pass through the control node NX, the resistor RC and capacitor CC of the compensation circuit 166, and finally conduct to the ground terminal GND. Therefore, the total current of the error signal ER and the adjustment current Icomp can generate a voltage difference at the control node NX, which is the second ramp signal RMP2. If the error signal ER output by the error amplifier circuit 164 is voltage-type, the adjustment current Icomp can generate a voltage difference at the control node NX, and this difference is superimposed on the voltage-type error signal ER to form the second ramp signal RMP2.

[0034] As can be seen from the above, the changing trend of the adjustment current Icomp is opposite to that of the first ramp signal RMP1, and the same as that of the error signal ER. That is, when the first ramp signal RMP1 rises (during the charging phase), the error signal ER decreases, and the adjustment current Icomp also decreases. Therefore, the adjustment current Icomp can strengthen the decreasing trend of the second ramp signal RMP2 through the compensation circuit 166, making the voltage of the second ramp signal RMP2 (compared to when the adjustment current Icomp is not injected) even lower. When the first ramp signal RMP1 falls (during the discharging phase), the error signal ER rises, and the adjustment current Icomp also increases. Therefore, the adjustment current Icomp can strengthen the increasing trend of the second ramp signal RMP2 through the compensation circuit 166, making the voltage of the second ramp signal RMP2 (compared to when the adjustment current Icomp is not injected) even higher. Thus, the adjustment current Icomp can help the second ramp signal RMP2 to more easily cross the first ramp signal RMP1 when crossover is required, and to separate more clearly from the first ramp signal RMP1 when separation from separation is required, thereby maintaining an appropriate separation degree.

[0035] Furthermore, adjusting the change trend of the current Icomp to be opposite to the change trend of the first ramp signal RMP1 can effectively increase the noise margin between the second ramp signal RMP2 and the first ramp signal RMP1, and prevent the comparator circuit 160 from generating double pulse or multi pulse phenomena due to noise interference in a single pulse cycle. This prevents abnormal disturbances or oscillations in the output voltage VOUT, improves the overall stability and reliability of the system, and performs better, especially in high-noise environments or under rapid load changes.

[0036] It should be noted that, Figure 1 The purpose is to present the core architecture and operating principle of the power converter circuit 10. Those skilled in the art should design or adjust its circuit architecture appropriately according to system requirements, application areas, etc.

[0037] In the power converter circuit 10, the ramp generation circuit 162 generates a first ramp signal RMP1 based on the first signal S1 of the switching node NP. Furthermore, when the power stage circuit 12 charges the inductor L, the first ramp signal RMP1 exhibits an upward trend, and when the inductor L discharges, the first ramp signal RMP1 exhibits a downward trend. Any circuit capable of achieving this trend can be used to implement the ramp generation circuit 162. For example, please refer to... Figure 2 , Figure 2 This is a schematic diagram of a ramp wave generating circuit 20 according to an embodiment of the present invention. The ramp wave generating circuit 20 is used to implement... Figure 1The ramp generation circuit 162 includes a resistor 200 and a capacitor 202 connected in series. Resistor 200 is coupled between the switching node NP and the negative input terminal (-) of the comparator circuit 160, while capacitor 202 is coupled between the negative input terminal (-) of the comparator circuit 160 and ground GND. Based on this connection, resistor 200 and capacitor 202 form a low-pass filter to low-pass filter the first signal S1 to generate the first ramp signal RMP1. In other words, the ramp generation circuit 20 includes a low-pass filter, which is similar to an integrator. When the first signal S1 of the switching node NP is a square wave, after integration by resistor 200 and capacitor 202, a first ramp signal RMP1 approaching a triangular waveform can be output. Furthermore, the waveform characteristics of the first ramp signal RMP1 can be controlled by adjusting the resistance value of resistor 200 or the capacitance value of capacitor 202.

[0038] Furthermore, in the aforementioned embodiments, the first signal S1 of the switching node NP is preferably a voltage type, which relates to the switching of the upper bridge switch UG and the lower bridge switch LG. The second signal S2 of the switching node NP can be either a voltage type or a current type; in other words, the second signal S2 can be the same voltage of the switching node NP as the first signal S1, or it can be different from the first signal S1 and represent the current from the switching node NP to the inductor L. Regardless of the choice of the second signal S2, as long as the changing trend of the current Icomp is adjusted to be approximately opposite to the changing trend of the first ramp signal RMP1, the requirements of this invention can be met.

[0039] For example, please refer to Figure 3 , Figure 3 This is a schematic diagram of an adjustment circuit 30 according to an embodiment of the present invention. The adjustment circuit 30 is used to implement... Figure 1 The adjustment circuit 168 is used, and in this embodiment, the first signal S1 is the voltage of the switching node NP, while the second signal S2 is the same as the first signal S1. The adjustment circuit 30 includes a ramp generation circuit 32, a filter circuit 34, and a voltage-to-current amplifier 36. The ramp generation circuit 32 includes a resistor 320 and a capacitor 322. The resistor 320 is coupled between the switching node NP and the negative input terminal (-) of the voltage-to-current amplifier 36, while the capacitor 322 is coupled between the negative input terminal (-) of the voltage-to-current amplifier 36 and ground GND. According to the above connection, the resistor 320 and the capacitor 322 form a low-pass filter to perform low-pass filtering on the first signal S1 to generate a ramp signal RX1. In other words, the ramp generation circuit 32 is similar to an integrator. When the first signal S1 of the switching node NP is a square wave, after integration by the resistor 320 and the capacitor 322, a ramp signal RX1 close to a triangular waveform can be output.

[0040] Filtering circuit 34 is coupled to ramp generation circuit 32 to filter ramp signal RX1 to generate a filtered signal RX2. Filtering circuit 34 includes a resistor 340 and a capacitor 342. One end of resistor 340 is coupled between resistor 320, capacitor 322, and the negative input terminal (-) of voltage-to-current amplifier 36. The other end is coupled between the positive input terminal (+) of voltage-to-current amplifier 36 and capacitor 342. Capacitor 342 is then coupled to ground (GND). Based on this connection, resistor 340 and capacitor 342 form a low-pass filter to perform low-pass filtering on ramp signal RX1 to generate filtered signal RX2. In other words, filtering circuit 34 also functions as an integrator, performing a second integration on ramp signal RX1 output by ramp generation circuit 32. In this case, if ramp signal RX1 is close to a triangular waveform, then filtered signal RX2 is close to a sine wave or DC signal.

[0041] The voltage-to-current amplifier 36 is coupled to the ramp generation circuit 320, the filter circuit 34, and the control node NX. It is used to compare the filtered signal RX2 with the ramp signal RX1, and generate an adjustment current Icomp based on the difference between the filtered signal RX2 and the ramp signal RX1 (i.e., RX2-RX1). This adjustment current is then used by the compensation circuit 166 to adjust the voltage of the second ramp signal RMP2. In other words, if the conversion gain of the voltage-to-current amplifier 36 is gm, then Icomp = gm × (RX2-RX1).

[0042] It should be noted that the comparison Figure 2 and Figure 3 It can be seen that, Figure 2 The ramp wave generating circuit 20 and Figure 3 The ramp generation circuits 32 in the circuits have the same structure and all generate ramp signals based on the voltage of the switching node NP. In this case, if the negative input terminal (-) of the comparator circuit 160 is connected to the negative input terminal (-) of resistors 320, 340, and voltage-to-current amplifier 36, then the resistors 200 and 202 of the ramp generation circuit 20 can be replaced by the resistors 320 and 322 of the ramp generation circuit 32, and the ramp signal RX1 is the first ramp signal RMP1. In this case, the adjustment circuit 168 only needs to include the filter circuit 34 and the voltage-to-current amplifier 36 to achieve the same operating result. That is, when both the first signal S1 and the second signal S2 are the voltage of the switching node NP, regardless of the voltage of the switching node NP, the ramp signal is generated by the voltage of the switching node NP. Figure 2 The ramp generation circuit 20 implements the ramp generation circuit 162 and uses it to generate ramps. Figure 3 The adjustment circuit 30 implements the adjustment circuit 168, or in the form of... Figure 3 The ramp generation circuit 32 in the middle implements the ramp generation circuit 162 and uses it to generate ramps. Figure 3The filter circuit 34 and voltage-to-current amplifier 36 in the circuit realize the adjustment circuit 168. The power converter circuit 10 can enhance the signal separation effect by adjusting the current Icomp, and avoid false triggering in high noise environment.

[0043] Please continue to refer to this. Figure 4 , Figure 4 This is a schematic diagram of the relevant signals of the power converter circuit 10 when both the first signal S1 and the second signal S2 are at the voltage of the switching node NP. Figure 4 Curves 400 to 414 are shown from top to bottom. Curve 400 represents the inductor current IL, curve 402 represents the output voltage VOUT, curve 404 represents the voltage of the switching node NP (i.e., the first signal S1 or the second signal S2), curve 406 represents the adjustment current Icomp, curve 408 represents the first ramp signal RMP1 (or ramp signal RX1), curve 410 represents the second ramp signal RMP2, curve 412 represents the filter signal RX2, and curve 414 represents the pulse width modulation signal PWM.

[0044] Depend on Figure 4As can be seen, when the PWM signal PWM (curve 414) is at a low level, the upper bridge switch UG is off, the lower bridge switch LG is on, the voltage of the switching node NP (curve 404) is at a low level, the inductor L is in the discharge stage, and the inductor current IL (curve 400) continues to decrease. At this time, the first ramp signal RMP1 (curve 408) generated by the ramp generation circuit 162 (implemented by ramp generation circuit 20 or 32) based on the voltage of the switching node NP (first signal S1) shows a decreasing trend. At the same time, the filter circuit 34 filters the first ramp signal RMP1 (or ramp signal RX1) to generate the filtered signal RX2 (curve 412), which has a small change amplitude. The voltage-to-current amplifier 36 compares the filtered signal RX2 with the first ramp signal RMP1 to generate the adjustment current Icomp (curve 406). As the first ramp signal RMP1 (curve 408) decreases, the adjustment current Icomp (curve 406) increases. The compensation circuit 166 then pulls the error signal ER high, strengthening the upward trend of the second ramp signal RMP2 (curve 410), which is opposite to the downward trend of the first ramp signal RMP1. When the second ramp signal RMP2 (curve 410) crosses the first ramp signal RMP1 (curve 408), the comparator circuit 160 outputs the control signal CTRL, triggering the SR latch 142 to set the PWM signal PWM (curve 414) to a high level, entering the charging cycle. When the PWM signal PWM (curve 414) is at a high level, the upper bridge switch UG is turned on, the voltage of the switching node NP (curve 404) is at a high level, and the power stage circuit 12 charges the inductor L, increasing the inductor current IL (curve 400). At this time, the first ramp signal RMP1 (curve 408) shows an upward trend, approaching a triangular waveform. Meanwhile, the filtered signal RX2 (curve 412) generated by the filter circuit 34 has a small amplitude variation, close to a sine wave signal. As the first ramp signal RMP1 rises, the adjustment current Icomp shows a downward trend. The compensation circuit 166 pulls the error signal ER down, strengthening the downward trend of the second ramp signal RMP2 (curve 410), which is opposite to the upward trend of the first ramp signal RMP1. This increases the noise tolerance between the two, avoids the comparator circuit 160 from generating double pulses or multiple pulses due to noise interference, and ensures the stability of the output voltage VOUT (curve 402).

[0045] Figure 4 The signal waveform diagram shows the opposite trend of the adjustment current Icomp (curve 406) and the first ramp signal RMP1 (curve 408), which can strengthen the opposite trend of the second ramp signal RMP2 (curve 410) and the first ramp signal RMP1, ensuring that the second ramp signal RMP2 can more easily cross the first ramp signal RMP1 when crossover is required, and can be more clearly separated when separation is required, thereby improving the stability and noise immunity of the power converter circuit 10.

[0046] On the other hand, please refer to Figure 5 , Figure 5 This is a schematic diagram of an adjustment circuit 50 according to an embodiment of the present invention. The adjustment circuit 50 is used to implement... Figure 1 The adjustment circuit 168 is included in this embodiment. In this embodiment, the first signal S1 is the voltage of the switching node NP, and the second signal S2 is different from the first signal S1, representing the current from the switching node NP to the inductor L. The adjustment circuit 50 includes a current sensor 500 and a current sensing amplifier 502. The current sensor 500 is coupled between the switching node NP and the inductor L to sense the inductor current IL, generating an inductor current sensing signal ILsen. The current sensing amplifier 502 is coupled between the current sensor 500 and the control node NX, generating an adjustment current Icomp based on the inductor current sensing signal ILsen. The adjustment current Icomp has an inverse relationship with the inductor current sensing signal ILsen, adjusting the voltage of the second ramp signal RMP2 through the compensation circuit 166. That is, when the inductor current sensing signal ILsen rises, the current sensing amplifier 502 outputs a decreasing adjustment current Icomp; conversely, when the inductor current sensing signal ILsen falls, the current sensing amplifier 502 outputs an increasing adjustment current Icomp. This reverse relationship ensures that the trend of the adjustment current Icomp is opposite to that of the first ramp signal RMP1, thereby strengthening the opposite trend of the second ramp signal RMP2 to the first ramp signal RMP1, and further improving the signal separation and crossover accuracy.

[0047] Please continue to refer to this. Figure 6 , Figure 6 This is a schematic diagram of the relevant signals of the power converter circuit 10 when the adjustment circuit 50 is used to implement the adjustment circuit 168. Figure 6 Curves 600 to 608 are shown from top to bottom. Curve 600 represents the inductor current sensing signal ILsen, curve 602 represents the adjustment current Icomp, curve 604 represents the first ramp signal RMP1, curve 606 represents the second ramp signal RMP2, and curve 608 represents the voltage of the switching node NP (i.e., the first signal S1).

[0048] Specifically, when the PWM signal PWM is at a high level, the upper bridge switch UG is turned on, and the voltage of the switching node NP (curve 608) is at a high level. The power stage circuit 12 charges the inductor L, increasing the inductor current IL. Correspondingly, the inductor current sensing signal ILsen (curve 600) shows an upward trend. At this time, the ramp generation circuit 162 generates a first ramp signal RMP1 (curve 604) based on the voltage of the switching node NP (first signal S1), which shows an upward trend and is close to a triangular waveform. Simultaneously, the current sensing amplifier 502 generates a reduced adjustment current Icomp (curve 602) based on the upward trend of the inductor current sensing signal ILsen (curve 600). This reduced adjustment current Icomp pulls the error signal ER low through the compensation circuit 166, strengthening the second ramp signal RMP2 (curve 606) to show a downward trend, which is opposite to the upward trend of the first ramp signal RMP1 (curve 604). This increases the noise tolerance between the two, avoids the comparator circuit 160 from generating double pulses or multiple pulses due to noise interference, and ensures the stability of the output voltage VOUT. When the pulse width modulation (PWM) signal turns to a low level, the upper bridge switch UG turns off, the lower bridge switch LG turns on, and the voltage of the switching node NP (curve 608) turns to a low level. Inductor L begins to discharge, and the inductor current IL decreases, corresponding to a downward trend in the inductor current sensing signal ILsen (curve 600). At this time, the first ramp signal RMP1 (curve 604) also shows a downward trend. Based on the downward trend of the inductor current sensing signal ILsen (curve 600), the current sensing amplifier 502 generates an increased adjustment current Icomp (curve 602). This increased adjustment current Icomp, through the compensation circuit 166, pulls the error signal ER high, strengthening the upward trend of the second ramp signal RMP2 (curve 606), which is opposite to the downward trend of the first ramp signal RMP1 (curve 604). When the second ramp signal RMP2 (curve 606) crosses the first ramp signal RMP1 (curve 604), the comparator circuit 160 outputs the control signal CTRL, triggering the SR latch 142 to set the pulse width modulation signal PWM to a high level, and enters the next charging cycle, stabilizing the cycle.

[0049] Figure 6 The signal waveform diagram shows the inverse relationship between the adjustment current Icomp (curve 602), the inductor current sensing signal ILsen (curve 600), and the first ramp signal RMP1 (curve 604), which strengthens the opposite trend between the second ramp signal RMP2 (curve 606) and the first ramp signal RMP1. This ensures that the second ramp signal RMP2 can more easily cross the first ramp signal RMP1 when crossover is required, and can be more clearly separated when separation is required, thereby improving the stability and noise immunity of the power converter circuit 10, which is especially suitable for application scenarios with drastic current changes.

[0050] As described above, regardless of the selection of the second signal S2 (e.g., the voltage of the switching node NP or the inductor current IL), the power converter circuit 10 of this embodiment can make the changing trend of the adjustment current Icomp approximately opposite to the changing trend of the first ramp signal RMP1, thereby strengthening the opposite trend between the second ramp signal RMP2 and the first ramp signal RMP1. In this way, this embodiment ensures that the second ramp signal RMP2 can cross over the first ramp signal RMP1 more quickly and accurately when it needs to, and maintain a larger signal spacing when separation is required. This effectively improves the noise tolerance of the comparator circuit 160, avoids the comparator circuit 160 from generating double or multiple pulses due to noise interference within a single pulse cycle, and thus prevents abnormal disturbances or oscillations in the output voltage VOUT. This significantly improves the stability and reliability of the power converter circuit 10, especially under high-noise environments or rapid load changes.

[0051] Furthermore, other components or circuits in the power converter circuit 10 can be modified according to actual application requirements. For example, the specific implementation of the ramp generation circuit 162, the error amplifier circuit 164, or the compensation circuit 166 can be adjusted according to the system's bandwidth requirements, load characteristics, or input voltage range. Similarly, the design of the switching circuit 14 can also be flexibly changed to adapt to different control strategies or voltage conversion requirements.

[0052] For example, please refer to Figure 7 , Figure 7 This is a schematic diagram of a conduction time generation circuit 70 according to an embodiment of the present invention. The conduction time generation circuit 70 can realize... Figure 1The on-time generation circuit 140 includes a node N, a current source 700, a capacitor 702, a switch 704, and a comparator 706. The current source 700 generates a charging current ICH to node N based on the input voltage VIN and a conversion gain gm_t. The conversion gain gm_t can adjust the conversion ratio of the input voltage VIN to the charging current ICH to adapt to different input voltage ranges or system requirements. The capacitor 702 is coupled between node N and ground GND and is used to charge according to the charging current ICH to generate a charging voltage VCH. The switch 704 is coupled to node N and controls the discharge of capacitor 702 according to the inverted signal PWMB. The comparator 706 is coupled to node N and the R terminal of the SR latch 142 and compares the charging voltage VCH with the output voltage VOUT to generate an on-time signal TON, which determines the off-time of the PWM signal PWM. When the pulse width modulation signal PWM is at a high level, switch 704 is turned off, and current source 700 charges capacitor 702, causing the charging voltage VCH to rise. When the charging voltage VCH exceeds the output voltage VOUT, the on-time signal TON output by comparator 706 is at a high level, resetting SR latch 142, causing the PWM signal PWM to switch to a low level, and turning on switch 704 to accelerate the discharge of capacitor 702. This structure provides fixed on-time control, ensuring stable operation over a wide input voltage range, and the on-time can be precisely controlled by adjusting the conversion gain gm_t or the capacitance value of capacitor 702 to meet the needs of different application scenarios.

[0053] The operation of the power converter circuit 10 described above can be summarized as a control flow 80, such as... Figure 8 As shown, but not limited to, control flow 80 includes the following steps:

[0054] Step 800: Begin.

[0055] Step 802: Generate the first ramp signal RMP1 based on the first signal S1 of the switch node NP.

[0056] Step 804: Generate an error signal ER based on the reference voltage signal VREF and the output voltage VOUT.

[0057] Step 806: Based on the second signal S2 of the switch node NP, an adjustment current Icomp is generated. The adjustment current Icomp affects the error signal ER through the compensation circuit 166 to generate a second ramp signal RMP2, and the changing trend of the adjustment current Icomp is opposite to the changing trend of the first ramp signal RMP1.

[0058] Step 808: Compare the first ramp signal RMP1 with the second ramp signal RMP2, and control the power stage circuit 12 accordingly.

[0059] Step 810: End.

[0060] For a detailed description of control flow 80 and its derivative variations, please refer to the foregoing; they will not be repeated here.

[0061] Existing power converter circuits are prone to double-pulse or multi-pulse phenomena in high-noise environments due to insufficient noise tolerance of the comparator input signal, leading to unstable or oscillating output voltage. This embodiment of the invention generates an adjustment current Icomp with a trend opposite to that of the first ramp signal RMP1 through an adjustment circuit 168, and combines this with the error signal ER from the error amplifier circuit 164 to form a second ramp signal RMP2 with a trend opposite to that of the first ramp signal RMP1. This design not only enhances the separation between signals but also ensures the accuracy of the crossover point, thereby significantly improving noise immunity and system stability. Furthermore, this invention allows for flexible selection of the second signal S2 (e.g., voltage or current), making it suitable for different application requirements and offering higher adaptability and reliability compared to existing technologies.

[0062] In summary, the embodiments of this utility model can effectively avoid the generation of double pulses or multiple pulses, and improve the stability and reliability of the system under high noise environment and rapid load change.

Claims

1. A control circuit for a power converter circuit, characterized in that, The power converter circuit includes a power stage circuit and generates an output voltage via an inductor. The control circuit includes: One control node; A comparator circuit includes a negative input terminal for receiving a first ramp signal and a positive input terminal for receiving a second ramp signal from the control node. The comparator circuit is used to compare the first ramp signal and the second ramp signal and control the power stage circuit accordingly. A ramp generation circuit is coupled to the negative input terminal of the comparator circuit and a switching node between the power stage circuit and the inductor, and is used to generate the first ramp signal according to a first signal of the switching node. An error amplifier circuit, coupled to the control node, is used to compare a reference voltage signal and the output voltage to generate an error signal to the control node. A compensation circuit is coupled between the control node and a ground terminal; as well as An adjustment circuit, coupled to the control node and the switch node, is used to generate an adjustment current to the control node according to a second signal from the switch node. The adjustment current affects the error signal through the compensation circuit and generates the second ramp signal at the control node. The trend of the adjustment current is opposite to the trend of the first ramp signal.

2. The control circuit as described in claim 1, characterized in that, When the comparator circuit controls the power stage circuit to charge the inductor, the adjustment current decreases to reduce the voltage of the second ramp signal, thereby increasing the separation between the second ramp signal and the first ramp signal; and when the comparator circuit controls the power stage circuit not to charge the inductor, the adjustment current increases to help increase the voltage of the second ramp signal to cross the first ramp signal.

3. The control circuit as described in claim 1, characterized in that, The first signal is the voltage of the switching node, and the second signal is the same as the first signal. The adjustment circuit includes: A filter circuit, coupled to the ramp generation circuit, is used to filter the first ramp signal to generate a filtered signal; and A voltage-to-current amplifier is coupled to the ramp generation circuit, the filter circuit, and the control node to compare the filtered signal with the first ramp signal and generate the adjustment current based on the difference between the filtered signal and the first ramp signal.

4. The control circuit as described in claim 3, characterized in that, The first ramp signal is close to a triangular waveform, and the filtered signal is close to a sine wave signal or a DC signal.

5. The control circuit as described in claim 3, characterized in that, The ramp generation circuit includes a first low-pass filter and a second low-pass filter. The first low-pass filter performs low-pass filtering on the first signal to generate a first ramp signal, and the second low-pass filter performs low-pass filtering on the first ramp signal to generate the filtered signal.

6. The control circuit as described in claim 1, characterized in that, The first signal is the voltage of the switching node, and the second signal is an inductor current from the switching node to the inductor. The adjustment circuit includes: A current sensor, coupled between the switching node and the inductor, is used to sense the inductor current to generate an inductor current sensing signal; and A current sensing amplifier, coupled to the current sensor and the control node, is used to generate the adjustment current based on the inductor current sensing signal, so as to adjust the voltage of the second ramp signal through the compensation circuit.

7. The control circuit as described in claim 1, characterized in that, The compensation circuit includes a resistor and a capacitor connected in series between the positive input terminal and the ground terminal of the comparator circuit.

8. The control circuit as described in claim 1, characterized in that, When the comparison result indicates that the second ramp signal continues to exceed the first ramp signal, the comparison circuit triggers all switching circuits of the power converter circuit to control the power stage circuit to operate according to a preset on-time, thereby increasing the current of the output voltage.

9. A power converter circuit for converting an input voltage into an output voltage, characterized in that, Include: One switch node; One output terminal is used to output the output voltage; An inductor is coupled between the switching node and the output terminal; A power stage circuit is coupled to the input voltage and the switching node; A switching circuit, coupled to the power stage circuit, is used to control the power stage circuit to switch the input voltage according to a control signal; A control circuit, comprising: One control node; A comparator circuit includes a negative input terminal for receiving a first ramp signal, a positive input terminal for receiving a second ramp signal from the control node, and a control terminal coupled to the switching circuit. The comparator circuit is used to compare the first ramp signal and the second ramp signal, and outputs the control signal to the switching circuit through the control terminal accordingly. A ramp generation circuit is coupled to the negative input terminal of the comparator circuit and the switching node, and is used to generate the first ramp signal according to a first signal of the switching node. An error amplifier circuit, coupled to the control node, is used to compare a reference voltage signal and the output voltage to generate an error signal to the control node. A compensation circuit is coupled between the control node and a ground terminal; as well as An adjustment circuit, coupled to the control node and the switch node, is used to generate an adjustment current to the control node according to a second signal from the switch node. The adjustment current affects the error signal through the compensation circuit and generates the second ramp signal at the control node. The trend of the adjustment current is opposite to the trend of the first ramp signal.

10. The power converter circuit as described in claim 9, characterized in that, The first signal is the voltage of the switching node, and the second signal is the same as the first signal. The adjustment circuit includes: A filter circuit, coupled to the ramp generation circuit, is used to filter the first ramp signal to generate a filtered signal; and A voltage-to-current amplifier is coupled to the ramp generation circuit, the filter circuit, and the control node to compare the filtered signal with the first ramp signal and generate the adjustment current based on the difference between the filtered signal and the first ramp signal.

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