A bleed circuit

Abstract

The utility model discloses a kind of discharge circuits, comprising: +15V power supply end, power supply main power loop connection end OUT V+, power supply output end VO+, OUT-, current discharge control signal end ON / OFF, comparator U1, triode Q1, MOS tube Q2, Q3, diode D1, capacitor C1, C2, C3, C4, resistance R1, R2, R3, R4, R5, R6, R7, R8, R9.The discharge circuit of the utility model, it can control to discharge current, to reach the current size of the need of stable discharge.

Description

Technical Field

[0001] This utility model relates to a discharge circuit. Background Technology

[0002] In power supply circuits, filter capacitors are often set up. When the power output is turned off, the charge on the capacitor is difficult to discharge quickly, which will affect the rate of voltage drop at the port when the power is turned off. Therefore, a discharge circuit needs to be designed to achieve the required current for stable discharge. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this utility model provides a discharge circuit, comprising: a +15V power supply terminal, a main power circuit connection terminal OUT V+, power output terminals VO+ and OUT-, a current discharge control signal terminal ON / OFF, a comparator U1, a transistor Q1, MOSFETs Q2 and Q3, a diode D1, capacitors C1, C2, C3, and C4, and resistors R1, R2, R3, R4, R5, R6, R7, R8, and R9; The current discharge control signal terminal ON / OFF is connected to the base of transistor Q1 through resistor R1. The emitter of transistor Q1 is connected to the power output terminal OUT-. The collector of transistor Q1 is connected to the +15V power supply terminal through resistor R2. The collector of transistor Q1 is also connected to the gate of MOSFET Q2 through resistor R4. The source of MOSFET Q2 is connected to the power output terminal OUT-. The drain of MOSFET Q2 is connected to the +15V power supply terminal through resistor R3. Resistor R5 and capacitor C1 are connected in parallel between the source and drain of MOSFET Q2. The drain is also connected to the non-inverting input of comparator U1. The inverting input of comparator U1 is connected to the output of comparator U1 through resistor R6 and capacitor C2. The inverting input of comparator U1 is also connected to the output of comparator U1 through diode D1. The inverting input of comparator U1 is also connected to the power output terminal OUT- through resistors R8 and R9. The output of comparator U1 is also connected to the gate of MOSFET Q3 through resistor R7. The source of MOSFET Q3 is connected between resistors R8 and R9. The drain of MOSFET Q3 is connected to the main power circuit connection terminal OUT V+. The drain of MOSFET Q3 is also connected to the power output terminal VO+. Capacitors C3 and C4 are connected in parallel between the drain of MOSFET Q3 and the power output terminal OUT-.

[0004] Preferably, the comparator U1 is an LM393.

[0005] Preferably, the MOS transistors Q2 and Q3 are NMOS transistors.

[0006] Preferably, the capacitor C4 is an electrolytic capacitor.

[0007] The advantages and beneficial effects of this utility model are as follows: it provides a discharge circuit that can control the discharge current to achieve a stable discharge current.

[0008] The main power circuit connection terminal OUT V+ is connected to the main power circuit. C3 and C4 are port filters, Q3 is a current discharge MOSFET, R3, R5, U1, and R9 form a discharge size control circuit, and Q1 and Q2 form a discharge control switch. The current discharge control signal ON / OFF at the current discharge control signal terminal is sent to Q1 and Q2 via R1 to control the magnitude of the discharge current. It drives the MOSFET Q3 through comparator U1. Q3 executes the actual current output. When the current i of Q3 flows through R9, it will form a voltage drop, which is sent back to the inverting input terminal of comparator U1 via R8. It is compared with the non-inverting input terminal of U1 to achieve the current magnitude required for stable discharge. Theoretical calculation of discharge current: I = 15 × R5 / ((R3 + R5) × R9). Attached Figure Description

[0009] Figure 1 This is the circuit diagram of the discharge circuit of this utility model. Detailed Implementation

[0010] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings and examples. The following examples are only used to more clearly illustrate the technical solution of this utility model and should not be construed as limiting the scope of protection of this utility model.

[0011] The specific technical solution of this utility model is as follows: like Figure 1 As shown, this utility model provides a discharge circuit, including: a +15V power supply terminal, a main power circuit connection terminal OUT V+, power output terminals VO+ and OUT-, a current discharge control signal terminal ON / OFF, a comparator U1, a transistor Q1, MOSFETs Q2 and Q3, a diode D1, capacitors C1, C2, C3, and C4, and resistors R1, R2, R3, R4, R5, R6, R7, R8, and R9; The comparator U1 is an LM393; MOSFETs Q2 and Q3 are NMOS transistors; capacitor C4 is an electrolytic capacitor; capacitor values: C1 is 220uF, C2 is 1nF, C3 is 560uF, and C4 is 0.47uF; resistor values: R1 is 10kΩ, R2 is 10kΩ, R3 is 10MΩ, R4 is 10Ω, R5 is 3kΩ, R6 is 10Ω, R7 is 10Ω, R8 is 1kΩ, and R9 is 10mΩ. The current discharge control signal terminal ON / OFF is connected to the base of transistor Q1 through resistor R1. The emitter of transistor Q1 is connected to the power output terminal OUT-. The collector of transistor Q1 is connected to the +15V power supply terminal through resistor R2. The collector of transistor Q1 is also connected to the gate of MOSFET Q2 through resistor R4. The source of MOSFET Q2 is connected to the power output terminal OUT-. The drain of MOSFET Q2 is connected to the +15V power supply terminal through resistor R3. Resistor R5 and capacitor C1 are connected in parallel between the source and drain of MOSFET Q2. The drain is also connected to the non-inverting input of comparator U1. The inverting input of comparator U1 is connected to the output of comparator U1 through resistor R6 and capacitor C2. The inverting input of comparator U1 is also connected to the output of comparator U1 through diode D1. The inverting input of comparator U1 is also connected to the power output terminal OUT- through resistors R8 and R9. The output of comparator U1 is also connected to the gate of MOSFET Q3 through resistor R7. The source of MOSFET Q3 is connected between resistors R8 and R9. The drain of MOSFET Q3 is connected to the main power circuit connection terminal OUT V+. The drain of MOSFET Q3 is also connected to the power output terminal VO+. Capacitors C3 and C4 are connected in parallel between the drain of MOSFET Q3 and the power output terminal OUT-.

[0012] The function and working principle of the discharge circuit of this utility model include: The main power circuit connection terminal is OUT V+, C3 and C4 are port filters, Q3 is a current discharge MOSFET, R3, R5, U1 and R9 form a discharge size control circuit, and Q1 and Q2 form a discharge control switch. The current discharge control signal ON / OFF at the current discharge control signal terminal is sent to Q1 and Q2 via R1 to control the magnitude of the discharge current. It drives the MOSFET Q3 through comparator U1. Q3 executes the actual current output. When the current i of Q3 flows through R9, it will form a voltage drop, which is sent back to the inverting input terminal of comparator U1 via R8. It is compared with the non-inverting input terminal of U1 to achieve the current magnitude required for stable discharge. Theoretical calculation of discharge current: I = 15 × R5 / ((R3 + R5) × R9).

[0013] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.

Claims

1. A bleed circuit, characterized by include: +15V power supply terminal, main power circuit connection terminal OUT V+, power output terminals VO+, OUT-, current discharge control signal terminal ON / OFF, comparator U1, transistor Q1, MOSFETs Q2, Q3, diode D1, capacitors C1, C2, C3, C4, resistors R1, R2, R3, R4, R5, R6, R7, R8, R9; The current discharge control signal terminal ON / OFF is connected to the base of transistor Q1 through resistor R1. The emitter of transistor Q1 is connected to the power output terminal OUT-. The collector of transistor Q1 is connected to the +15V power supply terminal through resistor R2. The collector of transistor Q1 is also connected to the gate of MOSFET Q2 through resistor R4. The source of MOSFET Q2 is connected to the power output terminal OUT-. The drain of MOSFET Q2 is connected to the +15V power supply terminal through resistor R3. Resistor R5 and capacitor C1 are connected in parallel between the source and drain of MOSFET Q2. The drain is also connected to the non-inverting input of comparator U1. The inverting input of comparator U1 is connected to the output of comparator U1 through resistor R6 and capacitor C2. The inverting input of comparator U1 is also connected to the output of comparator U1 through diode D1. The inverting input of comparator U1 is also connected to the power output terminal OUT- through resistors R8 and R9. The output of comparator U1 is also connected to the gate of MOSFET Q3 through resistor R7. The source of MOSFET Q3 is connected between resistors R8 and R9. The drain of MOSFET Q3 is connected to the main power circuit connection terminal OUT V+. The drain of MOSFET Q3 is also connected to the power output terminal VO+. Capacitors C3 and C4 are connected in parallel between the drain of MOSFET Q3 and the power output terminal OUT-.

2. The discharge circuit according to claim 1, characterized in that, The comparator U1 is model LM393.

3. The bleed circuit of claim 1, wherein, The MOS transistors Q2 and Q3 are NMOS transistors.

4. The bleed circuit of claim 1, wherein, The capacitor C4 is an electrolytic capacitor.

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