Amplifier circuit and switching power supply

Abstract

The application discloses an amplifier circuit and a switching power supply. A first amplification unit is configured to output an amplification voltage. A second amplification unit is configured to output a first identification signal at a first output end according to the amplification voltage. The second amplification unit is also configured to output a second identification signal at a second output end according to a mismatch voltage and the amplification voltage. A loop compensation circuit is configured to pole-compensate the first identification signal and output a third identification signal after pole compensation at a third output end. The amplifier circuit multiplexes an error amplifier, a low-power comparator and a mode switching comparator into the same circuit, avoids problems caused by mismatch of mismatch voltages among the three modules, solves the problem of output voltage precision dispersion under different loads, avoids false exit from a low-power mode without sacrificing transient response, and saves power consumption and design cost of the circuit due to multiplexing of multiple circuits.

Description

Technical Field

[0001] This application relates to the field of amplifier technology, and more specifically, to an amplifier circuit and a switching power supply. Background Technology

[0002] For applications operating under load, an error amplifier is required to ensure the output voltage accuracy of the switching power supply. Furthermore, loop compensation is necessary to ensure system stability. However, due to manufacturing variations in the electronic components of the error amplifier and the comparator in low-power mode, offset voltage can be affected. It cannot be guaranteed that the comparator's offset voltage will match the error amplifier's offset voltage in low-power mode, leading to inaccurate error voltage values ​​output in low-power mode.

[0003] When the system is in low-power mode, if a load suddenly enters, the system needs to respond promptly, quickly turn on the power transistor to supply power, and exit low-power mode, while simultaneously waking up all standby modules on the chip. Therefore, the switching power supply needs an additional comparator circuit to detect the load connection status in real time. The offset voltage VOS can be manually set. When the output voltage VFB is detected to drop below the reference voltage Vref minus the offset voltage VOS, the output logic signal determines that a load has entered the output, and the system exits low-power mode. However, the input offset deviation of the comparator may cause a significant difference between the actual VOS and the manually set value. If the manually set VOS is too small, it may not even cover the comparator's input offset deviation, potentially leading to an incorrect exit from low-power mode. If the manually set VOS is too large, it will cause a deterioration in the system's transient response to load changes. Utility Model Content

[0004] This application provides an amplifier circuit and a switching power supply.

[0005] The amplifier circuit provided in this application embodiment may include a first amplification unit, a second amplification unit, a loop compensation circuit, a first output terminal, a second output terminal, and a third output terminal. The first amplification unit is configured to output an amplified voltage based on the voltage difference between the output voltage of the switching power supply and a reference voltage of the switching power supply. The second amplification unit is configured to output a first identification signal at the first output terminal based on the amplified voltage to identify the comparison result between the voltage value of the output voltage and the voltage value of the reference voltage. The second amplification unit is further configured to determine an offset voltage based on the amplified voltage, and to output a second identification signal at the second output terminal based on the offset voltage and the amplified voltage to identify the comparison result between the sum of the voltage values ​​of the output voltage and the offset voltage and the voltage value of the reference voltage. The loop compensation circuit is connected to the first output terminal and the third output terminal. The loop compensation circuit is configured to perform pole compensation on the first identification signal and output a third identification signal after pole compensation at the third output terminal to identify the voltage difference between the output voltage and the reference voltage.

[0006] The amplifier circuit in this embodiment reuses the error amplifier, low-power comparator, and mode-switching comparator into a single circuit, avoiding the problems caused by offset voltage mismatch between the three modules. This solves the problem of output voltage accuracy dispersion under different loads and prevents erroneous exit from low-power mode without sacrificing transient response. Furthermore, the reuse of multiple circuits also saves on circuit power consumption and design costs.

[0007] In some embodiments, the amplified voltage includes a first voltage and a second voltage, wherein the first voltage is positively correlated with the output voltage minus the reference voltage, and the second voltage is negatively correlated with the output voltage minus the reference voltage. The second amplification unit includes a first current generation circuit and a second current generation circuit. The first current generation circuit is configured to provide a first current based on the first voltage and a first proportionality coefficient. The second current generation circuit is configured to provide a second current based on the second voltage and the first proportionality coefficient. The second amplification unit is configured to determine the first identification signal based on a comparison between the first current value and the second current value.

[0008] In some embodiments, the second amplification unit includes a third current generation circuit configured to provide a third current based on the second voltage and a second proportionality coefficient, and the second amplification unit is configured to determine the second identification signal based on a comparison between the current value of the first current and the current value of the third current, wherein the offset voltage value is positively correlated with the second proportionality coefficient.

[0009] In some embodiments, the first current generating circuit includes a first input transistor and a first mirror transistor, which are connected in series between the voltage source of the amplifier circuit and ground. The first voltage is positively correlated with the voltage applied to the control electrode of the first input transistor. The second current generating circuit includes a second input transistor and a second mirror transistor, which are connected in series between the voltage source of the amplifier circuit and ground. The second voltage is positively correlated with the voltage applied to the control electrode of the second input transistor. The aspect ratio of the first mirror transistor is substantially the same as that of the second mirror transistor, and the aspect ratio of the first input transistor is substantially the same as that of the second input transistor.

[0010] In some embodiments, the first current generating circuit further includes a bias resistor connected between the first mirror transistor and the first input transistor, and configured to provide a bias voltage to the first mirror transistor to turn it on.

[0011] In some implementations, the first output terminal is connected between the second input transistor and the second mirror transistor.

[0012] In some embodiments, the third current generating circuit includes a third input transistor and a third mirror transistor, which are connected in series between the voltage source of the amplifier circuit and ground. The second voltage is positively correlated with the voltage connected to the control electrode of the third input transistor, and the second proportionality coefficient is positively correlated with the aspect ratio of the third mirror transistor.

[0013] In some implementations, the second output is connected between the third input transistor and the third mirror transistor.

[0014] In some embodiments, the control electrode of the second input transistor is connected to the control electrode of the third input transistor, and the control electrode of the first mirror transistor is connected to the control electrodes of the second mirror transistor and the third mirror transistor.

[0015] In some embodiments, the loop compensation circuit includes a gating switch and a compensation capacitor. The gating switch is connected between the first output terminal and the third output terminal, and the compensation capacitor is connected between the third output terminal and ground. When the gating switch is open, the first output terminal is configured to output the first identification signal; when the gating switch is on, both the first output terminal and the third output terminal are configured to output the third identification signal.

[0016] In some embodiments, the first amplification unit includes a bias current generating circuit, a fourth input transistor, a fifth input transistor, a first load, and a second load. The bias current generating circuit is configured to provide a bias current. The bias current generating circuit is grounded through the fourth input transistor and the first load, and the control terminal of the fourth input transistor is configured to be connected to the reference voltage. The bias current generating circuit is grounded through the fifth input transistor and the second load, and the control terminal of the fifth input transistor is configured to be connected to the output voltage. The fourth input transistor and the first load are connected to a first node, and the fifth input transistor and the second load are connected to a second node. The first node or the second node is configured to output the amplified voltage.

[0017] In some embodiments, the first load includes a first load transistor and a second load transistor, and the second load includes a third load transistor and a fourth load transistor. The control terminals of the first load transistor and the third load transistor are connected to the first input transistor, and the control terminals of the second load transistor and the fourth load transistor are connected to the second input transistor.

[0018] In some embodiments, the bias current generating circuit includes a bias transistor, the voltage source of the amplifier circuit is connected to the first input transistor and the second input transistor through the bias transistor, and the bias current is the current flowing through the bias transistor.

[0019] The switching power supply provided in this application includes the amplifier circuit of any of the above embodiments.

[0020] This application provides an amplifier circuit and a switching power supply. The amplifier circuit may include a first amplification unit, a second amplification unit, a loop compensation circuit, a first output terminal, a second output terminal, and a third output terminal. The first amplification unit is configured to output an amplified voltage based on the voltage difference between the output voltage and a reference voltage of the switching power supply. The second amplification unit is configured to output a first identification signal at the first output terminal based on the amplified voltage to indicate the comparison result between the voltage value of the output voltage and the voltage value of the reference voltage. The second amplification unit is further configured to determine an offset voltage based on the amplified voltage, and to output a second identification signal at the second output terminal based on the offset voltage and the amplified voltage to indicate the comparison result between the sum of the voltage values ​​of the output voltage and the offset voltage and the voltage value of the reference voltage. The loop compensation circuit is connected to the first output terminal and the third output terminal. The loop compensation circuit is configured to perform pole compensation on the first identification signal and output a third identification signal after pole compensation at the third output terminal to indicate the voltage difference between the output voltage and the reference voltage.

[0021] The amplifier circuit in this embodiment reuses the error amplifier, low-power comparator, and mode-switching comparator into a single circuit, avoiding the problems caused by offset voltage mismatch between the three modules. This solves the problem of output voltage accuracy dispersion under different loads and prevents erroneous exit from low-power mode without sacrificing transient response. Furthermore, the reuse of multiple circuits also saves on circuit power consumption and design costs.

[0022] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0023] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0024] Figure 1 This is a circuit diagram of the amplifier circuit according to an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of a switching power supply according to an embodiment of this application;

[0026] Figure 3 This is a circuit diagram of an error amplifier in certain amplifier circuits in related technologies;

[0027] Figure 4 This is a circuit diagram of a mode switching comparator in some amplifier circuits in related technologies;

[0028] Figure 5 This is a circuit diagram of the first amplification unit in an embodiment of this application;

[0029] Figure 6 This is a circuit diagram of the second amplification unit in an embodiment of this application.

[0030] Reference numerals: Amplifier circuit 100, First amplification unit 10, Second amplification unit 20, First output terminal 31, Second output terminal 32, Third output terminal 33, Loop compensation circuit 40, First current generating circuit 21, Second current generating circuit 22, Third current generating circuit 23, Selector switch 41, Compensation capacitor 42, Bias current generating circuit 11, First load 12, Second load 13, Switching power supply 1000. Detailed Implementation

[0031] The embodiments of this application are described in detail below. These embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0032] Reference Figure 1 as well as Figure 2 This application provides an amplifier circuit 100 and a switching power supply 1000. The switching power supply 1000 provided in this application includes the amplifier circuit 100. The amplifier circuit 100 of the switching power supply 1000 provided in this application may include a first amplification unit 10, a second amplification unit 20, a first output terminal 31, a second output terminal 32, a third output terminal 33, and a loop compensation circuit 40. The first amplification unit 10 is configured to output an amplified voltage based on the voltage difference between the output voltage and a reference voltage of the switching power supply 1000. The second amplification unit 20 is configured to output a first identification signal at the first output terminal 31 based on the amplified voltage to identify the comparison result between the output voltage value and the reference voltage value. The second amplification unit 20 is further configured to determine an offset voltage based on the amplified voltage, and to output a second identification signal at the second output terminal 32 based on the offset voltage and the amplified voltage to identify the comparison result between the sum of the output voltage and the offset voltage and the reference voltage value. The loop compensation circuit 40 is connected to the first output terminal 31 and the third output terminal 33. The loop compensation circuit 40 is configured to perform pole compensation on the first identification signal and output the pole-compensated third identification signal at the third output terminal 33 to identify the voltage difference between the output voltage and the reference voltage.

[0033] In related technologies, for applications operating under load, an error amplifier is required to ensure the output voltage accuracy of the switching power supply. Furthermore, loop compensation is necessary for the error amplifier to ensure system stability. However, due to manufacturing variations in the electronic components of the error amplifier and the comparator in low-power mode, offset voltage can be affected. It cannot be guaranteed that the offset voltage of the comparator in low-power mode will match the offset voltage of the error amplifier, leading to inaccurate error voltage values ​​output in low-power mode.

[0034] Specifically, the circuit of the error amplifier can be referred to Figure 3 For standby applications, to ensure ultra-low standby power consumption, most of the circuits in the switching power supply are in the off state, and the error amplifier does not need to work. At this time, transistors MN1, MN2, MN3 and MN4 are all in the off state.

[0035] However, this approach ignores the impact of offset voltage caused by process variations. To ensure output accuracy, the transistors (PM2 and PM3) of the error amplifier are typically tuned. To guarantee yield, the tuning range is made slightly larger. However, this cannot guarantee that the comparator's offset voltage will match the error amplifier's offset voltage in low-power mode. When the actual error amplifier's input offset voltage is large and in the opposite direction to the comparator's offset voltage in low-power mode, the output voltage in low-power mode will be significantly lower than the output voltage in continuous conduction mode (CCM).

[0036] When the switching power supply is in low-power mode, if a load suddenly enters, the system needs to respond promptly, quickly turn on the power transistor to supply power, and exit low-power mode, while simultaneously waking up all standby modules on the chip. Therefore, the switching power supply needs an additional comparator circuit to detect the load connection status in real time. The offset voltage VOS can be manually set. When the output voltage VFB is detected to drop below the reference voltage Vref minus the offset voltage VOS, the output logic signal determines that a load has entered the output, and the system exits low-power mode. However, the input offset deviation of the comparator may cause a significant difference between the actual VOS and the manually set value. If the manually set VOS is too small, it may not even cover the comparator's input offset deviation, potentially leading to an incorrect exit from low-power mode. If the manually set VOS is too large, it will cause a deterioration in the system's transient response to load changes.

[0037] Specifically, the circuit of the mode switching comparator can be referred to Figure 4An artificial offset voltage, vos, is applied to the internal reference voltage vref, where vos = R1 × I1. When the output voltage vfb is detected to drop below vref - vos, the output logic signal determines that a load has entered the output and exits the low-power mode. However, this approach also has a problem: the artificially introduced vos is typically achieved by multiplying the current and resistance.

[0038] Process variations and offsets can cause a significant difference between the actual and expected VOS. Furthermore, considering the random input offset of the low-power comparator, a VOS that is too small may not even cover the comparator's input offset deviation. In low-power mode, when the output falls below the reference voltage Vref, the normal logic is to output a drive level signal until the output voltage drops back to Vref. However, due to the offset voltage and process variations, the comparator detecting the exit from low-power mode flips, causing an incorrect exit from low-power mode. To ensure yield and allow sufficient margin in the design, the VOS value is generally increased. However, this results in the output voltage dropping further before triggering the mode detection comparator to flip and exit low-power mode, and the load transient response also deteriorates.

[0039] The amplifier circuit 100 in this embodiment can reuse the error amplifier, low-power comparator, and mode-switching comparator into a single circuit, avoiding problems caused by offset voltage mismatch between the three modules. This solves the problem of output voltage accuracy dispersion under different loads and avoids erroneous exit from low-power mode without sacrificing transient response. Furthermore, by reusing multiple circuits, it also saves on circuit power consumption and design costs.

[0040] Specifically, in the first amplification unit 10, the first amplification unit 10 can be connected to the output voltage vfb of the switching power supply 1000 and the internal reference voltage vref respectively, and outputs an amplified voltage according to the voltage difference between the output voltage vfb and the reference voltage vref.

[0041] The first amplification unit 10 can be cascaded with the second amplification unit 20. The second unit can output a first identification signal at the first output terminal 31 based on the amplified voltage output by the first amplification unit 10, to indicate the comparison result between the output voltage vref and the reference voltage vfb. When the output voltage vref is higher than the reference voltage vfb, the first identification signal can be at a first level; when the output voltage vref is lower than the reference voltage vfb, the first identification signal can be at a second level; and when the output voltage vref is equal to the reference voltage vfb, the first identification signal can be at a third level.

[0042] The first output terminal 31 can be connected to the third output terminal 33 via the loop compensation circuit 40. When the switching power supply 1000 operates in low-power mode, and the amplifier circuit 100 acts as a low-power comparator, the loop compensation circuit 40 is not activated. When the switching power supply 1000 operates in load mode, the loop compensation circuit 40 is activated to perform pole compensation on the first identification signal, and outputs the pole-compensated third identification signal at the third output terminal 33 to indicate the voltage difference between the output voltage and the reference voltage.

[0043] The second unit can determine the offset voltage VOS based on the amplified voltage output by the first amplification unit 10, and output a second identification signal at the second output terminal 32 to identify the comparison result between the reference voltage Vref and Vfb+VOS. The second identification signal output at the second output terminal 32 can identify the comparison result output by the mode switching comparator. When the reference voltage Vref is higher than Vfb+VOS, that is, when the output voltage Vfb is detected to drop below Vref-VOS, the output logic signal determines that a load has been introduced into the output, and the switching power supply 1000 exits the low-power mode and enters the load operation mode.

[0044] Thus, the first identifier signal output from the first output terminal 31 can identify the comparison result output by the low-power comparator. The second identifier signal output from the second output terminal 32 can identify the comparison result output by the mode switching comparator. The third identifier signal output from the third output terminal 33 can identify the output result of the error amplifier.

[0045] Reference Figure 5 In some embodiments, the amplified voltage includes a first voltage and a second voltage. The value of the first voltage is positively correlated with the value of the output voltage minus the reference voltage, and the value of the second voltage is negatively correlated with the value of the output voltage minus the reference voltage. The second amplification unit 20 includes a first current generating circuit 21 and a second current generating circuit 22. The first current generating circuit 21 is configured to provide a first current based on the first voltage and a first proportionality coefficient. The second current generating circuit 22 is configured to provide a second current based on the second voltage and the first proportionality coefficient. The second amplification unit 20 is configured to determine a first identification signal based on a comparison between the value of the first current and the value of the second current.

[0046] Specifically, the first output unit can be connected to nodes N1 and N2, along with the second output unit. The voltage written to node N1 can be the first voltage V1 output by the first output unit, and the voltage written to node N2 can be the second voltage V2 output by the first output unit.

[0047] When the output voltage vfb is greater than the reference voltage vref, the first voltage V1 is greater than the second voltage V2. When the output voltage vfb is equal to the reference voltage vref, the first voltage V1 is equal to the second voltage V2. When the output voltage vfb is less than the reference voltage vref, the first voltage V1 is less than the second voltage V2.

[0048] The first current generating circuit 21 can provide a first current I1 based on a first proportional coefficient k1 and a first voltage V1, and the second current generating circuit 22 can provide a second current I2 based on a first proportional coefficient k1 and a second voltage V2. When the first current I1 is greater than the second current I2, it can be determined that the first voltage V1 is greater than the second voltage V2, and a first identification signal is output to indicate that the output voltage vfb is greater than the reference voltage vref. When the first current I1 is less than the second current I2, it can be determined that the first voltage V1 is less than the second voltage V2, and a first identification signal is output to indicate that the output voltage vfb is less than the reference voltage vref. When the first current I1 is equal to the second current I2, it can be determined that the first voltage V1 is equal to the second voltage V2, and a first identification signal is output to indicate that the output voltage vfb is equal to the reference voltage vref.

[0049] In some embodiments, the first current generating circuit 21 includes a first input transistor and a first mirror transistor, which are connected in series between the voltage source of the amplifier circuit 100 and ground. The first voltage is positively correlated with the voltage applied to the control electrode of the first input transistor. The second current generating circuit 22 includes a second input transistor and a second mirror transistor, which are connected in series between the voltage source of the amplifier circuit 100 and ground. The second voltage is positively correlated with the voltage applied to the control electrode of the second input transistor. The aspect ratio of the first mirror transistor is substantially the same as that of the second mirror transistor.

[0050] Specifically, with Figure 5 For example, the first input transistor may include transistor NM5, the first mirror transistor may include transistor PM4 and transistor PM5, the voltage source VDD can be grounded through transistors PM4, PM5 and NM5, and the control electrode of transistor NM5 can be connected to node N1. The first current I1 is the current flowing through transistor PM4. Both transistors PM4 and PM5 are normally on.

[0051] The second input transistor may include transistor NM6, and the second mirror transistor may include transistors PM6 and PM7. The voltage source VDD can be grounded through transistors PM6, PM7, and NM6. The control electrode of transistor NM6 can be connected to node N2. The first current I2 is the current flowing through transistor PM6. Both transistors PM6 and PM7 are normally on.

[0052] The current flowing through the transistor is positively correlated with the width-to-length ratio of the transistor. The width-to-length ratios of transistors NM5 and NM6 are basically the same, the width-to-length ratios of transistors PM4 and PM6 are basically the same, and the width-to-length ratios of transistors PM5 and PM7 are basically the same, so that the first current generating circuit 21 and the second current generating circuit can determine the first current I1 and the second current I2 according to the same proportionality coefficient.

[0053] In some embodiments, the first current generating circuit 21 further includes a bias resistor connected between the first mirror transistor and the first input transistor and configured to provide a bias voltage to the first mirror transistor to turn it on.

[0054] Specifically, the bias resistor may include resistor R1, the first terminal of transistor NM5 may be grounded, the first terminal of resistor R1 may be connected to the second terminal of transistor NM5 and the control terminal of transistor PM5, the second terminal of resistor R1 may be connected to the second terminal of transistor PM5 and the control terminal of transistor PM4, the first terminal of transistor PM5 may be connected to the second terminal of transistor PM4, and the first terminal of transistor PM4 may be connected to the voltage source VDD.

[0055] The voltage across the first terminal of resistor R1 is less than the voltage across the second terminal, causing the voltage connected to the control electrode of transistor PM5 to be less than the voltage connected to the second electrode of transistor PM5, thus turning on transistor PM5. The voltage across the second terminal of resistor R1 is less than the voltage provided by the voltage source VDD, causing the voltage connected to the control electrode of transistor PM4 to be less than the voltage connected to the second electrode of transistor PM4, thus turning on transistor PM4.

[0056] In some implementations, the first output terminal 31 is connected between the second input transistor and the second mirror transistor.

[0057] Specifically, the first output terminal 31 may include a PWM terminal, and transistor NM6 may be connected to transistor PM7 at the PWM terminal.

[0058] When the first current I1 is greater than the second current I2, it can be determined that the output voltage Vfb is greater than the reference voltage Vref, and the PWM terminal can output a low level. When the first current I1 is equal to the second current I2, it can be determined that the output voltage Vfb is equal to the reference voltage Vref, and the PWM terminal can output an intermediate level. When the first current I1 is less than the second current I2, it can be determined that the output voltage Vfb is less than the reference voltage Vref, and the PWM terminal can output a high level.

[0059] In some embodiments, the second amplification unit 20 includes a third current generation circuit 23. The third current generation circuit 23 is configured to provide a third current based on a second voltage and a second proportionality coefficient, and the second amplification unit 20 is configured to determine a second identification signal based on a comparison between the current value of the first current and the current value of the third current, wherein the voltage value of the offset voltage is positively correlated with the second proportionality coefficient.

[0060] Specifically, the third current generating circuit 23 can provide a third current I3 based on the second proportional coefficient k2 and the second voltage V2, and the ratio of the second proportional coefficient k2 to the first proportional coefficient k1 is M:1 (M is not equal to 1).

[0061] The ratio of the third current I3 to the first current I1 is M:1. When the output voltage vfb equals the reference voltage vref and M is greater than 1, the third current I3 is greater than the first current I1, and the offset voltage vos is positive. When the output voltage vfb further decreases to vref-vos, the third current I3 equals the first current I1.

[0062] When the output voltage vfb equals the reference voltage vref and M is less than 1, the third current I3 is less than the first current I1, and the offset voltage vos is negative. When the output voltage vfb rises further to vref - vos, the third current I3 equals the first current I1.

[0063] In some embodiments, the third current generating circuit 23 includes a third input transistor and a third mirror transistor, which are connected in series between the voltage source and ground of the amplifier circuit 100. The second voltage is positively correlated with the voltage connected to the control electrode of the third input transistor, and the second proportionality coefficient is positively correlated with the width-to-length ratio of the third mirror transistor.

[0064] Specifically, with Figure 5For example, the third input transistor may include transistor NM7, and the third mirror transistor may include transistor PM8 and transistor PM9. The voltage source VDD can be grounded through transistors PM8, PM9, and NM7. Transistors PM8 and PM9 can be in a normally on state. The control terminals of transistors NM7 and NM6 are connected to node N2, and both the control terminals of transistors NM7 and NM6 are connected to the second voltage V2.

[0065] The current flowing through the transistor is positively correlated with the width-to-length ratio of the transistor. The ratio of the width-to-length ratio of transistor PM8 to that of transistor PM4 is M:1, and the ratio of the width-to-length ratio of transistor PM9 to that of transistor PM5 is M:1 (M is not equal to 1). The ratio of the second proportionality coefficient k2 to the first proportionality coefficient k1 is M:1.

[0066] The ratio of the third current I3 to the first current I1 is M:1. The third current I3 flowing through transistor PM8 is M times the third current I3 flowing through transistor PM4.

[0067] When M is greater than 1, the offset voltage VOS is positive. When the output voltage Vfb further decreases to Vref - VOS, the third current I3 flowing through transistor PM8 is equal to the third current I3 flowing through transistor PM4. When M is less than 1, the offset voltage VOS is negative. When the output voltage Vfb further increases to Vref - VOS, the third current I3 flowing through transistor PM8 is equal to the third current I3 flowing through transistor PM4.

[0068] In some implementations, the second output terminal 32 is connected between the third input transistor and the third mirror transistor.

[0069] Specifically, with Figure 2 For example, the second output terminal 32 can be the mode_sel terminal, which is connected between transistor PM9 and transistor NM7. The threshold for the output voltage vfb to trigger the comparator to switch is vref-vos. When the width-to-length ratios of transistors NM5, NM6, and NM7 are the same, the offset voltage vos can be expressed as:

[0070]

[0071] Where AV1 is the gain of the first amplification unit 10, I1 is the current value of the first current, M is the ratio of the width-to-length ratio of transistor PM8 to that of transistor PM4, and gm NM7 Here are the transconductance parameters of transistor NM7.

[0072] When the output VFB is less than VRef - VOS, the level of the second identifier signal flips. The value of the offset voltage VOS can be flexibly set according to the transient response of the application. The smaller the offset voltage VOS, the easier it is for the comparator to flip out of low power mode when a load transient occurs, and the response will be faster. However, if the offset voltage VOS is too small, considering the comparator's own response time, if the load change is small (the load current does not meet the exit condition for low power load), the mode detection comparator may also flip. Therefore, the offset voltage VOS needs to be designed reasonably in combination with the design specifications and considering the impact of errors.

[0073] In some implementations, the control electrode of the second input transistor is connected to the control electrode of the third input transistor, and the control electrode of the first mirror transistor is connected to the control electrodes of the second and third mirror transistors.

[0074] by Figure 5 For example, the control electrode of transistor PM4 is connected to the control electrodes of transistors PM6 and PM8, and the control electrode of transistor PM5 is connected to the control electrodes of transistors PM7 and PM9.

[0075] As mentioned earlier, resistor R1 provides a bias voltage to transistors PM4 and PM5, keeping them normally on. When transistors PM4 and PM5 are on, transistors PM5, PM6, PM7, and PM8 are also on.

[0076] In some embodiments, the loop compensation circuit 40 includes a gating switch 41 and a compensation capacitor 42. The gating switch 41 is connected between the first output terminal 31 and the third output terminal 33, and the compensation capacitor 42 is connected between the third output terminal 33 and ground. When the gating switch 41 is open, the first output terminal 31 is configured to output a first identification signal. When the gating switch 41 is on, the first output terminal 31 and the third output terminal 33 are configured to output a third identification signal.

[0077] Specifically, with Figure 5 For example, the compensation capacitor 42 may include a capacitor element C1, the gating switch 41 may include a switching element S1, the third output terminal 33 may include an ea_out terminal, and the switching element S1 is connected between the pwm terminal and the ea_out terminal.

[0078] When the switching power supply 1000 is in low-power mode, the switching element S1 is open, and the loop compensation circuit 40 is not activated in order to reduce the capacitance of the output node and speed up the response of the low-power comparator. The identification signal output from the PWM terminal can be used as the identification signal output by the low-power comparator.

[0079] When the switching power supply 1000 is in non-power consumption mode, the switching element S1 is closed, and the loop compensation circuit 40 is activated. The amplifier circuit 100 is used as an error amplifier, and the signal output from the ea_out terminal participates in the modulation of the loop compensation circuit 40. The pole position of the output node of the second amplification unit 20 is much lower than the pole position of the output node of the first amplification unit 10. The bandwidth expression of the error amplifier is:

[0080]

[0081] Where AV1 is the gain of the first amplification unit 10, C1 is the capacitance value of the compensation capacitor 42, and gm NM6 Here are the transconductance parameters of transistor NM6.

[0082] The expression for the gain of the second amplification unit 20 is:

[0083] AV2=gm NM6 ×(rout NM6 / / gm GM7 ×rout PM7 ×rout PM6 )

[0084] Where AV2 is the gain of the second amplification unit 20, gm NM6 gm is the transconductance parameter of transistor NM6. GM7 Here are the transconductance parameters of transistor GM7, rout PM7 The on-resistance of transistor PM7 is rout. PM6 This is the on-resistance of transistor PM6.

[0085] In some embodiments, the first amplification unit 10 includes a bias current generating circuit 11, a fourth input transistor, a first load 12, a fifth input transistor, and a second load 13. The bias current generating circuit 11 is configured to provide a bias current. The bias current generating circuit 11 is grounded through the fourth input transistor and the first load 12, and the control terminal of the fourth input transistor is configured to be connected to a reference voltage. The bias current generating circuit 11 is grounded through the fifth input transistor and the second load 13, and the control terminal of the fifth input transistor is configured to be connected to an output voltage. The fourth input transistor and the first load 12 are connected to a first node, and the fifth input transistor and the second load 13 are connected to a second node. The first node or the second node is configured to output an amplified voltage.

[0086] Specifically, with Figure 6 For example, the fifth input transistor may include transistor PM2, and the sixth transistor may include transistor PM3. The voltage connected to the control electrode of transistor PM2 is the reference voltage vref, and the voltage connected to the control electrode of transistor PM3 is the output voltage vfb.

[0087] To achieve low-power applications, the bias current can be set to the nA level. Transistor PM2 and transistor PM3 are the input pair of the first amplification unit 10. The bias current generated by the bias current generation circuit 11 is the sum of the currents flowing through transistors PM2 and PM3. When the reference voltage vref equals the output voltage vfb, the currents flowing through transistors PM2 and PM3 are the same, and the first voltage V1 output by the first node is the same as the second voltage V2 output by the second node.

[0088] When the reference voltage vref is greater than the output voltage vfb, the current flowing through transistor PM2 is greater than the current flowing through transistor PM3, and the first voltage V1 is greater than the second voltage V2. When the reference voltage vref is less than the output voltage vfb, the current flowing through transistor PM2 is less than the current flowing through transistor PM3, and the first voltage V1 is less than the second voltage V2.

[0089] In some embodiments, the bias current generating circuit 11 includes a bias transistor, the voltage source of the amplifier circuit 100 is connected to the first input transistor and the second input transistor through the bias transistor, and the bias current is the current flowing through the bias transistor.

[0090] by Figure 6 For example, the bias transistor may include transistor PM1, the voltage source VDD may be connected to the first terminal of transistor PM1, the second terminal of transistor PM1 may be connected to the first terminals of transistors PM2 and PM3, the second terminal of transistor PM2 may be grounded through the first load 12, and the second terminal of transistor PM3 may be grounded through the second load 13.

[0091] The control electrode of transistor PM1 can be connected to a bias voltage vbp, so that transistor PM1 can provide corresponding bias currents to transistors PM2 and PM3.

[0092] In some embodiments, the first load 12 includes a first load transistor and a second load transistor, and the second load 13 includes a third load transistor and a fourth load transistor. The control electrodes of the first load transistor and the third load transistor are connected to the first input transistor, and the control electrodes of the second load transistor and the fourth load transistor are connected to the second input transistor.

[0093] Specifically, with Figure 6 For example, the first load transistor includes transistor NM1, the second load transistor includes transistor NM2, the third load transistor includes transistor NM3, and the fourth load transistor includes transistor NM4. The control electrodes of transistors NM1 and NM3 are connected to node N1, and the control electrodes of transistors NM2 and NM4 are connected to node N2.

[0094] In the first load 12, the first terminal of transistor NM1 is grounded, the second terminal of transistor NM1 is connected to the control terminal, the control terminal of transistor NM2 is connected to the second load 13 at node N2, transistor NM1 can be used as a bias diode, and transistor NM2 is coupled to the second load 13.

[0095] In the second load 13, the first terminal of transistor NM4 is grounded, the second terminal of transistor NM4 is connected to the control terminal, the control terminal of transistor NM3 is connected to the second load 13 at node N1, transistor NM3 can be used as a bias diode, and transistor NM4 is coupled to the second load 13.

[0096] Thus, the load of the first amplification unit 10 adopts a cross-coupled connection and a diode connection, which can achieve controllable gain and has little impact from deviations in device process, etc.

[0097] The expression for the gain AV1 of the first amplification unit 10 is:

[0098]

[0099] Among them, gm PM2 gm is the transconductance parameter of transistor PM2. NM2 gm is the transconductance parameter of transistor NM2. NM1 Here are the transconductance parameters of transistor NM1.

[0100] In the description of this specification, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, without contradiction, those skilled in the art can combine and integrate different embodiments or examples described in this specification, as well as features of different embodiments or examples.

[0101] Furthermore, the term "connection" should be interpreted broadly. For example, it can include fixed connections, detachable connections, or integral connections; it can include direct connections or indirect connections through an intermediate medium; and it can also include internal communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0102] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0103] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0104] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. An amplifier circuit for a switching power supply, characterized by include: The first amplification unit is configured to output an amplified voltage based on the voltage difference between the output voltage of the switching power supply and the reference voltage of the switching power supply. The second amplification unit is configured to output a first identification signal at the first output terminal according to the amplified voltage, so as to identify the comparison result between the voltage value of the output voltage and the voltage value of the reference voltage. The second output terminal, the second amplification unit is further configured to determine the offset voltage based on the amplified voltage, and to output a second identification signal at the second output terminal based on the offset voltage and the amplified voltage, to identify the voltage sum of the output voltage and the offset voltage, and the comparison result with the voltage value of the reference voltage; The loop compensation circuit is connected to the first output terminal and the third output terminal. The loop compensation circuit is configured to perform pole compensation on the first identification signal and output a third identification signal after pole compensation at the third output terminal to identify the voltage difference between the output voltage and the reference voltage.

2. The amplifier circuit of claim 1, wherein, The amplification voltage includes a first voltage and a second voltage. The value of the first voltage is positively correlated with the value of the output voltage minus the reference voltage, and the value of the second voltage is negatively correlated with the value of the output voltage minus the reference voltage. The second amplification unit includes: A first current generating circuit is configured to provide a first current based on the first voltage and a first proportionality coefficient; The second current generating circuit is configured to provide a second current based on the second voltage and a first proportional coefficient, and the second amplification unit is configured to determine the first identification signal based on a comparison between the current value of the first current and the current value of the second current.

3. The amplifier circuit of claim 2, wherein, The second amplification unit includes a third current generation circuit, which is configured to provide a third current based on the second voltage and a second proportional coefficient. The second amplification unit is configured to determine the second identification signal based on a comparison between the current value of the first current and the current value of the third current. The voltage value of the offset voltage is positively correlated with the second proportional coefficient.

4. The amplifier circuit according to claim 3, characterized in that, The first current generating circuit includes a first input transistor and a first mirror transistor. The first input transistor and the first mirror transistor are connected in series between the voltage source of the amplifier circuit and the ground. The first voltage is positively correlated with the voltage connected to the control electrode of the first input transistor. The second current generating circuit includes a second input transistor and a second mirror transistor. The second input transistor and the second mirror transistor are connected in series between the voltage source and ground of the amplifier circuit. The second voltage is positively correlated with the voltage connected to the control electrode of the second input transistor. The width-to-length ratio of the first mirror transistor is basically the same as that of the second mirror transistor, and the width-to-length ratio of the first input transistor is basically the same as that of the second input transistor.

5. The amplifier circuit of claim 4, wherein, The first current generating circuit further includes a bias resistor connected between the first mirror transistor and the first input transistor, and configured to provide a bias voltage to the first mirror transistor to turn it on.

6. The amplifier circuit of claim 4, wherein, The first output terminal is connected between the second input transistor and the second mirror transistor.

7. The amplifier circuit of claim 4, wherein, The third current generating circuit includes a third input transistor and a third mirror transistor. The third input transistor and the third mirror transistor are connected in series between the voltage source and ground of the amplifier circuit. The second voltage is positively correlated with the voltage connected to the control electrode of the third input transistor, and the second proportionality coefficient is positively correlated with the width-to-length ratio of the third mirror transistor.

8. The amplifier circuit of claim 7, wherein, The second output terminal is connected between the third input transistor and the third mirror transistor.

9. The amplifier circuit of claim 7, wherein, The control electrode of the second input transistor is connected to the control electrode of the third input transistor, and the control electrode of the first mirror transistor is connected to the control electrodes of the second mirror transistor and the third mirror transistor.

10. The amplifier circuit of claim 1, wherein, The loop compensation circuit includes a gating switch and a compensation capacitor. The gating switch is connected between the first output terminal and the third output terminal, and the compensation capacitor is connected between the third output terminal and the ground. When the gating switch is off, the first output terminal is configured to output the first identification signal; when the gating switch is on, the first output terminal and the third output terminal are configured to output the third identification signal.

11. The amplifier circuit of claim 4, wherein, The first amplification unit includes: The bias current generating circuit is configured to provide bias current; The fourth input transistor and the first load are connected, and the bias current generating circuit is grounded through the fourth input transistor and the first load. The control electrode of the fourth input transistor is configured to be connected to the reference voltage. The fifth input transistor and the second load are connected, and the bias current generating circuit is grounded through the fifth input transistor and the second load. The control electrode of the fifth input transistor is configured to be connected to the output voltage. The fourth input transistor is connected to the first load at the first node, and the fifth input transistor is connected to the second load at the second node. The first node or the second node is configured to output the amplified voltage.

12. The amplifier circuit of claim 11, wherein, The first load includes a first load transistor and a second load transistor, the second load includes a third load transistor and a fourth load transistor, the control electrode of the first load transistor and the third load transistor is connected to the first input transistor, and the control electrode of the second load transistor and the fourth load transistor is connected to the second input transistor.

13. The amplifier circuit according to claim 11, characterized in that, The bias current generating circuit includes a bias transistor. The voltage source of the amplifier circuit is connected to the first input transistor and the second input transistor through the bias transistor. The bias current is the current flowing through the bias transistor.

14. A switching power supply, characterized in that, The switching power supply includes the amplifier circuit according to any one of claims 1-13.

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