Low noise amplifier

Abstract

The utility model discloses a low noise amplifier, include: input port, input matching network, its input and input port are connected, first stage amplifier circuit, and input matching network's output is connected, interstage matching network, its input and first field effect tube's drain are connected, second stage amplifier circuit, and interstage matching network's output is connected, output matching network, its input and second field effect tube's drain are connected, output port, and output matching network's output is connected, first protection circuit, and input matching network's output is connected, second protection circuit, and interstage matching network's output is connected, bias network is connected with first field effect tube's grid and second field effect tube's grid respectively. Thus, can respectively to the protection of key node, avoid damaging core amplifier device, effectively promote overall reliability, guarantee amplification function stability.

Description

Technical Field

[0001] This utility model relates to the field of power electronics technology, specifically to a low-noise amplifier. Background Technology

[0002] In the field of power electronics technology, low-noise amplifiers, as key signal processing components, are widely used in various scenarios that require low-noise amplification of weak signals.

[0003] Currently, some low-noise amplifiers do not have dedicated protection structures for critical nodes in the signal transmission path. When the amplifier is subjected to abnormal signal impacts on the input side or inter-stage signal fluctuations between multi-stage amplifier circuits, the core amplifier components in each stage of the amplifier circuit are easily damaged by abnormal conditions such as overvoltage and overcurrent. Utility Model Content

[0004] The present invention aims to solve, to at least some extent, the technical problems in the above-mentioned technologies.

[0005] Therefore, this utility model discloses a low-noise amplifier, comprising:

[0006] Input port;

[0007] An input matching network is provided, with its input end connected to the input port.

[0008] The first-stage amplifier circuit includes a first field-effect transistor, the gate of which is connected to the output of the input matching network.

[0009] An interstage matching network, the input of which is connected to the drain of the first field-effect transistor;

[0010] The second-stage amplifier circuit includes a second field-effect transistor, the gate of which is connected to the output of the interstage matching network.

[0011] The output matching network has its input connected to the drain of the second field-effect transistor;

[0012] An output port, which is connected to the output end of the output matching network;

[0013] The first protection circuit includes a third field-effect transistor, the drain of which is connected to the output of the input matching network.

[0014] The second protection circuit is equipped with a fourth field-effect transistor, the drain of which is connected to the output of the interstage matching network.

[0015] A bias network is connected to the gate of the first field-effect transistor and the gate of the second field-effect transistor, respectively.

[0016] The low-noise amplifier disclosed in this utility model can protect the key nodes of the input matching network output terminal and the interstage matching network output terminal respectively, avoiding damage to core amplification devices such as the first and second field-effect transistors by abnormal signal impacts, effectively improving the overall reliability of the low-noise amplifier and ensuring the stability of the amplifier signal amplification function.

[0017] In addition, the low-noise amplifier disclosed in this utility model may also have the following additional technical features:

[0018] In one embodiment of this utility model, an inductor and a capacitor are connected in series on the gate of the first field-effect transistor, another inductor, another resistor and another capacitor are connected in series on the drain of the first field-effect transistor, another inductor is connected in series on the source of the first field-effect transistor, and the connection node of the inductor and capacitor on the gate of the first field-effect transistor is connected to the bias network.

[0019] In one embodiment of the present invention, the gate of the second field-effect transistor is connected in series with another inductor and another capacitor, the drain of the second field-effect transistor is connected in series with another inductor, another resistor and another capacitor, the source of the first field-effect transistor is connected in series with another inductor, and the connection node of the inductor and capacitor on the gate of the second field-effect transistor is connected to the bias network.

[0020] In one embodiment of this utility model, another resistor is connected in series with the gate of the third field-effect transistor, another resistor is connected in parallel with the drain and source of the third field-effect transistor, and another capacitor is connected in series between the drain of the third field-effect transistor and the output terminal of the input matching network.

[0021] In one embodiment of this utility model, another resistor is connected in series with the gate of the fourth field-effect transistor, another resistor is connected in parallel with the drain and source of the fourth field-effect transistor, and another capacitor is connected in series between the drain of the fourth field-effect transistor and the output terminal of the interstage matching network.

[0022] In one embodiment of this utility model, an inductor and an RF input pad are connected in series between the input port and the input matching network, and an RF output pad and an inductor are connected in series between the output matching network and the output port.

[0023] Additional features and advantages of this invention will be set forth in the description which follows, or may be learned by practicing this invention. Attached Figure Description

[0024] The technical solution and beneficial effects of this utility model will become apparent and easily understood from the following description in conjunction with the accompanying drawings, wherein:

[0025] Figure 1 This is a circuit diagram of the low-noise amplifier of this utility model;

[0026] Figure 2 This is a circuit diagram of the input matching network of the low-noise amplifier of this invention.

[0027] Figure 3 The circuit diagram shows the output matching network of the low-noise amplifier of this invention.

[0028] Figure 4 This is a circuit diagram of the interstage matching network of the low-noise amplifier of this invention.

[0029] Figure 5 This is a circuit diagram of the bias network of the low-noise amplifier of this invention. Detailed Implementation

[0030] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments.

[0031] The low-noise amplifier disclosed in this utility model will now be described with reference to the accompanying drawings.

[0032] like Figure 1 As shown, the low-noise amplifier includes:

[0033] Input port Term1;

[0034] The input matching network is connected to the input port Term1.

[0035] The first stage amplifier circuit includes a first field-effect transistor D1, whose gate is connected to the output of the input matching network Input RF PAD.

[0036] The interstage 1-2 Matching Network has its input connected to the drain of the first field-effect transistor D1;

[0037] The second-stage amplifier circuit includes a second field-effect transistor D2, whose gate is connected to the output of the interstage 1-2 Matching Network.

[0038] The input terminal of the output matching network is connected to the drain of the second field-effect transistor D2.

[0039] Output port Term2 is connected to the output of the Output Matching Network.

[0040] The first protection circuit, Protection1, includes a third field-effect transistor, D3, whose drain is connected to the output of the input matching network.

[0041] The second protection circuit, Protection2, is equipped with a fourth field-effect transistor, D4, whose drain is connected to the output of the interstage 1-2 Matching Network.

[0042] The biasing network is connected to the gate of the first field-effect transistor D1 and the gate of the second field-effect transistor D2, respectively.

[0043] The gate of the first field-effect transistor D1 is connected in series with an inductor L4 and a capacitor C3. The drain of the first field-effect transistor D1 is connected in series with another inductor L1, another resistor R1 and another capacitor C1. The source of the first field-effect transistor D1 is connected in series with another inductor L5. The connection node of the inductor L4 and capacitor C3 on the gate of the first field-effect transistor D1 is connected to the biasing network.

[0044] The gate of the second field-effect transistor D2 is connected in series with another inductor L6 and another capacitor C4. The drain of the second field-effect transistor D2 is connected in series with another inductor L2, another resistor R2 and another capacitor C2. The source of the first field-effect transistor D2 is connected in series with another inductor L7. The connection node of the inductor L6 and capacitor C4 on the gate of the second field-effect transistor D2 is connected to the biasing network.

[0045] Another resistor R3 is connected in series with the gate of the third field-effect transistor D3, another resistor R4 is connected in parallel with the drain and source of the third field-effect transistor D3, and another capacitor C5 is connected in series between the drain of the third field-effect transistor D3 and the output of the input matching network.

[0046] Another resistor R5 is connected in series with the gate of the fourth field-effect transistor D4, another resistor R6 is connected in parallel with the drain and source of the fourth field-effect transistor D4, and another capacitor C6 is connected in series between the drain of the fourth field-effect transistor D4 and the output of the interstage 1-2 Matching Network.

[0047] An inductor L3 and an RF input pad are connected in series between the input port Term1 and the input matching network. An RF output pad and an inductor L8 are connected in series between the output matching network and the output port Term2.

[0048] It should be noted that capacitors C1, C2, C3, and C4, inductors L5 and L7, the source of the third field-effect transistor D3, and the source of the fourth field-effect transistor D4 are all grounded. The connection nodes of inductor L1 and resistor R1, inductor L2 and resistor R2, resistor R3, and resistor R5 are all connected to the power supply.

[0049] It should also be noted that, as a possibility, such as Figure 2 As shown, the Input Matching Network includes an inductor L9 and a capacitor C7. The two ends of the inductor L9 are connected to the gate of the first field-effect transistor D1 and ground, respectively. The two ends of the capacitor C7 are connected to the gate of the first field-effect transistor D1 and the RF input pad, respectively.

[0050] It should also be noted that, as a possibility, such as Figure 3 As shown, the output matching network includes an inductor L10 and a capacitor C8. The two ends of the inductor L10 are connected to the drain of the second field-effect transistor D2 and one end of the capacitor C8, respectively. The other end of the capacitor C8 is grounded.

[0051] It should also be noted that, as a possibility, such as Figure 4 As shown, the interstage 1-2 Matching Network includes an inductor L11 and a capacitor C9. The two ends of the inductor L11 are connected to the drain of the first field-effect transistor D1 and one end of the capacitor C9, respectively. The other end of the capacitor C9 is grounded.

[0052] It should also be noted that, as a possibility, such as Figure 5As shown, the biasing network includes: capacitor C10, resistors R7, R8 and R9. Resistors R7 and R8 are connected in series. The other end of resistor R7 is connected to the power supply. The other end of resistor R8 is grounded. One end of resistor R9 is grounded, and the other end is connected to the source of the first field-effect transistor D1 and the source of the second field-effect transistor D2, respectively. Capacitor C10 is connected in parallel across resistor R9.

[0053] In summary, the low-noise amplifier disclosed in this utility model can protect the key nodes of the input matching network output and the interstage matching network output respectively, avoiding damage to core amplification devices such as the first and second field-effect transistors by abnormal signals, effectively improving the overall reliability of the low-noise amplifier and ensuring the stability of the amplifier's signal amplification function.

[0054] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A low-noise amplifier, characterized in that, include: Input port; An input matching network is provided, with its input end connected to the input port. The first-stage amplifier circuit includes a first field-effect transistor, the gate of which is connected to the output of the input matching network. An interstage matching network, the input of which is connected to the drain of the first field-effect transistor; The second-stage amplifier circuit includes a second field-effect transistor, the gate of which is connected to the output of the interstage matching network. The output matching network has its input connected to the drain of the second field-effect transistor; An output port, which is connected to the output end of the output matching network; The first protection circuit includes a third field-effect transistor, the drain of which is connected to the output of the input matching network. The second protection circuit is equipped with a fourth field-effect transistor, the drain of which is connected to the output of the interstage matching network. A bias network is connected to the gate of the first field-effect transistor and the gate of the second field-effect transistor, respectively.

2. The low-noise amplifier as described in claim 1, characterized in that, An inductor and a capacitor are connected in series at the gate of the first field-effect transistor. Another inductor, another resistor, and another capacitor are connected in series at the drain of the first field-effect transistor. Another inductor is connected in series at the source of the first field-effect transistor. The connection node of the inductor and capacitor on the gate of the first field-effect transistor is connected to the bias network.

3. The low-noise amplifier as described in claim 1, characterized in that, The gate of the second field-effect transistor is connected in series with another inductor and another capacitor. The drain of the second field-effect transistor is connected in series with another inductor, another resistor and another capacitor. The source of the first field-effect transistor is connected in series with another inductor. The connection node of the inductor and capacitor on the gate of the second field-effect transistor is connected to the bias network.

4. The low-noise amplifier as described in claim 1, characterized in that, Another resistor is connected in series with the gate of the third field-effect transistor, another resistor is connected in parallel with the drain and source of the third field-effect transistor, and another capacitor is connected in series between the drain of the third field-effect transistor and the output of the input matching network.

5. The low-noise amplifier as described in claim 1, characterized in that, Another resistor is connected in series with the gate of the fourth field-effect transistor, another resistor is connected in parallel with the drain and source of the fourth field-effect transistor, and another capacitor is connected in series between the drain of the fourth field-effect transistor and the output of the interstage matching network.

6. The low-noise amplifier as described in claim 1, characterized in that, Another inductor and an RF input pad are connected in series between the input port and the input matching network, and an RF output pad and another inductor are connected in series between the output matching network and the output port.

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