Low power solid state relay with protection circuit

Abstract

The utility model discloses a kind of low-power solid-state relays with protection circuit, including first isolation circuit, second isolation circuit, soft start circuit, first switching switch, second switching switch, first output drive circuit, second output drive circuit and current sampling circuit.First isolation circuit and second isolation circuit are respectively received and converted input signal into output signal.Soft start circuit generates control signal in start voltage delay time, respectively, so that switching switch is turned on according to the received control signal, so that output signal is further powered to electrically connected output drive circuit through switching switch.Output drive circuit is current signal by current sampling circuit, so that current signal is reduced output power consumption by flowing through first output drive circuit and second output drive circuit respectively with different channel area width length ratio of multiple source electrode design.

Description

Technical Field

[0001] This utility model relates to a solid-state relay, and more particularly to a low-power solid-state relay with a protection circuit. Background Technology

[0002] Please see Figure 11A , Figure 11B and Figure 11C This is a block diagram, circuit diagram, and output current diagram of a conventional solid-state relay. The solid-state relay 3 (SSR) includes an isolation circuit 31, a control circuit 32, and a drive circuit 33. The input terminal of the isolation circuit 31 receives the input signal. The output of the drive circuit 33 is connected to an AC signal. The solid-state relay 3 is a contactless relay in which the load is controlled by a semiconductor and flows through a solid-state switch. The input of the isolation circuit 31 is an optocoupler composed of semiconductor circuits such as light-emitting diodes, phototransistors, and power transistors. The internal control circuit 32 triggers the silicon controlled rectifier (SCR) or bidirectional silicon controlled rectifier (TRIAC) at the output of the drive circuit 33 to conduct the load current. Therefore, it can accept low-voltage DC or AC signal input and then conduct high-voltage, high-power output current, which has the effect of isolating output and input and controlling high-power output current.

[0003] As mentioned above, although the conventional solid-state relay 3 uses an optocoupler to isolate the input signal at the input terminal and the load at the output terminal, a surge current will still be generated when the solid-state relay 3 turns on the inductive load and the capacitive load. If the control circuit 32 cannot control the surge current, the generation of the surge current will damage the solid-state relay 3.

[0004] Furthermore, such as Figure 11C As shown, generally speaking, the output current of the conventional solid-state relay 3 is... For a large current, and when the output current When the current flows through the output resistor 34, it will increase the output power consumption of the solid-state relay 3, which will further cause the solid-state relay 3 to generate heat and overheat.

[0005] Therefore, how to provide a low-power solid-state relay with protection circuitry has become an urgent research topic. Utility Model Content

[0006] In view of the above problems, this utility model discloses a low-power solid-state relay with a protection circuit, comprising a first isolation circuit, a second isolation circuit, a soft-start circuit, a first switching switch, a second switching switch, a first output drive circuit, a second output drive circuit, and a current sampling circuit. The first isolation circuit receives and converts a first input signal into a first output signal. The second isolation circuit receives and converts a second input signal into a second output signal, wherein the signal level of the first output signal is lower than the signal level of the second output signal. The soft-start circuit generates a first control signal within a time delay less than the start-up voltage delay and generates a second control signal when the time delay is greater than or equal to the start-up voltage delay. The first switching switch is electrically connected to the first isolation circuit and the soft-start circuit, and is turned on according to the first control signal. The second switching switch is electrically connected to the second isolation circuit and the soft-start circuit, and is turned on according to the second control signal. The first output drive circuit is electrically connected to the first isolation circuit through the first switching switch when the first switching switch is on, and is electrically connected to the second isolation circuit through the second switching switch when the second switching switch is on. The second output drive circuit is electrically connected to the first output drive circuit. When the first switching switch is on, it is electrically connected to the first isolation circuit through the first switching switch, and when the second switching switch is on, it is electrically connected to the second isolation circuit through the second switching switch. The current sampling circuit is electrically connected to both the first and second output drive circuits, capturing the current signals output by both circuits. The first output drive circuit includes a first power MOSFET, and the second output drive circuit includes a second power MOSFET. The first power MOSFET has a first channel width-to-length ratio and a second channel width-to-length ratio, which is 1:n. The second power MOSFET has a third channel width-to-length ratio and a fourth channel width-to-length ratio, which are also 1:n, where n is a positive number.

[0007] As described above, the low-power solid-state relay with protection circuitry of this invention utilizes opto-isolated power supply via an isolation circuit and is powered by the converted signal, eliminating the need for additional power supply to individual circuits on the high-voltage side. Furthermore, by setting the startup voltage delay time through a soft-start circuit, and segmenting the startup high and low voltage signals to the gates of the first and second power MOSFETs, the influence of inrush current can be avoided. Moreover, by adjusting the width-to-length ratios of different channel regions of the power MOSFETs, and by using a smaller width-to-length ratio for the first channel region and a smaller width-to-length ratio for the third channel region to separate the sampling output current, the power consumption loss of the sampling element can be reduced. Additionally, by connecting a current sampling circuit, the solid-state relay can generate lower thermal power consumption. Attached Figure Description

[0008] Figure 1This is a block diagram of the low-power solid-state relay with protection circuit of this utility model.

[0009] Figure 2A This is a schematic diagram showing the relationship between gate voltage and output current.

[0010] Figure 2B This is a schematic diagram showing the corresponding curves of gate voltage and on-resistance.

[0011] Figure 3A This is a schematic diagram of the soft-start circuit of this utility model;

[0012] Figure 3B This is a schematic diagram of the startup voltage delay time;

[0013] Figure 4 This is a schematic diagram of another soft-start circuit connection logic circuit of this utility model;

[0014] Figure 5 This is a circuit diagram of the over-temperature protection circuit of this utility model;

[0015] Figure 6 This is a circuit diagram of the voltage regulator circuit of this utility model;

[0016] Figure 7 This is a circuit diagram of the logic circuit of this utility model;

[0017] Figure 8 This is a circuit diagram of another logic circuit of this utility model;

[0018] Figure 9 This is a circuit diagram of another logic circuit of this utility model;

[0019] Figure 10 This is a circuit diagram of the low-power solid-state relay with protection circuit of this utility model.

[0020] Figure 11A A block diagram illustrating a familiar solid-state relay;

[0021] Figure 11B A circuit diagram of a conventional solid-state relay; and

[0022] Figure 11C This is a schematic diagram of the output current of a familiar solid-state relay. Detailed Implementation

[0023] Please see Figure 1This is a block diagram of the low-power solid-state relay with protection circuit of this utility model. The solid-state relay 1 with multi-functional protection circuit includes a first isolation circuit 11, a second isolation circuit 12, a soft-start circuit 13, a current sampling circuit 10, a first switching switch S1, a second switching switch S2, a first output driving circuit 15, and a second output driving circuit 16. The first isolation circuit 11 receives and converts the first input signal. The first output signal The second isolation circuit 12 receives and converts the second input signal. For the second output signal The first output signal The signal level is lower than that of the second output signal. The signal level is determined. The soft-start circuit 13 generates a first control signal when the delay time is less than the start-up voltage delay time, and generates a second control signal when the delay time is greater than or equal to the start-up voltage delay time. The first switching switch S1 is electrically connected to the first isolation circuit 11 and the soft-start circuit 13, and is turned on (short circuit) according to the first control signal. The second switching switch S2 is electrically connected to the second isolation circuit 12 and the soft-start circuit, and is turned on according to the second control signal. When the first switching switch S1 is turned on, the first output drive circuit 15 is electrically connected to the first isolation circuit 11 through the first switching switch S1, so as to respond to the received first output signal. An output signal is generated and electrically connected to the second isolation circuit 12 via the second switch S2 when the second switch S2 is turned on, so as to receive the second output signal. An output signal is generated. The second output drive circuit 16 is electrically connected to the first output drive circuit 15, and when the first switching switch S1 is turned on, it is electrically connected to the first isolation circuit 11 through the first switching switch S1, so as to generate an output signal according to the received first output signal. An output signal is generated and electrically connected to the second isolation circuit 12 via the second switch S2 when the second switch S2 is turned on, so as to receive the second output signal. An output signal is generated. The current sampling circuit 10 is electrically connected to the first output driving circuit 15 and the second output driving circuit 16, and captures the current signal output by the first output driving circuit 15 and the second output driving circuit 16. The first output driving circuit 15 includes a first power field-effect transistor, and the second output driving circuit 16 includes a second power field-effect transistor. The first power field-effect transistor has a first channel region width-to-length ratio and a second channel region width-to-length ratio, which is 1:n. The second power field-effect transistor has a third channel region width-to-length ratio and a fourth channel region width-to-length ratio, which is 1:n, where n is a positive number.

[0024] In this embodiment of the invention, the first output drive circuit 15 and the second output drive circuit 16 of the low-power solid-state relay 1 with protection circuit are electrically connected to an AC load. In another embodiment of the invention, when the first output drive circuit 15 and the second output drive circuit 16 are electrically connected to a DC load, the second isolation circuit 12, the first switching switch S1, the second switching switch S2, and the second output drive circuit 16 can be omitted, and the DC load can be directly connected by the first isolation circuit 11. In other words, when the load is a DC load, the low-power solid-state relay 1 with protection circuit does not need to consider the problem of surge current, and the DC load can be connected using the same circuit of the low-power solid-state relay 1 with protection circuit, even with the omission of some components.

[0025] In this embodiment of the invention, the first output driving circuit 15 includes a first silicon power field-effect transistor (MOSFET), a first silicon carbide (SiC) power field-effect transistor, or a first gallium nitride (GaN) power field-effect transistor, and the second output driving circuit 16 includes a second silicon power field-effect transistor, a second silicon carbide power field-effect transistor, or a second gallium nitride power field-effect transistor. The gate of the first output driving circuit 15 is connected to the gate of the second output driving circuit 16, the source of the first output driving circuit 15 is connected to the source of the second output driving circuit 16, and the drain of the first output driving circuit 15 and the drain of the second output driving circuit 16 are respectively connected to an AC power supply, a DC power supply, or a load. The internal resistance of a silicon power field-effect transistor increases at high temperatures, making it prone to overheating. Compared to silicon power field-effect transistors, silicon carbide and gallium nitride power field-effect transistors have the advantage of a smaller temperature rise, meaning they are less susceptible to high temperatures and have higher heat resistance. Furthermore, in this embodiment of the present invention, the first silicon power field-effect transistor and the second silicon power field-effect transistor are multi-source power field-effect transistors (MOSFETs). The first silicon carbide power field-effect transistor has a first channel region width-to-length ratio and a second channel region width-to-length ratio, which is 1:n. The second silicon carbide power field-effect transistor has a third channel region width-to-length ratio and a fourth channel region width-to-length ratio, which is 1:n. The first gallium nitride power field-effect transistor has a fifth channel region width-to-length ratio and a sixth channel region width-to-length ratio, which is 1:n. The second gallium nitride power field-effect transistor has a seventh channel region width-to-length ratio and an eighth channel region width-to-length ratio, which is 1:n. The first silicon power MOSFET has a ninth channel width-to-length ratio and a tenth channel width-to-length ratio, which are both 1:n. The second silicon power MOSFET has an eleventh channel width-to-length ratio and a twelfth channel width-to-length ratio, which are both 1:n. According to the formula for calculating the current of a power MOSFET based on the channel width-to-length ratio, a smaller channel width-to-length ratio results in a smaller current, while a larger ratio results in a larger current. By adjusting different channel width-to-length ratios, different output currents can be generated. For example, when a power MOSFET has different channel width-to-length ratios of 1:n, the output current flowing through a channel with a width-to-length ratio of 1:n is 1:n.

[0026] Please see Figure 2A and Figure 2B , Figure 2A This is a graph showing the relationship between gate voltage and output current. Figure 2B This is a graph showing the relationship between gate voltage and on-resistance. For power MOSFETs, the gate voltage ( A threshold voltage is required for a power MOSFET to turn on. When the gate voltage reaches the saturation region, the on-resistance decreases to a minimum. However, when the gate voltage has not yet reached the saturation region, the power MOSFET has a high on-resistance, preventing it from being fully turned on by a smaller gate voltage. Between the point where the gate voltage cannot turn on and the point where the power MOSFET is fully turned on, there exists a transition period, such as... Figure 2B The gate voltage is approximately between 6.5V and 7.5V. ), the gate voltage in this range ( Although it can conduct power MOSFETs, it corresponds to Figure 2A Output current (i.e., the drain current of the power MOSFET) The first output signal is relatively small, meaning its ability to drive power MOSFETs is relatively small. The signal level is lower than that of the second output signal. The signal level, and the first input signal Since the input signal is generated during the startup voltage delay time, the low-power solid-state relay 1 with protection circuit of this invention can be controlled by the soft-start circuit 13 to start with a smaller first input signal during the initial startup phase of the startup voltage delay time. The input is given to the first isolation circuit 11 and the second isolation circuit 12, and a smaller first output signal is given. Drive the first output drive circuit 15 and the second output drive circuit 16, and use a larger second input signal during the period greater than the start-up voltage delay time. The input is given to the first isolation circuit 11 and the second isolation circuit 12, that is, with a larger second output signal. This drives the first output drive circuit 15 and the second output drive circuit 16. In other words, the first output signal... This is equivalent to the input to the first output drive circuit 15 and the second output drive circuit 16, during which the gate voltage is relatively small, and the second output signal... This is equivalent to the input to the first output drive circuit 15 and the second output drive circuit 16 reaching the saturation region and having a large on-gate voltage. Therefore, the soft-start circuit 13 dynamically adjusts and gently starts the first output drive circuit 15 and the second output drive circuit 16 by segmenting the start-up voltage delay time, thereby reducing the impact of the surge current generated during the start-up phase on the first output drive circuit 15 and the second output drive circuit 16. Alternatively, in another embodiment of this utility model, the first output signal generated during the start-up voltage delay time... Alternatively, it can be the magnitude of the gate voltage that can be turned on to reach the saturation region. Or, in another embodiment of this invention, the first output signal generated during the startup voltage delay time... The gate voltage, which was initially unable to conduct, can be gradually increased to the level that allows the gate to conduct. In this embodiment of the invention, the first output signal is not limited. Size.

[0027] This invention relates to a low-power solid-state relay 1 with a protection circuit. By setting an isolation circuit to control the flow of current, it achieves electrical isolation, preventing current from flowing directly from one area to another in the circuit system. In this embodiment, the first isolation circuit 11 and the second isolation circuit 12 include an inductive isolation circuit, a capacitive isolation circuit, and an opto-isolation circuit. Taking the opto-isolation circuit as an example, the first isolation circuit 11 and the second isolation circuit 12 are each optocouplers. Each optocoupler includes an infrared light-emitting diode and a set of photovoltaic voltage generators. The input terminal of the photovoltaic voltage generator receives infrared light generated by the infrared light-emitting diode to generate an output voltage to the output terminal of the photovoltaic voltage generator. The output terminal of the photovoltaic voltage generator is connected to a switching switch. In other words, when a valid input signal is applied to the input terminal, the input signal flows from the input terminal to the infrared light-emitting diode, which generates infrared light. This causes the photovoltaic voltage generator to generate an output voltage based on the sensed infrared light, which is then transmitted to the switching circuit and transmitted to the first output driving circuit 15 and the second output driving circuit 16 through the switching circuit. Furthermore, taking an inductive isolation circuit as an example, the first isolation circuit 11 and the second isolation circuit 12 each include an inductor coil circuit. Through the coil circuit, the input signal can also be received and converted into a voltage signal by electromagnetic induction. Therefore, since the isolation circuit is powered by opto-isolation or electromagnetic induction, the high-voltage side of the load, the control circuit, and the drive circuit do not need to be additionally connected to provide power. Furthermore, in this embodiment of the present invention, the low-power solid-state relay 1 with a protection circuit also includes a third isolation circuit 20. The third isolation circuit 20 is the same as the first isolation circuit 11 and the second isolation circuit 12, receiving and converting a third input signal. For the third output signal The third isolation circuit 20 will output the third signal. As a power supply, it provides power to the soft-start circuit 13, logic circuit 14, overcurrent protection circuit 17, overtemperature protection circuit 18, and voltage regulator circuit 19. Details of the soft-start circuit 13, logic circuit 14, and voltage regulator circuit 19 will be described in detail below.

[0028] In this embodiment of the invention, the current sampling circuit 10 includes a sampling resistor to capture the output currents of the first output driving circuit 15 and the second output driving circuit 16, i.e., to capture the current signals of the first output driving circuit 15 and the second output driving circuit 16. The sampling resistor has a small impedance value. Combined with the power MOSFETs with different channel width-to-length ratios, by sampling the small output current of the first output driving circuit 15 with a smaller channel width-to-length ratio, the overall power consumption is lower when the smaller output current passes through the sampling resistor. Furthermore, the first power MOSFET has a first channel width-to-length ratio and a second channel width-to-length ratio, where the ratio is 1:n. The second power MOSFET has a third channel width-to-length ratio and a fourth channel width-to-length ratio, where the ratio is 1:n. Moreover, in this embodiment of the invention, the current sampling circuit includes a circuit with an adjustable resistance value to dynamically adjust the power consumption according to the magnitude of the output current. Furthermore, the current sampling circuit includes various series, parallel, or series-parallel resistors, and by adjusting the resistance value, the power consumption can be dynamically adjusted.

[0029] Please see Figure 3A and Figure 3B , Figure 3A This is a schematic diagram of the soft-start circuit of this utility model. Figure 3B This is a schematic diagram of the start-up voltage delay time. In this embodiment of the invention, the soft-start circuit 13 includes a timing circuit 131, which includes a charging capacitor C and receives a control voltage. To generate capacitor voltage The startup voltage delay time T1 of the soft-start circuit 13 is based on the capacitor voltage. The size is set. Furthermore, the charging capacitor C of the timing circuit 131 is connected via resistors R7 and R8, and the gate bias voltage of the power MOSFET M9. and control voltage Set charging current Charging begins, with the set charging current. The capacitance value of the charging capacitor C determines the capacitor voltage. The rise time further determines the startup voltage delay time T1. The charging capacitor C can be built into the chip or connected to an external resistor with a large resistance value to obtain the desired startup voltage delay time T1. Figure 3B As shown, even if a current greater than the preset value is generated within the startup voltage delay time T1. Surge current, such as 10 The soft-start circuit 13 still generates a first control signal to the first switch S1 and the second switch S2 during the start-up voltage delay time, and generates a second control signal to the first switch S1 and the second switch S2 when the start-up voltage delay time is greater than or equal to the start-up voltage delay time. That is, the soft-start circuit 13 is not affected by the surge current and will not malfunction during the start-up voltage delay time.

[0030] Please see Figure 4 This is a schematic diagram of another soft-start circuit connection logic circuit of the present invention. In this embodiment, the soft-start circuit 13 includes a timing circuit 131, a first comparator 132, a first NOT gate 133, and a second NOT gate 134. The timing circuit 131 includes a charging capacitor C and receives a control voltage. To generate a capacitor voltage The first input terminal of the first comparator 132 is electrically connected to the charging capacitor C, and the second input terminal of the first comparator 132 receives the buffer voltage. The output of the first comparator 132 is electrically connected to the input of the first NOT gate 133. The output of the first NOT gate 133 is electrically connected to the input of the second NOT gate 134 and the first switch S1. The output of the second NOT gate 134 is electrically connected to the second switch S2. When the capacitor voltage... Less than buffer voltage When the capacitor voltage is high, the first comparator 132 outputs a low-level signal, and through the first NOT gate 133 outputs an inverted high-level signal to the first switch S1, turning on the first switch S1. Then, through the second NOT gate 134, it outputs an inverted low-level signal to the second switch S2, turning off the second switch S2. Greater than or equal to buffer voltage At this time, the first comparator 132 outputs a high-level signal and outputs an inverted low-level signal through the first NOT gate 133 to the first switching switch S1, causing the first switching switch S1 to de-conduct. Then, the second NOT gate 134 outputs an inverted high-level signal to turn on the second switching switch S2. The start-up voltage delay time of the soft-start circuit 13 is based on the buffer voltage. The size setting. Furthermore, when the buffer voltage... With a smaller setting value, the charging capacitor C can be charged within a shorter start-up voltage delay time, resulting in a higher capacitor voltage. Exceeding buffer voltage When the buffer voltage If the set value is large, the charging capacitor C requires a longer start-up voltage delay time T1 to charge, so that the capacitor voltage... Exceeding buffer voltage .

[0031] As mentioned above, if overcurrent occurs in the power MOSFETs included in the first output drive circuit 15 and the second output drive circuit 16, they may overheat or be damaged due to excessive output current. Overcurrent is the primary cause of permanent damage to the internal output power components of the solid-state relay, with the most severe case being a load short circuit. Furthermore, many loads generate large inrush currents at the moment the input signal is switched on, and due to insufficient heat dissipation, these inrush currents can also damage the internal power MOSFETs of the solid-state relay. Therefore, the low-power solid-state relay 1 with protection circuit of this invention further adds an overcurrent protection mechanism between the isolation circuit and the output drive circuit. Furthermore, the low-power solid-state relay 1 with protection circuit also includes an overcurrent protection circuit 17, a logic circuit 14, and a voltage pull-down circuit 21. Overcurrent protection circuit 17 is electrically connected to the output terminals of the first output drive circuit 15, the second output drive circuit 16, and the input terminal of logic circuit 14. The output terminal of logic circuit 14 is electrically connected to the first output drive circuit 15 and the second output drive circuit 16, and the input terminal of logic circuit 14 is electrically connected to the output terminal of soft-start circuit 13. Pull-down circuit 21 is electrically connected to the output terminal of logic circuit 14, the first output drive circuit 15, and the second output drive circuit 16. When the output current generated by the first output drive circuit 15 or the second output drive circuit 16 within the startup voltage delay time (i.e., less than the startup voltage delay time) actuates the overcurrent protection circuit 17, causing it to generate a high-level signal, that is, when the overcurrent protection circuit 17 detects that the current signal generated by the first output drive circuit 15 or the second output drive circuit 16 is greater than or equal to a preset current value within the startup voltage delay time, logic circuit 14 generates a current sustaining signal to the first output drive circuit 15 and the second output drive circuit 16 based on the high-level signal to maintain the first output signal. Signal level and second output signal The signal level. In other words, even if the output current generated by the first output drive circuit 15 or the second output drive circuit 16 is an excessive current (i.e., surge current) during the start-up voltage delay time, the overcurrent protection circuit 17 will not be triggered to avoid malfunction of the overcurrent protection circuit 17. When the output current generated by the first output drive circuit 15 or the second output drive circuit 16 within the time interval of the start-up voltage delay time T1 (i.e., the time interval between the start-up voltage delay time T1 and the protection time T2) actuates the overcurrent protection circuit 17, causing the overcurrent protection circuit 17 to generate a high-level signal (also known as an overcurrent trigger signal) to the logic circuit 14, that is, when the overcurrent protection circuit 17 detects that the current signal generated by the first output drive circuit 15 or the second output drive circuit 16 is greater than or equal to the current preset value within the time interval of the start-up voltage delay time, the overcurrent protection circuit 17 activates the overcurrent protection mechanism. The logic circuit 14 then generates an overcurrent voltage pull-down signal to the voltage pull-down circuit 21 based on the high-level signal, causing the voltage pull-down circuit 21 to pull down the first output signal through the first switching switch S1 or the second switching switch S2. Signal level and second output signal The signal level, and make the first output signal Signal level and second output signal The signal level is lower than the start-up voltage of the first output drive circuit 15 and the second output drive circuit 16, so as to close the first output drive circuit 15 and the second output drive circuit 16, thereby protecting the first output drive circuit 15 and the second output drive circuit 16 from being damaged by overcurrent.

[0032] Furthermore, after the overcurrent protection circuit 17 activates the overcurrent protection mechanism and disconnects the first switching switch S1 and the second switching switch S2, the low-power solid-state relay 1 with protection circuitry can be restarted manually via a status latch within the overcurrent protection circuit 17. In manual reset mode, when the status latch stores a high-level signal and the overcurrent protection circuit 17 generates a low-level signal to the status latch, the status latch still outputs a high-level signal to the logic circuit 14. In this case, the status latch needs to be disconnected by power-off to eliminate the stored high-level signal and achieve the manual reset and restart function.

[0033] Please see Figure 5This is a circuit diagram of the over-temperature protection circuit of this utility model. The low-power solid-state relay 1 with the protection circuit also includes an over-temperature protection circuit 18. The over-temperature protection circuit 18 is electrically connected to the input terminal of the logic circuit 14 and is disposed around the first output drive circuit 15 and the second output drive circuit 16 to sense the temperature signals generated by the first output drive circuit 15 and the second output drive circuit 16. When the temperature signal is greater than or equal to a preset temperature value, it indicates that the first output drive circuit 15 or the second output drive circuit 16 has overheated. The over-temperature protection circuit 18 then generates an over-temperature signal (high-level signal) to the logic circuit 14, causing the logic circuit 14 to generate a high-level signal of an over-temperature switching signal to the voltage pull-down circuit 21, causing the voltage pull-down circuit 21 to pull down the first output signal through the first switching switch S1 or the second switching switch S2. Signal level and second output signal The signal level, and make the first output signal Signal level and second output signal The signal level is lower than the start-up voltage of the first output drive circuit 15 and the second output drive circuit 16 to close the circuit, thereby protecting the first output drive circuit 15 and the second output drive circuit 16 from damage caused by overcurrent.

[0034] As described above, the over-temperature protection circuit 18 includes a first transistor 181, a second transistor 182, a third transistor 183, and a bias resistor 184. The first transistor 181 and the second transistor 182 receive a bias voltage. and a control voltage Bias resistor 184 is connected to the second transistor 182. The third transistor 183 is connected to the first transistor 181, the second transistor 182, and bias resistor 184. When the temperature signal is less than the preset temperature value, the voltage at the base of the third transistor 183 is less than the turn-on voltage, causing the third transistor 183 to turn off. When the temperature signal is greater than or equal to the preset temperature value, since the turn-on voltage of the transistor decreases as the temperature rises, the bias voltage at this time is... and control voltage The base voltage of the third transistor 183 is greater than or equal to its turn-on voltage. After the third transistor 183 is further turned on, a high-level signal is generated to logic circuit 14, causing logic circuit 14 to generate an over-temperature switching signal to the voltage pull-down circuit 21. When the temperature signals generated by the first output drive circuit 15 and the second output drive circuit 16 decrease, causing the temperature signal to be lower than the preset temperature value, the bias voltage at this time... and control voltage The voltage difference cannot be greater than or equal to the turn-on voltage of the third transistor 183. The third transistor 183 generates a low-level signal to the logic circuit 14, which in turn generates a signal to the voltage pull-down circuit 21 to re-turn on the first output drive circuit 15 and the second output drive circuit 16.

[0035] Please see Figure 6 This is a circuit diagram of the voltage regulator circuit of this utility model. The low-power solid-state relay 1 with protection circuit also includes a voltage regulator circuit 19, electrically connected to the third isolation circuit 20, and receiving the third output signal. Generate bias voltage Control voltage Convert the third output signal A fixed voltage signal is supplied to the electrically connected soft-start circuit 13, logic circuit 14, overcurrent protection circuit 17, and overtemperature protection circuit 18 to ensure stable power supply to each circuit.

[0036] Please see Figure 7 This is a circuit diagram of the logic circuit of this utility model. The logic circuit 14 includes a second comparator 141 and a third NOT gate 142. The second comparator 141 has a first input terminal, a second input terminal, and an output terminal. The third NOT gate 142 has an input terminal and an output terminal. The first input terminal of the second comparator 141 is connected to the output terminal of the overcurrent protection circuit 17, receiving the signal output by the overcurrent protection circuit 17. The second input terminal receives a current preset value. The output terminal is connected to the input terminal of the third NOT gate 142. The output terminal of the third NOT gate 142 is connected to the voltage pull-down circuit 21. When the current signal output by the overcurrent protection circuit 17 is a high-level signal greater than or equal to the current preset value, that is, after conversion, the voltage signal output by the overcurrent protection circuit 17 is greater than or equal to the voltage preset value. When the high-level signal is received, the second comparator 141 generates an overcurrent switch signal to the third NOT gate 142, causing the third NOT gate 142 to output a low-level signal to the voltage pull-down circuit 21, which then pulls down the first output signal. Signal level and second output signal The signal level, and make the first output signal Signal level and second output signal The signal level is less than the gate start-up voltage of the first output drive circuit 15 and the second output drive circuit 16. It should be noted that both the current preset value and the output current can be converted into voltage signal values ​​and input to the comparator for comparison. In this utility model, the signal value compared by the comparator is not limited to a current signal value or a voltage signal value.

[0037] Please see Figure 8This is a circuit diagram of another logic circuit of this utility model. Logic circuit 14 includes a third comparator 143 and a fourth NOT gate 144. The third comparator 143 has a first input terminal and a second input terminal. The first input terminal is connected to the output terminal of the over-temperature protection circuit 18 and receives the signal output by the over-temperature protection circuit 18. The second input terminal receives a preset voltage value. The fourth NOT gate 144 has an input terminal and an output terminal. The input terminal of the fourth NOT gate 144 is connected to the output terminal of the third comparator 143, and the output terminal of the fourth NOT gate 144 is connected to the voltage pull-down circuit 21. When the temperature signal output by the over-temperature protection circuit 18 is greater than or equal to the high-level signal of the preset temperature value, that is, after the third transistor 183 of the over-temperature protection circuit 18 is turned on, its output voltage is greater than the preset voltage value. At this time, the third comparator 143 generates an over-temperature switching signal to the fourth NOT gate 144, causing the fourth NOT gate 144 to output a low-level signal to the voltage pull-down circuit 21, which in turn pulls down the first output signal. Signal level and second output signal The signal level is adjusted so that the gate signal level of the first output drive circuit 15 and the second output drive circuit 16 is less than the gate start-up voltage of the first output drive circuit 15 and the second output drive circuit 16.

[0038] Please see Figure 9This is a circuit diagram of another logic circuit of the present invention. In this embodiment, logic circuit 14 is simultaneously connected to overcurrent protection circuit 17 and overtemperature protection circuit 18 to achieve the effect of simultaneously detecting overcurrent and overtemperature. Logic circuit 14 includes a state latch 145, a NOR gate 146, and the aforementioned second comparator 141 and third comparator 143. The input terminal of state latch 145 is electrically connected to the output terminal of second comparator 141, and generates and stores a logic signal according to the overcurrent switch signal. The first input terminal of NOR gate 146 is electrically connected to the output terminal of state latch 145, and the second input terminal of NOR gate 146 is electrically connected to the output terminal of third comparator 143. NOR gate 146 outputs a high-level signal or a low-level signal in reverse order according to the logic signal level generated by state latch 145 or the control signal level output by third comparator 143. Furthermore, when the logic signal level generated by the state latch 145 or the control signal level output by the third comparator 143 is both low, it indicates that the overcurrent protection circuit 17 has not detected overcurrent, and the overtemperature protection circuit 18 has not detected overheating in the first output drive circuit 15 and the second output drive circuit 16. In this case, the NOR gate 146 outputs a high-level signal to the voltage pull-down circuit 21 to disable the voltage pull-down circuit 21. When the logic signal level generated by the state latch 145 or the control signal level output by the third comparator 143 is high, it indicates that the overcurrent protection circuit 17 has detected overcurrent, or the overtemperature protection circuit 18 has detected overheating in the first output drive circuit 15 and the second output drive circuit 16. In this case, the NOR gate 146 outputs a low-level signal to the voltage pull-down circuit 21 to pull down the first output signal. Signal level and second output signal The signal level is adjusted so that the gate signal level of the first output drive circuit 15 and the second output drive circuit 16 is less than the gate start-up voltage of the first output drive circuit 15 and the second output drive circuit 16.

[0039] As described above, in the aforementioned embodiments, overcurrent protection circuit 17 and overtemperature protection circuit 18 are simultaneously configured for detection. In other embodiments of this utility model, the low-power solid-state relay 1 with protection circuits can simultaneously be configured with overcurrent protection circuit 17, overtemperature protection circuit 18, and soft-start circuit 13, so as to simultaneously detect overcurrent, overtemperature, and surge current, and pull down the first output signal when one of the overcurrent, overtemperature, or surge current conditions occurs. Signal level and second output signal The signal level. Alternatively, in other embodiments of this utility model, the low-power solid-state relay with protection circuits may also selectively provide at least two of the circuits for overcurrent protection circuit 17, overtemperature protection circuit 18, and soft-start circuit 13. This utility model does not limit the number of circuits provided.

[0040] Please see Figure 10 This is a circuit diagram of the low-power solid-state relay with protection circuit of this utility model. In this embodiment, the low-power solid-state relay 1 with protection circuit includes the first isolation circuit 11, the second isolation circuit 12, the first switching switch S1, the second switching switch S2, the soft-start circuit 13, the first comparator 132, the first NOT gate 133, the second NOT gate 134, the logic circuit 14, the overcurrent protection circuit 17, the overtemperature protection circuit 18, and the voltage pull-down circuit 21. The logic circuit 14 includes the second comparator 141, the third comparator 143, the fourth comparator 147, the state latch 145, and the NOR gate 146. The soft-start circuit 13 includes the timing circuit 131, which includes a charging capacitor C and receives the control voltage. To generate capacitor voltage The first input terminal of the first comparator 132 is electrically connected to the charging capacitor C, and the second input terminal of the first comparator 132 receives the buffer voltage. The output of the first comparator 132 is electrically connected to the input of the first NOT gate 133. The output of the first NOT gate 133 is electrically connected to the input of the second NOT gate 134 and the first switch S1. The output of the second NOT gate 134 is electrically connected to the second switch S2. When the capacitor voltage... Less than buffer voltage When the voltage delay time is less than the startup voltage delay time, a first control signal is generated by the first comparator 132 and the first NOT gate 133 to the first switching switch S1 to turn on the first switching switch S1. When the capacitor voltage... Greater than or equal to buffer voltage When the delay time is greater than or equal to the start-up voltage delay time, a second control signal is generated by the first comparator 132, the first NOT gate 133, and the second NOT gate 134 to the second switching switch S2 to turn on the second switching switch S2. The input terminal of the overcurrent protection circuit 17 is electrically connected to the first output drive circuit 15 and the second output drive circuit 16, and when the current signal generated by the first output drive circuit 15 or the second output drive circuit 16 is greater than or equal to a preset current value, the overcurrent protection circuit 17 generates an overcurrent signal. The overtemperature protection circuit 18 is disposed around the first output drive circuit 15 and the second output drive circuit 16 to sense the temperature signals generated by the first output drive circuit 15 and the second output drive circuit 16. The logic circuit 14 has a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal, the second input terminal, and the third input terminal of the logic circuit 14 are electrically connected to the soft-start circuit 13, the overcurrent protection circuit 17, and the overtemperature protection circuit 18, respectively. The output terminal of the logic circuit 14 is electrically connected to the voltage pull-down circuit 21. The voltage pull-down circuit 21 is electrically connected to the output terminal of the logic circuit 14, the first switch S1, and the second switch S2. When the temperature signal is greater than or equal to a preset temperature value, the over-temperature protection circuit 18 generates an over-temperature signal to the logic circuit 14, causing the logic circuit 14 to generate a high-level signal to the voltage pull-down circuit 21, which then pulls down the first output signal. Signal level and second output signal The signal level, and make the first output signal Signal level and second output signal The signal level is lower than the gate startup voltage of the first output drive circuit 15 and the second output drive circuit 16. For example... Figure 10As shown, logic circuit 14 includes a second comparator 141, a third comparator 143, a fourth comparator 147, a state latch 145, and a NOR gate 146. The second comparator 141 has a first input, a second input, and an output. The first input is connected to an overcurrent protection circuit 17 and receives an overcurrent signal generated by the overcurrent protection circuit 17. The second input receives a preset threshold for the overcurrent. When the overcurrent signal is greater than or equal to the preset threshold, the second comparator 141 outputs a high-level overcurrent signal to the state latch 145. The state latch 145 has an input and an output. The input is electrically connected to the output of the second comparator 141. It generates a logic signal based on the high-level overcurrent signal and sends it to the NOR gate 146, storing the logic signal. The third comparator 143 has a first input, a second input, and an output. The first input is connected to an overtemperature protection circuit 18 and receives an overtemperature signal. The second input receives a preset temperature value. When the over-temperature signal is greater than or equal to the preset temperature value, the third comparator 143 outputs an over-temperature high-level signal to the NOR gate 146. The fourth comparator 147 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the fourth comparator 147 is connected to the soft-start circuit 13, and the second input terminal receives a preset voltage value. And according to the preset voltage value An overcurrent delay time is generated. When the second comparator 141 outputs an overcurrent high-level signal when the overcurrent delay time is less than the overcurrent delay time, the fourth comparator 147 generates an overcurrent high-level signal. When the second comparator 141 outputs an overcurrent high-level signal when the overcurrent delay time is greater than or equal to the overcurrent delay time, the fourth comparator 147 generates an overcurrent low-level signal. The NOR gate 146 has several input terminals and one output terminal. The input terminals are electrically connected to the output terminals of the third comparator 143, the fourth comparator 147, and the state latch 145, respectively, to receive overcurrent high-level signals, overtemperature high-level signals, overcurrent high-level signals, or overcurrent low-level signals. It inverts these signals and generates a voltage pull-down signal to the electrically connected voltage pull-down circuit 21. When the second comparator 141 outputs an overcurrent high-level signal less than the overcurrent delay time, the soft-start circuit 13 determines the capacitor voltage of the timing circuit 131. Is the voltage preset value greater than or equal to the overcurrent delay time? Or whether the voltage is less than the preset value within the overcurrent delay time. This corresponds to whether the overcurrent protection mechanism is activated or not. That is, when the capacitor voltage... The overcurrent delay time is less than the preset voltage value. Even in the event of an overcurrent, the soft-start circuit 13 will not trigger the overcurrent protection mechanism. When the capacitor voltage... When the overcurrent delay time is exceeded, the voltage is greater than or equal to the preset value. When an overcurrent occurs, the soft-start circuit 13 triggers the overcurrent protection mechanism. In other words, if an overcurrent occurs within the overcurrent delay time, the voltage pull-down circuit 21 will not be activated. When the second comparator 141 generates an overcurrent greater than or equal to the overcurrent delay time, the soft-start circuit 13 triggers the overcurrent protection mechanism, causing the fourth comparator 147 to generate an overcurrent low-level signal to the NOR gate 146, which inverts the output of the NOR gate 146 to generate a high-level signal, activating the voltage pull-down circuit 21. That is, when an overcurrent occurs greater than or equal to the overcurrent delay time, the voltage pull-down circuit 21 is activated, causing it to pull down the first output signal. Signal level and second output signal The signal level, and make the first output signal Signal level and second output signal The signal level is lower than the gate startup voltage of the first output drive circuit 15 and the second output drive circuit 16. By setting the soft-start circuit 13, overcurrent protection circuit 17, and overtemperature protection circuit 18 as described above, multiple detection and protection functions for overcurrent, overtemperature, or surge current can be achieved. The principle is similar to that described above and will not be repeated here. In addition, it should be noted that in the embodiments of this utility model, the overcurrent delay time can be less than, equal to, or greater than the startup voltage delay time T1 mentioned above. The overcurrent delay time T1 and the startup voltage delay time correspond to the capacitor voltage settings, and are not limited in this utility model.

[0041] In this embodiment of the present invention, each circuit can be disposed in different chips. For example, the components (such as light-emitting diodes and photovoltaic voltage generators) in the first isolation circuit 11, the second isolation circuit 12, and the third isolation circuit 20 are disposed in the first integrated package, the soft-start circuit 13 and the logic circuit 14 are disposed in the second integrated package, the first output drive circuit 15 is disposed in the third integrated package, and the second output drive circuit 16 is disposed in the fourth integrated package. Other packaging types are not limited in this invention.

[0042] In addition, Figure 3A , Figure 4 and Figure 6 It includes electronic components such as field-effect transistors M1~M7, M9~M15, resistors R1~R8, and diode D1.

[0043] In summary, this invention's low-power solid-state relay with protection circuitry utilizes opto-isolated power supply via an isolation circuit and is powered by the converted signal, eliminating the need for additional power supply to the control, logic, and drive circuits on the high-voltage side. Furthermore, by setting the startup voltage delay time through a soft-start circuit and segmenting the high and low voltage signals, the gate startup voltage of the output drive circuit can be dynamically adjusted during startup, achieving low thermal dissipation and reducing the impact of inrush current. It also prevents malfunction of the overcurrent protection circuit during the startup voltage delay time. Moreover, by adjusting the width-to-length ratio of the different channel regions of the power MOSFET and splitting the sampling output current, thermal dissipation loss on the sampling element can be reduced. Additionally, connecting a current sampling circuit further reduces the thermal dissipation of the solid-state relay. Furthermore, the silicon power MOSFET in the output drive circuit can be replaced by a silicon carbide power MOSFET or a gallium nitride power MOSFET to reduce the impact of high temperatures on the output drive circuit. In addition, the isolation circuit can be replaced by an inductor circuit or a capacitive sensing circuit, besides optocouplers.

Claims

1. A low-power solid-state relay with a protection circuit, characterized in that, Include: A first isolation circuit receives and converts a first input signal into a first output signal; A second isolation circuit receives and converts a second input signal into a second output signal; wherein a signal level of the first output signal is lower than a signal level of the second output signal. A soft-start circuit generates a first control signal when the delay time is less than a start-up voltage delay time, and generates a second control signal when the delay time is greater than or equal to the start-up voltage delay time. A first switching switch is electrically connected to the first isolation circuit and the soft-start circuit, and is turned on according to the first control signal; A second switching switch is electrically connected to the second isolation circuit and the soft-start circuit, and is turned on according to the second control signal; A first output drive circuit is electrically connected to the first isolation circuit through the first switching switch when the first switching switch is turned on, and is electrically connected to the second isolation circuit through the second switching switch when the second switching switch is turned on. A second output drive circuit is electrically connected to the first output drive circuit, and when the first switch is turned on, it is electrically connected to the first isolation circuit through the first switch, and when the second switch is turned on, it is electrically connected to the second isolation circuit through the second switch; and A current sampling circuit is electrically connected to the first output driving circuit and the second output driving circuit to capture a current signal output by the first output driving circuit and the second output driving circuit. The first output driving circuit includes a first power MOSFET, and the second output driving circuit includes a second power MOSFET. The first power MOSFET has a first channel width-to-length ratio and a second channel width-to-length ratio, which is 1:n. The second power MOSFET has a third channel width-to-length ratio and a fourth channel width-to-length ratio, which is 1:n, where n is a positive number.

2. The low-power solid-state relay with protection circuit as described in claim 1, characterized in that, The first power field-effect transistor includes a first silicon power field-effect transistor, a first silicon carbide power field-effect transistor, or a first gallium nitride power field-effect transistor, and the second power field-effect transistor includes a second silicon power field-effect transistor, a second silicon carbide power field-effect transistor, or a second gallium nitride power field-effect transistor.

3. The low-power solid-state relay with protection circuit as described in claim 1, characterized in that, The soft-start circuit includes a timing circuit, which includes a charging capacitor and receives a control voltage to generate a capacitor voltage; wherein the start-up voltage delay time of the soft-start circuit is set according to the magnitude of the capacitor voltage.

4. The low-power solid-state relay with protection circuit as described in claim 1, characterized in that, The soft-start circuit includes a timing circuit, a first comparator, a first NOT gate, and a second NOT gate. The timing circuit includes a charging capacitor, receives a control voltage, and generates a capacitor voltage according to the control voltage. A first input terminal of the first comparator is electrically connected to the charging capacitor to receive the capacitor voltage. A second input terminal of the first comparator receives a buffer voltage. An output terminal of the first comparator is electrically connected to an input terminal of the first NOT gate. An output terminal of the first NOT gate is electrically connected to an input terminal of the second NOT gate and the first switching switch. An output terminal of the second NOT gate is electrically connected to the second switching switch. When the capacitor voltage is less than the buffer voltage, the first comparator and the first NOT gate generate the first control signal to the first switching switch; When the capacitor voltage is greater than or equal to the buffer voltage, the first comparator, the first NOT gate, and the second NOT gate generate the second control signal to the second switching switch.

5. The low-power solid-state relay with protection circuit as described in claim 1, characterized in that, Also includes: An overcurrent protection circuit is provided, wherein an input terminal of the overcurrent protection circuit is electrically connected to the first output driving circuit and the second output driving circuit, and the overcurrent protection circuit generates a high-level signal when the current signal generated by the first output driving circuit or the second output driving circuit is greater than or equal to a current preset value. A logic circuit, wherein one input terminal of the logic circuit is electrically connected to one output terminal of the soft-start circuit; A voltage pull-down circuit is electrically connected to the output terminal of the logic circuit; When the overcurrent protection circuit detects that the current signal generated by the first output driving circuit or the second output driving circuit is greater than or equal to the current preset value within a time less than an overcurrent delay, the logic circuit generates a current sustaining signal to the first output driving circuit and the second output driving circuit based on the high level signal, so as to maintain the signal level of the first output signal and the signal level of the second output signal. When the overcurrent protection circuit detects that the current signal generated by the first output driving circuit or the second output driving circuit is greater than or equal to the current preset value within an overcurrent delay time greater than or equal to the overcurrent delay time, the logic circuit generates a voltage pull-down signal to the voltage pull-down circuit based on the high-level signal. This causes the voltage pull-down circuit to pull down the signal level of the first output signal and the signal level of the second output signal, making the signal level of the first output signal and the signal level of the second output signal less than the gate start-up voltage of the first output driving circuit and the second output driving circuit.

6. The low-power solid-state relay with protection circuit as described in claim 1, characterized in that, Also includes: An over-temperature protection circuit is disposed around the first output drive circuit and the second output drive circuit to sense a temperature signal generated by the first output drive circuit and the second output drive circuit. A logic circuit, wherein one input terminal of the logic circuit is electrically connected to the over-temperature protection circuit, and one output terminal of the logic circuit is electrically connected to the first output driving circuit and the second output driving circuit; A voltage pull-down circuit is electrically connected to the output terminal of the logic circuit; When the temperature signal is greater than or equal to a preset temperature value, the over-temperature protection circuit generates an over-temperature signal to the logic circuit, causing the logic circuit to generate a high-level signal to the voltage pull-down circuit, causing the voltage pull-down circuit to pull down the signal level of the first output signal and the signal level of the second output signal, and making the signal level of the first output signal and the signal level of the second output signal less than the gate start-up voltage of the first output driving circuit and the second output driving circuit.

7. The low-power solid-state relay with protection circuit as described in claim 6, characterized in that, The over-temperature protection circuit includes: A first transistor receives a bias voltage and a control voltage; A second transistor receives the bias voltage and the control voltage; A bias resistor is connected to the second transistor; and A third transistor is connected to the first transistor, the second transistor, and the bias resistor; When the temperature signal is less than the preset temperature value, the bias voltage and the control voltage are less than the on-state voltage of the third transistor, and the third transistor is turned off. When the temperature signal is greater than or equal to the preset temperature value, the bias voltage and the control voltage are greater than or equal to the turn-on voltage of the third transistor, and the third transistor is turned on to generate the over-temperature signal.

8. The low-power solid-state relay with protection circuit as described in claim 5, characterized in that, This logic circuit includes: A second comparator has a first input terminal, a second input terminal and an output terminal, the first input terminal being connected to the overcurrent protection circuit, and the second input terminal receiving the current preset value; A third NOT gate has an input terminal and an output terminal. The input terminal of the third NOT gate is electrically connected to the output terminal of the second comparator, and the output terminal of the third NOT gate is electrically connected to the voltage pull-down circuit. When the high-level signal generated by the overcurrent protection circuit is greater than or equal to the current preset value, the second comparator generates an overcurrent switching signal to the third NOT gate, and the third NOT gate outputs a low-level signal to the voltage pull-down circuit, causing the voltage pull-down circuit to pull down the signal level of the first output signal and the signal level of the second output signal, and making the signal level of the first output signal and the signal level of the second output signal less than the gate start-up voltage of the first output driving circuit and the second output driving circuit.

9. The low-power solid-state relay with protection circuit as described in claim 6, characterized in that, The logic circuit also includes: A third comparator has a first input terminal, a second input terminal and an output terminal. The first input terminal is connected to the over-temperature protection circuit, and the second input terminal receives the preset temperature value. A fourth NOT gate has an input terminal and an output terminal. The input terminal of the fourth NOT gate is connected to the output terminal of the third comparator, and the output terminal of the fourth NOT gate is electrically connected to the voltage pull-down circuit. When the high-level signal generated by the over-temperature protection circuit is greater than or equal to the preset temperature value, the third comparator generates an over-temperature switching signal to the fourth NOT gate, and the fourth NOT gate outputs a low-level signal to the voltage pull-down circuit, causing the voltage pull-down circuit to pull down the signal level of the first output signal and the signal level of the second output signal, and making the signal level of the first output signal and the signal level of the second output signal less than the gate start-up voltage of the first output driving circuit and the second output driving circuit.

10. The low-power solid-state relay with protection circuit as described in claim 1, characterized in that, The soft-start circuit includes a timing circuit, a first comparator, a first NOT gate, and a second NOT gate. The timing circuit includes a charging capacitor, receives a control voltage, and generates a capacitor voltage based on the control voltage. A first input terminal of the first comparator is electrically connected to the charging capacitor to receive the capacitor voltage. A second input terminal of the first comparator receives a buffer voltage. An output terminal of the first comparator is electrically connected to an input terminal of the first NOT gate. An output terminal of the first NOT gate is electrically connected to an input terminal of the second NOT gate and a first switching switch. An output terminal of the second NOT gate is electrically connected to a second switching switch. When the capacitor voltage is less than the buffer voltage, the first comparator and the first NOT gate generate a first control signal to the first switching switch. When the capacitor voltage is greater than or equal to the buffer voltage, the first comparator, the first NOT gate, and the second NOT gate generate a second control signal to the second switching switch. The low-power solid-state relay with protection circuitry also includes: An overcurrent protection circuit is provided, wherein an input terminal of the overcurrent protection circuit is electrically connected to the first output driving circuit and the second output driving circuit, and the overcurrent protection circuit generates an overcurrent signal when the current signal generated by the first output driving circuit or the second output driving circuit is greater than or equal to a current preset value. An over-temperature protection circuit is disposed around the first output drive circuit and the second output drive circuit to sense a temperature signal generated by the first output drive circuit and the second output drive circuit. A logic circuit has a first input terminal, a second input terminal, a third input terminal and an output terminal. The first input terminal, the second input terminal and the third input terminal of the logic circuit are electrically connected to the soft start circuit, the overcurrent protection circuit and the overtemperature protection circuit, respectively. A voltage pull-down circuit is electrically connected to the output terminal of the logic circuit; When the temperature signal is greater than or equal to a preset temperature value, the over-temperature protection circuit generates an over-temperature signal to the logic circuit, causing the logic circuit to generate a voltage pull-down signal to the voltage pull-down circuit, causing the voltage pull-down circuit to pull down the signal level of the first output signal and the signal level of the second output signal, and making the signal level of the first output signal and the signal level of the second output signal less than the gate start-up voltage of the first output driving circuit and the second output driving circuit.

11. The low-power solid-state relay with protection circuit as described in claim 10, characterized in that, This logic circuit includes: A second comparator has a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the overcurrent protection circuit and receives the overcurrent signal. The second input terminal receives the current preset value. When the overcurrent signal is greater than or equal to the current preset value, the second comparator outputs an overcurrent high level signal. A state latch has an input terminal and an output terminal, the input terminal being electrically connected to the output terminal of the second comparator, and generates and stores a logic signal based on the overcurrent high level signal; A third comparator has a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the over-temperature protection circuit and receives the over-temperature signal. The second input terminal receives the temperature preset value. When the over-temperature signal is greater than or equal to the temperature preset value, the third comparator outputs an over-temperature high-level signal. A fourth comparator has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the fourth comparator is connected to the soft-start circuit. The second input terminal receives a preset voltage value and generates an overcurrent delay time based on the preset voltage value. When the second comparator outputs an overcurrent high-level signal when the overcurrent delay time is less than the preset overcurrent delay time, the fourth comparator generates an overcurrent high-level signal. When the second comparator outputs an overcurrent high-level signal when the overcurrent delay time is greater than or equal to the preset overcurrent delay time, the fourth comparator generates an overcurrent low-level signal. A NOR gate has several input terminals and one output terminal. The several input terminals are electrically connected to the output terminal of the third comparator, the output terminal of the fourth comparator, and the output terminal of the state latch, respectively. It receives the overcurrent high level signal, the overtemperature high level signal, the overcurrent high level signal, and the overcurrent low level signal, respectively, and inverts the overcurrent high level signal, the overtemperature high level signal, the overcurrent high level signal, or the overcurrent low level signal. It generates the voltage pull-down signal based on the inverted overcurrent high level signal, the overtemperature high level signal, or the overcurrent low level signal.

12. The low-power solid-state relay with protection circuit as described in claim 10, characterized in that, Also includes: A third isolation circuit receives and converts a third input signal into a third output signal; A voltage regulator circuit receives a bias voltage, a control voltage, and the third output signal, and transmits the third output signal to the electrically connected soft-start circuit, the logic circuit, the overcurrent protection circuit, and the overtemperature protection circuit.

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