A timing control circuit for a gallium nitride power device

Abstract

The utility model provides a kind of timing control circuit when powering on gallium nitride, including triode Q1, switch MOS tube M1, resistance R3, capacitor C1, resistance R4;Positive voltage input connects the drain of switch MOS tube M1, negative voltage input is connected to the emitter of triode Q1 through resistance R3, the collector of triode Q1 connects the gate of switch MOS tube M1, still pass through capacitor C1 ground between resistance R3 and the emitter of triode Q1;Resistance R4 is arranged between the drain and gate of switch MOS tube M1, the source of switch MOS tube M1 forms positive voltage and is connected to the drain of gallium nitride depletion mode MOS tube;Negative voltage input is connected to the gate of gallium nitride depletion mode MOS tube by forming negative voltage through stabilivolt D1;The negative pole of stabilivolt D1 is connected to negative voltage input.The timing control circuit does not need external control, simple structure, small, easy to integrate, ensure that power-on timing is correct.

Description

Technical Field

[0001] This utility model relates to gallium nitride power-on timing control circuits, and in particular to a gallium nitride (GaN) negative and positive voltage power-on timing control circuit. Background Technology

[0002] Gallium nitride (GaN) power semiconductor technology is suitable for high-frequency, high-temperature, and high-power applications. As a wide-bandgap material, compared with traditional semiconductor materials such as silicon, it has higher breakdown field strength, faster electron mobility, and higher saturation electron velocity. It also boasts advantages such as low conduction loss, high switching frequency, and bidirectional conduction. It is currently the mainstream technology in the radio frequency industry and is widely used in RF power amplifier design.

[0003] Gallium nitride (GaN) power amplifiers, with their high power density, high frequency capability, and high temperature resistance, are rapidly emerging in high-end markets such as 5G base stations, millimeter-wave radar, and satellite communications. However, the power-on sequence of GaN power amplifiers is more complex than that of LDMOS technology, and even slight errors can burn out the device. Gallium nitride (GaN) is a depletion-mode MOSFET. This structure is based on a P-type substrate, with an N+ doped region between the source (S) and drain (D). However, there is a natural conductive channel here, meaning that the source and drain are conductive even when the gate is not powered. It can only be turned off by applying a negative gate voltage (VG < 0V). This means that if the drain (V-DD) is powered on first, and no negative voltage is applied to the gate, GaN will immediately conduct, generating a large current surge, and even burning out. Therefore, the power-on sequence for GaN is to apply V-GG (negative voltage) first, then V-DD (positive voltage), and the power-off sequence is to turn off V-DD first, then turn off V-GG (negative voltage). During actual power amplifier module debugging, the power-on and power-off sequence needs to be manually controlled. Debugging personnel may make operational errors by repeatedly powering on and off, leading to incorrect power-on and power-off timing, which could easily damage the GaN power amplifier.

[0004] Utility Model Authorization Announcement No. CN 219611750 U discloses a GaN power-on timing control circuit. This circuit includes a negative voltage generation circuit, a gate voltage selection circuit, a logic gate circuit, a drain voltage switching circuit, and a GaN power amplifier. The negative voltage generation circuit includes a first negative voltage chip and a second negative voltage chip. Both the first and second negative voltage chips output negative voltages and both output a PowerGood signal via open drain. The first negative voltage chip outputs a negative voltage of -2.5V, and the second negative voltage chip outputs a negative voltage of -5V. The gate voltage selection circuit uses a negative voltage analog switch. The negative voltage output terminals of both the first and second negative voltage chips are connected to the input terminals of the negative voltage analog switch. The output terminal of the pseudo-switch is connected to the gate of the GaN power amplifier; the logic gate circuit includes two NOT gates and one AND gate. The PowerGood signal output terminals of the first and second negative voltage chips are respectively connected to the input terminals of the two NOT gates, and the output terminals of the two NOT gates are connected to the input terminals of the AND gate; the drain voltage switch circuit includes an NPN transistor and a PMOS transistor. The output terminal of the AND gate is connected to the base of the NPN transistor, the emitter of the NPN transistor is grounded, the collector of the NPN transistor is connected to the gate and source of the PMOS transistor, and the drain of the PMOS transistor is connected to the drain of the GaN power amplifier.

[0005] Such GaN power-on timing control circuits use multiple chips and devices, resulting in the following optimization opportunities: 1. Low system integration, with the multi-chip architecture leading to excessive PCB footprint; 2. High BOM cost due to the large number of components; 3. System reliability limited by the complexity of interconnections between discrete components; 4. Reduced maintainability due to the complexity of the circuit topology. Utility Model Content

[0006] This invention addresses the aforementioned shortcomings of current gallium nitride (GaN) power-on timing circuits by providing a GaN power-on timing control circuit. This timing control circuit requires no external control, has a simple structure, small size, is easy to integrate, and ensures correct power-on timing.

[0007] The technical solution for achieving the technical objective of this utility model is: a gallium nitride power-on timing control circuit, including a transistor Q1, a switching MOSFET M1, a resistor R3, a capacitor C1, and a resistor R4;

[0008] The positive voltage input is connected to the drain of the switching MOSFET M1, the negative voltage input is connected to the emitter of the transistor Q1 via resistor R3, and the collector of the transistor Q1 is connected to the gate of the switching MOSFET M1. A capacitor C1 is also connected between resistor R3 and the emitter of the transistor Q1 to ground. Resistor R4 is placed between the drain and gate of the switching MOSFET M1, and the source of the switching MOSFET M1 forms a positive voltage connected to the drain of the gallium nitride depletion-type MOSFET.

[0009] The negative voltage input is generated by the Zener diode D1 and connected to the gate of the gallium nitride depletion-type MOSFET; the negative terminal of the Zener diode D1 is connected to the negative voltage input.

[0010] Furthermore, in the above-mentioned gallium nitride power-on timing control circuit, a capacitor C5 is also provided between the drain and gate of the switching MOS transistor M1.

[0011] Furthermore, the gallium nitride power-on timing control circuit described above also includes voltage divider resistors R1 and R2; the negative voltage input is connected to the negative terminal of Zener diode D1 after being divided by the voltage divider resistors R1 and R2.

[0012] The gallium nitride amplifier negative and positive voltage power-on timing control circuit adopted in this utility model solves the difficulty of manually controlling the power-on timing, meets the power-on timing requirements of gallium nitride power amplifiers, and protects gallium nitride power amplifiers.

[0013] The power-on timing circuit of this invention requires no external control, has a simple structure, small size, and is easy to integrate. It ensures correct power-on timing while suppressing surge current.

[0014] The present invention will be described in more detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0015] Appendix Figure 1 This is a schematic diagram of the gallium nitride power-on timing control circuit of this utility model;

[0016] Appendix Figure 2 This is a schematic diagram of the gallium nitride power-on timing control circuit of Embodiment 1 of this utility model;

[0017] Appendix Figure 3 This is a simulation result diagram of the gallium nitride power-on timing control circuit of Embodiment 1 of this utility model. Detailed Implementation

[0018] This embodiment is a gallium nitride power-on timing control circuit, such as... Figure 1 As shown: It includes transistor Q1, switching MOSFET M1, resistor R3, capacitor C1, and resistor R4.

[0019] The positive voltage input is connected to the drain of the switching MOSFET M1, and the negative voltage input is connected to the emitter of the transistor Q1 via resistor R3. The collector of transistor Q1 is connected to the gate of the switching MOSFET M1. A capacitor C1 is also connected to ground between resistor R3 and the emitter of transistor Q1. Resistor R4 is placed between the drain and gate of the switching MOSFET M1, and the source of the switching MOSFET M1 forms a positive voltage connected to the drain V-DD of the gallium nitride depletion-mode MOSFET. Here, the switching MOSFET M1 is an FQB11P06 series N-channel enhancement-mode power MOSFET, featuring a miniaturized package design suitable for high-frequency switching and low-power applications.

[0020] The negative input voltage is generated by Zener diode D1 and applied to the gate Vg of the gallium nitride depletion-mode MOSFET; the negative terminal of Zener diode D1 is connected to the negative input voltage. Zener diode D1 is a BAS40HY series low forward voltage (low VF) Schottky barrier diode, mainly suitable for low current rectification applications. This series uses an SOT-23 package, featuring small size and high design flexibility, suitable for electronic devices with high stability requirements.

[0021] A capacitor C5 is also provided between the drain and gate of the switching MOSFET M1 to provide surge protection for the switching transistor. It also includes voltage divider resistors R1 and R2; the negative voltage input is connected to the negative terminal of the Zener diode D1 after being divided by the voltage divider resistors R1 and R2. The ratio of resistor R1 to resistor R2 is 4.3:1.

[0022] In this embodiment, the GaN negative and positive power-on timing control circuit achieves the amplifier being powered on first with V-GG (negative voltage) and then with V-DD (positive voltage). This is achieved through the coordinated operation of an RC delay circuit (a delay circuit composed of resistor R3 and capacitor C1), a transistor, and a MOSFET. The detailed circuit diagram is as follows. Figure 2 As shown. The load resistors (560 ohms, 100K) connected after VDD (positive voltage) and Vg (negative voltage to the gate) are close to the actual input and output impedance values ​​of GaN. That is to say, the above attached... Figure 2 In the circuit, resistors R5 and R12 are the loads.

[0023] During power-on timing control, the negative voltage path uses a first-order RC delay circuit composed of resistor R3 and capacitor C1, with a time constant of R3*C1. This network controls the conduction timing of transistor Q1 to achieve delayed turn-on for positive voltage. Specifically:

[0024] 1. The negative voltage, after passing through a voltage divider resistor and a filter capacitor, is directly supplied to the gate of the gallium nitride (GaN) amplifier. Here, the filtering is... Figure 2 C2, C3, and C4 are connected between the negative voltage and ground for filtering.

[0025] 2. The positive voltage path is controlled by the conduction state of the switching tube MOSFET M1, and its gate drive voltage is generated by a level conversion circuit composed of R4 and Q1;

[0026] 3. When the RC network is charged to the conduction threshold of triode Q1 (VBE≈0.6V), triode Q1 enters the saturation region and generates a drive current Io=(-0.6+3.3) / R3, which makes VGS of switching tube MOSFET M1 reach the turn-on voltage, and this voltage is the voltage across resistor R4.

[0027] A capacitor C5 is connected in parallel between the gate and source of MOSFET M1, and this design has two functions:

[0028] 1. Suppressing abrupt gate voltage change caused by the Miller effect (dV / dt control);

[0029] 2. Providing a high-frequency bypass path to effectively attenuate surge current during switching.

[0030] The power-down sequence management adopts a charge holding circuit composed of Zener diode D1:

[0031] 1. Blocking the discharge path of the capacitor through the power supply loop by using the reverse cut-off characteristic of the Zener diode;

[0032] 2. Implementing the gradual drop of V-GG through the bleeder resistor at the load terminal (gate) to ensure meeting the sequence requirement of td(V-DD-off)<td(V-GG-off).

[0033] The above circuit is simulated with Ltspice software, and the results are shown in Figure 3 : it can be seen from Figure 3 that during power-on: the negative voltage completes powering up to about -2.6V first, and after about 0.2S, the positive voltage completes rising to 25V; during power-down: when the positive voltage drops from 25V to 0V, the negative voltage then slowly rises from -2.6V to -1V. The simulation results show that the circuit realizes the function of applying V-GG (negative voltage) first and then V-DD (positive voltage), and the specific power-on, power-down, negative voltage and positive voltage delay times can be adjusted arbitrarily. According to actual requirements, while realizing correct power-on and power-off, it can meet the time requirement of transceiving conversion in radio frequency transceivers.

[0034] The key point of this embodiment is to control the power-on sequence of the amplifier through the cooperative work of the RC delay circuit, the triode and the MOS tube, so that the negative voltage is powered on first, and the positive voltage is powered on later. The reverse cut-off characteristic of the Zener diode is used to slow down the power-down speed of the gate, so that when the amplifier is powered down, the negative voltage is powered down after the positive voltage completes power down. This protects the GaN amplifier from damage during power-on and power-off.

[0035] This embodiment has the following characteristics:

[0036] The power-on timing circuit of this embodiment requires no external control, ensuring normal timing and guaranteeing that negative voltage is applied first and positive voltage is applied last. It features a simple structure, small size, and ease of integration. This circuit does not affect the gain, noise performance, or linearity of GaN, while protecting GaN from damage caused by large current surges during power-on and power-off processes.

[0037] During power-on timing control, the negative voltage path uses a first-order RC delay circuit consisting of resistor R3 and capacitor C1, with a time constant of R3*C1. This network controls the conduction timing of transistor Q1 to achieve delayed activation under positive voltage.

[0038] A capacitor C5 is connected in parallel between the gate and source of MOSFET M1 to provide a high-frequency bypass path and effectively attenuate the surge current during the switching process.

Claims

1. A gallium nitride power-on timing control circuit, characterized in that: Includes transistor Q1, switching MOSFET M1, resistor R3, capacitor C1, and resistor R4; The positive voltage input is connected to the drain of the switching MOSFET M1, the negative voltage input is connected to the emitter of the transistor Q1 via resistor R3, and the collector of the transistor Q1 is connected to the gate of the switching MOSFET M1. A capacitor C1 is also connected between resistor R3 and the emitter of the transistor Q1 to ground. Resistor R4 is placed between the drain and gate of the switching MOSFET M1, and the source of the switching MOSFET M1 forms a positive voltage connected to the drain (V-DD) of the gallium nitride depletion-type MOSFET. The negative voltage input is generated by Zener diode D1 and connected to the gate (Vg) of the gallium nitride depletion-type MOSFET; the negative terminal of Zener diode D1 is connected to the negative voltage input.

2. The timing control circuit on GaN power-up according to claim 1, wherein: A capacitor C5 is also provided between the drain and gate of the aforementioned switching MOSFET M1.

3. The timing control circuit on GaN power-up according to claim 1, wherein: It also includes voltage divider resistors R1 and R2; the negative voltage input is connected to the negative terminal of Zener diode D1 after being divided by the voltage divider resistors R1 and R2.

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