A high-low level output switching circuit

Abstract

The utility model discloses a high low level output switching circuit, electric connection is in between main control chip and output interface, including first delay circuit, second delay circuit, first switch tube and second switch tube, and main control chip links to each other with first delay circuit and second delay circuit respectively, and first delay circuit links to each other through first switch tube with output interface, and second delay circuit links to each other through second switch tube with output interface, and first switch tube links to each other with high voltage end, and second switch tube links to each other with ground. The utility model discloses a high low level output switching circuit electric connection is in between main control chip and output interface, through setting and high voltage end link's first switch tube and with ground link's second switch tube, and main control chip links to each other with first switch tube and second switch tube through first delay circuit and second delay circuit respectively, to cooperate staggered high low level switching time difference, ensure that high level does not exist with low level simultaneously in switching process and lead to short circuit.

Description

Technical Field

[0001] This utility model relates to the field of level conversion circuit technology, and in particular to a high-low level output switching circuit. Background Technology

[0002] In existing circuit designs, when outputting high or low levels through the same interface, there is a risk of short circuits caused by the simultaneous presence of high and low levels during level switching, which could damage circuit components. Utility Model Content

[0003] The purpose of this invention is to provide a high-low level output switching circuit to avoid the problem of short circuits and damage to circuit components caused by the simultaneous presence of high and low levels during the level switching process when high and low level outputs are performed through the same interface.

[0004] To solve the above-mentioned technical problems, this utility model provides a high-low level output switching circuit, electrically connected between the main control chip and the output interface, including a first delay circuit, a second delay circuit, a first switching transistor, and a second switching transistor. The main control chip is connected to the first delay circuit and the second delay circuit respectively. The first delay circuit is connected to the output interface through the first switching transistor, and the second delay circuit is connected to the output interface through the second switching transistor. The first switching transistor is connected to the high voltage terminal, and the second switching transistor is connected to ground.

[0005] The further technical solution is as follows: the high-low level output switching circuit further includes a sixth switching transistor, the first end of which is connected to the main control chip and the first delay circuit, and the second end of which is connected to the main control chip and the second delay circuit.

[0006] The further technical solution is as follows: the first switch is a PMOS transistor, and the second and sixth switches are both NMOS transistors.

[0007] The further technical solution is as follows: the source of the first switching transistor is connected to the high voltage terminal, the drain of the first switching transistor is connected to the output interface through a fourth diode and a first fuse connected in series, and the first input / output pin of the main control chip is connected to the gate of the first switching transistor through the first delay circuit.

[0008] The further technical solution is as follows: the first delay circuit includes a 37th resistor, a 65th capacitor, a 4th resistor, a 27th switch, and a 57th resistor. The 27th switch is a transistor. The 37th resistor is connected in series with the 4th resistor. The first input / output pin of the main control chip is connected to the 37th resistor. The base of the 27th switch is electrically connected to the series node of the 37th resistor and the 4th resistor. The emitter of the 27th switch is grounded. The collector of the 27th switch is connected to the gate of the first switch via the 57th resistor. The first terminal of the 65th capacitor and the drain of the 6th switch are both electrically connected to the series node of the 37th resistor and the 4th resistor. The source of the 6th switch is grounded.

[0009] The further technical solution is as follows: the source of the second switching transistor is grounded, the second input / output pin of the main control chip is connected to the gate of the second switching transistor after passing through the second delay circuit, the drain of the second switching transistor is connected to the cathode of the twelfth diode, and the anode of the twelfth diode is electrically connected to the series node of the fourth diode and the first fuse, so that the second input / output pin of the main control chip is connected to the output interface after passing through the second delay circuit and the second switching transistor, the twelfth diode and the first fuse.

[0010] The further technical solution is as follows: the second delay circuit includes a twenty-first diode, a sixty-sixth resistor, a sixty-seventh resistor, a thirty-eighth resistor, and a seventy-third capacitor. The sixty-sixth resistor is connected in series with the thirty-eighth resistor. The second input / output pin of the main control chip is connected to the sixty-sixth resistor. The gate of the second switching transistor is electrically connected to the series connection node of the sixty-sixth resistor and the thirty-eighth resistor. The sixty-seventh resistor is connected in series with the twenty-first diode and then in parallel with the sixty-sixth resistor. One end of the seventy-third capacitor is electrically connected to the connection node of the sixty-sixth resistor and the gate of the second switching transistor. The other end of the seventy-third capacitor is grounded.

[0011] The further technical solution is as follows: the second input / output pin of the main control chip is connected to the 39th and 40th resistors connected in series, and the gate of the sixth switch is electrically connected to the series node of the 39th and 40th resistors.

[0012] The further technical solution is as follows: a sixth diode, a sixty-sixth capacitor, and a fifty-fourth resistor are electrically connected in parallel between the source and gate of the first switching transistor.

[0013] A further technical solution is as follows: an 84th grounding capacitor and a 51st grounding diode are electrically connected in parallel at the connection node between the output interface and the first fuse.

[0014] The beneficial technical effects of this utility model are as follows: The high-low level output switching circuit of this utility model is electrically connected between the main control chip and the output interface. By setting a first switching transistor connected to the high voltage end and a second switching transistor connected to ground, and the main control chip is connected to the first switching transistor and the second switching transistor through a first delay circuit and a second delay circuit respectively, the time difference of high-low level switching is staggered to ensure that the high level and the low level do not exist at the same time during the switching process, so as to prevent short circuit and avoid damage to circuit components. The first switching transistor and the second switching transistor are connected to the output interface to realize high-low level output switching of the same interface. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram illustrating the framework of the high / low level output switching circuit provided by this utility model in a specific application.

[0017] Figure 2 The circuit diagram of the high / low level output switching circuit provided by this utility model. Detailed Implementation

[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0019] Please see Figures 1 to 2 , Figure 1This is a schematic diagram of the high / low level output switching circuit provided by this utility model in a specific application. The high / low level output switching circuit 10 is electrically connected between the main control chip U1 and the output interface DOUT, and includes a first delay circuit 11, a second delay circuit 12, a first switch Q32, and a second switch Q29. The main control chip U1 is connected to the first delay circuit 11 and the second delay circuit 12 respectively. The first delay circuit 11 is connected to the output interface DOUT through the first switch Q32, and the second delay circuit 12 is connected to the output interface DOUT through the second switch Q29. The first switch Q32 is connected to the high voltage terminal VCC_12V, and the second switch Q29 is connected to ground.

[0020] Among them, the high-voltage terminal VCC_12V is a power supply voltage of 12V, and the high-voltage terminal VCC_12V can be the output terminal of the high-voltage generation circuit. The main control chip U1 can be an MCU. The first delay circuit 11 and the second delay circuit 12 can stagger the time regions where high-level output and low-level output exist simultaneously, preventing high and low levels from existing at the same time. The high / low level output switching circuit 10 is electrically connected between the main control chip U1 and the output interface DOUT. It uses a first switch Q32 connected to the high-voltage terminal VCC_12V and a second switch Q29 connected to ground. Furthermore, the main control chip U1 is connected to the first switch Q32 via a first delay circuit 11, and to the second switch Q29 via a second delay circuit 12. This design ensures that the high and low levels do not coexist during the switching process, preventing short circuits and damage to circuit components. The first switch Q32 and the second switch Q29 are connected to the output interface DOUT, enabling high / low level output switching from the same interface. This design is highly practical, safe, and reliable, and can be applied to electronic devices with a single tail wire.

[0021] Specifically, in this embodiment, the high-low level output switching circuit 10 further includes a sixth switch Q6. The first end of the sixth switch Q6 is connected to the main control chip U1 and the first delay circuit 11, and the second end of the sixth switch Q6 is connected to the main control chip U1 and the second delay circuit 12. This is to prevent a short circuit caused by the simultaneous existence of high and low levels in the output due to a logic error in the main control chip U1. The main control chip U1 sends a signal to control the sixth switch Q6 to be turned on or off, thereby controlling the output to be high or low.

[0022] Specifically, the first switch Q32 is a PMOS transistor, and the second switch Q29 and the sixth switch Q6 are both NMOS transistors.

[0023] Preferably, the first switch Q32 can be a PMOS transistor of type AGM60P85E, and the second switch Q29 and the sixth switch Q6 can both be NMOS transistors of type NCE6003.

[0024] Specifically, the source of the first switching transistor Q32 is connected to the high-voltage terminal VCC_12V, and the drain of the first switching transistor Q32 is connected to the output interface DOUT via a fourth diode D4 connected in series and a first fuse P1. The first input / output pin IO1 of the main control chip U1 is connected to the gate of the first switching transistor Q32 via the first delay circuit 11. The cathode of the fourth diode D4 is connected to the output interface DOUT via the first fuse P1, and the anode of the fourth diode D4 is connected to the drain of the first switching transistor Q32. The fourth diode D4 is used to prevent reverse current from the external power supply to the high / low level output switching circuit 10, thus avoiding damage to circuit components. The fourth diode D4 can be connected in parallel with the forty-sixth resistor R46. The first fuse P1 is a PPTC (Polymeric Positive Temperature Coefficient) self-resetting fuse, which serves as a current-limiting protection. At the connection point between the drain of the first switching transistor Q32 and the anode of the fourth diode D4, a sixty-fourth grounding resistor R64 and a ninety-sixth grounding capacitor C96 can be connected in parallel.

[0025] Specifically, the first delay circuit 11 includes a 37th resistor R37, a 65th capacitor C65, a 4th resistor R4, a 27th switch Q27, and a 57th resistor R57. The 27th switch Q27 is a transistor. The 37th resistor R37 is connected in series with the 4th resistor R4. The first input / output pin IO1 of the main control chip U1 is connected to the 37th resistor R37. The base of the 27th switch Q27 is electrically connected to the series node of the 37th resistor R37 and the 4th resistor R4. The emitter of the 27th switch Q27 is grounded. The collector of the 27th switch Q27 is connected to the gate of the first switch Q32 via the 57th resistor R57. The first terminal of the 65th capacitor R65 and the drain of the 6th switch Q6 are both electrically connected to the series node of the 37th resistor R37 and the 4th resistor R4. The source of the 6th switch Q6 is grounded.

[0026] Specifically, the source of the second switching transistor Q29 is grounded, and the second input / output pin IO2 of the main control chip U1 is connected to the gate of the second switching transistor Q29 after passing through the second delay circuit 12. The drain of the second switching transistor Q29 is connected to the cathode of the twelfth diode D12, and the anode of the twelfth diode D12 is electrically connected to the series node of the fourth diode D4 and the first fuse P1, so that the second input / output pin IO2 of the main control chip U1 is connected to the output interface DOUT through the second delay circuit 12 and the second switching transistor Q29, the twelfth diode D12, and the first fuse P1. The sixth switch Q6 and the second switch Q29 are both NMOS transistors of the same type and are connected to the second input / output pin IO2 of the main control chip U1. They are controlled by the signal output from the second input / output pin IO2 of the main control chip U1, so that the sixth switch Q6 and the second switch Q29 are in the same state, meaning they are simultaneously turned on or off. The first terminal of the sixth switch Q6 is connected to the first input / output pin IO1 of the main control chip U1 to prevent logic errors. This avoids the high-voltage terminal VCC_12V from being damaged if the main control chip U1 mistakenly pulls up both its first input / output pin IO1 and its second input / output pin IO2 simultaneously. The voltage is connected to ground after passing through the first switch Q32, the fourth diode D4, the twelfth diode D12, and the second switch Q29, preventing damage to circuit components caused by a short circuit between the high level and ground. By setting a sixth switch Q6, when the main control chip U1 erroneously pulls up its first input / output pin IO1 and its second input / output pin IO2, the first input / output pin IO1 of the main control chip will be pulled down to ground by the sixth switch Q6, causing the first switch Q32 to turn off. This prevents the voltage at the high-voltage terminal VCC_12V from being connected to ground after passing through the first switch Q32, the fourth diode D4, the twelfth diode D12, and the second switch Q29, thereby avoiding damage to circuit components.

[0027] Specifically, the second delay circuit 12 includes a twenty-first diode D21, a sixty-sixth resistor R66, a sixty-seventh resistor R67, a thirty-eighth resistor R38, and a seventy-third capacitor C73. The sixty-sixth resistor R66 and the thirty-eighth resistor R38 are connected in series. The second input / output pin IO2 of the main control chip U1 is connected to the sixty-sixth resistor R66. The gate of the second switching transistor Q29 is electrically connected to the series connection node of the sixty-sixth resistor R66 and the thirty-eighth resistor R38. The sixty-seventh resistor R67 is connected in series with the twenty-first diode D21 and then in parallel with the sixty-sixth resistor R66. One end of the seventy-third capacitor C73 is electrically connected to the connection node of the sixty-sixth resistor R66 and the gate of the second switching transistor Q29, and the other end of the seventy-third capacitor C73 is grounded. The high-low level output switching modes include switching from high-level output to low-level output and switching from low-level output to high-level output. When the high-low level output switching mode is switching from high-level output to low-level output, the first switch Q32 needs to be turned off quickly while the second switch Q29 is turned on slowly. When the high-low level output switching mode is switching from low-level output to high-level output, the first switch Q32 needs to be turned on slowly while the second switch Q29 is turned off quickly. In this case, the switches need to be turned on slowly and turned off quickly. For the first delay circuit 11, the turn-on and turn-off speeds of the first switch Q32 are at an intermediate speed. The turn-on time of the first switch Q32 can be 2ms and the turn-off time can be 8ms. For the second delay circuit 12, when the second input / output pin IO2 of the main control chip U1 is pulled up, the branch where the sixty-seventh resistor R67 and the twenty-first diode D21 are located is not conducting. The current charges the seventy-third capacitor C73 through the sixty-sixth resistor R66. The voltage across the seventy-third capacitor C73 rises slowly. By adjusting the values ​​of the sixty-sixth resistor R66 and the seventy-third capacitor C73, the voltage rise of the second switch Q29 can be slowed down, thereby achieving slow turn-on of the second switch Q29. When it is necessary to turn off the second switch Q29, the second input / output pin IO2 of the main control chip U1 is pulled down, and the seventy-third capacitor C73 discharges to the main control chip U1 through the twenty-first diode D21 and the sixty-seventh resistor R67. By reducing the value of the sixty-seventh resistor R67, the seventy-third capacitor C73 can be discharged quickly, which causes the gate voltage of the second switch Q29 to drop rapidly and turn off the second switch Q29 quickly. The turn-on time of the second switch Q29 can be 18ms and the turn-off time can be 670μs.If the turn-on time of the second switch Q29 is greater than the turn-off time of the first switch Q32, then the turn-on speed of the second switch Q29 is lower than the turn-off speed of the first switch Q32. If the turn-off time of the second switch Q29 is less than the turn-on time of the first switch Q32, then the turn-off speed of the second switch Q29 is higher than the turn-on speed of the first switch Q32. This completely separates the time regions of high-level output and low-level output during the high-low level output switching process, ensuring that the circuit will not be damaged.

[0028] Specifically, the second input / output pin IO2 of the main control chip U1 is connected to the 39th resistor R39 and the 40th resistor R40 connected in series. The gate of the sixth switch Q6 is electrically connected to the series node of the 39th resistor R39 and the 40th resistor R40. One end of the 40th resistor R40 is connected to the 39th resistor R39, and the other end of the 40th resistor R40 is grounded. The source of the sixth switch Q6 is grounded.

[0029] Specifically, a sixth diode D6, a sixty-sixth capacitor C66, and a fifty-fourth resistor R54 are electrically connected in parallel between the source and gate of the first switching transistor Q32. The sixth diode D6 is a Zener diode, used to limit the voltage between the gate and source of the first switching transistor Q32 to a maximum of 10V and stabilize it at 10V, so as to protect the first switching transistor Q32.

[0030] Specifically, the output interface DOUT is electrically connected to the connection node of the first fuse P1 with an 84th grounding capacitor C84 and a 51st grounding diode D51 connected in parallel.

[0031] Based on the above design, during operation, for the first delay circuit, when the first input / output pin of the main control chip is pulled up, the base of the second seventeenth transistor is pulled high through the voltage divider and current limiting of the 37th and 4th resistors, making the collector and emitter of the second seventeenth transistor conduct. At this time, the high-voltage terminal is grounded after being connected to the second seventeenth transistor through the 54th and 57th resistors, causing a voltage difference between the gate and source of the first switching transistor, making the source and drain of the first switching transistor conduct. Thus, the first switching transistor is turned on, and the voltage at the high-voltage terminal is output to the output interface through the first switching transistor and the fourth diode and then through the first fuse, so the output interface can output a high level normally. When the first input / output pin of the main control chip is pulled up, no current flows between the collector and emitter of the second seventeenth transistor, which is equivalent to an open circuit, and the gate voltage of the first switching transistor is raised to When the voltage at the source and gate is equal, there is no voltage difference between the gate and source of the first switch, and the source and drain of the first switch are disconnected, thus the first switch is turned off, stopping the output of a high level, and the output interface is in a high-impedance state. Corresponding to the second delay circuit, when the second input / output pin of the main control chip is pulled up, the gate of the second switch is pulled up, a voltage difference is generated between the gate and source of the second switch, and the source and drain of the second switch are connected. The second switch is turned on, so that the output interface is connected to ground through the first fuse, the twelfth diode, and the second switch, causing the output interface to output a low level. When the second input / output pin of the main control chip is pulled up, there is no voltage difference between the gate and source of the second switch, the drain and source of the second switch are disconnected, the second switch is turned off, stopping the output of a low level, and the output interface returns to a high-impedance state.

[0032] In summary, the high / low level output switching circuit of this utility model is electrically connected between the main control chip and the output interface. By setting a first switching transistor connected to the high voltage end and a second switching transistor connected to ground, and the main control chip being connected to the first and second switching transistors respectively through a first delay circuit and a second delay circuit, the time difference between high and low level switching is staggered to ensure that a high level does not exist simultaneously with a low level during the switching process, thereby preventing short circuits and avoiding damage to circuit components. The first and second switching transistors are connected to the output interface to achieve high / low level output switching through the same interface.

[0033] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this utility model, and these modifications or substitutions should all be covered within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the scope of the claims.

Claims

1. A high / low level output switching circuit, characterized in that, The high / low level output switching circuit is electrically connected between the main control chip and the output interface, and includes a first delay circuit, a second delay circuit, a first switching transistor, and a second switching transistor. The main control chip is connected to the first delay circuit and the second delay circuit respectively. The first delay circuit is connected to the output interface through the first switching transistor, and the second delay circuit is connected to the output interface through the second switching transistor. The first switching transistor is connected to the high voltage terminal, and the second switching transistor is connected to ground.

2. The high / low level output switching circuit according to claim 1, characterized in that, The high / low level output switching circuit further includes a sixth switching transistor. The first end of the sixth switching transistor is connected to the main control chip and the first delay circuit, and the second end of the sixth switching transistor is connected to the main control chip and the second delay circuit.

3. The high / low level output switching circuit according to claim 2, characterized in that, The first switch is a PMOS transistor, and the second and sixth switches are both NMOS transistors.

4. The high / low level output switching circuit according to claim 3, characterized in that, The source of the first switching transistor is connected to the high-voltage terminal, and the drain of the first switching transistor is connected to the output interface via a fourth diode and a first fuse connected in series. The first input / output pin of the main control chip is connected to the gate of the first switching transistor via the first delay circuit.

5. The high / low level output switching circuit according to claim 4, characterized in that, The first delay circuit includes a 37th resistor, a 65th capacitor, a 4th resistor, a 27th switch, and a 57th resistor. The 27th switch is a transistor. The 37th resistor is connected in series with the 4th resistor. The first input / output pin of the main control chip is connected to the 37th resistor. The base of the 27th switch is electrically connected to the series node of the 37th resistor and the 4th resistor. The emitter of the 27th switch is grounded. The collector of the 27th switch is connected to the gate of the first switch via the 57th resistor. The first terminal of the 65th capacitor and the drain of the 6th switch are both electrically connected to the series node of the 37th resistor and the 4th resistor. The source of the 6th switch is grounded.

6. The high / low level output switching circuit according to claim 4, characterized in that, The source of the second switching transistor is grounded. The second input / output pin of the main control chip is connected to the gate of the second switching transistor after passing through the second delay circuit. The drain of the second switching transistor is connected to the cathode of the twelfth diode. The anode of the twelfth diode is electrically connected to the series node of the fourth diode and the first fuse, so that the second input / output pin of the main control chip is connected to the output interface through the second delay circuit and the second switching transistor, the twelfth diode, and the first fuse.

7. The high / low level output switching circuit according to claim 6, characterized in that, The second delay circuit includes a twenty-first diode, a sixty-sixth resistor, a sixty-seventh resistor, a thirty-eighth resistor, and a seventy-third capacitor. The sixty-sixth resistor is connected in series with the thirty-eighth resistor. The second input / output pin of the main control chip is connected to the sixty-sixth resistor. The gate of the second switching transistor is electrically connected to the series connection node of the sixty-sixth and thirty-eighth resistors. The sixty-seventh resistor is connected in series with the twenty-first diode and then in parallel with the sixty-sixth resistor. One end of the seventy-third capacitor is electrically connected to the connection node of the sixty-sixth resistor and the gate of the second switching transistor, and the other end of the seventy-third capacitor is grounded.

8. The high / low level output switching circuit according to claim 4, characterized in that, The second input / output pin of the main control chip is connected to the 39th and 40th resistors connected in series, and the gate of the sixth switch is electrically connected to the series node of the 39th and 40th resistors.

9. The high / low level output switching circuit according to claim 4, characterized in that, The source and gate of the first switching transistor are electrically connected in parallel by a sixth diode, a sixty-sixth capacitor, and a fifty-fourth resistor.

10. The high / low level output switching circuit according to claim 4, characterized in that, The output interface is electrically connected to the connection node of the first fuse, with the 84th grounding capacitor and the 51st grounding diode connected in parallel.

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