A phase-locked loop circuit, a chip and an electronic device

Abstract

The application provides a phase-locked loop circuit, a chip and an electronic device, and belongs to the technical field of electronics. The phase-locked loop circuit comprises a frequency discrimination module, a voltage-controlled oscillation output module, a frequency division module and a preset voltage adjustment module. The first input end of the frequency discrimination module is connected with the output end of the frequency division module, the second input end is used for receiving a reference clock signal, and the output end is used for outputting a frequency discrimination result between the reference clock signal and a feedback clock signal output by the frequency division module. The preset voltage adjustment module is used for outputting a preset voltage to the voltage-controlled oscillation output module according to the frequency discrimination result. The voltage-controlled oscillation output module is used for outputting a target oscillation signal based on the preset voltage. The input end of the frequency division module is connected with the output end of the voltage-controlled oscillation output module, and the feedback clock signal has the same frequency as the target oscillation signal. By using the application, the preset voltage of the phase-locked loop circuit can be adaptively adjusted, the accuracy of the preset voltage is improved, and the locking process is accelerated.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a phase-locked loop circuit, chip, and electronic device. Background Technology

[0002] A phase-locked loop (PLL) is a control system used to achieve automatic phase synchronization by adjusting the phase of the output signal to match the phase of the input signal.

[0003] A traditional phase-locked loop (PLL) circuit may include a phase detector, a loop filter, and a voltage-controlled oscillator (VCO). During operation, when a phase difference exists between the input and output signals, the phase detector generates an error voltage. After processing by the loop filter, this error voltage drives the VCO to adjust the frequency of the output signal, ultimately aligning the output signal's phase with the input signal. This process is repeated whenever a phase difference exists between the input and output signals to ensure the circuit maintains a stable phase-locked state under dynamic conditions.

[0004] Figure 1 The timing diagram of the locking process of a conventional phase-locked loop circuit is shown, including the frequency acquisition stage T1, the phase error elimination stage T2, and the locking stage T3. Figure 1 As can be seen, the frequency acquisition stage T1 has a significant impact on the locking process time. Before the locking process begins, a preset voltage can be input to the phase-locked loop circuit. This preset voltage has a certain frequency, making the initial frequency of the output signal close to the target frequency to be locked (e.g., ...). Figure 2 The preset voltage Vp1 shown corresponds to the frequency, thereby reducing the frequency acquisition stage T1 and accelerating the locking process.

[0005] However, the aforementioned preset voltage is usually a fixed voltage. Due to the influence of PVT (Process-Voltage-Temperature), different phase-locked loop circuits will ultimately lock onto different target frequencies. If the preset voltage causes a large error between the initial frequency and the target frequency of the output signal (e.g., ...), ... Figure 3 If the preset voltages Vp2 and Vp3 (corresponding to frequencies) are not adjusted, the locking acceleration effect will be worsened. Therefore, a phase-locked loop circuit is urgently needed that can adjust the preset voltage according to the target frequency to improve the accuracy of the preset voltage. Utility Model Content

[0006] To address the problems of existing technologies, this application provides a phase-locked loop (PLL) circuit, a chip, and an electronic device. The preset voltage of this PLL circuit can be adaptively adjusted, improving the accuracy of the preset voltage and accelerating the locking process. The technical solution is as follows: According to one aspect of this application, a phase-locked loop circuit is provided, the phase-locked loop circuit including a frequency discrimination module, a voltage-controlled oscillator output module, a frequency division module and a preset voltage adjustment module; The first input terminal of the frequency discrimination module is connected to the output terminal of the frequency divider module, the second input terminal is used to receive a reference clock signal, and the output terminal is used to output the frequency discrimination result between the reference clock signal and the feedback clock signal output by the frequency divider module. The preset voltage adjustment module is used to output a preset voltage to the voltage-controlled oscillator output module according to the frequency discrimination result; The voltage-controlled oscillator output module is used to output a target oscillation signal based on the preset voltage; The input terminal of the frequency divider module is connected to the output terminal of the voltage-controlled oscillator output module, and the feedback clock signal has the same frequency as the target oscillation signal.

[0007] According to another aspect of this application, a chip is provided that includes the above-described phase-locked loop circuit.

[0008] According to another aspect of this application, an electronic device is provided, including the phase-locked loop circuit described above.

[0009] In this application, the phase-locked loop circuit includes a frequency discrimination module, a voltage-controlled oscillator output module, a frequency divider module, and a preset voltage adjustment module. During the preset voltage configuration stage, the preset voltage adjustment module is connected to the loop. This module adaptively adjusts the preset voltage based on the reference clock signal, improving the accuracy of the preset voltage, significantly reducing the time consumed in the frequency acquisition stage, and accelerating the locking process. Attached Figure Description

[0010] Further details, features, and advantages of this application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which: Figure 1 A timing diagram illustrating the locking process of a conventional phase-locked loop circuit provided according to an exemplary embodiment of this application is shown. Figure 2 A timing diagram of a locking process based on a preset voltage, provided according to an exemplary embodiment of this application, is shown. Figure 3 A timing diagram of another locking process based on a preset voltage, provided according to an exemplary embodiment of this application, is shown; Figure 4 A schematic diagram of a phase-locked loop circuit provided according to an exemplary embodiment of this application is shown; Figure 5 A schematic diagram of another phase-locked loop circuit provided according to an exemplary embodiment of this application is shown; Figure 6A schematic diagram of a preset voltage adjustment module provided according to an exemplary embodiment of this application is shown; Figure 7 A schematic diagram of a gear selection submodule provided according to an exemplary embodiment of this application is shown; Figure 8 A schematic diagram of a preset voltage output submodule provided according to an exemplary embodiment of this application is shown; Figure 9 A schematic diagram of another preset voltage adjustment module provided according to an exemplary embodiment of this application is shown; Figure 10 A schematic diagram of yet another phase-locked loop circuit provided according to an exemplary embodiment of this application is shown; Figure 11 A schematic diagram of a frequency discrimination module provided according to an exemplary embodiment of this application is shown; Figure 12 A schematic diagram of a voltage-controlled oscillator output module provided according to an exemplary embodiment of this application is shown; Figure 13 A schematic diagram of a phase-locked loop circuit in the preset voltage configuration stage provided according to an exemplary embodiment of this application is shown; Figure 14 A schematic diagram of a phase-locked loop circuit for a general locking process provided according to an exemplary embodiment of this application is shown.

[0011] In the picture, 1. Frequency discrimination module; 11. Frequency discrimination unit; 12. Charge pump unit; 2. Voltage-controlled oscillator output module; 21. Loop filter unit; 22. Voltage-controlled oscillator unit; 3. Frequency divider module; 4. Preset voltage adjustment module; 41. Range selection submodule; 411. Counter unit; 412. Decoder unit; 42. Preset voltage output submodule; 421. Preset voltage generation unit; 43. Delay submodule; 5. First switch module; 6. Second switch module; 7. Third switch module. Detailed Implementation

[0012] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0013] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc., mentioned in this application are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0014] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0015] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0016] The names of the messages or information exchanged between multiple devices in the embodiments of this application are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0017] This application provides a phase-locked loop circuit that can be integrated into a chip or placed in an electronic device.

[0018] Reference Figure 4 The schematic diagram of the phase-locked loop (PLL) circuit shown includes a frequency discriminator module 1, a voltage-controlled oscillator (VCO) output module 2, a frequency divider module 3, and a preset voltage adjustment module 4. The input terminal of the preset voltage adjustment module 4 is connected to the output terminal of the frequency discriminator module 1, and its output terminal is connected to the input terminal of the VCO output module 2. The input terminal of the VCO output module 2 is connected to the output terminal of the preset voltage adjustment module 4, and its output terminal is connected to the input terminal of the frequency divider module 3.

[0019] The first input terminal of the frequency discrimination module 1 is connected to the output terminal of the frequency divider module 3, the second input terminal is used to receive the reference clock signal, and the output terminal is used to output the frequency discrimination result between the reference clock signal and the feedback clock signal output by the frequency divider module 3. The preset voltage adjustment module 4 is used to output a preset voltage to the voltage-controlled oscillator output module 2 based on the frequency discrimination result; Voltage-controlled oscillator output module 2 is used to output a target oscillation signal based on a preset voltage; The input terminal of frequency divider module 3 is connected to the output terminal of voltage-controlled oscillator output module 2, and the output terminal is used to output a feedback clock signal. The feedback clock signal is the same as the target oscillation signal, and the frequency of the reference clock signal is equal to the target frequency ultimately locked by the phase-locked loop circuit.

[0020] In one possible implementation, the frequency discrimination module 1, the voltage-controlled oscillator output module 2, and the frequency divider module 3 can perform a general locking process (i.e., including a frequency acquisition phase T1, a phase error elimination phase T2, and a locking phase T3). Before performing the general locking process, the preset voltage adjustment module 4 is connected to the loop.

[0021] When the phase-locked loop circuit starts working, the preset voltage adjustment module 4 generates an initial preset voltage and connects this initial preset voltage to the voltage-controlled oscillator output module 2. Driven by this initial preset voltage, the voltage-controlled oscillator output module 2 outputs a target oscillation signal with a corresponding frequency. The frequency divider module 3 receives the target oscillation signal, processes it, outputs a clock signal with the corresponding frequency, and feeds this clock signal back to the frequency discriminator module 1. For ease of explanation, this embodiment refers to the clock signal output by the frequency divider module 3 as the feedback clock signal. In the frequency discriminator module 1, the frequency of the feedback clock signal is compared with the frequency of the reference clock signal, and the corresponding frequency discrimination result is output. The preset voltage adjustment module 4 receives the frequency discrimination result, adjusts its output preset voltage according to the frequency discrimination result, and connects the adjusted preset voltage to the voltage-controlled oscillator output module 2. Thereafter, the above process is repeated until the frequency discrimination result output by the frequency discriminator module 1 meets a preset condition, such as the frequency of the feedback clock signal being greater than or equal to the frequency of the reference clock signal, indicating that the current preset voltage can make the frequency of the target oscillation signal close to or equal to the target frequency. This process can be called the preset voltage configuration stage.

[0022] Optional, refer to Figure 5 The schematic diagram of the phase-locked loop circuit shown may also include a first switch module 5. The first end of the first switch module 5 is connected to the output end of the frequency discrimination module 1, and the second end of the first switch module 5 is connected to the input end of the voltage-controlled oscillator output module 2.

[0023] The first switch module 5 is turned off during the preset voltage configuration phase and closed after the preset voltage configuration phase.

[0024] In one possible implementation, during the aforementioned preset voltage configuration stage, the first switch module 5 can be turned off, connecting the preset voltage adjustment module 4 to the loop. When the frequency discrimination result meets the preset conditions, the first switch module 5 can be turned off, forming a loop based on the frequency discrimination module 1, the voltage-controlled oscillator output module 2, and the frequency divider module 3, ending the aforementioned preset voltage configuration stage and entering the general locking process. Since the frequency of the target oscillation signal is equal to or close to the target frequency, the time consumed in the frequency acquisition stage T1 can be greatly reduced, accelerating the locking process.

[0025] Therefore, in this embodiment, the phase-locked loop (PLL) circuit may include a frequency discrimination module 1, a voltage-controlled oscillator (VCO) output module 2, a frequency divider module 3, and a preset voltage adjustment module 4. During the preset voltage configuration stage, the preset voltage adjustment module 4 is connected to the loop. Using the preset voltage adjustment module 4, the preset voltage is adaptively adjusted according to the reference clock signal, improving the accuracy of the preset voltage. Furthermore, regardless of how the PVT conditions change the target frequency of the PLL circuit, the adaptive preset voltage can take into account temperature and process fluctuations, reducing the impact of PVT conditions without the need for additional temperature sensors or other temperature detection circuits. Therefore, it exhibits excellent robustness and effectively accelerates locking over a wide temperature range.

[0026] Optional, refer to Figure 6 The schematic diagram of the preset voltage adjustment module shown indicates that the preset voltage adjustment module 4 may include a range selection submodule 41 and a preset voltage output submodule 42. The input terminal of the range selection submodule 41 is connected to the output terminal of the frequency discrimination module 1, and the output terminal is connected to the input terminal of the preset voltage output submodule 42. The input terminal of the preset voltage output submodule 42 is connected to the output terminal of the range selection submodule 41, and the output terminal is connected to the input terminal of the voltage-controlled oscillator output module 2.

[0027] The gear selection submodule 41 is used to output a gear selection signal to the preset voltage output submodule 42 based on the frequency discrimination result; The preset voltage output submodule 42 is used to output the preset voltage corresponding to the gear selection signal.

[0028] In one possible implementation, the gear selection submodule 41 can receive the frequency discrimination result output by the frequency discrimination module 1, process the frequency discrimination result, and output a corresponding gear selection signal. The preset voltage output submodule 42 can receive the gear selection signal and select the preset voltage corresponding to the gear selection signal for output.

[0029] Optional, refer to Figure 7The schematic diagram of the gear selection submodule shown indicates that the gear selection submodule 41 may include a counter unit 411 and a decoder unit 412. The input terminal of the counter unit 411 is connected to the output terminal of the frequency discrimination module 1, and the output terminal is connected to the input terminal of the decoder unit 412. The input terminal of the decoder unit 412 is connected to the output terminal of the counter unit 411, and the output terminal is connected to the input terminal of the preset voltage output submodule 42.

[0030] The counter unit 411 is used to output the counting result based on the frequency discrimination result to the decoder unit 412; The decoder unit 412 is used to output a digital code value based on the counting result as a gear selection signal.

[0031] In one possible implementation, the counter unit 412 can receive the frequency discrimination result output by the frequency discrimination module 1 and perform integration processing on the frequency discrimination result to obtain a counting result, for example, which can refer to the number of times the frequency of the feedback clock signal is less than the frequency of the reference clock signal. When the frequency discrimination result output by the frequency discrimination module 1 meets a preset condition, such as the frequency of the feedback clock signal being greater than or equal to the frequency of the reference clock signal, the counter unit 412 can stop counting.

[0032] The decoder unit 412 can receive the counting result and convert it into a digital code value as a gear selection signal, and transmit the digital code value to the preset voltage output submodule 42. After receiving the digital code value, the preset voltage output submodule 42 can select the corresponding preset voltage for output through the control of the digital code value.

[0033] Through the processing of the frequency discrimination module 1, counter unit 411, and decoder unit 412 described above, frequency-related information is converted into digital code values. Therefore, the circuit composed of the frequency discrimination module 1, counter unit 411, and decoder unit 412 can be called a "frequency-to-digital converter". Traditional phase-locked loop circuits are usually analog circuits, and the phase-locking time is usually on the order of milliseconds. The phase-locked loop circuit provided in this embodiment uses digital circuits, and the phase-locking time can be on the order of microseconds, which speeds up the locking time and improves the locking efficiency.

[0034] Optional, refer to Figure 8 The schematic diagram of the preset voltage output submodule shown shows that the preset voltage output submodule 42 may include multiple preset voltage generation units 421, each of which generates a different preset voltage.

[0035] In one possible implementation, by considering PVT fluctuations during circuit design, the minimum and maximum values ​​of the preset voltage can be determined. Typically, the minimum preset voltage ensures that the frequency of the feedback clock signal is lower than the frequency of the reference clock signal, thereby guaranteeing entry into the preset voltage configuration phase for adaptive adjustment of the preset voltage. The maximum preset voltage ensures that the frequency of the feedback clock signal is higher than the frequency of the reference clock signal, thereby guaranteeing the termination of the preset voltage configuration phase and entry into the normal locking process.

[0036] Based on the minimum and maximum values ​​of the preset voltages mentioned above, different levels can be set according to the accuracy required for actual applications, with each level corresponding to a different preset voltage. Furthermore, different preset voltage generation units 421 can generate the corresponding preset voltages. This embodiment does not limit the specific level settings or the circuit structure of the preset voltage generation unit 421.

[0037] Furthermore, each preset voltage can correspond to a different digital code value. After the preset voltage output submodule 42 receives the digital code value output by the decoder unit 412, it can select the corresponding preset voltage for output through the control of the digital code value.

[0038] Optional, refer to Figure 9 The schematic diagram of the preset voltage adjustment module shown is provided. The preset voltage adjustment module 4 may also include a delay submodule 43.

[0039] The input terminal of the delay submodule 43 is connected to the output terminal of the frequency discrimination module 1, and the output terminal is connected to the input terminal of the gear selection submodule 41.

[0040] In one possible implementation, a delay submodule 43 can be set after the frequency discrimination module 1, so that the frequency discrimination result of the frequency discrimination module 1 in the current clock can be transmitted to the gear selection submodule 41 in the next clock. Thus, in the next clock, the gear selection submodule 41 can receive the frequency discrimination result of the previous clock and perform the aforementioned gear selection to determine the frequency discrimination result of the current clock. That is to say, this embodiment can provide a successive approximation preset voltage determination and adjustment method.

[0041] Optional, refer to Figure 10 The schematic diagram of the phase-locked loop circuit shown may also include a second switch module 6 and a third switch module 7.

[0042] The first end of the second switch module 6 is connected to the output end of the frequency discrimination module 1, and the second end is connected to the input end of the preset voltage adjustment module 4. The second switch module 6 is closed during the preset voltage configuration stage and turned off after the preset voltage configuration stage. The first end of the third switch module 7 is connected to the output end of the preset voltage adjustment module 4, and the second end is connected to the input end of the voltage-controlled oscillation output module 2. The third switch module 7 is closed during the preset voltage configuration stage and is turned off after the preset voltage configuration stage.

[0043] In one possible implementation, when the phase-locked loop circuit starts working, the second switch module 6 and the third switch module 7 can be controlled to close, and the first switch module 5 can be turned off in combination with the above-mentioned control, so that the preset voltage adjustment module 4 can be connected to the loop.

[0044] When the above-mentioned preset voltage configuration stage ends, the second switch module 6 and the third switch module 7 can be turned off, and the first switch module 5 can be closed, so that the preset voltage adjustment module 4 will no longer be connected to the loop during the above-mentioned general locking process.

[0045] Optional, refer to Figure 11 The schematic diagram of the frequency discrimination module shown indicates that the frequency discrimination module 1 may include a frequency discrimination unit 11 and a charge pump unit 12.

[0046] The first input terminal of the frequency discrimination unit 11 is connected to the output terminal of the frequency divider module 3, the second input terminal is used to receive the reference clock signal, and the output terminal is connected to the input terminal of the charge pump unit 12. The output terminal of the charge pump unit 12 is connected to the input terminal of the preset voltage adjustment module 4.

[0047] The frequency discrimination unit 11 can be a phase and frequency detector (PFD), a frequency to voltage converter (FVC) based on switched capacitors, a frequency comparison circuit based on digital counting, etc. This embodiment does not limit the specific circuit structure of the frequency discrimination unit 11.

[0048] In one possible implementation, the frequency discrimination unit 11 can compare the frequency of the feedback clock signal with the frequency of the reference clock signal and output an initial frequency discrimination result. The charge pump unit 12 can receive this initial frequency discrimination result and convert it into a corresponding high or low level as the frequency discrimination result output by the frequency discrimination module 1. For example, a high level "1" in the frequency discrimination result can indicate that the frequency of the feedback clock signal is less than the frequency of the reference clock signal; a low level "0" in the frequency discrimination result can indicate that the frequency of the feedback clock signal is greater than or equal to the frequency of the reference clock signal.

[0049] Optional, refer to Figure 12 The schematic diagram of the voltage-controlled oscillator output module shown can be included in the voltage-controlled oscillator output module 2, which may include a loop filter unit 21 and a voltage-controlled oscillator unit 22.

[0050] The input terminal of the loop filter unit 21 is connected to the output terminal of the preset voltage adjustment module 4, and the output terminal is connected to the input terminal of the voltage-controlled oscillator unit 22. The output of the voltage-controlled oscillator unit 22 is connected to the input of the frequency divider module 3.

[0051] In one possible implementation, during the preset voltage configuration stage described above, the preset voltage output by the preset voltage adjustment module 4 can be transmitted to the loop filter unit 21 for filtering. Then, the filtered preset voltage can be used as a control voltage to control the voltage-controlled oscillator unit 22 to adjust the frequency of the target oscillation signal. After the frequency divider module 3 divides the target oscillation signal to obtain a feedback clock signal of the corresponding frequency, the frequency of the feedback clock signal is compared with the frequency of the reference clock signal by the frequency discriminator unit 11.

[0052] As a concrete example, Figure 13 A specific phase-locked loop (PLL) circuit is shown. In this PLL circuit, the counter unit 411 can be a 2-bit binary counter; the decoder unit 412 can be a 2-to-4 decoder, whose input is a 2-bit counting result and whose output is a 4-bit digital code value (c1, c2, c3, c4); the preset voltage includes 4 levels, namely V1 (corresponding to digital code value c1), V2 (corresponding to digital code value c2), V3 (corresponding to digital code value c3) and V4 (corresponding to digital code value c4); the preset voltage output submodule 42 includes multiple resistor units connected in series (corresponding to preset voltage generation unit 421), and each resistor unit obtains a different preset voltage through voltage division, which corresponds to different switches.

[0053] During the preset voltage configuration phase, the second switch module 6 and the third switch module 7 are closed, and the first switch module 5 is turned off.

[0054] Within the first clock cycle, the initial value of counter unit 411 is 00, decoder unit 412 outputs digital code value 0001, and c4 controls the corresponding switch to close, connecting the preset voltage V4 to loop filter unit 21. At this time, the frequency of the feedback clock signal CKNDIV after frequency division corresponding to the preset voltage V4 is less than the frequency of the reference clock signal CKREF, so charge pump unit 12 will output a high-level signal 1.

[0055] Within the second clock cycle, a high-level signal is transmitted to the counter unit 411 via the delay submodule 43. The counting result output by the counter unit 411 changes from 00 to 01. The decoder unit 412 then outputs the digital code value 0010. c3 controls the corresponding switch to close, connecting the preset voltage V3 to the loop filter unit 21. If the frequency discrimination unit 11 determines that the frequency of the feedback clock signal CKNDIV after frequency division corresponding to the preset voltage V3 is greater than or equal to the frequency of the reference clock signal CKREF, the charge pump unit 12 will output a low-level signal 0. When the output of the charge pump unit 12 is identified as 0, it indicates that the preset voltage V3 has reached a suitable value. The second switch module 6 and the third switch module 7 can be turned off, and the first switch module 5 can be closed, connecting the loop in the form of a traditional phase-locked loop circuit (e.g., ...). Figure 14 As shown), it enters the normal locking process.

[0056] If the frequency discrimination unit 11 determines that the frequency of the feedback clock signal after frequency division corresponding to the preset voltage V3 is less than the frequency of the reference clock signal, then the charge pump unit 12 will output a high-level signal 1. Within the third clock cycle, the high-level signal is transmitted to the counter unit 411 through the delay submodule 43. The counting result output by the counter unit 411 jumps from 01 to 10, then the decoder unit 412 outputs the digital code value 0100, and c2 controls the corresponding switch to close, connecting the preset voltage V2 to the loop filter unit 21. The subsequent processing is the same as that of the preset voltage V3, and will not be described again here.

[0057] In summary, during the preset voltage configuration stage, this phase-locked loop circuit can sequentially change the preset voltage in the order of V4, V3, V2, and V1, gradually approaching the appropriate preset voltage until the output of the charge pump unit 12 is 0, thus entering the normal locking process.

[0058] The embodiments of this application can achieve the following beneficial effects: The phase-locked loop circuit includes a frequency discrimination module, a voltage-controlled oscillator output module, a frequency divider module, and a preset voltage adjustment module. During the preset voltage configuration stage, the preset voltage adjustment module is connected to the loop. This module adaptively adjusts the preset voltage based on the reference clock signal, improving the accuracy of the preset voltage, significantly reducing the time consumed in the frequency acquisition stage, and accelerating the locking process.

[0059] Furthermore, regardless of how the target frequency of the phase-locked loop circuit changes due to PVT conditions, the adaptive preset voltage can take into account both temperature and process fluctuations. It can reduce the impact of PVT conditions without the need for additional temperature sensors or other temperature detection circuits, thus exhibiting excellent robustness and effectively accelerating locking over a wide temperature range.

[0060] An exemplary embodiment of this application also provides a chip including the phase-locked loop (PLL) circuit provided in the embodiments of this application. The PLL circuit includes a frequency discrimination module, a voltage-controlled oscillator (VCO) output module, a frequency divider module, and a preset voltage adjustment module. By connecting the preset voltage adjustment module to the loop during the preset voltage configuration stage, and using the preset voltage adjustment module to adaptively adjust the preset voltage according to the reference clock signal, the accuracy of the preset voltage is improved, the time consumed in the frequency acquisition stage is greatly reduced, and the locking process is accelerated.

[0061] An exemplary embodiment of this application also provides an electronic device, including the phase-locked loop (PLL) circuit provided in the embodiments of this application. The PLL circuit includes a frequency discrimination module, a voltage-controlled oscillator (VCO) output module, a frequency divider module, and a preset voltage adjustment module. By connecting the preset voltage adjustment module to the loop during the preset voltage configuration stage, and using the preset voltage adjustment module to adaptively adjust the preset voltage according to the reference clock signal, the accuracy of the preset voltage is improved, the time consumed in the frequency acquisition stage is greatly reduced, and the locking process is accelerated.

[0062] The phase-locked loop circuit, chip, and electronic device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A phase-locked loop circuit, characterized in that, The phase-locked loop circuit includes a frequency discrimination module, a voltage-controlled oscillator output module, a frequency divider module, and a preset voltage adjustment module; The first input terminal of the frequency discrimination module is connected to the output terminal of the frequency divider module, the second input terminal is used to receive a reference clock signal, and the output terminal is used to output the frequency discrimination result between the reference clock signal and the feedback clock signal output by the frequency divider module. The preset voltage adjustment module is used to output a preset voltage to the voltage-controlled oscillator output module according to the frequency discrimination result; The voltage-controlled oscillator output module is used to output a target oscillation signal based on the preset voltage; The input terminal of the frequency divider module is connected to the output terminal of the voltage-controlled oscillator output module, and the feedback clock signal has the same frequency as the target oscillation signal.

2. The phase-locked loop circuit according to claim 1, characterized in that, The phase-locked loop circuit further includes a first switching module, the first end of which is connected to the output end of the frequency discrimination module, and the second end of which is connected to the input end of the voltage-controlled oscillator output module. The first switch module is turned off during the preset voltage configuration phase and closed after the preset voltage configuration phase.

3. The phase-locked loop circuit according to claim 1, characterized in that, The preset voltage adjustment module includes a gear selection submodule and a preset voltage output submodule; The gear selection submodule is used to output a gear selection signal to the preset voltage output submodule based on the frequency discrimination result; The preset voltage output submodule is used to output the preset voltage corresponding to the gear selection signal.

4. The phase-locked loop circuit according to claim 3, characterized in that, The gear selection submodule includes a counter unit and a decoder unit; The counter unit is used to output a counting result based on the frequency discrimination result to the decoder unit; The decoder unit is used to output a digital code value based on the counting result as the gear selection signal.

5. The phase-locked loop circuit according to claim 3, characterized in that, The preset voltage output submodule includes multiple preset voltage generation units, each of which generates a different preset voltage.

6. The phase-locked loop circuit according to claim 3, characterized in that, The preset voltage adjustment module also includes a delay submodule; The input terminal of the delay submodule is connected to the output terminal of the frequency discrimination module, and the output terminal is connected to the input terminal of the gear selection submodule.

7. The phase-locked loop circuit according to claim 1, characterized in that, The phase-locked loop circuit also includes a second switching module and a third switching module; The first terminal of the second switching module is connected to the output terminal of the frequency discrimination module, and the second terminal is connected to the input terminal of the preset voltage adjustment module. The second switching module is closed during the preset voltage configuration phase and closed after the preset voltage configuration phase. The first end of the third switch module is connected to the output end of the preset voltage adjustment module, and the second end is connected to the input end of the voltage-controlled oscillation output module. The third switch module is closed during the preset voltage configuration phase and closed after the preset voltage configuration phase.

8. The phase-locked loop circuit according to claim 1, characterized in that, The frequency discrimination module includes a frequency discrimination unit and a charge pump unit; The first input terminal of the frequency discrimination unit is connected to the output terminal of the frequency divider module, the second input terminal is used to receive the reference clock signal, and the output terminal is connected to the input terminal of the charge pump unit. The output terminal of the charge pump unit is connected to the input terminal of the preset voltage adjustment module.

9. The phase-locked loop circuit according to claim 1, characterized in that, The voltage-controlled oscillator output module includes a loop filter unit and a voltage-controlled oscillator unit; The input terminal of the loop filter unit is connected to the output terminal of the preset voltage adjustment module, and the output terminal is connected to the input terminal of the voltage-controlled oscillator unit. The output terminal of the voltage-controlled oscillator unit is connected to the input terminal of the frequency divider module.

10. A chip, characterized in that, Includes the phase-locked loop circuit as described in any one of claims 1-9.

11. An electronic device, characterized in that, Includes the phase-locked loop circuit as described in any one of claims 1-9.

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