A multi-channel voice over internet protocol (VoIP) voice processing device based on hardware clock synchronization

Abstract

The utility model provides a kind of multi-channel VoIP voice processing device based on hardware clock synchronization, it is related to voice communication equipment technical field, device includes VPX case, VPX backplane, main control panel, at least one multi-channel voice processing board, high-precision clock synchronization board and power board, VPX backplane is fixedly installed in the inside of the VPX case, and clock synchronization bus, high-speed data bus, power bus are integrated on VPX backplane;Main control panel, multi-channel voice processing board, high-precision clock synchronization board and power board are electrically connected with VPX backplane by VPX connector.The utility model solves the existing multi-channel VoIP voice processing device in one-to-many voice communication scene, due to lack of hardware level global clock synchronization mechanism, leading to the technical problems of voice sampling asynchronization between multi-channel cross board card, timing deviation is big, interface expandability is poor and system reliability is insufficient.

Description

Technical Field

[0001] This utility model relates to the field of voice communication equipment technology, and in particular to a multi-channel VoIP voice processing device based on hardware clock synchronization. Background Technology

[0002] With the widespread application of IP-based communication technology in professional communication fields, VoIP (Voice over IP) has become the mainstream voice carrier in dispatch communication, emergency communication, and industrial communication due to its advantages such as flexible deployment, long transmission distance, and convenient service integration. In a one-to-many voice communication system, a master control node is usually required to simultaneously complete the synchronous acquisition, processing, mixing, encoding, IP encapsulation, and connection and synchronous playback of multiple voice signals with E1 digital trunks; this places stringent requirements on the channel consistency, time synchronization accuracy, operational stability, interface compatibility, and environmental adaptability of the equipment.

[0003] Currently, traditional multi-channel VoIP voice processing devices mainly suffer from the following technical problems in one-to-many application scenarios: First, the multi-channel synchronization capability is weak, and the timing deviation across boards is large. Traditional equipment mostly uses local independent clocks, and there is a lack of a unified clock and synchronization mechanism between channels and boards. After long-term operation, each channel is prone to accumulated clock drift and phase deviation, which leads to problems such as asynchronous sampling of multiple voice channels, voice misalignment, mixing noise, and echo suppression failure in one-to-many calls, seriously affecting voice clarity and system availability.

[0004] Second, time synchronization relies on software implementation, which lacks accuracy and stability. Existing devices mostly use software timestamps or the common Network Time Protocol (NTP) for synchronization, which has limited accuracy and is easily affected by processor load fluctuations, network congestion, and software scheduling delays. In complex network environments such as vehicles and the field, voice stuttering, interruptions, and excessively high latency will frequently occur, making it difficult to meet the requirements of high real-time performance and high reliability in professional communication scenarios.

[0005] Third, the lack of a hardware-level global clock mechanism leads to a decrease in synchronization performance after expansion. Traditional devices do not have dedicated high-precision clock synchronization hardware and global clock distribution circuits, so the synchronization signal cannot stably cover all boards. When users need to expand voice channels or increase the number of boards, it is difficult to guarantee the synchronization consistency between boards, which severely limits the system's scalability and cannot meet the expansion needs of large-scale scheduling.

[0006] Fourth, the entire voice processing chain lacks a unified time base for scheduling. The acquisition, encoding, transmission, and playback of voice are mostly triggered by local counters, lacking a synchronous scheduling mechanism with absolute hardware timestamps. This results in weak buffer management and jitter resistance, making it difficult to maintain continuous stability of one-to-many voice communication in complex network environments.

[0007] Fifth, the interface types are limited and compatibility with existing networks is poor. Most traditional equipment only supports analog voice interfaces and lacks standard E1 digital trunk interfaces, making it impossible to directly connect to existing TDM transmission networks and traditional dispatching and switching networks. When implementing projects, additional protocol conversion equipment is required, which increases deployment costs and introduces additional fault nodes.

[0008] In summary, existing multi-channel VoIP voice processing devices cannot simultaneously meet the comprehensive requirements of high-precision hardware time synchronization, multi-channel cross-board collaboration, E1 digital trunk compatibility, global clock distribution, end-to-end synchronous scheduling, and high-reliability architecture in one-to-many voice communication scenarios. There is an urgent need for a multi-channel VoIP voice processing device based on hardware-level global clock synchronization that can simultaneously support multiple analog voice channels and E1 digital trunks, in order to improve the performance of professional communication and command and dispatch systems. Utility Model Content

[0009] To address the aforementioned problems, this utility model provides a multi-channel VoIP voice processing device based on hardware clock synchronization. This device solves the technical problems of existing multi-channel VoIP voice processing devices in one-to-many voice communication scenarios, which suffer from a lack of hardware-level global clock synchronization mechanism, resulting in asynchronous voice sampling, large timing deviations, poor interface scalability, and insufficient system reliability across multiple channels and boards.

[0010] This utility model provides a multi-channel VoIP voice processing device based on hardware clock synchronization. The device includes a VPX chassis, a VPX backplane, a main control board, at least one multi-channel voice processing board, a high-precision clock synchronization board, and a power supply board. The VPX backplane is fixedly installed inside the VPX chassis, and the VPX backplane integrates a clock synchronization bus, a high-speed data bus, and a power bus. The main control board, the multi-channel voice processing board, the high-precision clock synchronization board, and the power board are all electrically connected to the VPX backplane via VPX connectors; The main control board communicates and interconnects with the multi-channel voice processing board through the high-speed data bus, and is used to realize voice registration, call control and routing scheduling. The multi-channel voice processing board is used to synchronously acquire, convert analog to digital, encode, decode, and mix multiple analog voice signals or E1 digital voice signals under the drive of the audio sampling clock signal and the frame synchronization signal. The high-precision clock synchronization board is used to generate a unified audio sampling clock signal and frame synchronization signal, and transmits them to the main control board and each of the multi-channel voice processing boards respectively through the clock synchronization bus. The power board is used to provide isolated operating power to each board.

[0011] Furthermore, the main control board includes an Ethernet switching module, a PHY module, a main processor, an FPGA, an MCU, and a clock management module; the Ethernet switching module, PHY module, MCU, and clock management module on the main control board are all connected to the VPX connector; and the Ethernet switching module, PHY module, main processor, and FPGA are connected in sequence; the clock management module is connected to all functional modules on the main control board; wherein, the input terminal of the clock management module is electrically connected to the clock synchronization bus, and is used to distribute the received signals from the clock synchronization bus to each module on the main control board.

[0012] Furthermore, the multi-channel voice processing board includes: a VPX connector, a main processor, a VoIP module, an FPGA module, a multi-channel audio codec chip, an analog voice interface module, and a clock management module; the main processor, the analog voice interface module, and the clock management module on the multi-channel voice processing board are all connected to the VPX connector; and the main processor, VoIP module, FPGA module, multi-channel audio codec chip, and analog voice interface module are connected in sequence; the clock management module is connected to all functional modules on the main control board; wherein, the input terminal of the clock management module is electrically connected to the clock synchronization bus, and is used to receive the audio sampling clock signal and the frame synchronization signal and distribute them to the various functional modules in the multi-channel voice processing board.

[0013] Furthermore, the analog voice interface module also includes an analog telephone interface and an E1 digital trunk interface; the analog telephone interface integrates a power supply circuit, a ringing circuit, an overcurrent protection circuit, and an overvoltage protection circuit; the E1 digital trunk interface integrates a line interface unit, a clock recovery circuit, and an HDB3 codec circuit.

[0014] Furthermore, the multi-channel voice processing board also includes an E1 data transceiver module, which internally includes a clock synthesis submodule. The input of the clock synthesis submodule is electrically connected to the clock synchronization bus and is used to convert the audio sampling clock signal into a 2.048MHz operating clock required by the E1 digital trunk interface. The output of the clock synthesis submodule is electrically connected to the clock input of the E1 digital trunk interface and is used to provide a synchronization clock for the transmission and reception of the E1 line.

[0015] Furthermore, the high-precision clock synchronization board includes a VPX connector, a main processor, a clock processing module, a BeiDou timing module, and an FPGA module; the main processor, clock processing module, BeiDou timing module, and FPGA module on the high-precision clock synchronization board are all connected to the VPX connector; and the BeiDou timing module, clock processing module, FPGA module, and main processor are connected in sequence.

[0016] Furthermore, the high-precision clock synchronization board is configured to support at least one of the following synchronization modes: BeiDou dual-mode synchronization, external wired synchronization, and local timekeeping synchronization. The output audio sampling clock signal is 8.192MHz, and the frame synchronization signal is 8kHz.

[0017] Furthermore, the power board is a wide-input isolated DC-DC power module or a wide-input AC-DC power module; the input voltage range of the DC-DC power module is 18V-36V, and the input voltage range of the AC-DC power module is AC85V-265V; the power board outputs multiple isolated power supplies and has the functions of overcurrent protection, overvoltage protection, undervoltage protection and reverse connection protection.

[0018] Furthermore, the device also includes a heat dissipation module; the heat dissipation module adopts a combined structure of conductive cooling and air cooling, the VPX chassis is equipped with a temperature-controlled fan, and the VPX backplate is equipped with heat dissipation fins.

[0019] Furthermore, multiple devices are connected to the management and dispatch computer via an Ethernet ring network, and each device establishes a voice communication connection with the user terminal through an analog telephone interface or an E1 digital trunk interface to realize remote dispatch applications.

[0020] Overall, this utility model provides a multi-channel VoIP voice processing device based on hardware clock synchronization, which achieves the following beneficial effects compared with the prior art: (1) This invention sets up a high-precision clock synchronization board, which generates a unified audio sampling clock signal and frame synchronization signal. These signals are then distributed to the main control board and each multi-channel voice processing board via the clock synchronization bus on the VPX backplane, ensuring that all boards and channels operate under the same hardware clock source. Compared with existing solutions that rely on software synchronization or local independent clocks, this invention fundamentally eliminates clock drift and phase deviation between multiple channels and between boards, ensuring precise alignment of multi-channel voice acquisition, mixing, and playback, and significantly improving the quality of one-to-many voice communication.

[0021] (2) The multi-channel voice processing board of this utility model integrates both analog telephone interfaces and E1 digital trunk interfaces. Furthermore, the clock synthesis submodule within the E1 transceiver module can directly reuse the global audio sampling clock, converting it into the working clock required by the E1 interface. This achieves unified synchronization between the analog voice channel and the E1 digital trunk channel under the same hardware clock system. Compared to existing devices that only support a single interface type, this application can directly interface with analog equipment and traditional TDM networks without requiring additional conversion equipment, thus reducing engineering deployment and modification costs.

[0022] (3) The high-precision clock synchronization board of this utility model supports multiple synchronization modes, including GPS / BeiDou dual-mode synchronization, 1PPS external synchronization, E1 line synchronization, and IEEE1588 Ethernet synchronization, and can achieve automatic and seamless switching between multiple modes. In scenarios without an external clock source, the high-precision clock synchronization board can enter a local timekeeping mode based on a high-stability temperature-controlled crystal oscillator to maintain accurate timing for a long time. Compared with the existing technology that relies on a single synchronization source, this application can maintain stable high-precision synchronization performance in different application environments, and its environmental adaptability is significantly enhanced.

[0023] (4) This utility model achieves global clock distribution through a dedicated clock synchronization bus on the VPX backplane, enabling all boards to obtain a consistent synchronization clock signal. When the device needs to add multiple voice processing boards to expand the number of channels, the newly added boards are also connected to the same clock bus, and the synchronization performance will not decrease due to the increase in the number of boards. Compared with the existing technology where it is difficult to guarantee synchronization consistency after expansion, this application can meet the needs of large-scale, multi-scenario voice communication.

[0024] (5) This utility model adopts a standard VPX modular ruggedized architecture, and each board supports hot-swapping, which facilitates on-site maintenance and system expansion. At the same time, with the heat dissipation module combining conductive cooling and air cooling, wide voltage isolated power supply and wide temperature design, the device can operate stably for a long time in a temperature range of -40℃ to +85℃ and in vibration environments such as vehicle-mounted and airborne, meeting the high reliability requirements of professional communication equipment. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. The drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the device structure principle of a multi-channel VoIP voice processing device based on hardware clock synchronization provided by this utility model; Figure 2 This is a schematic diagram of the main control board of a multi-channel VoIP voice processing device based on hardware clock synchronization provided by this utility model; Figure 3 This is a schematic diagram of the structure of a multi-channel voice processing board of a multi-channel VoIP voice processing device based on hardware clock synchronization provided by this utility model; Figure 4 This is a schematic diagram of the structure of a high-precision clock synchronization board for a multi-channel VoIP voice processing device based on hardware clock synchronization provided by this utility model; Figure 5 This is a schematic diagram of a multi-channel VoIP voice processing device based on hardware clock synchronization applied to a remote dispatching system, provided by this utility model. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0028] It should be noted that in the description of the embodiments of this utility model, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a method, step, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to the method, step, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of additional identical elements in the method, step, or apparatus that includes that element.

[0029] With the rapid development of communication technology, VoIP (Voice over IP) has become an important component of modern communication systems, widely used in telecommunications, enterprise communications, multimedia communications, and other fields. VoIP technology significantly reduces communication costs and improves communication efficiency by digitizing voice signals and transmitting them over IP networks.

[0030] To address the technical problems of existing multi-channel VoIP voice processing devices in one-to-many voice communication scenarios, such as asynchronous voice sampling, large timing deviations, poor interface scalability, and insufficient system reliability due to the lack of a hardware-level global clock synchronization mechanism, this invention provides a multi-channel VoIP voice processing device based on hardware clock synchronization. The core of this invention lies in solving the synchronization problem in VoIP multi-channel communication with a complete hardware solution. Starting from the lowest-level clock source, it constructs a high-precision, highly reliable, and highly scalable voice processing platform through hardware-level clock distribution, global absolute timestamp scheduling, and unified synchronization across all interfaces. It is particularly suitable for one-to-many centralized voice communication scenarios with extremely high requirements for real-time performance and reliability, such as command and dispatch, emergency communication, and industrial communication.

[0031] Specifically, such as Figure 1 As shown, the device includes a VPX chassis, a VPX backplane, a main control board, at least one multi-channel voice processing board, a high-precision clock synchronization board, and a power supply board.

[0032] The VPX backplane is fixedly installed inside the VPX chassis, and the VPX backplane integrates a clock synchronization bus, a high-speed data bus, and a power bus. The main control board, multi-channel voice processing board, high-precision clock synchronization board, and power board are all electrically connected to the VPX backplane via VPX connectors. The main control board communicates and interconnects with the multi-channel voice processing board via a high-speed data bus to realize voice registration, call control and routing scheduling; The multi-channel voice processing board is used to synchronously acquire, convert analog to digital, encode, decode, and mix multiple analog voice signals or E1 digital voice signals under the drive of the audio sampling clock signal and the frame synchronization signal. The high-precision clock synchronization board is used to generate a unified audio sampling clock signal and frame synchronization signal, and transmits them to the main control board and each multi-channel voice processing board respectively via the clock synchronization bus. The power board is used to provide isolated operating power to each board.

[0033] like Figure 1As shown, the VPX chassis of this device integrates a main control board, multiple multi-channel voice processing boards, a high-precision clock synchronization board, and a power supply board. The interconnection and global clock synchronization between the boards are achieved through the VPX backplane. The overall architecture can be subdivided into a service interface layer, a board-level processing layer, a backplane bus layer, and a basic support layer.

[0034] It should be noted that the VPX chassis can use the 3U standard VPX chassis, which is made of aluminum alloy. It is sturdy, lightweight, and has good heat dissipation performance. It also has good vibration and shock resistance, making it suitable for use in harsh environments such as vehicles and aircraft.

[0035] The service interface layer consists of various external service and auxiliary interfaces, which may include network interfaces, digital voice interfaces, analog voice interfaces, satellite time synchronization interfaces, power input interfaces, and other types of interfaces.

[0036] Network interfaces, such as eight gigabit Ethernet ports and two 100 Mbps Ethernet ports, are mainly used for data interaction between the device and external IP networks (such as Ethernet ring networks and management and scheduling computers), carrying the transmission and reception of VoIP voice data packets, system configuration, and status queries.

[0037] Digital voice interfaces, such as two sets of E1 digital trunk interfaces, are used to connect to traditional TDM-based digital voice networks, enabling 2M line trunk communication with PBX or PDN networks.

[0038] Analog voice interface, such as 2 sets of analog voice interfaces, each set supports 8 analog voice channels, for a total of 16 analog voice inputs and outputs, for direct connection to conventional analog telephones or fax terminals.

[0039] Satellite timing interfaces, such as the BeiDou antenna interface, are used to receive BeiDou satellite signals or GPS satellite signals, providing the system with a high-precision absolute time reference and a 1PPS pulse signal per second.

[0040] The power input interface provides two power supply modes: AC220V AC input and DC24V DC input, meeting the AC / DC power supply needs of different application scenarios such as vehicle-mounted, airborne, and fixed stations.

[0041] The main control board, multi-channel voice processing board, high-precision clock synchronization board, and power board, among other core functional boards, are all plugged into the VPX backplane via VPX connectors and electrically connected to the VPX backplane.

[0042] The main control board serves as the control center of the device, responsible for VoIP call control, routing scheduling, protocol conversion, and the status monitoring and network management response of the entire system. The main control board interacts with other boards at high speed through the high-speed data bus on the VPX backplane.

[0043] Multi-channel voice processing boards, such as Multi-channel Voice Processing Board #1 to Multi-channel Voice Processing Board #8, each board is responsible for specific voice acquisition, analog-to-digital conversion (A / D), VoIP encoding and decoding, mixing processing, and time-slot switching of E1 / TDM signals. The parallel operation of multiple voice processing boards enables the device to support the access and processing of a massive number of voice channels.

[0044] The high-precision clock synchronization board is the core of the entire device's time synchronization. It integrates a phase-locked loop, a temperature-controlled crystal oscillator, and a BeiDou time synchronization module. It is responsible for generating and distributing a globally unified audio sampling clock and frame synchronization signal, ensuring that all boards work under the same hardware clock domain.

[0045] The power board is responsible for converting the external AC220V or DC24V power supply into isolated low-voltage DC power required by various boards and the VPX backplane, and has overcurrent, overvoltage, undervoltage and reverse connection protection functions.

[0046] The VPX backplane is fixedly mounted inside the VPX chassis, conforms to the OpenVPX VITA 65 standard, integrates multiple slots and physical buses, supports hot-swapping of 3U VPX boards, and is key to achieving hardware-level synchronization and high-speed data exchange, as well as facilitating system expansion and field maintenance. Specifically, it may include one system slot for inserting the main control board, multiple service slots for inserting multi-channel voice processing boards, one clock synchronization slot for inserting a high-precision clock synchronization board, and one power supply slot for inserting the power supply board.

[0047] The VPX backplane includes: clock synchronization bus, high-speed data bus, and power bus.

[0048] The clock synchronization bus is a dedicated hardware clock synchronization bus, typically an LVDS differential signal. The high-precision clock synchronization board distributes a unified global clock signal to the main control board and all multi-channel voice processing boards through the clock synchronization bus, thus solving the problem of asynchronous voice sampling across multiple channels and boards at the physical layer.

[0049] The high-speed data bus establishes a low-latency, high-bandwidth data channel between the main control board and multiple voice processing boards for real-time transmission of large amounts of voice data packets, control signals, and status information. For example, gigabit Ethernet switching buses (such as SGMII) and PCIe Gen3 high-speed communication buses ensure that voice data exchange and mixing scheduling can be completed quickly between the boards, thereby supporting concurrent processing and stable communication of multiple VoIP voice channels.

[0050] The power bus is a dedicated line for transmitting electrical energy. It is used to distribute the multi-channel isolated DC power (such as 3.3V and 12V) output from the power board to various boards such as the main control board, multi-channel voice processing board, and high-precision clock synchronization board. Through the power bus, each board can obtain a stable power supply without an independent external power supply, thereby simplifying system wiring and improving power supply reliability.

[0051] In addition, the VPX backplane also includes an I²C control bus, which serves as a system management bus for basic control information exchange between boards, board presence detection, temperature acquisition, and power status monitoring.

[0052] The core working principle of this device is as follows: using a high-precision clock synchronization board as the hardware-level time reference source, and directly connecting each board through the clock synchronization bus on the VPX backplane, a unified audio sampling clock signal and frame synchronization signal are distributed to all boards, constructing a hardware-level high-precision time synchronization architecture covering all boards, multiple analog voice channels, and E1 interfaces. This architecture allows the main control board and all multi-channel voice processing boards to share the same clock source at the physical level, completely eliminating the jitter and drift caused by traditional software synchronization, and realizing one-to-many synchronous acquisition, processing, and playback of voice signals; at the same time, through the high-speed data bus, combined with the parallel processing capabilities of the multi-channel voice processing boards, low-latency, high-fidelity processing and scheduling of massive voice channels under a unified timing is achieved.

[0053] The main control board is mounted in the system slot and electrically connected to the VPX backplane via a VPX connector. As one example, such as... Figure 2 As shown, the main control board includes a VPX connector, an Ethernet switching module, a PHY module, a main processor, an FPGA, an MCU, and a clock management module. The Ethernet switching module, PHY module, MCU, and clock management module on the main control board are all connected to the VPX connector; and the Ethernet switching module, PHY module, main processor, and FPGA are connected sequentially. The clock management module is connected to all functional modules on the main control board. The input terminal of the clock management module is electrically connected to the clock synchronization bus, used to distribute signals received from the clock synchronization bus to the various modules on the main control board. The various modules on the main control board are interconnected through physical buses and signal lines, jointly realizing voice data routing and scheduling, protocol processing, system management, and high-precision clock synchronization.

[0054] The VPX connector on the main control board serves as the sole connection between the main control board and the VPX backplane, as well as the external physical world. It includes multiple interfaces responsible for transmitting power, Ethernet data, clock signals, and system management signals. The first interface connects to the onboard power module, providing -12V DC power. The second interface connects to the Ethernet switching module, providing external signals from eight Gigabit Ethernet ports and two 100Mbps Ethernet ports. The third interface connects to the clock management module, receiving signals from the clock synchronization bus on the VPX backplane. The fourth interface connects to the MCU, providing I / O signals. 2 C controls the signals of the bus.

[0055] The Ethernet switching module on the main control board serves as the onboard data forwarding hub, providing multiple external Ethernet interfaces, such as eight Gigabit and two 100Mbps, and handling high-speed internal data exchange. The external interfaces of the Ethernet switching module are brought out via VPX connectors, and internally connected to four PHY modules via four QSGMII (Quad Serial Gigabit Media Independent Interface) buses, enabling the transmission and reception of four Gigabit physical layer signals. Simultaneously, the Ethernet switching module is also connected to the main processor via an MDIO (Management Data Input / Output) bus for configuring and querying the status of the Ethernet switching chip.

[0056] The PHY module on the main control board is an Ethernet physical layer interface chip, used to drive the Ethernet physical layer interface, convert the digital signals output by the Ethernet switching module into transmittable analog signals (transmit), and convert the received analog signals back into digital signals (receive). Figure 2 The system is configured with four PHY modules, each corresponding to eight Gigabit Ethernet ports, with each PHY typically handling two ports. One end of each PHY module is connected to the Ethernet switching module via a QSGMII bus; the other end is connected to the VPX backplane or external interface via an SGMII bus.

[0057] The main processor on the main control board is the core control unit, running an embedded operating system. It is responsible for voice service registration, call control, routing and scheduling logic, network protocol stack processing, and interaction with external management and scheduling computers. The main processor manages the Ethernet switching module via the MDIO bus; it performs high-speed data exchange and control command issuance with the FPGA via the L1O (Local I / O) bus; furthermore, it can have bidirectional control and status interaction with the MCU. For example, the main processor can be a quad-core embedded processor, compatible with the ARM v8 architecture, configured with DDR4 memory and eMMC flash memory, running an embedded Linux operating system, and equipped with SIP, RTP, and RTCP protocol stacks to realize voice registration, call control, routing and scheduling, channel management, status monitoring, and remote configuration.

[0058] The FPGA (Field-Programmable Gate Array) on the main control board is responsible for high-speed data processing, including rapid encapsulation / decapsulation of VoIP packets, real-time mixing of multiple voice streams, timestamping (TDM over IP), and high-speed data synchronization with the multi-channel voice processing board. The FPGA connects to the main processor via the L1O bus, enabling data interaction; it connects to the Ethernet switching module via 16 SGMII buses, achieving high-speed throughput of massive voice data; and it obtains a precise global operating clock through the clock management module.

[0059] The MCU (microcontroller) on the main control board is responsible for low-level board management, including power monitoring, temperature monitoring, board presence detection, fault alarms, I2C bus management, and system reset control. This is achieved through the I / O pins on the VPX connector. 2 The C bus connects to the VPX backplane, reporting board status and receiving configuration commands, as well as reset signals from the VPX connector. Additionally, it can connect to the main processor to report underlying hardware status.

[0060] The clock management module on the main control board is responsible for receiving the external global clock, performing frequency multiplication, division, and phase locking to generate the precise operating clocks required by various modules within the board. The input of the clock management module connects to the VPX connector, receiving the global clock signal and synchronization clock signal from the VPX backplane; the output generates various clocks on the main control board and distributes them to various modules within the main control board, including the Ethernet switching module, PHY module, main processor, FPGA, and MCU. The global clock signal is a global reference clock (25MHz clock) generated by a high-precision clock synchronization board and distributed via the backplane. The clock management module imports the 25MHz global clock from the VPX backplane, providing a precise timing reference for the entire main control board. This ensures strict clock synchronization with other boards during multi-channel VoIP voice processing, thereby guaranteeing low-latency, high-fidelity voice transmission.

[0061] In another embodiment, the main control board also includes a power module. The power module provides multi-domain isolated power to the main control board, converting the -12V high-voltage DC power introduced through the VPX connector into the operating voltages required by various circuits within the board (including the Ethernet switching module, PHY module, main processor, FPGA, MCU, and clock management module, etc.), such as 3.3V, 1.8V, and 1.0V. The input terminal of the power module is connected to the -12V pin of the VPX connector; the output terminal is connected to the power input terminals of all functional modules within the board.

[0062] In addition, the main control board can also be equipped with a watchdog circuit, an RS422 debugging interface and status indicator lights to ensure stable operation of the device in an unattended environment.

[0063] The multi-channel voice processing board is a service expansion board installed in the service slot and electrically connected to the VPX backplane via a VPX connector. The multi-channel voice processing board features a modular and scalable structure, designed based on the VPX standard. Each voice processing board integrates multiple functional modules, including core processing, voice encoding / decoding, digital trunk interface, clock management, and low-level control. These modules include a main processor, DDR4 memory, Nor Flash, eMMC storage disk, FPGA, multi-channel audio codec chip, VoIP module, PHY module, voice interface circuit, level conversion circuit, protection circuit, E1 transceiver module, power supply module, and MCU module. Through the VPX connector, it interconnects with the VPX backplane and external interfaces, enabling synchronous processing and IP-based conversion of analog and E1 digital voice.

[0064] As an example, such as Figure 3 As shown, the multi-channel voice processing board includes: a VPX connector, a main processor, a VoIP module, an FPGA module, a multi-channel audio codec chip, an analog voice interface module, and a clock management module. The main processor, analog voice interface module, and clock management module on the multi-channel voice processing board are all connected to the VPX connector. The main processor, VoIP module, FPGA module, multi-channel audio codec chip, and analog voice interface module are connected in sequence. The clock management module is connected to all functional modules on the main control board. The input terminal of the clock management module is electrically connected to the clock synchronization bus, which is used to receive the audio sampling clock signal and frame synchronization signal and distribute them to the various functional modules in the multi-channel voice processing board.

[0065] The VPX connector on the multi-channel voice processing board serves as the physical interface between the multi-channel voice processing board and the VPX backplane. The first end is electrically connected to the VPX backplane, and the second end includes multiple interfaces that are electrically connected to the main processor, FPGA module, clock management module, and power module within the board, respectively, for transmitting power, high-speed data, clock signals, and I / O signals. 2C control signals. The first interface connects to the onboard power module, providing a -12V DC power supply; the second interface connects to the main processor, bringing out the SGMII 1 and SGMII 2 high-speed data buses, and connecting them to Ethernet switching circuitry; the third interface, such as a voice interface and an E1 interface, connects to the analog voice interface module and the E1 data transceiver module; the fourth interface connects to the clock management module, receiving signals from the clock synchronization bus on the VPX backplane; the fifth interface connects to the MCU, receiving I... 2 C controls the signals of the bus.

[0066] The main processor on the multi-channel voice processing board is the control core of the board, responsible for board-level task scheduling. The first end connects to two PHY modules via the RGMII bus. Both PHY modules are simultaneously connected to the VPX connector, and then electrically connected to the high-speed data bus on the VPX backplane via the VPX connector for signaling interaction with the main control board. The second end connects to the VoIP module via the SGMII bus, used to send voice processing control commands to the VoIP module. In addition, there is an internal bus connection between the main processor and the MCU for status reporting and reset control.

[0067] It should be noted that the PHY (Physical Layer Interface) chip between the main processor and the VPX connector on the multi-channel voice processing board is used to convert the MAC layer data output by the main processor into standard Ethernet physical layer signals, or to convert the received physical layer signals into MAC layer data for the main processor. One end of the main processor is connected to the PHY via the RGMII bus; the other end is connected to the VPX connector. For example, the main processor uses a quad-core processor, equipped with 4GB of DDR4 memory and 256MB of Flash memory, and is responsible for board-level task scheduling, completing voice signal acquisition, analog-to-digital conversion, digital filtering, echo cancellation, gain adjustment, silence suppression, noise suppression, voice encoding, decoding, mixing, and other processing.

[0068] The VoIP module is used for VoIP voice data encoding, decoding, and protocol processing. One end of the VoIP module is electrically connected to the main processor to receive control commands. Specifically, it is electrically connected to the main processor through the PHY interface and the SGMII serial gigabit media-independent interface to send and receive RTP-encapsulated IP voice data packets. The other end is electrically connected to the FPGA module through the PCM time-division multiplexing bus to send and receive raw PCM format voice data.

[0069] The FPGA (Field-Programmable Gate Array) module on the multi-channel voice processing board is responsible for the data scheduling center and timing core of the voice processing board. One end of the FPGA module is electrically connected to the VoIP module via the PCM bus, used to receive PCM voice data to be encoded or to send decoded PCM voice data; the other end is connected via I... 2 The S-channel digital audio bus is electrically connected to the multi-channel audio codec chip to control the analog-to-digital and digital-to-analog conversion of multiple analog voice signals. The FPGA module is also electrically connected to the clock management module to receive the global synchronization clock for precise timing control of voice processing. Furthermore, when an E1 data transceiver module is present on the multi-channel voice processing board, it is also connected to the E1 data transceiver module via the E1 data bus to handle E1 frame formation, deframering, and HDB3 encoding / decoding.

[0070] The multi-channel audio codec chip (CODEC module) is responsible for analog-to-digital conversion (ADC) and digital-to-analog conversion (DAC) of analog voice signals. It converts the PCM digital signal from the FPGA into an analog voice signal and outputs it to the analog voice interface module; simultaneously, it converts the analog voice signal from the analog voice interface module into a PCM digital signal and sends it to the FPGA. One end of the CODEC module connects to I... 2 The S-channel digital audio bus is electrically connected to the FPGA module to receive digital audio signals or send converted digital audio signals. The other end is electrically connected to the analog voice interface module via an analog audio signal line to output analog voice signals or receive externally input analog voice signals. For example, the multi-channel audio codec chip uses the CJC8988, which supports the I²S / PCM digital audio interface and features FPGA gain adjustment, mute control, zero-crossing detection, and audio mixing functions, effectively improving the voice signal-to-noise ratio and system stability.

[0071] The analog voice interface module is the electrical interface circuit between the voice processing board and external analog voice terminals (ordinary analog phones, dispatch handles, microphones, etc.). One end of the analog voice interface module is electrically connected to the analog audio signal line of the multi-channel audio codec chip; the other end is electrically connected to an external analog phone or dispatch terminal through a VPX connector.

[0072] As an example, the analog voice interface module also includes an analog telephone interface and an E1 digital trunk interface; wherein, the analog telephone interface integrates a power supply circuit, a ringing circuit, an overcurrent protection circuit, and an overvoltage protection circuit; the E1 digital trunk interface integrates a line interface unit, a clock recovery circuit, and an HDB3 codec circuit.

[0073] The overvoltage protection circuit has its input connected to the external analog phone line and its output connected to the input of the overcurrent protection circuit. It absorbs transient overvoltages caused by lightning strikes or power line induction. The overcurrent protection circuit's input is connected to the overvoltage protection circuit's output, and its output is connected to the common node of both the power supply circuit and the ringing current circuit. This limits abnormally high currents on the line. The power supply circuit's input is connected to the onboard DC power supply, and its output, after passing through the overcurrent protection circuit, is connected to the external phone line to provide power to the analog phone. The ringing current circuit's input is connected to the onboard ringing current generator, and its output, after passing through the overcurrent protection circuit, is connected to the external phone line to generate a ringing signal to drive the phone to ring when a call comes in.

[0074] The input of the line interface unit is connected to an external E1 line, and the output is connected to the input of the clock recovery circuit, used to achieve electrical characteristic adaptation and signal coupling of the E1 line. The input of the clock recovery circuit is connected to the output of the line interface unit, and the output is connected to the clock input of the HDB3 codec circuit, used to extract the 2.048MHz clock signal from the received E1 line signal. The data input of the HDB3 codec circuit is connected to the data output of the line interface unit, its clock input is connected to the output of the clock recovery circuit, and its parallel data output is connected to the E1 data bus of the FPGA module, used to convert the HDB3 code on the line into NRZ code that the FPGA can process, or to convert the NRZ code sent by the FPGA into HDB3 code and send it to the line.

[0075] The analog voice interface module supports up to 64 analog telephone interfaces and 16 E1 digital trunk interfaces. The clock synthesis submodule inside the E1 data transceiver module directly reuses the global synchronization clock to achieve timing synchronization of the analog voice channels. It can directly interface with analog equipment and traditional TDM networks without additional conversion.

[0076] It should also be noted that there are multiple analog phone interfaces, each with independent drive and protection, ensuring that the channels do not interfere with each other, thus guaranteeing channel isolation and voice quality when multiple voices communicate simultaneously.

[0077] As another embodiment, the analog telephone interface can be replaced with an E1 digital voice interface. A single voice processing board provides two E1 interfaces, each supporting 30 voice channels; eight voice processing boards can achieve 240 digital voice access channels. The E1 interface integrates a line interface unit, clock recovery circuit, and HDB3 codec circuit, working in conjunction with the clock synchronization module to ensure stable E1 link synchronization, making it suitable for high-capacity digital trunk voice dispatching scenarios.

[0078] The clock management module on the multi-channel voice processing board serves as the board's time reference. It receives a global synchronization clock (e.g., 25MHz) from the VPX backplane or an external 50MHz clock, and uses a phase-locked loop (PLL) to multiply / divide the frequency to generate the necessary operating clocks for each module on the board, such as an 8.192MHz audio sampling clock, an 8kHz frame synchronization clock, and an E1 clock, ensuring strict hardware synchronization of all voice channels. The input of the clock management module is electrically connected to the VPX connector, receiving audio sampling clock and frame synchronization signals from the high-precision clock synchronization board via the clock synchronization bus on the VPX backplane. Its output is electrically connected to the clock inputs of the main processor, VoIP module, FPGA module, and multi-channel audio codec chip, providing a unified operating clock for all modules on the board.

[0079] In addition, the multi-channel voice processing board also includes a power module, which converts the +12V power supplied by the VPX connector into multiple isolated low-voltage DC power supplies required by the various modules on the board, such as 5V, 3.3V, 2.5V, and 1.8V, and has overcurrent and overvoltage protection functions. The input terminal of the power module on the multi-channel voice processing board is also connected to the VPX connector on the multi-channel voice processing board; the output terminals are connected to the power pins of the other modules on the multi-channel voice processing board.

[0080] As an example, the multi-channel voice processing board also includes an E1 data transceiver module, which has a clock synthesis submodule inside. The input of the clock synthesis submodule is electrically connected to the clock synchronization bus to convert the audio sampling clock signal into a 2.048MHz operating clock required by the E1 digital trunk interface. The output of the clock synthesis submodule is electrically connected to the clock input of the E1 digital trunk interface to provide a synchronization clock for the transmission and reception of the E1 line.

[0081] It should be noted that the E1 data transceiver module is used to implement the electrical characteristic conversion and protocol processing of the E1 digital trunk interface. One end connects to the FPGA module via the E1 data bus, and the other end connects to the VPX connector via the E1 interface. In addition, it connects to the clock management module to receive the 50MHz clock or the E1 line clock, achieving synchronization of the E1 link.

[0082] The power module on the multi-channel voice processing board enables board-level power isolation and replacement, while the MCU module is responsible for board-level status monitoring and fault diagnosis, which will not be elaborated here.

[0083] As can be seen, the multi-channel voice processing board achieves standardized access through VPX connectors and provides efficient isolated power supply using a power module. Its core lies in the collaborative work of the main processor and the FPGA module: the main processor is responsible for task scheduling and protocol processing, while the FPGA module, relying on a global synchronization clock introduced by the clock management module, achieves precise synchronous processing of analog voice (via CODEC), digital voice (via E1 transceiver), and IP voice (via VoIP module) within the same hardware clock domain. This design completely eliminates the clock drift problem between multiple interfaces in traditional solutions, ensuring low-latency, high-fidelity voice transmission. Simultaneously, the introduction of the MCU enhances the system's maintainability and environmental adaptability, enabling it to meet the needs of high-reliability applications such as private network communication and emergency command.

[0084] As an example, such as Figure 4 As shown, the high-precision clock synchronization board includes a VPX connector, a main processor, a clock processing module, a BeiDou timing module, and an FPGA module. The main processor, clock processing module, BeiDou timing module, and FPGA module on the high-precision clock synchronization board are all connected to the VPX connector; and the BeiDou timing module, clock processing module, FPGA module, and main processor are connected in sequence.

[0085] The VPX connector on the high-precision clock synchronization board serves as the physical interface between the high-precision clock synchronization board and the VPX backplane, enabling the transmission of power, high-speed data, clock synchronization signals, and management bus signals. It is the core hub for interaction between the board and external systems. The VPX connector includes multiple ports: a power port, connected to the +12V output of the DC / DC power module to receive external power; a data port, connected to the RGMII interface of the main processor and the 1PPS / clock synchronization interface of the FPGA module to achieve data interaction with external systems; a clock port, connected to the external clock input of the clock processing module and the BeiDou antenna interface of the BeiDou timing module to receive / transmit clock synchronization signals; and a management port, connected to the IPMB interface of the main processor and the management port of the OCXC (clock cross matrix), and connected to the 1PMB bus of the VPX backplane for board-level management.

[0086] The main processor on the high-precision clock synchronization board is its control core. Running an embedded system, it interacts with the main control board (or other service boards) of the VPX backplane, processing clock synchronization-related configuration commands; managing the PHY's MDIO configuration, such as PHY address and operating mode settings; monitoring the status of each module within the board and reporting faults or alarms via the IPMB bus; and coordinating the clock synchronization logic of the clock processing module, BeiDou timing module, and FPGA module, such as clock source switching and synchronization accuracy calibration. The main processor on the high-precision clock synchronization board also includes multiple interfaces: a network interface, connected to the PHY via the RGMII bus for Ethernet data transmission and reception, used to exchange clock configuration information with external devices; a management interface, connected to the IPMB pin of the VPX connector via the IPMB bus, accessing the 1PMB management bus of the VPX backplane; a clock interface, connected to the 1PPS signal terminal of the clock processing module to receive high-precision second pulse synchronization signals; and a control interface, connected to the logic control terminal of the OCXC to configure the routing and synchronization strategies of the clock cross-matrix.

[0087] The BeiDou timing module receives timing signals from BeiDou satellites via a BeiDou antenna, including UTC time, 1PPS pulse per second, and satellite ephemeris. After parsing, it outputs high-precision time information and a pulse per second signal, providing an absolute time reference for onboard clock synchronization. The BeiDou timing module connects to the BeiDou antenna pins of the VPX connector to receive satellite radio frequency signals; it also connects to the external clock input of the clock processing module, sending the parsed 1PPS signal and satellite time information to the clock processing module for clock synthesis and synchronization calibration.

[0088] The clock processing module on the high-precision clock synchronization board is the core processing unit for high-precision clock synchronization. It is configured to: receive multi-source clock inputs, such as the 1PPS from the BeiDou timing module, the clock from the OCXC, and external clocks; generate various clocks required within the board, such as the system clock, the 1PPS output clock, and the E1 / Ethernet synchronization clock, through a phase-locked loop (PLL) and clock synthesizer; perform clock frequency synthesis (e.g., multiplying a 25MHz external clock to a 156.25MHz Ethernet clock), phase adjustment (calibrating clock jitter and drift), and multiplexing (providing synchronization clocks for FPGA, main processor, PHY, etc.); and output a 1PPS (pulses per second) signal as the core marker for time synchronization, ensuring strict alignment of the clock edges of all modules within the board. The input terminals of the clock processing module on the high-precision clock synchronization board are connected not only to the clock output of the BeiDou timing module to receive satellite timing signals, but also to the clock output of the OCXC to receive the backplane global clock; furthermore, they are connected to the external clock pins of the VPX connector to receive external synchronization clocks (such as GPS and ground link clocks). The output terminal is connected not only to the clock input of the FPGA module to provide a high-precision synchronous clock, but also to the 1PPS input of the main processor to provide a second pulse synchronization signal; in addition, it is connected to the clock input of the PHY to provide a synchronous clock (such as a 125MHz SGMII clock) for the Ethernet PHY.

[0089] The FPGA module on the high-precision clock synchronization board is used to implement digital processing and protocol conversion of the high-precision clock. It is configured to: receive the synchronization clock output from the clock processing module; generate various digital clocks required within the board (such as I2S audio clock, E1 line clock, and FPGA internal logic clock); implement hardware acceleration processing for clock synchronization protocols (such as IEEE 1588 PTP and NTP), converting physical layer clock signals into timestamp information required for protocol messages; interact with the OCXC to participate in the cross-synchronization of the VPX backplane global clock (such as clock routing, calibration, and redundancy backup); and output a 1PPS / clock synchronization signal to the VPX connector to provide synchronization clocks for other boards on the VPX backplane (such as voice processing boards and switching boards). The input of the FPGA module on the high-precision clock synchronization board is connected to the clock output of the clock processing module to receive the high-precision synchronization clock; its output is connected to the 1PPS / clock synchronization pin of the VPX connector to output a synchronization signal to the backplane. In addition, it connects to the logic control terminal of the OCXC (clock cross matrix / clock distribution chip) to configure the routing strategy of the clock cross matrix; and connects to the L1O (local I / O) bus of the main processor to realize high-speed data interaction (such as clock status reporting and configuration parameter distribution).

[0090] It should also be noted that the OCXC (Clock Cross Matrix / Clock Distribution Chip) serves as the global clock hub for the VPX backplane, enabling cross-distribution and synchronization calibration of multiple clock sources. It is configured to: receive the synchronization clock output from the clock processing module and route it to various slots on the VPX backplane, providing a global synchronization clock for the main control board, voice processing board, switching board, etc.; collect clock feedback signals from each board and adjust the phase and frequency of the output clock through a clock calibration algorithm to ensure global synchronization of clocks across all boards; support clock redundancy (such as primary / backup clock source switching) and fault detection (monitoring clock link status), improving system reliability.

[0091] The 1PMB bus is the management bus for the VPX backplane, based on I... 2 The C protocol extension is used for board-level management (such as status monitoring, fault alarms, and configuration distribution). The high-precision clock synchronization board reports its own status, such as clock synchronization accuracy, BeiDou time synchronization status, and power status, to the main control board of the VPX backplane via the 1PMB bus, while simultaneously receiving remote configuration commands from the management unit.

[0092] As an example, the high-precision clock synchronization board is configured to support at least one of the following synchronization modes: BeiDou dual-mode synchronization, external wired synchronization, and local timekeeping synchronization. The output audio sampling clock signal is 8.192MHz and the frame synchronization signal is 8kHz.

[0093] In other words, the high-precision clock synchronization board provides a unified 8.192MHz audio sampling clock and 8kHz frame synchronization signal to all boards through the VPX backplane. The high-precision clock synchronization board is configured to support at least one synchronization mode, such as GPS / BeiDou dual-mode synchronization, 1PPS external synchronization, E1 line synchronization, and IEEE1588 Ethernet synchronization, outputting a unified 8.192MHz audio sampling clock and 8kHz frame synchronization signal. This ensures strict synchronization of voice sampling across multiple channels and boards, avoiding problems such as echo, noise, dropouts, and phase shifts caused by clock deviations, thus improving the overall system voice quality.

[0094] Preferably, a combination of hardware-level IEEE 1588 PTPv2 and a highly stable temperature-compensated crystal oscillator can be used, which provides high synchronization accuracy and lays the foundation for high-quality one-to-many voice processing.

[0095] Furthermore, in BeiDou mode, nanosecond-level synchronization is achieved by receiving 1PPS and TOD signals from BeiDou satellites and using a clock processing chip to discipline a temperature-controlled crystal oscillator. In external wired synchronization, synchronization is achieved by connecting an external 1PPS, a 10MHz standard frequency clock, or an IRIG-B reference clock. In local timekeeping mode, a local time reference with a 24-hour microsecond-level error is maintained based on the disciplined temperature-controlled crystal oscillator. These three synchronization modes can automatically and seamlessly switch, exhibiting strong environmental adaptability and enabling stable operation for extended periods even without an external clock source.

[0096] In addition, the high-precision clock synchronization board also includes a DC / DC power module. This module converts the +12V input voltage provided by the VPX backplane into multiple isolated power supplies required by the various modules on the board, such as 3.3V, 1.8V, and 1.2V, and provides overvoltage and overcurrent protection to ensure stable board operation. The input terminal connects to the +12V pin of the VPX connector to receive external power; the output terminal connects to the power input terminals of various modules on the board, such as the main processor, clock processing module, BeiDou timing module, and FPGA module, to provide operating power.

[0097] It should be noted that the power board is electrically connected to the VPX backplane via a VPX connector and is installed in the power supply slot.

[0098] As an example, the power board is a wide-input isolated DC-DC power module or a wide-input AC-DC power module; the input voltage range of the DC-DC power module is 18V-36V, and the input voltage range of the AC-DC power module is AC85V-265V; the power board outputs multiple isolated power supplies and has the functions of overcurrent protection, overvoltage protection, undervoltage protection and reverse connection protection.

[0099] The AC-DC power module has an input voltage range of AC85V-265V, compatible with standard AC220V and special platform power supplies such as 24V and 28V for automotive applications. The power board outputs multiple isolated power supplies, including 3.3V and 12V, each equipped with LC filtering, voltage regulation, overcurrent, overvoltage, undervoltage, and reverse connection protection to reduce power supply noise interference with weak audio signals and improve system electromagnetic compatibility and operational stability.

[0100] Furthermore, the device also includes a heat dissipation module; the heat dissipation module adopts a combination of conductive cooling and air cooling structure, with a temperature-controlled fan installed inside the VPX chassis and heat dissipation fins on the VPX backplate.

[0101] The heat dissipation module provides forced cooling for the entire unit. Each board is in close contact with the chassis's cooling base plate via high thermal conductivity pads. The VPX backplate is equipped with heat dissipation fins, and the VPX chassis features dual temperature-controlled fans that automatically adjust their speed based on the internal temperature. Combined with directional cooling airflow, it provides stable heat dissipation within a wide temperature range of -40℃ to +85℃, ensuring the device operates at normal temperatures and meeting the requirements for long-term reliable operation in harsh environments.

[0102] Through intelligent heat dissipation structure, multi-domain isolated power supply and ruggedized architecture, the device is guaranteed to operate stably for a long time under harsh conditions. The introduction of AC / DC dual-mode power input and intelligent temperature-controlled air cooling gives the device a strong environmental adaptability, perfectly meeting the needs of high-reliability application scenarios such as private network communication, emergency command and vehicle dispatch.

[0103] Throughout the process, all voice acquisition, processing, and transmission across all boards are driven by a unified 8.192MHz audio sampling clock and an 8kHz frame synchronization signal, ensuring precise synchronization of multiple voice channels. The main control board monitors the real-time operating status, channel status, power status, temperature information, and clock synchronization status of each board, and supports local debugging and remote network management configuration. All multiple voice channels are driven by the same source and direction clock, fundamentally eliminating clock drift and phase difference between multiple voice channels and across boards, ensuring precise alignment of voice acquisition, mixing, and playback. This global clock distribution mechanism ensures consistent synchronization performance across all boards, and the synchronization capability remains unchanged after device expansion, meeting the needs of large-scale, multi-scenario voice communication.

[0104] Furthermore, a 3U VPX compact chassis can be used, equipped with two 8-channel voice processing boards, providing 16 voice channels in total. It features small size, light weight, and low power consumption, making it suitable for unmanned aerial vehicles (UAVs), portable stations, and small vehicle-mounted applications where space and weight are strictly limited. Testing shows that the device has an end-to-end voice latency of less than 50ms, an echo cancellation tail length of greater than 64ms, a total harmonic distortion of less than 1%, and an operating temperature range of -40℃ to +85℃, meeting the high reliability requirements for private networks, emergency communications, and command and dispatch applications.

[0105] As another embodiment, the multi-channel voice processing module of this device can also be designed independently in the form of a standard VPX functional sub-board, separate from the original device's main control and synchronization system, and embedded as a general voice expansion unit in a third-party standard VPX chassis, ruggedized computer, or communication server chassis, working in conjunction with the target chassis's main control unit, power supply unit, and heat dissipation system to achieve rapid expansion of voice processing capabilities.

[0106] The multi-channel voice processing module strictly adheres to the VITA 46 VPX standard, employing uniform mechanical dimensions, standard VPX connectors, and standardized signal definitions. It provides standardized clock interfaces, synchronization signal interfaces, high-speed data interfaces, control interfaces, and service interfaces. The module retains complete voice processing capabilities, including analog voice interfaces, CODEC conversion, channel scheduling, TDM multiplexing, E1 trunking, VoIP protocol processing, local clock management, and status detection. It requires only an external standard operating clock, synchronization trigger signal, and power supply to independently complete the acquisition, encoding, mixing, playback, and E1 integration of 8 / 16 / 32 channels of voice.

[0107] After inserting the voice processing module into the corresponding service slot of a third-party standard VPX chassis, the following interconnection is achieved through the chassis backplane: First, the voice processing module's clock management unit obtains a unified reference clock provided by a third-party system from the global clock bus on the chassis backplane. The synchronization signal interface receives an external 1PPS and an absolute timestamp to ensure that voice sampling, processing, and transmission are strictly aligned with the timing of the entire system.

[0108] Next, the voice processing module completes real-time interaction of voice data, control signaling and status information with the third-party chassis main control board through the VPX high-speed data bus, supporting data forwarding, mixing scheduling and service configuration.

[0109] Then, the voice processing module's analog voice interface, E1 digital trunk interface, and Ethernet interface are brought out through the front panel or back panel connectors of the chassis and directly connected to the external communication network and user terminal.

[0110] Finally, the built-in MCU of the voice processing module reports the working status, channel status, synchronization status, voltage and temperature information to the third-party chassis management unit to achieve unified monitoring, fault location and alarm.

[0111] This application transforms the voice processing module from a component of a dedicated device into a general-purpose VPX voice extension component, which can be widely adapted to various standard VPX hardware platforms such as vehicle-mounted, airborne, and ground fixed stations. Without changing the original chassis architecture, it can quickly provide command and dispatch, emergency communication, and dispatch exchange systems with highly reliable, highly synchronized, and high-fidelity multi-channel VoIP and E1 voice processing capabilities.

[0112] like Figure 5 The diagram shown is a schematic of the remote dispatching application of the device in this application. As an example, multiple devices are connected to the management and dispatching computer through an Ethernet ring network, and each device establishes a voice communication connection with the user terminal through an analog telephone interface or an E1 digital trunk interface to realize the remote dispatching application.

[0113] In summary, this device is suitable for professional voice processing scenarios that require high synchronization accuracy, real-time performance, reliability, interface compatibility, and environmental adaptability, such as command and dispatch communication platforms, emergency communication platforms, industrial communication systems, multi-party teleconferences, broadcast intercom systems, digital trunk one-to-many aggregation, multi-channel recording systems, and one-to-many centralized voice communication scenarios such as dispatch switching.

[0114] It should be noted that, for the sake of simplicity, the foregoing embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0115] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0116] In the several embodiments provided in this application, it should be understood that the disclosed methods or systems can be implemented in other ways. For example, the embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0117] The foregoing description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of embodiments of this disclosure upon considering the specification and practicing the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described herein. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

[0118] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A multipath voice over Internet protocol (VoIP) voice processing apparatus based on hardware clock synchronization, characterized by, The device includes a VPX chassis, a VPX backplane, a main control board, at least one multi-channel voice processing board, a high-precision clock synchronization board, and a power supply board. The VPX backplane is fixedly installed inside the VPX chassis, and the VPX backplane integrates a clock synchronization bus, a high-speed data bus, and a power bus. The main control board, the multi-channel voice processing board, the high-precision clock synchronization board, and the power board are all electrically connected to the VPX backplane via VPX connectors; The main control board communicates and interconnects with the multi-channel voice processing board through the high-speed data bus, and is used to realize voice registration, call control and routing scheduling. The multi-channel voice processing board is used to synchronously acquire, convert analog to digital, encode, decode, and mix multiple analog voice signals or E1 digital voice signals under the drive of the audio sampling clock signal and the frame synchronization signal. The high-precision clock synchronization board is used to generate a unified audio sampling clock signal and frame synchronization signal, and transmits them to the main control board and each of the multi-channel voice processing boards respectively through the clock synchronization bus. The power board is used to provide isolated operating power to each board.

2. The multi-path VoIP voice processing apparatus based on hardware clock synchronization according to claim 1, wherein, The main control board includes an Ethernet switching module, a PHY module, a main processor, an FPGA, an MCU, and a clock management module. The Ethernet switching module, PHY module, MCU, and clock management module on the main control board are all connected to VPX connectors. The Ethernet switching module, PHY module, main processor, and FPGA are connected in sequence. The clock management module is connected to all functional modules on the main control board. The input terminal of the clock management module is electrically connected to the clock synchronization bus and is used to distribute the received signals from the clock synchronization bus to the various modules on the main control board.

3. The hardware clock synchronization based multi-path VoIP voice processing apparatus according to claim 1, wherein, The multi-channel voice processing board includes: a VPX connector, a main processor, a VoIP module, an FPGA module, a multi-channel audio codec chip, an analog voice interface module, and a clock management module. The main processor, analog voice interface module, and clock management module on the multi-channel voice processing board are all connected to the VPX connector. The main processor, VoIP module, FPGA module, multi-channel audio codec chip, and analog voice interface module are connected in sequence. The clock management module is connected to all functional modules on the main control board. The input terminal of the clock management module is electrically connected to the clock synchronization bus and is used to receive the audio sampling clock signal and the frame synchronization signal and distribute them to the various functional modules in the multi-channel voice processing board.

4. The hardware clock synchronization based multi-path VoIP voice processing apparatus according to claim 3, wherein, The analog voice interface module also includes an analog telephone interface and an E1 digital trunk interface; the analog telephone interface integrates a power supply circuit, a ringing circuit, an overcurrent protection circuit, and an overvoltage protection circuit; the E1 digital trunk interface integrates a line interface unit, a clock recovery circuit, and an HDB3 codec circuit.

5. A multi-channel VoIP voice processing device based on hardware clock synchronization according to claim 4, characterized in that, The multi-channel voice processing board also includes an E1 data transceiver module, which has a clock synthesis submodule inside. The input of the clock synthesis submodule is electrically connected to the clock synchronization bus and is used to convert the audio sampling clock signal into a 2.048MHz operating clock required by the E1 digital trunk interface. The output of the clock synthesis submodule is electrically connected to the clock input of the E1 digital trunk interface and is used to provide a synchronization clock for the transmission and reception of the E1 line.

6. The multi-channel VoIP voice processing device based on hardware clock synchronization according to claim 1, characterized in that, The high-precision clock synchronization board includes a VPX connector, a main processor, a clock processing module, a BeiDou timing module, and an FPGA module. The main processor, clock processing module, BeiDou timing module, and FPGA module on the high-precision clock synchronization board are all connected to the VPX connector. The BeiDou timing module, clock processing module, FPGA module, and main processor are connected in sequence.

7. A multi-channel VoIP voice processing device based on hardware clock synchronization according to claim 6, characterized in that, The high-precision clock synchronization board is configured to support at least one of the following synchronization modes: BeiDou dual-mode synchronization, external wired synchronization, and local timekeeping synchronization. The output audio sampling clock signal is 8.192MHz, and the frame synchronization signal is 8kHz.

8. A multi-channel VoIP voice processing device based on hardware clock synchronization according to claim 1, characterized in that, The power board is a wide-input isolated DC-DC power module or a wide-input AC-DC power module; the input voltage range of the DC-DC power module is 18V-36V, and the input voltage range of the AC-DC power module is AC85V-265V; the power board outputs multiple isolated power supplies and has the functions of overcurrent protection, overvoltage protection, undervoltage protection and reverse connection protection.

9. A multi-channel VoIP voice processing device based on hardware clock synchronization according to any one of claims 1 to 8, characterized in that, The device also includes a heat dissipation module; the heat dissipation module adopts a structure combining conductive cooling and air cooling, the VPX chassis is equipped with a temperature-controlled fan, and the VPX backplate is equipped with heat dissipation fins.

10. A multi-channel VoIP voice processing device based on hardware clock synchronization according to claim 9, characterized in that, Multiple devices are connected to the management and dispatch computer via an Ethernet ring network, and each device establishes a voice communication connection with the user terminal through an analog telephone interface or an E1 digital trunk interface to realize remote dispatch applications.

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