Semiconductor device

Abstract

The semiconductor device according to the present application includes: a source / drain member sandwiched between a first channel region and a second channel region, each of the first channel region and the second channel region including a plurality of channel members; a first gate structure surrounding each of the channel members in the first channel region; and a second gate structure surrounding each of the channel members in the second channel region. The semiconductor device further includes: an interlayer dielectric (ILD) layer on the source / drain member; and a cap layer on the interlayer dielectric layer and disposed between the first gate structure and the second gate structure.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for forming the same, and particularly to the thickness control of gate spacers. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in various generations of ICs, each with smaller and more complex circuits than the previous generation. In this evolution, functional density (e.g., the number of interconnect elements per wafer area) has generally increased, while geometry (e.g., the smallest components (or traces) that can be created using a manufacturing process) has shrunk. This shrinking of size generally benefits production efficiency and reduces associated costs. However, this size reduction also increases the complexity of manufacturing ICs.

[0003] For example, as integrated circuit technology evolved to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) (or multi-gate devices) were introduced to improve gate control by increasing gate channel coupling, reducing off-state current, and reducing the short-channel effect (SCE). Multi-gate devices generally represent devices with a gate structure or portion thereof disposed on more than one side of the channel region. The gate-all-around (GAA) transistor is an example of a multi-gate device and has become a popular and reliable choice for high-performance and low-leakage-current applications. A GAA transistor has a gate structure that extends (partially or completely) around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, a GAA transistor can also be called a surrounding gate transistor (SGT) or a multi-bridge channel (MBC) transistor. Utility Model Content

[0004] A semiconductor device includes: a source / drain component sandwiched between a first channel region and a second channel region, each of the first and second channel regions including a plurality of channel members; a first gate structure surrounding each channel member in the first channel region; and a second gate structure surrounding each channel member in the second channel region. The semiconductor device further includes: an interlayer dielectric layer on the source / drain component; and a capping layer on the interlayer dielectric layer and disposed between the first gate structure and the second gate structure.

[0005] In some embodiments, the top surface of the capping layer, the top surface of the first gate structure, and the top surface of the second gate structure are coplanar.

[0006] In some embodiments, the semiconductor device further includes: a first gate spacer extending along a sidewall of a first gate structure; and a second gate spacer extending along a sidewall of a second gate structure.

[0007] In some embodiments, the semiconductor device further includes: a contact etch stop layer extending from between the first gate spacer and the interlayer dielectric layer to between the interlayer dielectric layer and the source / drain components, and then to between the second gate spacer and the interlayer dielectric layer.

[0008] In some embodiments, the contact etch stop layer further extends between the first gate spacer and the capping layer, and between the second gate spacer and the capping layer.

[0009] In some embodiments, the top surface of the capping layer, the top surface of the contact etch stop layer, the top surface of the first gate spacer, the top surface of the second gate spacer, the top surface of the first gate structure, and the top surface of the second gate structure are coplanar.

[0010] In some embodiments, the semiconductor device further includes a plurality of inner spacer components vertically disposed between two adjacent channel members in a first channel region and between two adjacent channel members in a second channel region.

[0011] In some embodiments, a plurality of inner spacer components are in direct contact with the first gate structure in the first channel region and in direct contact with the second gate structure in the second channel region.

[0012] In some embodiments, a plurality of inner spacer components separate the source / drain components from the first gate structure and separate the source / drain components from the second gate structure.

[0013] In some embodiments, the source / drain components extend vertically through the depth of the multiple channel members and partially into the substrate. Attached Figure Description

[0014] The embodiments of this utility model will now be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale but are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this utility model.

[0015] Figure 1 This is a flowchart illustrating a method for forming a semiconductor device according to one or more aspects of the present invention.

[0016] Figures 2 to 18 The diagram illustrates the structure in progress according to one or more aspects of this utility model. Figure 1 A cross-sectional diagram during the fabrication process of the method.

[0017] Figure 19 This is a flowchart illustrating a method for forming a semiconductor device according to one or more aspects of the present invention.

[0018] Figures 20-38 The diagram illustrates the structure in progress according to one or more aspects of this utility model. Figure 19 A cross-sectional view during the fabrication process of the method.

[0019] The reference numerals in the attached figures are explained as follows:

[0020] 100: Method

[0021] 102: Square

[0022] 104: Box

[0023] 106: Square

[0024] 108: Square

[0025] 110: Square

[0026] 112: Square

[0027] 114: Square

[0028] 116: Square

[0029] 118: Square

[0030] 120: Square

[0031] 122: Square

[0032] 124: Square

[0033] 126: Square

[0034] 200: In-progress structure

[0035] 202: Base

[0036] 204: Stacking

[0037] 206: Sacrificial Layer

[0038] 208: Channel Layer

[0039] 210: Hard mask layer

[0040] 212: Fin-like structure

[0041] 212B: Base fin structure

[0042] 212C: Passage Area

[0043] 212SD: Source / Drain Region

[0044] 214: Isolation component

[0045] 216: Virtual Dielectric Layer

[0046] 218: Dummy Electrode Layer

[0047] 220: Dummy Gate Stack

[0048] 222: Top gate hard mask layer

[0049] 223: Silicon oxide layer

[0050] 224: Silicon nitride layer

[0051] 226: Gate spacer layer

[0052] 228: Source / Drain Trench

[0053] 230: Inner spacer groove

[0054] 231: Virtual Layer

[0055] 232: Inner spacer groove

[0056] 234: Internal spacer component

[0057] 240: Source / Drain Components

[0058] 242: Contact Etching Stop Layer

[0059] 244: Interlayer dielectric layer

[0060] 245: Cap layer

[0061] 246: Gate Trench

[0062] 250: Gate structure

[0063] 300: Method

[0064] 302: Box

[0065] 304: Box

[0066] 306: Box

[0067] 308: Box

[0068] 310: Square

[0069] 312: Box

[0070] 314: Box

[0071] 316: Box

[0072] 318: Square

[0073] 320: Square

[0074] 322: Box

[0075] 324: Box

[0076] 326: Square

[0077] 328: Square

[0078] 1000: Ion implantation process

[0079] 2000: Annealing Process

[0080] 2080: Channel Components

[0081] 2440: Top recess

[0082] A-A': line segment Detailed Implementation

[0083] The following disclosure provides numerous different embodiments or examples for implementing various components of the provided service. Specific examples of components and configurations are described below to simplify the embodiments of this utility model. Of course, these are merely examples and are not intended to limit the embodiments of this utility model. For example, references to a first component being formed on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of this utility model. Such repetition is for simplification and clarity and does not in itself govern the relationship between the various embodiments and / or configurations discussed.

[0084] Spatially related terms such as “below,” “below,” “lower,” “higher,” “above,” and similar terms may be used here to describe the relationship between an element or component and other elements or components, as shown in the diagrams. Spatially related terms are intended to encompass different orientations of these elements in use or operation, other than those depicted in the diagrams. When the device is rotated to other orientations (90° rotation or other orientations), the spatially relative descriptions used here can also be interpreted according to the orientation after rotation.

[0085] Furthermore, when using terms such as "approximately" or "about," to describe a number or range of numbers, this terminology is intended to cover a reasonable range of numbers that takes into account the inherent variations in the manufacturing process as understood by those skilled in the art. For example, based on known manufacturing tolerances for manufacturing parts with the characteristics associated with that number, the number or range of numbers covers a reasonable range that includes the number, such as within ±10% of the number. For example, those skilled in the art know that the manufacturing tolerance associated with a deposited material layer is ±15%, and a material layer with a thickness of "approximately 5 nanometers" can cover a size range of 4.25 nanometers to 5.75 nanometers. In this invention, source / drain regions may represent the source or drain individually or collectively, depending on the context.

[0086] This invention generally relates to a fully wound gate transistor and a method for manufacturing the same. A fully wound gate transistor can be manufactured using a replacement gate process, wherein a dummy gate stack is formed as a placeholder and subsequently replaced by a functional gate structure. The sidewalls of the dummy gate stack are covered with gate spacers, which help define the boundaries of the dummy gate stack. After forming the source / drain components, the dummy gate stack is removed and replaced with a functional gate structure. The functional gate structure may include an interfacial layer (IL) formed using an oxidation process. It has been observed that dangling bonds present on the surface of the gate spacers can lead to an increase in the thickness of the interfacial layer. A thicker interfacial layer can lead to an increase in channel resistance or a decrease in channel current. It can be seen that dangling bonds present on the gate spacers can be a source of process variation.

[0087] This invention provides a method for forming a fully wrapped gate transistor. In an example process, a fin structure having a channel layer and a sacrificial layer is formed on a substrate. After forming a dummy gate stack on the channel region of the fin structure, at least one gate spacer is formed on the dummy gate stack, and the source / drain regions of the fin structure are etched. After forming source / drain components on the source / drain regions, a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer are deposited on the source / drain components. Then, the interlayer dielectric layer is selectively etched to form a top recess. Subsequently, an ion implantation process and an annealing process are performed to neutralize surface dangling bonds on at least one gate spacer. After the annealing process, a capping layer is formed on the top recess. Next, the dummy gate stack is removed, and the channel layer in the channel region is released. A gate structure is formed to wrap around each channel layer. Ion implantation and annealing processes can not only avoid thickening of the interface layer in the gate structure, but also improve performance by adjusting the channel layer.

[0088] Various aspects of this utility model will now be described in detail with reference to the drawings. In this respect, Figure 1 and Figure 19 This diagram illustrates flowcharts of methods 100 and 300 for forming a semiconductor structure from a work-in-progress (WIP) structure, according to embodiments of the present invention. Methods 100 and 300 are merely exemplary and not intended to limit the present invention to the portions specifically illustrated in methods 100 and 300. Additional steps may be provided before, during, and after method 100 or 300, and some described steps may be substituted, eliminated, or moved in additional embodiments of methods 100 and 300. For clarity of discussion, not all steps are detailed herein. Method 100 will be combined with... Figures 2 to 18 The details are as follows. Figures 2 to 18 It is based on Figure 1 An embodiment of method 100, showing cross-sectional views of structure 200 at different manufacturing stages. Method 300 will combine... Figures 20-38 The details are as follows. Figures 20-38 It is based on Figure 19 The embodiment of method 300 is illustrated by cross-sectional views of the structure 200 in progress at different manufacturing stages. Since the structure 200 in progress will be manufactured into a semiconductor device, it may be referred to herein as a semiconductor device for the purposes of this text. For the avoidance of ambiguity, Figures 2 to 18 and Figures 20-38 The X, Y, and Z directions are perpendicular to each other. Throughout this invention, the same components or steps may be designated by the same symbols, unless otherwise specified.

[0089] Methods 100 and 300 are both methods for forming a fully wound gate transistor. Both methods 100 and 300 begin with forming a stack on a substrate, wherein the stack includes multiple channel layers and multiple sacrificial layers alternately arranged. Both methods 100 and 300 include the step of patterning the stack to form a fin structure. Method 100 retains the sacrificial layers in the channel regions of the fin structure until after the source / drain components are formed in the source / drain regions of the fin structure. Unlike Method 100, Method 300 removes the sacrificial layers after forming the dummy gate stack, and deposits dummy layers alternately with the channel layers. After forming the source / drain components in the source / drain regions of the fin structure, the dummy layers are removed. Methods 100 and 300 will be described below. Detailed descriptions of similar operations may be omitted for simplicity. The same references used in conjunction with Methods 100 and 300 should be considered interchangeable unless explicitly stated herein. The focus is initially on... Figure 1 Method 100.

[0090] Reference Figure 1 and Figure 2Method 100 includes block 102, wherein a stack 204 of interleaved semiconductor layers is formed on the structure 200 in progress. Figure 2 As shown, the structure 200 in progress includes a substrate 202. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. The substrate 202 may include various doping configurations, depending on design requirements. In embodiments where the semiconductor element is P-type, an N-type doped profile (e.g., an N-type well) may be formed on the substrate 202. In some embodiments, the N-type dopant used to form the N-type well may include phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor element is N-type, a P-type doped profile (e.g., a P-type well) may be formed on the substrate 202. In some embodiments, the P-type dopant used to form the P-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of the dopant. The substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn), or diamond. Alternatively, substrate 202 may include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 202 may optionally include an epitaxial layer, a strainable epitaxial layer to improve performance, which may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable reinforcing components.

[0091] In some embodiments, the stack 204 on the substrate 202 includes an alternating arrangement of a channel layer 208 of a first semiconductor composition and a sacrificial layer 206 of a second semiconductor composition. Alternatively, the sacrificial layer 206 and the channel layer 208 can be considered to be alternating. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layer 206 comprises silicon-germanium or germanium-tin, while the channel layer 208 comprises silicon. It should be noted that four sacrificial layers 206 and three channel layers 208 are arranged in an alternating manner (e.g., Figure 2 (As shown), it is for illustrative purposes only and is not intended to limit the scope beyond what is specifically described in the claims. It should be understood that any number of epitaxial layers may be formed in the stack 204. The number of film layers depends on the desired number of channel components of the semiconductor device. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0092] Molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), and / or other suitable epitaxial growth processes can be used to deposit the sacrificial layer 206 and the channel layer 208 in the stack 204. As described above, in at least some examples, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium layer, and the channel layer 208 comprises an epitaxially grown silicon layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially doped (e.g., having about 0 atoms / cm²). 3 Up to 1×10 17 atoms / cm 3 The external dopant concentration), wherein, for example, during the epitaxial growth process of stacked 204, no deliberate doping is performed.

[0093] Reference Figure 1 and Figure 3 Method 100 includes a box 104, wherein a fin-like structure 212 is formed by a stack 204 and a substrate 202. To pattern the stack 204, a hard mask layer 210 (illustrated in...) can be deposited on the stack 204. Figure 2 (In the middle) to form an etch mask. The hard mask layer 210 can be a single layer or multiple layers. For example, the hard mask layer 210 may include a pad oxide layer and a pad nitride layer disposed on the pad oxide layer. The fin structure 212 can be patterned from the stack 204 and the substrate 202 using lithography and etching processes. Lithography processes may include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching (RIE)), wet etching, and / or other etching methods. Figure 3 As shown, the etching process of box 104 forms trenches extending vertically through stack 204 and a portion of substrate 202. The trenches define fin structures 212. In some embodiments, dual patterning or multiple patterning processes can be used to define the fin structures, having, for example, a pattern with a smaller pitch than that obtained using a single, direct lithography process. For example, in one embodiment, a material layer is formed over the substrate and patterned using a lithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used as a mask to etch stack 204 and a portion of substrate 202 to pattern the fin structure 212. Figure 3 As shown, the fin structure 212, including the sacrificial layer 206 and the channel layer 208, extends vertically along the Z direction and along the length direction of the X direction. Figure 3As shown, the fin structure 212 includes a base fin structure 212B patterned by the substrate 202. A patterned stack 204 (which includes a sacrificial layer 206 and a channel layer 208) is disposed directly above the base fin structure 212B.

[0094] In box 104, an isolation member 214 is formed adjacent to the fin structure 212. Figure 3 In some embodiments, the isolation member 214 is disposed on the sidewall of the base fin structure 212B. In some embodiments, the isolation member 214 may be formed in a trench to isolate adjacent fin structures 212. The isolation member 214 may also be referred to as a shallow trench isolation (STI) member. For example, in some embodiments, a dielectric layer is first deposited on the substrate 202 to fill the trench. In some embodiments, the dielectric layer may include silicon oxide (SiO), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, a dielectric layer can be deposited using chemical vapor deposition (CVD), sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCVD), spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized using processes such as chemical mechanical polishing (CMP). The planarized dielectric layer is further etched or pulled back using dry etching, wet etching, and / or combinations thereof to form shallow trench isolation components (illustrated in...). Figure 3 (Middle). After the etch, the fin structure 212 rises above the shallow trench isolation member, while the base fin structure 212B is embedded or buried in the isolation member 214.

[0095] Reference Figure 1 , Figure 4 and Figure 5 Method 100 includes block 106, wherein a dummy gate stack 220 is formed on the channel region 212C of the fin structure 212. Figure 5 For along Figure 4A cross-sectional schematic diagram of line segment A-A' cut into the image. In some embodiments, a gate replacement process (or gate-last process) is employed, wherein the dummy gate stack 220 (illustrated in...) Figure 4 and Figure 5 (The middle) acts as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are possible. Figure 5 In some embodiments shown, a dummy gate stack 220 is formed on the fin structure 212, and the fin structure 212 can be divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 5 As shown, the source / drain region 212SD is disposed between the two channel regions 212C along the X direction.

[0096] The formation of the dummy gate stack 220 may include depositing and patterning film layers in the dummy gate stack 220. (Refer to...) Figure 4 A dummy dielectric layer 216, a dummy electrode layer 218, and a top gate hard mask layer 222 can be deposited on the structure 200 in progress using a blanket deposition method. In some embodiments, the dummy dielectric layer 216 can be formed on the fin structure 212 using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, an oxygen plasma oxidation process, or other suitable processes. In some cases, the dummy dielectric layer 216 may include silicon oxide. Subsequently, a dummy electrode layer 218 can be deposited on the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable processes. In some cases, the dummy electrode layer 218 may include polysilicon. For patterning purposes, a top gate hard mask layer 222 can be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable processes. Then, the top gate hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can be patterned to form a dummy gate stack 220, such as... Figure 5As shown. For example, the patterning process may include lithography (e.g., photolithography or electron beam lithography) and etching. The lithography process may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The photolithography process forms a patterned photoresist layer. Then, the patterned photoresist layer is applied as an etching mask in the etching process to pattern the top gate hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching), wet etching, and / or other etching methods. In some embodiments, the top gate hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 on the silicon oxide layer 223. Figure 5 As shown, the patterned dummy gate stack 220 is disposed only on the channel region 212C and not on the source / drain region 212SD.

[0097] Reference Figure 1 and Figure 6 In block 106, a gate spacer layer 226 is deposited on the structure in progress 200, including on the dummy gate stack 220. In some embodiments, the gate spacer layer 226 is compliantly deposited on the structure in progress 200, including on the top surface and sidewalls of the dummy gate stack 220. The term "compliantly" is used here to describe a film layer having a substantially uniform thickness over various regions. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or silicon nitride (SiN). The gate spacer layer 226 may be deposited on the dummy gate stack 220 using methods such as chemical vapor deposition, subatmospheric chemical vapor deposition, atomic layer deposition, or other suitable processes.

[0098] Reference Figure 1 and Figure 7Method 100 includes block 108, wherein the source / drain regions 212SD of the fin structure 212 are anisotropically etched to form source / drain trenches 228. The anisotropic etching may include dry etching or a suitable etching process that etches the source / drain regions 212SD and portions of the substrate 202 below the source / drain regions 212SD. The resulting source / drain trenches 228 extend vertically through the depth of the stack 204 and partially into the substrate 202. The example dry etching process in box 108 can be implemented using oxygen-containing gases, fluorine-containing gases (e.g., carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3), octafluorocyclobutane (C4F8), and / or hexafluoroethane (C2F6)), chlorine-containing gases (e.g., chlorine (Cl2), trichloromethane (CHCl3), tetrachloromethane (CCl4), and / or boron trichloride (BCl3)), bromine-containing gases (e.g., hydrogen bromide (HBr) and / or tribromomethane (CHBr3)), iodine-containing gases, other suitable gases, plasma, and / or combinations thereof. Figure 7 As shown, the source / drain region 212SD of the etched fin structure 212 exposes the sidewalls of the sacrificial layer 206 and the channel layer 208. Since the source / drain trench 228 extends below the stack 204 into the substrate 202, the source / drain trench 228 includes a bottom surface and lower sidewalls defined in the substrate 202.

[0099] Reference Figure 1 , Figure 8 and Figure 9 Method 100 includes block 110, in which an inner spacer component 234 is formed. Although not explicitly shown, operation of block 110 may include selectively and partially removing the sacrificial layer 206 to form an inner spacer recess 230 (shown in...). Figure 8 In the middle), depositing inner spacer material on the structure 200 in progress, and etching back the inner spacer material to form inner spacer component 234 in inner spacer groove 230 (illustrated in Figure 9 (Chinese). Reference Figure 8In this process, the sacrificial layer 206 exposed in the source / drain trench 228 is selectively and partially etched to form the inner spacer recess 230, while the gate spacer layer 226, the exposed portion of the substrate 202, and the channel layer 208 are substantially left unetched. In embodiments where the channel layer 208 substantially comprises silicon and the sacrificial layer 206 substantially comprises silicon-germanium, selective wet etching or selective dry etching processes can be used for the selective etching of the sacrificial layer 206. Examples of selective dry etching processes may include the use of one or more fluorine-based etchants, such as fluorine (F2) or hydrofluorocarbons. Examples of selective wet etching processes may include etching with an ammonia hydroxide–hydrogen peroxide-water mixture (APM).

[0100] After the inner spacer recess 230 is formed, an inner spacer material is deposited on the structure in progress 200, including on the inner spacer recess 230. The inner spacer material may include metal nitrides, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-dielectric-constant dielectric material. The metal oxide may include aluminum oxide (Al₂O₃), zirconium oxide (ZrO₂), tantalum oxide (Ta₂O₅), yttrium oxide (Y₂O₃), titanium oxide (TiO₂), lanthanum oxide (La₂O₃), or other suitable materials. Although not explicitly illustrated, the inner spacer material may be a single layer or multiple layers. In some embodiments, chemical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), subatmospheric pressure chemical vapor deposition, atomic layer deposition, or other suitable methods may be used to deposit the inner spacer material. The spacer material is deposited in the spacer recess 230 and on the sidewalls of the channel layer 208 exposed in the source / drain trench 228. (Refer to...) Figure 9 The deposited inner spacer material is then etched back to remove it from the sidewalls of the channel layer 208, thereby forming an inner spacer component 234 in the inner spacer recess 230. In block 110, the inner spacer material can also be removed from the top surface and / or sidewalls of the top gate hard mask layer 222 and the gate spacer layer 226. For example... Figure 9 As shown, each inner spacer component 234 is in direct contact with the etched sacrificial layer 206 and is disposed perpendicularly between two adjacent channel layers 208 (along the Z direction).

[0101] Although not explicitly illustrated, method 100 may include a cleaning process to clean the surface of the structure 200 in progress before the formation of any epitaxial layer. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include the use of Radio Company of America standard clean 1 (RCASC-1, a mixture of deionized (DI) water, ammonium hydroxide (NH4OH), and hydrogen peroxide (H2O2), RCA standard clean 2 (RCA SC-2, a mixture of deionized water, hydrochloric acid (HCl), and hydrogen peroxide), sulfuric acid-hydrogen peroxide mixture (SPM), and / or hydrofluoric acid (HF) to remove oxides. Dry cleaning processes may include helium (He) and hydrogen (H2) treatment. Hydrogen treatment can convert silicon on the surface into silane (SiH4), which can be pumped out for removal.

[0102] Reference Figure 1 and Figure 10 Method 100 includes block 112, wherein a source / drain component 240 is formed on a source / drain region 212SD. The source / drain component 240 may be N-type or P-type. When the source / drain component 240 is N-type, it may include silicon and N-type dopants (such as phosphorus, arsenic, antimony, or combinations thereof). When the source / drain component 240 is P-type, it may include silicon-germanium and P-type dopants (such as boron or boron difluoride (BF2)). In some embodiments, the source / drain component 240 may include multiple epitaxial layers with different doping concentrations. In some embodiments, the source / drain component 240 may be deposited using molecular beam epitaxy, vapor phase epitaxy, and / or other suitable epitaxial growth processes.

[0103] Reference Figure 1 and Figure 11 Method 100 includes block 114, in which a contact etch stop layer 242 and an interlayer dielectric layer 244 are deposited. (See reference...) Figure 11A contact etch stop layer 242 is deposited on the structure 200 in progress (including on the source / drain components 240). The contact etch stop layer 242 may comprise silicon nitride or aluminum nitride (AlN). In some embodiments, chemical vapor deposition or atomic layer deposition may be used to deposit the contact etch stop layer 242. Then, an interlayer dielectric layer 244 is deposited on the contact etch stop layer 242. In some embodiments, the interlayer dielectric layer 244 comprises a material such as tetraethyl ortho silicate (TEOS) oxide, undoped silicate glass (USG), or silicon oxide-doped material (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials). The interlayer dielectric layer 244 can be deposited using chemical vapor deposition, flow-through chemical vapor deposition, spin coating, or other suitable deposition techniques. After depositing the interlayer dielectric layer 244, the structure 200 in progress can be planarized by a planarization process to expose the dummy gate stack 220.

[0104] Reference Figure 1 and Figure 12 Method 100 includes block 116, wherein an interlayer dielectric layer 244 is etched to form a top recess 2440. To protect the interlayer dielectric layer 244 from damage during the channel release step, the interlayer dielectric layer 244 is etched anisotropically and selectively to form the top recess 2440. In some embodiments, anisotropic etching of the interlayer dielectric layer 244 may include using plasma containing a fluorine-containing gas (e.g., carbon tetrafluoride, sulfur hexafluoride, difluoromethane, trifluoromethane, hexafluoroethane, and / or hexafluoropropene (C3F6)).

[0105] Reference Figure 1 and Figure 13Method 100 includes block 118, in which an ion implantation process 1000 is performed. In some embodiments, the ion implantation process 1000 implants nitrogen (N), germanium, or silicon. In one embodiment, the ion implantation process 1000 implants nitrogen. In some embodiments, the ion implantation process 1000 includes an ion implantation energy between about 0.5 keV and 2 keV. This implantation energy range is not negligible because it represents the desired implantation range to reach the contact etch stop layer 242 without damaging the source / drain components 240. In terms of dosage, the ion implantation process 1000 may include between about 5 × 10⁻⁶ keV. 14 cm -2 and 2×10 15 cm -2 The dosage between [specific parameters]. Because the ion implantation process 1000 is performed after the interlayer dielectric layer 244 and before the capping layer is formed on the top recess 2440, the ion implantation process 1000 can better reach the dangling bonds on the gate spacer layer 226. The ion implantation process 1000 is configured to neutralize the dangling bonds on or around the gate spacer layer 226 without causing unwanted and irreversible damage to adjacent structures.

[0106] Reference Figure 1 and Figure 14 Method 100 includes block 120, in which an annealing process 2000 is performed. Although the parameters of the ion implantation process 1000 are selected to minimize damage, damaged bonds may inevitably occur near or around the gate spacer layer 226. These damaged bonds, if left untreated, may become sources of dangling bonds or oxygen atoms. In block 120, an annealing process 2000 is performed to repair and reduce the damage or defects caused by the ion implantation process 1000. In some embodiments, the annealing process 2000 may include micro sub-second annealing (μssA). In some cases, the annealing process 2000 may include an annealing temperature between about 900°C and 1300°C, and an annealing time between about 100 milliseconds and 10 seconds.

[0107] Reference Figure 1 and Figure 15Method 100 includes block 122, wherein a capping layer 245 is formed on a top recess 2440. In some embodiments, the capping layer 245 may include a dielectric material that allows selective etching of the dummy electrode layer 218, the dummy dielectric layer 216, and the sacrificial layer 206. In some embodiments, the capping layer 245 may include silicon nitride. The function of the capping layer 245 is to protect the interlayer dielectric layer 244 from damage during the removal of the sacrificial layer 206. A planarization process is performed to remove excess capping layer 245 and expose the dummy gate stack 220. After planarization, the top surface of the capping layer 245, the top surface of the contact etch stop layer 242, the top surface of the gate spacer layer 226, and the top surface of the dummy gate stack 220 are coplanar.

[0108] Reference Figure 1 , Figure 16 and Figure 17 Method 100 includes block 124, in which a plurality of channel layers 208 are released as channel members 2080. Operations in block 124 may include removing a dummy gate stack 220 (illustrated in...). Figure 16 (in the middle), and selectively removing the sacrificial layer 206 to release the channel layer 208 (illustrated in Figure 17 (Chinese). First refer to Figure 16 Removal of the dummy gate stack 220 may include one or more etching processes that selectively etch the material of the dummy gate stack 220. For example, selective wet etching, selective dry etching, or a combination thereof may be used to remove the dummy gate stack 220. After removal of the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 212C are exposed. The sacrificial layer 206 between the channel layers 208 is selectively removed in the channel region 212C. The selective removal of the sacrificial layer 206 releases the channel layer 208 to form the channel member 2080 (illustrated in...). Figure 17 (Middle). The sacrificial layer 206 is selectively removed to form a gate trench 246, which includes a spacing between adjacent channel members 2080. The selective removal of the sacrificial layer 206 can be performed by selective dry etching, selective wet etching, or other selective etching processes. Examples of selective dry etching processes may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Examples of selective wet etching processes may include etching with an ammonia-hydrogen peroxide mixture.

[0109] Reference Figure 1 and Figure 18Method 100 includes block 126, wherein a gate structure 250 is formed to surround each channel structure 2080 after release. After the channel structure 2080 is released, the gate structure 250 is formed to surround each channel structure 2080. Although not explicitly shown, the gate structure 250 includes an interface layer to interface the channel structure 2080 and the substrate 202 in the channel region 212C, a gate dielectric layer on the interface layer, and a gate electrode layer on the gate dielectric layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate (HfSiO), or silicon oxynitride. The interface layer may be formed by chemical oxidation or thermal oxidation. The gate dielectric layer may include a high-k dielectric material such as hafnium oxide (HfO2). Alternatively, the gate dielectric layer may comprise other high dielectric constant dielectric materials, such as titanium oxide or hafnium zirconium oxide (HfZrO). x Hafnium oxide, tantalum oxide, hafnium silicon oxide (HfSiO4), zirconium oxide, zirconium silicon oxide (ZrSiO2), lanthanum oxide, aluminum oxide, yttrium oxide, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The gate dielectric layer can be formed by atomic layer deposition, physical vapor deposition (PVD), chemical vapor deposition, oxidation, and / or other suitable methods.

[0110] The gate electrode layer of the gate structure 250 may include a single layer or alternatively a multilayer structure, such as various combinations of metal layers with selected work functions to enhance device performance (work function metal layers), a liner, a wetting layer, an adhesive layer, a metal alloy, or a metal silicide. For example, the gate electrode layer may include titanium nitride, titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode layer may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. In various embodiments, a chemical mechanical polishing process may be performed to remove excess metal, thereby providing a substantially flat top surface for the gate structure 250. The gate structure 250 includes a portion inserted into the channel region 212C between the channel members 2080.

[0111] The ion implantation process 1000 in block 118 and the annealing process 2000 in block 120 reduce dangling bond aggregation along the sidewalls of the gate spacer layer 226. When the interface layer is formed in block 126 using chemical oxidation or thermal oxidation, the interface layer thickness is smaller. Experimental data show that performing the ion implantation process 1000 reduces the effective gate oxide thickness, increases the on-state current, and reduces the channel resistance. Additionally, experimental data also show that the interlayer dielectric layer 244 exhibits compressive stress without the ion implantation process 1000. However, when the ion implantation process 1000 is performed, the interlayer dielectric layer 244 exhibits tensile stress, which helps increase carrier mobility, particularly for P-type fully wound gate transistors.

[0112] Now focus on Figure 19 Method 300.

[0113] Reference Figure 19 and Figure 20 Method 300 includes block 302, wherein a stack 204 of interleaved semiconductor layers is formed on the structure 200 in progress. The operation of block 302 is substantially similar to that of block 102 described above. Therefore, the operational details of block 302 are omitted for simplicity.

[0114] Reference Figure 19 and Figure 21 Method 300 includes block 304, in which a fin structure 212 is formed by stack 204 and substrate 202. The operation of block 304 is substantially similar to that of block 104 described above. Therefore, the operational details of block 304 are omitted for simplicity.

[0115] Reference Figure 19 and Figures 22-24 Method 300 includes block 306, wherein a dummy gate stack 220 is formed on the channel region 212C of the fin structure 212. The operation of block 306 is substantially similar to that of block 106 described above. Therefore, the operational details of block 306 are omitted for simplicity.

[0116] Reference Figure 19 and Figure 25 Method 300 includes block 308, in which the source / drain regions 212SD of the fin structure 212 are anisotropically etched to form source / drain trenches 228. The operation of block 308 is substantially similar to that of block 108 described above. Therefore, the operational details of block 308 are omitted for simplicity.

[0117] Reference Figure 19 and Figure 26 Method 300 includes block 310, wherein a plurality of channel layers 208 are released as channel members 2080 in channel region 212C. After forming source / drain trench 228, sacrificial layers 206 interleaved with the channel layers 208 are selectively removed in channel region 212C. The selective removal of sacrificial layers 206 releases channel layers 208 (illustrated in...). Figure 25 (in the middle) to form channel component 2080 (drawn in Figure 26 (Middle). The sacrificial layer 206 is selectively removed to form a spacing between and around the channel member 2080. The selective removal of the sacrificial layer 206 can be performed by selective dry etching, selective wet etching, or other selective etching processes. Examples of selective dry etching processes may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Examples of selective wet etching processes may include etching with an ammonia-hydrogen peroxide mixture.

[0118] Reference Figure 19 and Figure 27Method 300 includes block 312, wherein a dummy layer 231 is deposited around channel member 2080 and on source / drain trench 228. The dummy layer 231 may include silicon oxide and may be deposited using plasma-assisted chemical vapor deposition or atomic layer deposition. Figure 27 As shown, the dummy layer 231 fills the spacers in the channel member 2080 and covers the sidewall ends of the channel member 2080. Additionally, the dummy layer 231 is in direct contact with the sidewalls of the gate spacer layer 226 and the top surface of the substrate 202. Depending on the design, the channel member 2080 may take the shape of a nanowire, nanosheet, or other nanostructure.

[0119] Reference Figure 19 , Figure 28 and Figure 29 Method 300 includes a block 314 in which an inner spacer component 234 is formed. (See reference...) Figure 28 The dummy layer 231 is selectively and partially etched to form inner spacer recesses 232, while the gate spacer layer 226, the dummy gate stack 220, the exposed portion of the substrate 202, and the channel layer 208 are substantially unetched. In embodiments where the channel layer 208 substantially comprises silicon and the dummy layer 231 is formed of silicon oxide, selective wet etching or selective dry etching processes can be used to selectively etch the dummy layer 231. Examples of selective dry etching processes may include the use of carbon tetrafluoride, nitrogen trifluoride (NF3), hydrogen, or mixtures thereof. Examples of selective wet etching processes may include the use of hydrofluoric acid, ammonium fluoride (NH4F), or mixtures thereof.

[0120] To form the inner spacer component 234, an inner spacer layer is deposited on the structure in progress 200, including on the source / drain trench 228 and the inner spacer recess 232. In some embodiments, the inner spacer layer may include silicon carbonitride, silicon oxycarbonitride, silicon nitride, silicon oxycarbonitride, or silicon oxynitride. In some embodiments, chemical vapor deposition or atomic layer deposition may be used to deposit the inner spacer layer. The deposited inner spacer layer is then etched back to form the inner spacer component 234 in the inner spacer recess 232. In some embodiments, the etch-back may include using a dry etching process (such as reactive ion etching, which is plasma-assisted). Examples of dry etching processes may include using boron trichloride, chlorine, hydrochloric acid, methane (CH4), nitrogen trifluoride, carbon tetrafluoride, sulfur hexafluoride, nitrogen (N2), or combinations thereof.

[0121] Although not explicitly illustrated, prior to the formation of any epitaxial layer, method 300 may include a cleaning process to clean the surfaces of the structure 200 underway, particularly the surfaces of the channel member 2080 and the substrate 202. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include using RCA Standard Clean 1 (a mixture of deionized water, ammonium hydroxide, and hydrogen peroxide), RCA Standard Clean 2 (a mixture of deionized water, hydrochloric acid, and hydrogen peroxide), a sulfuric acid-hydrogen peroxide mixture, and / or hydrofluoric acid to remove oxides. Dry cleaning processes may include helium and hydrogen treatment. Hydrogen treatment may convert silicon on the surface into silanes, which can be pumped out for removal.

[0122] Reference Figure 19 and Figure 30 Method 300 includes block 316, wherein a source / drain component 240 is formed on a source / drain region 212SD. Although not explicitly shown in the figures, the source / drain component 240 may include a bottom epitaxial component and a body epitaxial component on the bottom epitaxial component. The source / drain component 240 may be N-type or P-type. When the source / drain component 240 is N-type, the bottom epitaxial component may include undoped silicon or undoped silicon-germanium, while the body epitaxial component may include silicon and an N-type dopant (such as phosphorus, arsenic, antimony, or a combination thereof). When the source / drain component 240 is P-type, the bottom epitaxial component may include undoped silicon or undoped silicon-germanium, while the body epitaxial component may include silicon-germanium and a P-type dopant (such as boron, boron fluoride, or a combination thereof). As used herein, the semiconductor material is considered undoped when not intentionally doped. In an alternative embodiment, the bottom epitaxial component may include a reverse dopant to reduce leakage current into the body substrate 202. For example, the bottom epitaxial component in the N-type source / drain component 240 may include a P-type dopant (such as boron). In another example, the bottom epitaxial component in the P-type source / drain component 240 may include an N-type dopant (such as phosphorus, arsenic, or antimony). The source / drain component 240 can be formed using vapor phase epitaxy, ultra-high vacuum chemical vapor deposition (UHV-CVD), or molecular beam epitaxy. In-situ doping can be used to achieve doping of the source / drain component 240.

[0123] Reference Figure 19 and Figure 31Method 300 includes block 318, in which a contact etch stop layer 242 and an interlayer dielectric layer 244 are deposited. In block 318, the contact etch stop layer 242 is deposited on the structure in progress 200 (including on the source / drain components 240). The contact etch stop layer 242 may comprise silicon nitride or aluminum nitride. In some embodiments, chemical vapor deposition or atomic layer deposition may be used to deposit the contact etch stop layer 242. The interlayer dielectric layer 244 is then deposited on the contact etch stop layer 242. In some embodiments, the interlayer dielectric layer 244 comprises a material such as tetraethoxysilane oxide, undoped glass silicate, or silicon oxide-doped (such as boron-doped phosphosilicate glass, fused silica glass, phosphosilicate glass, boron-doped glass silicate, and / or other suitable dielectric materials). Chemical vapor deposition, flow-through chemical vapor deposition, spin coating, or other suitable deposition techniques may be used to deposit the interlayer dielectric layer 244. After depositing the interlayer dielectric layer 244, the structure 200 in progress can be planarized by a planarization process to expose the dummy gate stack 220. After the planarization process, the top surface of the dummy gate stack 220, the top surface of the contact etch stop layer 242, the top surface of the interlayer dielectric layer 244, and the top surface of the gate spacer layer 226 are coplanar.

[0124] Reference Figure 19 and Figure 32 Method 300 includes block 320, wherein an interlayer dielectric layer 244 is etched to form a top recess 2440. To protect the interlayer dielectric layer 244 from damage during the channel release step, the interlayer dielectric layer 244 is etched anisotropically and selectively to form the top recess 2440. In some embodiments, anisotropic etching of the interlayer dielectric layer 244 may include using a plasma containing a fluorine-containing gas (e.g., carbon tetrafluoride, sulfur hexafluoride, difluoromethane, trifluoromethane, hexafluoroethane, and / or hexafluoropropylene).

[0125] Reference Figure 19 and Figure 33 Method 300 includes block 322, in which an ion implantation process 1000 is performed. In some embodiments, the ion implantation process 1000 implants nitrogen, germanium, or silicon. In one embodiment, the ion implantation process 1000 implants nitrogen. In some embodiments, the ion implantation process 1000 includes an ion implantation energy between about 0.5 keV and 2 keV. This implantation energy range is not negligible because it represents the required implantation range to reach the contact etch stop layer 242 without damaging the source / drain components 240. In terms of dosage, the ion implantation process 1000 may include between about 5 × 10⁻⁶ keV. 14 cm -2 and 2×10 15 cm -2The dosage between [specific parameters]. Because the ion implantation process 1000 is performed after the interlayer dielectric layer 244 and before the capping layer is formed on the top recess 2440, the ion implantation process 1000 can better reach the dangling bonds on the gate spacer layer 226. The ion implantation process 1000 is configured to neutralize the dangling bonds on or around the gate spacer layer 226 without causing unwanted and irreversible damage to adjacent structures.

[0126] Reference Figure 19 and Figure 34 Method 300 includes block 324, in which an annealing process 2000 is performed. Although the parameters of the ion implantation process 1000 are selected to minimize damage, damaged bonds may inevitably occur near or around the gate spacer layer 226. These damaged bonds, if left untreated, may become sources of dangling bonds or oxygen atoms. In block 324, an annealing process 2000 is performed to repair and reduce the damage or defects caused by the ion implantation process 1000. In some embodiments, the annealing process 2000 may include microsecond annealing. In some cases, the annealing process 2000 may include an annealing temperature between about 900°C and 1300°C, and an annealing time between about 100 milliseconds and 10 seconds.

[0127] Reference Figure 19 and Figure 35 Method 300 includes block 326, wherein a capping layer 245 is formed on a top recess 2440. In some embodiments, the capping layer 245 may include a dielectric material that allows selective etching of the dummy electrode layer 218, the dummy dielectric layer 216, and the sacrificial layer 206. In some embodiments, the capping layer 245 may include silicon nitride. The function of the capping layer 245 is to protect the interlayer dielectric layer 244 from damage during the removal of the dummy layer 231. A planarization process is performed to remove excess capping layer 245 and expose the dummy gate stack 220. After planarization, the top surface of the capping layer 245, the top surface of the contact etch stop layer 242, the top surface of the gate spacer layer 226, and the top surface of the dummy gate stack 220 are coplanar.

[0128] Reference Figure 19 and Figures 36-38 Method 300 includes block 328, wherein a dummy gate stack 220 and a dummy layer 231 are replaced with a gate structure 250. The operation at block 328 may include removing the dummy gate stack 220 (illustrated in…). Figure 36 (middle), remove virtual layer 231 (drawn in) Figure 37 (in the middle), and deposited gate structure 250 to surround each channel member 2080 (illustrated in ...). Figure 38(Middle). At the end of the operation in block 326, a planarization process is performed to expose the dummy gate stack 220. Exposing the dummy gate stack 220 allows it to be removed. Removal of the dummy gate stack 220 may include one or more etching processes that selectively target the material of the dummy gate stack 220. For example, the dummy gate stack 220 may be removed using selective wet etching, selective dry etching, or a combination thereof. Figure 36 As shown, after removing the dummy gate stack 220, the channel component 2080 and the dummy layer 231 are exposed in the channel region 212C.

[0129] After removing the dummy gate stack 220, individual etching processes can be performed to selectively remove the dummy layer 231 in the channel region 212C. For example, selective wet etching or selective dry etching processes can be performed to remove the dummy layer 231. Examples of selective wet etching processes may include using diluted hydrofluoric acid, or a mixture of hydrofluoric acid and ammonium fluoride. Examples of selective dry etching processes may include using anhydrous hydrogen fluoride vapor, trifluoromethane, nitrogen trifluoride, hydrogen, ammonia (NH3), carbon tetrafluoride, sulfur hexafluoride, or combinations thereof. In one embodiment, a selective wet etching process is used at block 328. After the selective removal of the dummy layer 231, the channel member 2080 in the channel region 212C is exposed again, as shown. Figure 37 As shown.

[0130] After the channel member 2080 is released, a gate structure 250 is formed to surround each channel member 2080, such as Figure 38 As shown. Although not explicitly illustrated, gate structure 250 includes an interface layer to interface channel structure 2080 and substrate 202 in channel region 212C, a gate dielectric layer on the interface layer, and a gate electrode layer on the gate dielectric layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition, chemical vapor deposition, and / or other suitable methods. The gate dielectric layer may include a high dielectric constant dielectric material such as hafnium oxide. Alternatively, the gate dielectric layer may include other high dielectric constant dielectric materials such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium oxide, lanthanum oxide, aluminum oxide, yttrium oxide, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, combinations thereof, or other suitable materials. The gate dielectric layer can be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, oxidation, and / or other suitable methods.

[0131] The gate electrode layer of gate structure 250 may include a multilayer structure, such as various combinations of metal layers having a selected work function to enhance device performance (work function metal layer), a substrate, a wetting layer, an adhesive layer, a metal alloy, or a metal silicide. For example, the gate electrode layer may include titanium nitride, aluminum titanium nitride, aluminum titanium nitride, tantalum nitride, aluminum tantalum nitride, aluminum tantalum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, tantalum silicon nitride, copper, other refractory metals, other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode layer may be formed by atomic layer deposition, physical vapor deposition, chemical vapor deposition, electron beam evaporation, or other suitable processes. In various embodiments, a chemical mechanical polishing process may be performed to remove excess metal, thereby providing a substantially flat top surface for gate structure 250. Gate structure 250 includes a portion inserted between channel members 2080 in channel region 212C. In some embodiments, the gate structure 250 may include a P-type gate structure portion and an N-type gate structure portion. The P-type gate structure portion includes a P-type work function metal layer disposed near the channel member 2080. The N-type gate structure portion includes an N-type work function metal layer disposed near the channel member 2080.

[0132] In one exemplary aspect, this invention relates to a method for forming a semiconductor device. The method for forming the semiconductor device includes a receiving structure. The structure includes: a source / drain component sandwiched between a first channel region and a second channel region; a first dummy gate stack on the first channel region; a first gate spacer extending along the sidewall of the first dummy gate stack; a second dummy gate stack on the second channel region; a second gate spacer extending along the sidewall of the second dummy gate stack; and an interlayer dielectric layer on the source / drain component and disposed between the first gate spacer and the second gate spacer. The method for forming the semiconductor device further includes: selectively etching the interlayer dielectric layer to form a top recess; performing an ion implantation process on the structure after the selective etching; and forming a capping layer in the top recess after the ion implantation process.

[0133] In some embodiments, the ion implantation process implants nitrogen, germanium, or silicon. In some embodiments, the method of forming a semiconductor device further includes performing an annealing process after the ion implantation process. In some embodiments, the annealing process includes a microsecond annealing process. In some embodiments, the ion implantation process and the annealing process are configured to obtain tensile stress in the interlayer dielectric layer. In some embodiments, the ion implantation process includes implantation energy between 0.5 keV and 2 keV. In some embodiments, the ion implantation process includes implantation energy between 0.5 × 10⁻⁶ keV and 0.5 × 10⁻⁶ keV. 14 and 2×10 15The implantation dose between the two gate spacers. In some embodiments, the ion implantation process is configured to remove dangling bonds along the surfaces of the first gate spacer and the second gate spacer. In some embodiments, the structure further includes a contact etch stop layer extending from between the first gate spacer and the interlayer dielectric layer, to between the interlayer dielectric layer and the source / drain components, and then to between the second gate spacer and the interlayer dielectric layer. In some embodiments, the capping layer comprises silicon nitride.

[0134] In another exemplary aspect, the present invention relates to a method for forming a semiconductor device. The method for forming the semiconductor device includes a receiving structure. The structure includes: a source / drain component sandwiched between a first channel region and a second channel region; each of the first and second channel regions includes a plurality of channel layers and a plurality of sacrificial layers alternately disposed; a first dummy gate stack on the first channel region; a first gate spacer extending along the sidewall of the first dummy gate stack; a second dummy gate stack on the second channel region; a second gate spacer extending along the sidewall of the second dummy gate stack; and an interlayer dielectric layer on the source / drain component and disposed between the first gate spacer and the second gate spacer. The method for forming a semiconductor device further includes: selectively etching an interlayer dielectric layer to form a trench; performing an ion implantation process on the structure after selective etching; performing an annealing process; forming a capping layer in the trench after the annealing process; removing a first dummy gate stack and a second dummy gate stack; selectively removing a sacrificial layer in a first channel region and a second channel region; and forming a first gate structure to surround each channel layer in the first channel region, and forming a second gate structure to surround each channel layer in the second channel region.

[0135] In some embodiments, the sacrificial layer comprises silicon germanium. In some embodiments, the sacrificial layer comprises silicon oxide. In some embodiments, an ion implantation process implants nitrogen, germanium, or silicon. In some embodiments, the annealing process comprises a microsecond annealing process.

[0136] In another exemplary aspect, the present invention relates to a method for forming a semiconductor device. The method for forming a semiconductor device includes a receiving structure. The structure includes: a source / drain component sandwiched between a first channel region and a second channel region; a first dummy gate stack on the first channel region; a first gate spacer extending along the sidewall of the first dummy gate stack; a second dummy gate stack on the second channel region; a second gate spacer extending along the sidewall of the second dummy gate stack; a contact etch stop layer extending along the sidewall of the first gate spacer, the top surface of the source / drain component, and the sidewall of the second gate spacer; and an interlayer dielectric layer on the contact etch stop layer. The method for forming the semiconductor device further includes: selectively etching the interlayer dielectric layer to form a top recess; performing an ion implantation process on the structure after the selective etching; performing an annealing process after the ion implantation process; and forming a capping layer in the top recess layer after the annealing process.

[0137] In some embodiments, the ion implantation process implants nitrogen, germanium, or silicon. In some embodiments, the annealing process includes a microsecond annealing process. In some embodiments, the ion implantation process includes implantation energies between 0.5 keV and 2 keV. In some embodiments, the ion implantation process includes implantation energies between 5 × 10⁻⁶ and 10⁻⁶ keV. 14 and 2×10 15 The dosage between the two.

[0138] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the viewpoints of the embodiments of this utility model. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of this utility model to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this utility model, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of this utility model.

Claims

1. A semiconductor device, characterized by comprising: include: A source / drain component is sandwiched between a first channel region and a second channel region, each of the first channel region and the second channel region including a plurality of channel components; A first gate structure surrounds each channel component in the first channel region; A second gate structure surrounds each channel member in the second channel region; An interlayer dielectric layer is applied to the source / drain component; as well as A capping layer is disposed on the interlayer dielectric layer and between the first gate structure and the second gate structure.

2. The semiconductor device according to claim 1, wherein The top surface of the capping layer, the top surface of the first gate structure, and the top surface of the second gate structure are coplanar.

3. The semiconductor device according to claim 1, wherein Including: A first gate spacer extends along the sidewall of the first gate structure; and A second gate spacer extends along the sidewall of the second gate structure.

4. The semiconductor device according to claim 3, wherein Including: A contact etch stop layer extends from between the first gate spacer and the interlayer dielectric layer to between the interlayer dielectric layer and the source / drain component, and then to between the second gate spacer and the interlayer dielectric layer.

5. The semiconductor device according to claim 4, wherein The contact etch stop layer further extends between the first gate spacer and the capping layer, and between the second gate spacer and the capping layer.

6. The semiconductor device according to claim 5, wherein The top surface of the capping layer, the top surface of the contact etch stop layer, the top surface of the first gate spacer, the top surface of the second gate spacer, the top surface of the first gate structure, and the top surface of the second gate structure are coplanar.

7. The semiconductor device according to claim 1, wherein Including: Multiple inner spacer components are vertically disposed between two adjacent channel members in the first channel area and between two adjacent channel members in the second channel area.

8. The semiconductor device as claimed in claim 7, characterized in that, The plurality of inner spacer components are in direct contact with the first gate structure in the first channel region and in direct contact with the second gate structure in the second channel region.

9. The semiconductor device according to claim 8, wherein The plurality of internal spacer components separate the source / drain component from the first gate structure and separate the source / drain component from the second gate structure.

10. The semiconductor device according to claim 1, wherein The source / drain component extends vertically through the depth of the multiple channel components and partially enters a substrate.

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