Integrated circuit chip device

Abstract

An integrated circuit chip device includes: first and second opposite long sides; first and second opposite short sides; a surface surrounded by the four sides; a full pin array disposed on the surface and including a first sub-full pin array and a second sub-full pin array, the pins of the first sub-full pin array disposed adjacent and parallel to the first long side, the pins of the second sub-full pin array disposed extending obliquely toward a junction of the second long side and the first short side; and a reduced pin array disposed on the surface and including a first sub-reduced pin array and a second sub-reduced pin array, the pins of the first sub-reduced pin array disposed parallel to the first sub-full pin array, the pins of the second sub-reduced pin array disposed extending parallel to the second sub-full pin array, wherein a length of the second sub-reduced pin array is less than a length of the second sub-full pin array.

Description

Technical Field

[0001] This utility model relates to an integrated circuit chip, and more particularly to an integrated circuit chip device that can reduce chip size. Background Technology

[0002] Figure 1 The diagram schematically shows an existing display panel, which includes a glass substrate 10. The active area 101 on the glass substrate 10 has a plurality of pixels for display, touch or fingerprint recognition and other functions. The non-display area from the lower side of the active area 101 to the lower edge of the glass substrate 10 is defined as a border area 102. An integrated circuit chip 15 may be disposed on the border area 102. The external pins 151 of the integrated circuit chip 15 are connected to the data line 121 of the active area 101 to control the display, touch or fingerprint recognition and other operations of the active area 101.

[0003] At Figure 1 In a display panel, the size of its boundary area 102 is related to the screen ratio of the display panel. In particular, mobile phone products require a high screen ratio to improve the appearance of the product. Therefore, reducing the boundary area 102 has become a very important product specification. However, the existing pin design of the integrated circuit chip 15 places all the external pins 151 on one side of the integrated circuit chip 15 close to the display active area 101. With this pin design, the area required for wire take-up is large, which makes it impossible to reduce the boundary area 102.

[0004] To address the aforementioned problem of the inability to shrink the boundary region 102, a known solution is to reduce the number of data lines 121 in the active display area 101 by switching multiplexers, thereby correspondingly reducing the number of external pins 151 connected to the data lines 121. The reduction in the number of external pins 151 shrinks the area required for line take-up, thus reducing the boundary region 102. However, the additional multiplexer not only increases costs but also complicates circuit control, making it unsuitable for display panels using, for example, amorphous silicon (a-Si) technology, and thus failing to meet practical requirements.

[0005] Therefore, the current design of integrated circuit chip devices cannot meet the requirements of high screen-to-body ratio for display panels, and there is a need to improve them. Utility Model Content

[0006] The purpose of this invention is to provide an integrated circuit chip device to address the deficiencies of the aforementioned prior art, particularly to increase the screen-to-body ratio of display devices.

[0007] To achieve the aforementioned objectives, this utility model proposes an integrated circuit chip device for a display panel. The integrated circuit chip device includes: a first long side and a second long side facing the first long side; a first short side and a second short side facing the first short side; a surface surrounded by the first long side, the second long side, the first short side, and the second short side; and at least one complete external pin array disposed on the surface. The complete external pin array includes a first sub-complete external pin array having a plurality of spaced-apart external pins and a second sub-complete external pin array having a plurality of spaced-apart external pins. The external pins of the first sub-complete external pin array are positioned adjacent to and along the first long side, and the external pins of the second sub-complete external pin array are positioned facing the first long side from the first sub-complete external pin array. One end of the short side extends obliquely towards the first short side adjacent to the junction of the second long side and the first short side; and at least one reduced outer pin array is disposed on the surface, the reduced outer pin array including a first sub-reduced outer pin array having a plurality of spaced-apart outer pins and a second sub-reduced outer pin array having a plurality of spaced-apart outer pins, the outer pins of the first sub-reduced outer pin array being disposed between the first sub-complete outer pin array and the second long side, the outer pins of the second sub-reduced outer pin array being configured to extend from the end of the first sub-reduced outer pin array facing the first short side at a distance from the second sub-complete outer pin array towards the second long side adjacent to the junction of the second long side and the first short side, wherein the length of the second sub-reduced outer pin array is less than the length of the second sub-complete outer pin array. Preferably, the outer pins of the aforementioned first sub-complete outer pin array can be disposed adjacent to and parallel to the first long side. Preferably, the outer pins of the aforementioned first sub-reduced outer pin array can also be parallel to the first sub-complete outer pin array, and the outer pins of the second sub-reduced outer pin array can preferably be parallel to the second sub-complete outer pin array.

[0008] The above overview and the following detailed description are illustrative in nature, and other objects and advantages of this utility model will be explained in the following description and drawings. Attached Figure Description

[0009] Figure 1 An existing integrated panel is shown schematically.

[0010] Figure 2 This schematically illustrates an integrated circuit chip device according to an embodiment of the present invention.

[0011] Figure 3 This schematically illustrates an integrated circuit chip device according to another embodiment of the present invention.

[0012] Figure 4 This schematically illustrates an integrated circuit chip device according to another embodiment of the present invention.

[0013] Figure 5This schematically illustrates an integrated circuit chip device according to another embodiment of the present invention.

[0014] Symbol explanation: Glass substrate 10 Display active area 101 Boundary area 102 Integrated circuit chip 15 External pin 151 Data line 121 Integrated circuit chip device 2 Display Panel 1 First longer side L1 Second longer side L2 First shorter side S Second short side S2 Surface 21 External pins 201, 201' Complete external pinout 25 First complete external pinout 25(1) Second complete external pin row 25(2) Reduced external pin header 26 First reduced external pinout 26(1) Second reduced external pin row 26(2) The third reduced external pin row 26(3) First complete external pinout 25-1 The second complete external pin row is 25-2, 25(1)-2, 25(2)-2 First sub-reduction external pin row 26-1 The second sub-reduction outer pin row is 26-2, 26(1)-2, 26(2)-2, 26(3)-2 Third child complete external pinout 25-3 Third child reduced external pin row 26-3 Detailed Implementation To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the implementation of this utility model and are not intended to limit the scope of this utility model.

[0015] Figure 2The diagram schematically illustrates an integrated circuit chip device 20 according to an embodiment of the present invention. The integrated circuit chip device 20 is used in a display panel 1, such as an amorphous silicon (a-Si) display panel, and includes a glass substrate 10 and a display active area 101 disposed on the glass substrate. The non-display area from the lower side of the display active area 101 to the lower edge of the glass substrate 10 is defined as a boundary region 102, and the integrated circuit chip device 20 is disposed on this boundary region 102. The integrated circuit chip device 20 includes: a first long side L1 and a second long side L2 opposite to the first long side L1; a first short side S1 and a second short side S2 opposite to the first short side S1; a surface 21 surrounded by the first long side L1, the second long side L2, the first short side S1, and the second short side S2; at least one complete external lead array 25 disposed on the surface 21; and at least one reduced external lead array 26 disposed on the surface 21. For clarity, Figure 2 The diagram shows only a complete external pinout 25 and a reduced external pinout 26, but this invention is not limited thereto. In practical applications, the number of both the complete external pinout 25 and the reduced external pinout 26 can be greater than two. Furthermore, the integrated circuit chip device 20 is disposed on the glass substrate 10 with its first long side L1 adjacent to the display active area 101.

[0016] The aforementioned complete external pin array 25 includes a first sub-complete external pin array 25-1 and a second sub-complete external pin array 25-2. The first sub-complete external pin array 25-1 has a plurality of spaced-apart external pins 201, and the second sub-complete external pin array 25-2 also has a plurality of spaced-apart external pins 201. The external pins 201 of the first sub-complete external pin array 25-1 are positioned adjacent to and along the first long side L1, while the external pins 201 of the second sub-complete external pin array 25-2 are positioned to extend obliquely from one end of the first sub-complete external pin array 25-2 facing the first short side S1 towards the first short side S1 adjacent to the junction of the second long side L2 and the first short side S1. It is worth noting that the plurality of external pins of the aforementioned first sub-complete external pin array 25-1 and second sub-complete external pin array can be spaced equidistantly or non-equidistantly according to design requirements. In the aforementioned embodiment, the external pins 201 of the first sub-complete external pin array 25-1 are preferably positioned parallel to the first long side L1. In one embodiment, the second sub-complete external pin array 25-2 may extend at an angle A of approximately 5 degrees toward the connection between the second long side L2 and the first short side S1, where angle A is the horizontal angle between the extended dashed lines of the second sub-complete external pin array 25-2 and the first sub-complete external pin array 25-1. By arranging the pins of the second sub-complete external pin array 25-2 at an angle toward the connection between the second long side L2 and the first short side S1, the external pins 201 of the second sub-complete external pin array 25-2 can be recessed toward the boundary region 102, thus freeing up more surface space around the connection between the first short side S1 and the first long side L1 (the boundary region 102 adjacent to the display area 101), which can be used for signal routing layout, thereby effectively improving the screen ratio.

[0017] The aforementioned reduced outer pin array 26 includes a first sub-reduced outer pin array 26-1 and a second sub-reduced outer pin array 26-2. The first sub-reduced outer pin array 26-1 has a plurality of spaced outer pins 201, and the second sub-reduced outer pin array 26-2 has a plurality of spaced outer pins 201. The outer pins 201 of the first sub-reduced outer pin array 26-1 may be configured to be spaced apart from (e.g. parallel to) the first sub-complete outer pin array 25-1 and located between the first sub-complete outer pin array 25-1 and the second long side L2. The outer pins 201 of the second sub-reduced outer pin array 26-2 may be configured to extend from one end of the first sub-reduced outer pin array 26-1 facing the first short side S1 at a distance spaced apart from (e.g. parallel to) the second sub-complete outer pin array 25-2 to the second long side L2 adjacent to the connection point between the second long side L2 and the first short side S1. The length of the second sub-reduced outer pin array 26-2 is less than the length of the second sub-complete outer pin array 25-2. In one embodiment, the majority of external pins 201 included in the complete external pin row 25 and the reduced external pin row 26 are arranged at equal intervals. Therefore, the number of external pins 201 in the aforementioned second sub-reduced external pin row 26-2 is less than the number of external pins 201 in the second sub-complete external pin row 25-2. However, the present invention is not limited thereto. In another embodiment, the interval between the external pins 201 in the second sub-reduced external pin row 26-2 may be less than the interval between the external pins 201 in the second sub-complete external pin row 25-2, so that although the length of the second sub-reduced external pin row 26-2 is less than the length of the second sub-complete external pin row 25-2, the number of external pins 201 in the second sub-reduced external pin row 26-2 may still be the same as the number of external pins 201 in the second sub-complete external pin row 25-2.

[0018] In the aforementioned embodiments, the first and second sub-reduced outer pin arrays 26-1, 26-2 and the first and second sub-complete outer pin arrays 25-1, 25-2 can be arranged and extended in a parallel manner. However, in other embodiments, the first and second sub-reduced outer pin arrays 26-1, 26-2 and the first and second sub-complete outer pin arrays 25-1, 25-2 can also be arranged at an appropriate interval, rather than in a parallel manner. For example, the second sub-reduced outer pin array 26-2 and the second sub-complete outer pin array 25-2 are arranged at non-equidistant intervals and extend towards the second long side L1 and the first short side S1, respectively, where the second long side L2 and the first short side S1 connect. The second sub-reduced outer pin array 26-2 can also extend towards the second long side L2 and the first short side S1 at an angle B of approximately 5 degrees, where angle B is the horizontal angle between the extended dashed lines of the second sub-reduced outer pin array 26-2 and the first sub-reduced outer pin array 26-1. By arranging the pins of the second sub-reduced external pin array 26-2 at an angle towards the connection between the second long side L2 and the first short side S1, the external pins 201 of the second sub-reduced external pin array 26-2 can be recessed into the boundary region 102, freeing up the surface around the connection between the first short side S1 and the first long side L1 (the boundary region 102 adjacent to the display region 101) for signal routing layout, thereby effectively improving the screen ratio.

[0019] Furthermore, such as Figure 2As shown, the aforementioned complete external pin array 25 may also include a third sub-complete external pin array 25-3. The third sub-complete external pin array 25-3 has a plurality of spaced external pins 201. The external pins 201 of the third sub-complete external pin array 25-3 are configured to extend obliquely from one end of the first sub-complete external pin array 25-1 facing the second short side S2 to the second short side S2 adjacent to the connection between the second long side L2 and the second short side S1. The aforementioned reduced outer pin row 26 may also include a third sub-reduced outer pin row 26-3. The third sub-reduced outer pin row 26-3 has a plurality of spaced outer pins 201. The outer pins 201 of the third sub-reduced outer pin row 26-3 are configured to extend from one end of the first sub-reduced outer pin row 26-1 facing the second short side S2 at a distance from (e.g., parallel to) the third sub-complete outer pin row 25-3 to the second long side L2 adjacent to the connection between the second long side L2 and the second short side S2. Furthermore, the inclined extension angle of the third sub-complete outer pin row 25-3 and the third sub-reduced outer pin row 26-3 may be similar to the inclined extension angle of the second sub-complete outer pin row 25-2 and the second sub-reduced outer pin row 26-2, so it will not be described in detail again. As mentioned above, in other embodiments, the third sub-reduced outer pin array 26-3 and the third sub-complete outer pin array 25-3 can also be arranged in a non-parallel manner. For example, the outer pins 201 of the third sub-reduced outer pin array 26-3 and the third sub-complete outer pin array 25-3 are arranged in a non-equidistant manner, extending towards the second long side L2 and the second short side S2, respectively, at the connection point of the second long side L2 and the second short side S2. Figure 2 In this configuration, the full external pin array 25 and the reduced external pin array 26 are arranged in a slightly parallel manner. However, the full external pin array 25 and the reduced external pin array 26 can also be arranged in a non-parallel manner. For example, the full external pin array 25 and the reduced external pin array 26 can be arranged in a suitable non-equidistant manner. The second sub-full external pin array 25-2 and the second sub-reduced external pin array 26-2, as well as the third sub-full external pin array 25-3 and the third sub-reduced external pin array 26-3 extend at an angle in the opposite direction to the first sub-full external pin array 25-1 and the first sub-reduced external pin array 26-1, respectively.

[0020] Similar to the arrangement of the second sub-reduced outer pin array 26-2 and the second sub-complete outer pin array 25-2, the length of the third sub-reduced outer pin array 26-3 is less than the length of the third sub-complete outer pin array 25-3. In one embodiment, the majority of outer pins 201 included in the complete outer pin array 25 and the reduced outer pin array 26 are arranged at equal intervals. Therefore, the number of outer pins 201 in the aforementioned third sub-reduced outer pin array 26-3 is less than the number of outer pins 201 in the third sub-complete outer pin array 25-3. In another embodiment, the interval between the outer pins 201 in the third sub-reduced outer pin array 26-3 may be less than the interval between the outer pins 201 in the third sub-complete outer pin array 25-3, such that although the length of the third sub-reduced outer pin array 26-3 is less than the length of the third sub-complete outer pin array 25-3, the number of outer pins 201 in the third sub-reduced outer pin array 26-3 may still be the same as the number of outer pins 201 in the third sub-complete outer pin array 25-3. In one embodiment, the outer pins 201 of the full outer pin row 25 and the outer pins 201 of the reduced outer pin row 26 may also be arranged at non-equidistant intervals, so that the full outer pin row 25 and the reduced outer pin row 26 can be arranged in a non-parallel manner.

[0021] Furthermore, where the surface 21 of the integrated circuit chip device 202 does not have a complete external pin array 25 and a reduced external pin array 26, additional external pins 201' can be provided, such as... Figure 2 As shown, a plurality of external pins 201' can be provided on the surface 21 adjacent to the second long side L2. These plurality of external pins 201' can be used as power supply, control, interface, voltage regulation or ground pins.

[0022] Figure 3 This schematically illustrates an integrated circuit chip device 20 according to another embodiment of the present invention, which is similar to... Figure 2 The embodiment differs in that the complete external pin array 25 in this embodiment includes a first sub-complete external pin array 25-1 and a second sub-complete external pin array 25-2, and the reduced external pin array 26 includes a first sub-reduced external pin array 26-1 and a second sub-reduced external pin array 26-2. Furthermore, the end of the first sub-complete external pin array 25-1 facing the second short side S2 extends vertically to the vicinity of the second short side S2, and the end of the first sub-reduced external pin array 26-1 facing the second short side S2 also extends vertically to the vicinity of the second short side S2. Therefore, the first sub-complete external pin array 25-1 and the first sub-reduced external pin array 26-1 in this embodiment can be relatively... Figure 2 In this embodiment, the first full external pinout 25-1 and the first reduced external pinout 26-1 are of length. Other features and effects of this embodiment are applicable to... Figure 2 The description of the embodiments is omitted here.

[0023] Figure 4 This schematically illustrates an integrated circuit chip device 20 according to another embodiment of the present invention, which is similar to... Figure 2 The embodiment differs in that the complete external pin array 25 in this embodiment includes a first sub-complete external pin array 25-1 and a third sub-complete external pin array 25-3, and the reduced external pin array 26 includes a first sub-reduced external pin array 26-1 and a third sub-reduced external pin array 26-3. Furthermore, the end of the first sub-complete external pin array 25-1 facing the first short side S1 extends vertically to a position adjacent to the first short side S1, and the end of the first sub-reduced external pin array 26-1 facing the first short side S1 also extends vertically to a position adjacent to the first short side S1. Therefore, the first sub-complete external pin array 25-1 and the first sub-reduced external pin array 26-1 in this embodiment can be relatively... Figure 2 In this embodiment, the first full external pinout 25-1 and the first reduced external pinout 26-1 are of length. Other features and effects of this embodiment are applicable to... Figure 2 The description of the embodiments is omitted here.

[0024] Figure 5 This schematically illustrates an integrated circuit chip device 20 according to another embodiment of the present invention, which is similar to... Figure 2 The embodiment differs in that Figure 5 The diagram shows that at least one complete external pin array 25 includes a first complete external pin array 25(1) and a second complete external pin array 25(2), and at least one reduced external pin array 26 includes a first reduced external pin array 26(1), a second reduced external pin array 26(2), and a third reduced external pin array 26(3). The second complete external pin array 25(2) is disposed between the first complete external pin array 25(1) and the at least one reduced external pin array 26, and the length of the second sub-complete external pin array 25(1)-2 included in the first complete external pin array 25(1) is equal to the length of the second sub-complete external pin array 25(2)-2 included in the second complete external pin array 25(2).

[0025] The aforementioned first reduced outer pin array 26(1) is disposed between the second reduced outer pin array 26(2) and at least one complete outer pin array 25. The length of the second sub-reduced outer pin array 26(2)-2 included in the second reduced outer pin array 26(2) is less than the length of the second sub-reduced outer pin array 26(1)-2 included in the first reduced outer pin array 26(1). The second reduced outer pin array 26(2) is disposed between the first reduced outer pin array 26(1) and the third reduced outer pin array 26(3). The length of the second sub-reduced outer pin array 26(3)-2 included in the third reduced outer pin array 26(3) is less than the length of the second sub-reduced outer pin array 26(2)-2 included in the second reduced outer pin array 26(2). Other features and effects of this embodiment can be applied to... Figure 2The description of the embodiments is omitted here.

[0026] As can be seen from the above description, this utility model reduces the length and number of external pins of a portion of the external pin arrays. Since the reduced length of the external pin arrays does not occupy the short side length of the integrated circuit chip, the chip size can be reduced, and the boundary area can be further reduced. Moreover, the reduced external pins can be dummy pads of the integrated circuit chip, so they will not affect the electrical operation of the integrated circuit chip.

Claims

1. An integrated circuit chip device for a display panel, characterized in that, The integrated circuit chip device includes: A first long side and a second long side opposite to the first long side; A first short side and a second short side opposite to the first short side; A surface surrounded by the first long side, the second long side, the first short side, and the second short side; At least one complete external pin array is disposed on the surface. The complete external pin array includes a first sub-complete external pin array having a plurality of spaced-apart external pins and a second sub-complete external pin array having a plurality of spaced-apart external pins. The external pins of the first sub-complete external pin array are configured to be adjacent to and along the first long side, and the external pins of the second sub-complete external pin array are configured to extend obliquely from one end of the first sub-complete external pin array facing the first short side toward the first short side adjacent to the junction of the second long side and the first short side; and At least one reduced outer pin array is disposed on the surface. The reduced outer pin array includes a first sub-reduced outer pin array having a plurality of spaced-apart outer pins and a second sub-reduced outer pin array having a plurality of spaced-apart outer pins. The outer pins of the first sub-reduced outer pin array are disposed between the first sub-complete outer pin array and the second long side. The outer pins of the second sub-reduced outer pin array are configured to extend from one end of the first sub-reduced outer pin array facing the first short side, spaced apart from the second sub-complete outer pin array, towards the second long side adjacent to the junction of the second long side and the first short side. The length of the second sub-reduced outer pin array is less than the length of the second sub-complete outer pin array.

2. The integrated circuit chip device as described in claim 1, characterized in that, The second sub-reduced outer pin row has fewer outer pins than the second sub-full outer pin row.

3. The integrated circuit chip device as described in claim 1, characterized in that, The complete external pin array also includes a third sub-complete external pin array having a plurality of spaced external pins, wherein the external pins of the third sub-complete external pin array are configured to extend obliquely from one end of the first sub-complete external pin array facing the second short side toward the second short side adjacent to the junction of the second long side and the second short side.

4. The integrated circuit chip device as described in claim 3, characterized in that, The reduced outer pin array also includes a third sub-reduced outer pin array having a plurality of spaced outer pins, wherein the outer pins of the third sub-reduced outer pin array are configured to extend from one end of the first sub-reduced outer pin array facing the second short side at a distance from the third sub-complete outer pin array to the second long side adjacent to the junction of the second long side and the second short side.

5. The integrated circuit chip device as described in claim 4, characterized in that, The length of the third sub-reduced outer pin array is less than the length of the third sub-complete outer pin array.

6. The integrated circuit chip device as described in claim 5, characterized in that, The third sub-reduced outer pin row has fewer outer pins than the third sub-full outer pin row.

7. The integrated circuit chip device as claimed in claim 1, characterized in that, The at least one complete external pinout includes a first complete external pinout and a second complete external pinout, the second complete external pinout being disposed between the first complete external pinout and the at least one reduced external pinout, and the length of the second sub-complete external pinout included in the first complete external pinout is equal to the length of the second sub-complete external pinout included in the second complete external pinout.

8. The integrated circuit chip device as claimed in claim 1, characterized in that, The at least one reduced external pinout includes a first reduced external pinout and a second reduced external pinout, the first reduced external pinout being disposed between the second reduced external pinout and the at least one complete external pinout, and the length of the second sub-reduced external pinout included in the second reduced external pinout is less than the length of the second sub-reduced external pinout included in the first reduced external pinout.

9. The integrated circuit chip device as claimed in claim 8, characterized in that, The at least one reduced external pin array further includes a third reduced external pin array, the second reduced external pin array being disposed between the first reduced external pin array and the third reduced external pin array, wherein the length of the second sub-reduced external pin array included in the third reduced external pin array is less than the length of the second sub-reduced external pin array included in the second reduced external pin array.

10. The integrated circuit chip device as claimed in claim 1, characterized in that, The display panel includes a glass substrate and a display active area disposed on the glass substrate, the integrated circuit chip device is disposed on the glass substrate and the first long side is adjacent to the display active area.

Images