Display panel and display device

Abstract

The display panel comprises a substrate, a first metal layer, a second metal layer, a semiconductor layer and a third metal layer which are sequentially arranged on the substrate; the first metal layer comprises a first electrode plate of a first capacitor, the second metal layer comprises a second electrode plate of the first capacitor, and the third metal layer comprises a gate electrode of a driving transistor; the first electrode plate of the first capacitor and the gate electrode of the driving transistor are electrically connected; the display panel further comprises a first fan-out data line and a first low-voltage power supply signal line extending in a first direction, and a second low-voltage power supply signal line and a data signal line extending in a second direction; the first direction and the second direction intersect; at least one of the first fan-out data line and the first low-voltage power supply signal line and the second low-voltage power supply signal line is arranged in the same layer; and the first fan-out data line is configured to be connected to at least one data signal line.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display panel and a display device. Background Technology

[0002] With the development of display technology, Active-Matrix Organic Light-Emitting Diode (AMOLED) has been increasingly used in display devices such as mobile phones, tablets, and digital cameras due to its advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Therefore, AMOLED has a promising future. As display technology continues to advance, flexible displays using AMOLED as the light-emitting device and thin-film transistors (TFTs) for signal control have become the mainstream products in the display field. Optimizing the display effect of display devices has become an inevitable trend. For example, with the increasing pursuit of visual effects in display products, high resolution (PPI, pixels per inch) and narrow bezels are gradually becoming the development trend of OLED display products. Utility Model Content

[0003] Embodiments of this disclosure relate to a display panel and a display device. The display panel combines metal oxide thin film transistors with fan-out line (FIP) technology based on the special characteristics of metal oxide thin film transistor circuits, enabling the display panel to have the advantages of both narrow bottom bezels and a novel pixel circuit architecture.

[0004] At least one embodiment of this disclosure provides a display panel, the display panel comprising: a substrate; a first metal layer, a second metal layer, a semiconductor layer, and a third metal layer sequentially stacked on the substrate; wherein, the first metal layer includes a first electrode of a first capacitor, the second metal layer includes a second electrode of the first capacitor, the third metal layer includes a gate of a driving transistor, and the first electrode of the first capacitor and the gate of the driving transistor are electrically connected; the display panel further includes a first fan-out data line and a first low-voltage power signal line extending in a first direction, and a second low-voltage power signal line and a data signal line extending in a second direction, the first direction and the second direction intersecting, the first fan-out data line and at least one of the first low-voltage power signal line and the second low-voltage power signal line being disposed on the same layer, and the first fan-out data line being configured to connect to at least one of the data signal lines.

[0005] For example, the display panel provided in at least one embodiment of this disclosure further includes a first conductive layer and a second conductive layer, wherein the first conductive layer is disposed on the side of the third metal layer away from the substrate, the second conductive layer is disposed on the side of the first conductive layer away from the substrate, and an insulating layer is disposed between the first conductive layer and the second conductive layer.

[0006] For example, in a display panel provided in at least one embodiment of this disclosure, the first conductive layer includes a first high-voltage power signal line and a first low-voltage power signal line extending in the first direction; the second conductive layer includes a second high-voltage power signal line and a second low-voltage power signal line extending in the second direction, and the first fan-out data line is located in at least one of the first conductive layer and the second conductive layer.

[0007] For example, in a display panel provided in at least one embodiment of this disclosure, a plurality of first high-voltage power signal lines and a plurality of second high-voltage power signal lines intersect and are electrically connected to form a mesh structure, and a plurality of first low-voltage power signal lines and a plurality of second low-voltage power signal lines intersect and are electrically connected to form a mesh structure.

[0008] For example, a display panel provided in at least one embodiment of this disclosure further includes a data writing transistor, a first reset transistor, and a second reset transistor. The first conductive layer includes a scan signal line, a first reset control line, a second reset control line, and a first connection electrode. The scan signal line is configured to provide a control signal to the data writing transistor, the first reset control line is configured to provide a control signal to the first reset transistor, and the second reset control line is configured to provide a control signal to the second reset transistor. The data writing transistor is configured to provide a data signal to a pixel circuit, the first reset transistor is configured to provide a first reset signal, and the second reset transistor is configured to provide an initialization voltage signal. The first connection electrode is electrically connected to the gate of the driving transistor, the second electrode of the data writing transistor, and the second electrode of the first reset transistor.

[0009] For example, in a display panel provided in at least one embodiment of this disclosure, the first fan-out data line is disposed on the first conductive layer, the second conductive layer is provided with a second low-voltage power signal line extending in the second direction, and at least a portion of the second low-voltage power signal line covers the gate of the driving transistor.

[0010] For example, in a display panel provided in at least one embodiment of this disclosure, the first fan-out data line is disposed on the first conductive layer, the second conductive layer is provided with a second low-voltage power signal line extending in the second direction, and at least a portion of the second low-voltage power signal line covers the first connection electrode.

[0011] For example, at least one embodiment of the present disclosure provides a display panel that further includes a third conductive layer, wherein the third conductive layer is disposed on the side of the second conductive layer away from the substrate, the third conductive layer includes a second fan-out data line and the data signal line, and the second fan-out data line and the data signal line are arranged adjacent to each other between adjacent sub-pixels in the first direction.

[0012] For example, in a display panel provided in at least one embodiment of this disclosure, the first conductive layer includes a first low-voltage power signal line, a first initialization signal line, and a second initialization signal line extending in the first direction; the second conductive layer includes a second low-voltage power signal line, a first initialization signal connection line, and a second initialization signal connection line extending in the second direction; the first fan-out data line is located in at least one of the first conductive layer and the second conductive layer; the first low-voltage power signal line and the second low-voltage power signal line are connected, the first initialization signal line and the first initialization signal connection line are connected, and the second initialization signal line and the second initialization signal connection line are connected to form a mesh.

[0013] For example, at least one embodiment of the present disclosure provides a display panel that further includes a first conductive layer, a second conductive layer and a third conductive layer stacked together, wherein the first fan-out data line is in the first conductive layer, the second fan-out data line is in the third conductive layer, and the first fan-out data line is connected to the second fan-out data line through the second conductive layer.

[0014] For example, in a display panel provided in at least one embodiment of this disclosure, a first planarization layer is provided between the first conductive layer and the second conductive layer, and a second planarization layer is provided between the second conductive layer and the third conductive layer.

[0015] For example, in a display panel provided in at least one embodiment of this disclosure, the first fan-out data line located in the first conductive layer has a first break, and the first break is blocked by the third low-voltage power signal line located in the second conductive layer.

[0016] For example, in a display panel provided in at least one embodiment of this disclosure, the second fan-out data line located in the third conductive layer has a second break, and the second break is blocked by the first fan-out data line located in the first conductive layer.

[0017] For example, in a display panel provided in at least one embodiment of this disclosure, the first conductive layer further includes a second connecting electrode, the second conductive layer further includes a first anode connecting electrode, and the third conductive layer further includes a second anode connecting electrode. The first anode connecting electrode is electrically connected to the second connecting electrode and the second anode connecting electrode, respectively.

[0018] For example, in a display panel provided in at least one embodiment of this disclosure, the second metal layer further includes a first repair line, the first conductive layer includes a second connecting electrode, and the orthographic projection of the first repair line on the substrate and the orthographic projection of the second connecting electrode on the substrate have an overlapping portion.

[0019] For example, at least one embodiment of the present disclosure provides a display panel that further includes a third conductive layer disposed on the side of the second conductive layer away from the substrate, wherein the first fan-out data line is in the second conductive layer, the second fan-out data line is in the third conductive layer, an insulating layer is disposed between the second conductive layer and the third conductive layer, and the first fan-out data line and the second fan-out data line are electrically connected through a via structure disposed in the insulating layer.

[0020] At least one embodiment of this disclosure also provides a display panel, the display panel comprising: a substrate; a first metal layer, a second metal layer, a semiconductor layer, and a third metal layer sequentially stacked on the substrate; wherein, the first metal layer includes a first electrode of a first capacitor, the second metal layer includes a second electrode of the first capacitor, the third metal layer includes a gate of a driving transistor, and the first electrode of the first capacitor and the gate of the driving transistor are electrically connected; the display panel further includes a first fan-out data line extending in a first direction and a second fan-out data line extending in a second direction, the first direction and the second direction intersecting, the first fan-out data line and the second fan-out data line being located in different layers, and at least one organic insulating layer being disposed between the first fan-out data line and the second fan-out data line.

[0021] For example, the display panel provided in at least one embodiment of this disclosure further includes a first conductive layer and a second conductive layer, wherein the first conductive layer is disposed on the side of the third metal layer away from the substrate, the second conductive layer is disposed on the side of the first conductive layer away from the substrate, and at least a portion of the at least one insulating layer is disposed between the first conductive layer and the second conductive layer.

[0022] For example, a display panel provided in at least one embodiment of this disclosure further includes a third conductive layer, wherein the first fan-out data line is disposed on the first conductive layer, the second fan-out data line is disposed on the third conductive layer, the second conductive layer is provided with a second low-voltage power supply signal line extending in the second direction, and at least a portion of the second low-voltage power supply signal line covers the gate of the driving transistor.

[0023] For example, at least one embodiment of the present disclosure provides a display panel that further includes a third conductive layer, wherein the first fan-out data line is disposed on the first conductive layer, the second fan-out data line is disposed on the third conductive layer, the second conductive layer is provided with a second low-voltage power signal line extending in the second direction, and at least a portion of the second low-voltage power signal line covers the first connection electrode.

[0024] At least one embodiment of this disclosure also provides a display device, including the display panel described in any of the above embodiments. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0026] Figure 1 This is a wiring diagram for a medium to large-sized display panel;

[0027] Figure 2 This is a wiring diagram of a medium-to-large-sized display panel optimized using fan-out technology.

[0028] Figure 3 for Figure 2 The diagram shows the distribution of the display area after the medium-to-large-sized display panel adopts fan-out technology;

[0029] Figure 4 This is a schematic diagram of the structure of a display panel provided in at least one embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of the planar structure of a display panel provided for at least one embodiment of this disclosure;

[0031] Figure 6 This is a schematic diagram of the structure of a display panel provided in at least one embodiment of the present disclosure;

[0032] Figure 7 A schematic diagram of the planar structure of the first border region provided in at least one embodiment of this disclosure;

[0033] Figure 8This is a cross-sectional structural diagram of a display panel provided in at least one embodiment of the present disclosure;

[0034] Figure 9 A schematic diagram of a pixel driving circuit provided for at least one embodiment of this disclosure;

[0035] Figure 10 for Figure 9 The timing diagram of the pixel driving circuit shown is shown.

[0036] Figure 11 A schematic diagram of the planar structure of a first metal layer in a display panel provided for at least one embodiment of the present disclosure;

[0037] Figure 12 A schematic diagram of the planar structure of a second metal layer in a display panel provided for at least one embodiment of the present disclosure;

[0038] Figure 13 A schematic diagram of the structure of a first metal layer and a second metal layer stack provided in at least one embodiment of this disclosure;

[0039] Figure 14 A schematic diagram of a planar structure of a semiconductor layer pattern in a display panel, provided for at least one embodiment of the present disclosure;

[0040] Figure 15 This is a schematic diagram of the structure of a stack of a first metal layer, a second metal layer, and a semiconductor layer provided in at least one embodiment of the present disclosure;

[0041] Figure 16 A schematic diagram of the planar structure of a third metal layer in a display panel provided in at least one embodiment of the present disclosure;

[0042] Figure 17 A schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer and a third metal layer provided in at least one embodiment of the present disclosure;

[0043] Figure 18 A schematic diagram of the planar structure of a fourth insulating layer in a display panel provided for at least one embodiment of the present disclosure;

[0044] Figure 19 This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, and a fourth insulating layer provided in at least one embodiment of the present disclosure;

[0045] Figure 20 A schematic diagram of the planar structure of a fifth insulating layer in a display panel provided in at least one embodiment of the present disclosure;

[0046] Figure 21A schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, and a fifth insulating layer provided for at least one embodiment of this disclosure;

[0047] Figure 22 A schematic diagram of a planar structure of a first conductive layer in a display panel provided for at least one embodiment of the present disclosure;

[0048] Figure 23 A schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer and a first conductive layer provided for at least one embodiment of this disclosure;

[0049] Figure 24 A schematic diagram of the planar structure of a first planarization layer and a sixth insulating layer in a display panel provided in at least one embodiment of the present disclosure;

[0050] Figure 25 This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, and a first planarization layer provided for at least one embodiment of this disclosure;

[0051] Figure 26 A schematic diagram of a planar structure of a second conductive layer in a display panel, provided for at least one embodiment of the present disclosure;

[0052] Figure 27 A schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, and a second conductive layer provided for at least one embodiment of this disclosure;

[0053] Figure 28 A schematic diagram of the planar structure of a second planarization layer in a display panel provided in at least one embodiment of the present disclosure;

[0054] Figure 29 A schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, a second conductive layer, and a second planarization layer provided for at least one embodiment of this disclosure;

[0055] Figure 30 A schematic diagram of a planar structure of a third conductive layer in a display panel, provided for at least one embodiment of the present disclosure;

[0056] Figure 31A schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, a second conductive layer, a second planarization layer, and a third conductive layer provided for at least one embodiment of this disclosure;

[0057] Figure 32 A schematic diagram of the planar structure of a third planarization layer in a display panel provided for at least one embodiment of the present disclosure;

[0058] Figure 33 A schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, a second conductive layer, a second planarization layer, a third conductive layer, and a third planarization layer provided for at least one embodiment of this disclosure;

[0059] Figure 34 This is a schematic diagram of the planar structure of the anode layer in a display panel provided in at least one embodiment of the present disclosure;

[0060] Figure 35 A schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, a second conductive layer, a second planarization layer, a third conductive layer, a third planarization layer, and an anode layer provided for at least one embodiment of this disclosure;

[0061] Figure 36 A schematic diagram of a planar structure of a pixel definition layer in a display panel provided in at least one embodiment of this disclosure;

[0062] Figure 37 A schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, a second conductive layer, a second planarization layer, a third conductive layer, a third planarization layer, an anode layer, and a pixel definition layer provided for at least one embodiment of this disclosure;

[0063] Figure 38 For the above Figures 11-37 A partially enlarged schematic diagram of a portion of the layout structure shown;

[0064] Figure 39 for Figure 38 A schematic diagram of the stacked structure of some pixel circuits and their surrounding transition areas;

[0065] Figure 40 A schematic diagram of the design of a horizontal fan-out data line and a vertical fan-out data line provided for at least one embodiment of this disclosure;

[0066] Figure 41 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided in at least one embodiment of this disclosure.

[0067] Figure 42 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0068] Figure 43 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0069] Figure 44 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0070] Figure 45 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0071] Figure 46 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0072] Figure 47 This is a partially enlarged schematic diagram of a portion of a layout structure of a pixel circuit provided in at least one embodiment of the present disclosure;

[0073] Figure 48 for Figure 47 A schematic diagram of the stacked structure of some pixel circuits and their surrounding transition areas;

[0074] Figure 49 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0075] Figure 50 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0076] Figure 51 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0077] Figure 52 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0078] Figure 53 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0079] Figure 54 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0080] Figure 55 This is a schematic diagram illustrating the design of another horizontal fan-out data line and a vertical fan-out data line, provided for at least one embodiment of this disclosure.

[0081] Figure 56 This is a schematic diagram of another pixel circuit stacked structure provided in at least one embodiment of the present disclosure;

[0082] Figure 57 This is a schematic diagram of another pixel circuit stacked structure provided in at least one embodiment of the present disclosure;

[0083] Figure 58 This is a schematic diagram of another pixel circuit stacked structure provided in at least one embodiment of the present disclosure;

[0084] Figure 59 This is a schematic diagram of another pixel circuit stacked structure provided in at least one embodiment of the present disclosure;

[0085] Figure 60 A schematic diagram of another pixel circuit stack-up structure provided in at least one embodiment of this disclosure; and

[0086] Figure 61 A block diagram of a display device provided for at least one embodiment of the present disclosure. Detailed Implementation

[0087] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0088] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0089] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0090] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0091] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0092] The characteristics such as "perpendicular" and "identical" used in this disclosure include "perpendicular" and "identical" in a strict sense, as well as "approximately perpendicular" and "approximately identical," which include a certain degree of error. Taking into account the measurement and the error associated with the measurement of a specific quantity (i.e., the limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. The term "center" in this disclosure can include a position strictly located at the geometric center as well as a position approximately at the center within a small area surrounding the geometric center. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0093] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0094] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged. In embodiments of this disclosure, the gate electrode can be referred to as the control electrode.

[0095] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0096] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0097] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0098] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0099] In the embodiments of this disclosure, "about" means a value that is not strictly limited and allows for process and measurement errors.

[0100] In recent years, with the rapid development of the organic light-emitting diode (OLED) display industry, consumers have become increasingly demanding in terms of display bezels. Narrow bezels or even zero bezels have gradually become a popular trend. Fanout in Panel (FIP) technology is currently an important technical means to solve the problem of narrow bezels. At the same time, fanout technology for medium and large-sized panels optimizes the correspondence between data line adapters and integrated circuits (ICs) or chip-on-film (COF) in the display area, significantly reducing the distance between the display area AA and the back panel cutting line, thereby improving wiring efficiency, reducing production costs and increasing production efficiency.

[0101] For example, Figure 1 This is a wiring diagram for a medium to large-sized display panel. Figure 2 This is a wiring diagram of a medium-to-large-sized display panel optimized using fan-out technology. Figure 1 and Figure 2 Both diagrams show the data line connected to an integrated circuit (IC) or a chip-on-film (COF) via an adapter cable. Figure 1 The diagram shows data lines 01 arranged from the edge of display area AA to the middle of display area AA, which are sequentially connected to an integrated circuit (IC) or a chip-on-film (COF) film. Figure 2 The diagram illustrates how, in a medium to large-sized display panel employing fan-out technology, the data line 01, located at the edge of the display area AA, is moved via fan-out line 03 to the center of the display area AA, where it connects to the adapter line 04. This allows the adapter line 04 of the data line 01, originally located at the edge of the display area AA, to connect to the integrated circuit (IC) or chip-on-film (COF) in the center of the display area AA. Figure 1 and Figure 2 The comparison shows that, Figure 2 The length of the adapter cable 04 is significantly shortened, and the data cable 01, which was located at the edge, is moved to a position closer to the center of the display area AA via the fan-out cable 03, resulting in a more compact cable layout. This design also significantly reduces the distance between the display area AA and the lower back panel cut line 02, thus enabling a narrow bezel, for example, in... Figure 1 The distance between the central display area AA and the lower back panel cutting line 02 is d1. Figure 2 The distance between the central display area AA and the lower back panel cutting line 02 is d2, which is significantly smaller than d1. This improves the efficiency of data line 01 wiring, reduces the production cost of the display panel, and increases production efficiency.

[0102] For example, Figure 3 for Figure 2 The diagram shown illustrates the display area distribution of a medium to large-sized display panel using fan-out technology. Figure 3 As shown, the H area of ​​the FanoutIn Panel (FIP) represents the horizontal routing area of ​​the FIP. Vertically, FIP dummy patterns are retained to avoid visual issues when the screen is off and the image disappears. These FIP dummy patterns are connected to the low-voltage power signal VSS. The V area of ​​the FIP represents the vertical routing area. Horizontally, FIP dummy patterns are retained and connected to the low-voltage power signal VSS. The transition position between the H and V areas of the FIP indicates the location of the vias connecting the horizontal and vertical FIP routing. The normal display area represents the area without FIP ​​routing. This area still retains both horizontal and vertical FIP dummy patterns. Both horizontal and vertical FIP dummy patterns in this normal display area are connected to the low-voltage power signal VSS.

[0103] When the channel region of a thin-film transistor is formed using metal oxide, and the thin-film transistor in the pixel circuit is a metal oxide thin-film transistor, the pixel circuit has advantages such as low leakage current, low process cost, and good low grayscale display effect. Therefore, it is highly favored by researchers in the field. The inventors of this disclosure have noticed that, based on the special characteristics of the metal oxide thin-film transistor circuit, the metal oxide thin-film transistor can be combined with fan-out line (FIP) technology, so that the display panel has the advantages of both narrow bottom bezel and novel pixel circuit architecture.

[0104] The inventors of this disclosure also noted that by combining pixel circuits including metal oxide thin-film transistors (MTBTs) with FIP technology, for example, by integrating a 6T2C discrete high / low refresh rate circuit with multiple conductive metal layers with FIP technology, and combining it with a repair structure design, it is possible to narrow the bottom bezel of the display panel without reducing pixel resolution. For example, by using a 6T2C circuit architecture based on MTBTs and the adapter cable and access method for FIP data lines, the space occupied by the data lines is reduced by compressing the pixels horizontally and vertically. That is, by combining 6T2C pixel circuits including MTBTs with FIP technology, high / low refresh rate, low power consumption, superior image quality, and narrow bezels can be achieved, thereby significantly reducing the distance between the display area and the bottom back panel cut-out line while improving the screen performance and market competitiveness of the display panel.

[0105] At least one embodiment of this disclosure provides a display panel, the display panel comprising: a substrate; a first metal layer, a second metal layer, a semiconductor layer, and a third metal layer sequentially stacked on the substrate; wherein, the first metal layer includes a first electrode of a first capacitor, the second metal layer includes a second electrode of the first capacitor, the third metal layer includes a gate of a driving transistor, and the first electrode of the first capacitor and the gate of the driving transistor are electrically connected; the display panel further includes a first fan-out data line and a first low-voltage power signal line extending in a first direction, and a second low-voltage power signal line and a data signal line extending in a second direction, the first direction and the second direction intersecting, the first fan-out data line and at least one of the first low-voltage power signal line and the second low-voltage power signal line being disposed on the same layer, and the first fan-out data line being configured to connect to at least one of the data signal lines.

[0106] At least one embodiment of this disclosure also provides a display panel, the display panel comprising: a substrate; a first metal layer, a second metal layer, a semiconductor layer, and a third metal layer sequentially stacked on the substrate; wherein, the first metal layer includes a first electrode of a first capacitor, the second metal layer includes a second electrode of the first capacitor, the third metal layer includes a gate of a driving transistor, and the first electrode of the first capacitor and the gate of the driving transistor are electrically connected; the display panel further includes a first fan-out data line extending in a first direction and a second fan-out data line extending in a second direction, the first direction and the second direction intersecting, the first fan-out data line and the second fan-out data line being located in different layers, and at least one organic insulating layer being disposed between the first fan-out data line and the second fan-out data line.

[0107] For example, Figure 4 This is a schematic diagram of the structure of a display panel provided in at least one embodiment of the present disclosure, such as... Figure 4As shown, the display panel includes a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is connected to multiple data signal lines (D1 to Dn), the scan signal driving circuit is connected to multiple scan signal lines (G1 to Gm), and the light emission signal driving circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines (which may be referred to as data lines). In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driving circuit to the data signal driving circuit, clock signals, scan start signals, etc. of specifications suitable for the scan signal driving circuit to the scan signal driving circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driving circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driving circuit can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driving circuit can sequentially provide scan signals with conduction level pulses to scan signal lines G1 to Gm. For example, a scan signal driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A light-emitting signal driving circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, a light-emitting signal driving circuit can sequentially provide transmit signals with cutoff level pulses to light-emitting signal lines E1 to Eo. For example, a light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0108] Figure 5This is a schematic diagram of a planar structure of a display panel provided for at least one embodiment of the present disclosure. Figure 5 As shown, the display panel includes multiple pixel units P arranged in an array. At least one of the pixel units P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0109] For example, in one example, pixel unit P includes a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B). In exemplary embodiments, the shape of the sub-pixels in a pixel unit can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; the embodiments of this disclosure do not limit this.

[0110] For example, Figure 6 This is a schematic diagram of the structure of a display panel provided in at least one embodiment of the present disclosure. Figure 6 As shown, the display panel includes a display area AA and a bezel area BB surrounding the display area AA. In some examples, the bezel area BB may include: a first bezel area (bottom bezel) B1 and a second bezel area (top bezel) arranged opposite each other in the second direction Y, and a third bezel area (left bezel) B3 and a fourth bezel area (right bezel) arranged opposite each other in the first direction X. The first bezel area B1 is connected to the third bezel area B3 and the fourth bezel area B4, and the second bezel area B2 is connected to the third bezel area B3 and the fourth bezel area B4. For example, in some examples, the display area AA may include a first edge (bottom edge) and a second edge (top edge) arranged opposite each other in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) arranged opposite each other in the first direction X. The display area AA may include a plurality of regularly arranged sub-pixels Pxij. The sub-pixels may include pixel driving circuits and light-emitting devices. The first bezel area B1 includes a bonding circuit that connects signal lines to an external driving device. The third bezel area B3 and the fourth bezel area B4 include gate driving circuits and a second power line VSS (low-voltage power signal line) that transmits voltage signals to the plurality of sub-pixels.

[0111] For example, Figure 7 This is a schematic diagram of the planar structure of the first border region provided in at least one embodiment of the present disclosure, combined with... Figure 6 and Figure 7 As shown, in a plane parallel to the display surface of the display panel, the first bezel area B1 includes a first fan-out area 11, a bending area 12, a second fan-out area 13, and a bonding area 14 arranged sequentially along the direction away from the display area AA. The bonding area 14 includes a driver chip area 141, a third fan-out area 142, and a bonding electrode area 143 arranged sequentially along the direction away from the bending area 12 from the second fan-out area 13. The first fan-out area 11 includes a fan-out data line, a first power line, and a second power line VSS. The fan-out data line is located in the middle of the first fan-out area 11 and includes multiple data connection lines configured to connect to the data signal lines (Data Line) of the display area AA in a fan-out routing manner. The first power line is configured to connect to the high-voltage power line (VDD) of the display area AA, and the second power line is a low-voltage power line (VSS) located in the third bezel area B3 and the fourth bezel area B4. The bending area 12 may include a composite insulating layer with grooves, configured to bend the bonding area 14 to the back of the display area AA. The second fan-out area 13 includes multiple data connection lines led out in a fan-out routing manner. The driver chip area 141 may house an integrated circuit (IC) 20, configured to connect to the multiple data connection lines. The bonding electrode area 143 includes multiple bonding pads, configured to bond to the flexible printed circuit (FPC) 30. In an exemplary embodiment, the integrated circuit (IC) 20 is bonded to the driver chip area 141, and the flexible printed circuit (FPC) 30 may be bonded to the bonding electrode area 142. In an exemplary embodiment, the integrated circuit 20 (referred to as a data driving circuit, or driving circuit) may generate driving signals required to drive sub-pixels and may provide the driving signals to the sub-pixel Pxij located in the display area AA. For example, the driving signal may be a data signal controlling the brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode area 143 may be provided with a pad including a plurality of pins, and the flexible circuit board 30 may be bonded to the pad.

[0112] For example, Figure 8 This is a cross-sectional structural diagram of a display panel provided in at least one embodiment of the present disclosure. Figure 8 The diagram illustrates the structure of three sub-pixels in an OLED display panel. (See diagram for example.) Figure 8 As shown, on a plane perpendicular to the main surface of the display panel, the display panel includes a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some embodiments, the display panel also includes other film layers, such as spacers, etc., which are not limited in the embodiments of this disclosure.

[0113] For example, in some examples, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 for each sub-pixel can include multiple transistors and storage capacitors constituting the pixel driving circuit. The light-emitting structure layer 103 can include an anode 301, an organic light-emitting layer 302, and a cathode 303. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via structure. The organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 emits light of a corresponding color under the driving force of the anode 301 and the cathode 303. The encapsulation layer 104 includes a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 are formed of inorganic materials, while the second encapsulation layer 402 is formed of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, ensuring that external moisture cannot enter the light-emitting structure layer 103.

[0114] For example, in one embodiment, the organic light-emitting layer 302 includes a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked sequentially. In an exemplary embodiment, the hole injection layers of all sub-pixels are connected into a common layer, the electron injection layers of all sub-pixels are connected into a common layer, the hole transport layers of all sub-pixels are connected into a common layer, the electron transport layers of all sub-pixels are connected into a common layer, the hole block layers of all sub-pixels can be connected into a common layer, the emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0115] For example, in embodiments of this disclosure, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, 8T1C, or 7T2C structure. Embodiments of this disclosure are illustrated using a 6T2C pixel circuit structure as an example. Figure 9 A schematic diagram of a pixel driving circuit provided in at least one embodiment of this disclosure, such as... Figure 9 As shown, the pixel driving circuit includes six transistors (first transistor T1 to sixth transistor T6) and two capacitors C (first capacitor C1 and second capacitor C2). The pixel driving circuit can be connected to ten signal lines (data signal line D, scan signal line Gate, first reset control line Reset1, second reset control line Reset2, first light emission control line EM1, second light emission control line EM2, first initialization signal line Vinit1, second initialization signal line Vinit2, first power supply line VDD, and second power supply line VSS). The following is a combination of... Figure 9 The pixel driving circuit is described below:

[0116] For example, in Figure 9 The pixel driving circuit shown includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the control electrode of the third transistor T3, the second electrode of the fourth transistor T4, the first terminal of the first capacitor C1, and the second electrode of the first transistor T1. The second node N2 is connected to the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5. The third node N3 is connected to the second terminal of the first capacitor C1, the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the first terminal of the second capacitor C2. The fourth node N4 is connected to the second electrodes of the sixth transistor T6, the second electrode of the second transistor T7, and the anode of the light-emitting device EL. The first transistor T1 is a first reset transistor, the second transistor T2 is a second reset transistor, the third transistor T3 is a driving transistor, the fourth transistor T4 is a data writing transistor, the fifth transistor T5 is a first light-emitting control transistor, and the sixth transistor T6 is a second light-emitting control transistor.

[0117] For example, such as Figure 9 As shown, the first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal of the first capacitor C1 is connected to the third node N3; the first terminal of the second capacitor C2 is connected to the third node N3, and the second terminal of the second capacitor C2 is connected to the DC signal line, for example, as shown. Figure 9 As shown, the second terminal of the second capacitor C2 is connected to the first power line VDD, which helps to save space on the display substrate.

[0118] For example, the second terminal of the first capacitor C1 and the first terminal of the second capacitor C2 are both coupled to the second terminal of the third transistor T3, the first terminal of the first capacitor C1 is coupled to the first node N1, and the second terminal of the second capacitor C2 is coupled to the high-voltage power supply signal line VDD.

[0119] For example, such as Figure 9 As shown, the control electrode of the first transistor T1 is connected to the first reset control line Reset1, the first electrode of the first transistor T1 is connected to the first initialization signal line Vinit1, and the second electrode of the first transistor is connected to the first node N1. When a conduction-level reset signal is applied to the first reset control line Reset1, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge on the control electrode of the third transistor T3.

[0120] For example, such as Figure 9 As shown, the control electrode of the second transistor T2 is connected to the second reset control line Reset2, the first electrode of the second transistor T2 is connected to the second initialization signal line Vinit2, and the second electrode of the second transistor T2 is connected to the first electrode of the light-emitting device (also the fourth node N4). When a conduction-level reset signal is applied to the second reset control line Reset2, the second transistor T2 transmits an initialization voltage to the first electrode of the light-emitting device EL, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device EL.

[0121] For example, such as Figure 9 As shown, the control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 is called the driving transistor, and the amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its control electrode and its first electrode.

[0122] For example, such as Figure 9 As shown, the control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 is called a switching transistor. When a conduction-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0123] For example, such as Figure 9As shown, the control electrode of the fifth transistor T5 is connected to the first light-emitting control line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the second light-emitting control line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device (also the fourth node N4). The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors (or light-emitting control transistors). When a conduction-level light-emitting signal is applied to the first light-emitting control line EM1 and the second light-emitting control line EM2, the fifth transistor T5 and the sixth transistor T6 conduct, forming a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device to emit light.

[0124] For example, such as Figure 9 As shown, the second electrode of the light-emitting device is connected to the second power line VSS, where the signal on the second power line VSS is a low-level signal, while the signal on the first power line VDD is a continuously high-level signal. In an exemplary embodiment, the first transistor T1 to the sixth transistor T6 are N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0125] For example, in Figure 9 In the structure shown, the first reset control line Reset1, the second reset control line Reset2, the scan signal line Gate, the first light emission control line EM1, and the second light emission control line EM2 are gate control signal lines.

[0126] In an exemplary embodiment, the first transistor T1 to the sixth transistor T6 are oxide thin-film transistors (referred to as N-type transistors). Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. The active layer of the oxide thin-film transistor is made of metal-oxide-semiconductor (Oxide). Metal-oxide-semiconductor thin-film transistors have advantages such as low leakage current, low-frequency driving capability, and low power consumption.

[0127] In an exemplary embodiment, the light-emitting device EL can be an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode (QD) display device, a sub-millimeter light-emitting diode (Mini LED) or a micro-light-emitting diode (Micro-LED), including a stacked first electrode (anode), an organic light-emitting layer and a second electrode (cathode).

[0128] For example, Figure 10 for Figure 9 The timing diagram of the pixel driving circuit shown is as follows: Figure 9The operation of a pixel driving circuit is illustrated using the example of six N-type transistors in the pixel driving circuit (high-level signal for turn-on, low-level signal for turn-off). Figure 10 As shown, the operation of the pixel driving circuit can include:

[0129] Phase 1, P11, can be called the reset phase. The second reset control line, Reset2, is a high-level signal, while the scan signal line, Gate, and the first light-emitting control line, EM1, are low-level signals. Because Reset2 is high, the second transistor T2 is turned on, and the signal from the second initialization signal line, Vinit2, is provided to the fourth node, N4, via the second transistor T2, clearing the charge from N4. The potential of N4 is the voltage of the second initialization signal, VINIT2. Because the scan signal line, Gate1, and the first light-emitting control line, EM1, are low, the fourth transistor, T4, and the sixth transistor, T6, are turned off, and the OLED does not emit light during this phase. Phase 1, P11, can be divided into three sub-phases based on the signal changes of the first reset control line, Reset1, and the second light-emitting control line, EM2 (sub-phase 1, P01, sub-phase 2, and sub-phase 3).

[0130] The first sub-stage P01 can be called the first reset sub-stage. The first reset control line Reset1 is a low-level signal, and the second light-emitting control line EM2 is a high-level signal. Since the second light-emitting control line EM2 is a high-level signal, the sixth transistor T6 is turned on. The signal of the fourth node N4 is written to the third node N3 through the sixth transistor T6. The potential of the third node N3 is the voltage VINIT2 of the second initialization signal. The potential of the third node N3 is coupled to the first node N1, and the signal of the first node N1 changes from high level to low level. The third transistor T3 is turned off. Since the first reset control line Reset1 is a low-level signal, the first transistor T1 is turned off.

[0131] The second sub-stage P02 can be called the second reset sub-stage. The first reset control line Reset1 and the second light emission control line EM2 are high-level signals. Since the first reset control line Reset1 is high-level, the first transistor T1 is turned on, and the signal of the first initialization signal line Vinit1 is provided to the first node N1 to initialize the first plate of the first capacitor C1 and the control electrode of the third transistor T3, clearing the charge of the first node N1. The potential of the first node N1 is the voltage VINIT1 of the first initialization signal, and the third transistor T3 is turned on. Since the second light emission control line EM2 is high-level, the sixth transistor T6 is turned on, and the signal of the fourth node N4 is continuously written to the third node N3 through the sixth transistor T6. The potential of the third node N3 is the voltage VINIT2 of the second initialization signal.

[0132] The third sub-stage P03 can be called the third reset sub-stage. The first reset control line Reset1 is a high-level signal, and the second light-emitting control line EM2 is a low-level signal. Since the first reset control line Reset1 is a high-level signal, the first transistor T1 is continuously turned on, and the signal of the first initialization signal line Vinit1 is continuously provided to the first node N1 to initialize the first plate of the first capacitor C1 and the control electrode of the third transistor T3, clearing the charge of the first node N1. The potential of the first node N1 is the voltage of the first initialization signal VINIT1, and the third transistor T3 is turned on. Since the second light-emitting control line EM2 is a low-level signal, the sixth transistor T6 is turned off, and the signals of the third node N3 and the fourth node N4 remain unchanged.

[0133] The second stage, P12, can be called the threshold compensation stage. The scanning signal line Gate and the second light emission control line EM2 are low-level signals, while the first reset control line Reset1, the second reset control line Reset2, and the first light emission control line EM1 are high-level signals. Since the first reset control line Reset1, the second reset control line Reset2, and the first light emission control line EM1 are high-level signals, the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on. Since the first transistor T1 is turned on, the signal of the first initialization signal line Vinit1 is provided to the first node N1 to initialize the first plate of the first capacitor C1 and the control electrode of the third transistor T3. The potential of the first node N1 is the voltage VINIT1 of the first initialization signal, and the third transistor T3 is turned on. Since the second transistor T2 is turned on, the signal of the second initialization signal line Vinit2 initializes the fourth node N4, and the potential of the fourth node N4 is VINIT2. Since the fifth transistor T5 is turned on, the voltage of the first power supply line VDD is written to the third node N3 through the fifth transistor T5, the second node N2, and the third transistor T3 until the voltage of the third node N3 satisfies VINIT2-Vth, where Vth is the threshold voltage of the third transistor T3. The potential of the second node N2 is the voltage of the first power supply line VDD. Since the scan signal line Gate and the second light emission control line EM2 are low-level signals, the fourth transistor T4 and the sixth transistor T6 are disconnected, and the potential of the fourth node N4 maintains the voltage VINIT2 of the second initialization signal.

[0134] Phase 3 (P13): This can be called the data writing phase. The first reset control line (Reset1), the first light emission control line (EM1), and the second light emission control line (EM2) are low-level signals, while the scan signal line (Gate) and the second reset control line (Reset2) are high-level signals. Because the first reset control line (Reset1), the first light emission control line (EM1), and the second light emission control line (EM2) are low-level signals, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are disconnected, and the fourth node N4 maintains the voltage VINIT2 of the second initialization signal. Because the scan signal line (Gate) and the second reset control line (Reset2) are high-level signals, the second transistor T2 and the fourth transistor T4 are turned on. Because the second transistor T2 is turned on, the second initialization signal line Vinit2 is written to the fourth node N4 via the second transistor T2, and the potential of the fourth node N4 is the voltage VI of the second initialization signal. NIT2; Due to the conduction of the fourth transistor T4, the data voltage output from the data signal line D is written to the first node N1 via the fourth transistor T4, and the potential of the first node N1 becomes VData, which is the data voltage output from the data signal line D. The third transistor T3 is turned on; Due to the deactivation of the sixth transistor T6, the potential of the fourth node N4 cannot be written to the third node N3, and the voltage of the first node N1 is coupled to the third node N3, causing the third node N3 to rise, i.e., Data is written, Vg = N1 = Vdata, Vs = N3 = Vinit1 - Vth + Vdata * C1 / (C1 + C2).

[0135] The fourth stage, P14, can be called the light-emitting stage. The first light-emitting control line EM1 and the second light-emitting control line EM2 are high-level signals, while the first reset control line Reset1, the scan signal line Gate, and the second reset control line Reset2 are low-level signals. Since the first reset control line Reset1, the scan signal line Gate, and the second reset control line Reset2 are low-level signals, the first transistor T1, the second transistor T2, and the fourth transistor T4 are disconnected. The voltage across the first capacitor C1 will not change abruptly, and the first node N1 basically maintains the potential of the previous stage. The third transistor T3 is turned on. Since the first light-emitting control line EM1 and the second light-emitting control line EM2 are high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting device EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the organic light-emitting diode to emit light. Vs = N3 = Voled + VSS, Vg = N1 = Vdata + [Voled + VSS - [Vinit1 - Vth + Vdata * C1 / (C1 + C2)]].

[0136] According to the current saturation formula: I_oled=Kx(Vgs-Vth) 2=Kx

Vdata-[Vinit1-Vth+Vdata*C1 / (C1+C2)-vth]

[0137] As can be seen from the formula, the discrete circuit separates Vth compensation and Vdata writing. I_oled is not affected by the high-voltage power supply voltage, but only by Vdata and Vinti1. Compared with Vdd, Vinti1 has a smaller current flow and a lower risk of voltage drop due to resistance. This characteristic increases the freedom of display area linewidth design and further proves the rationality of using virtual area FIP traces for low-voltage power supply signal lines.

[0138] exist Figure 10 shown Figure 9 In the timing diagram of the pixel driving circuit, threshold compensation is performed in the second stage P12 to the third stage P13. The threshold compensation time is relatively long, which can reduce the technical problem of insufficient threshold voltage compensation to a certain extent.

[0139] The following combination Figures 11 to 37 The layer structure of a display panel provided in the embodiments of this disclosure will be described. It should be noted that, in the embodiments of this disclosure, in order to clearly show the relevant structures, each insulating layer and each planarization layer is shown in the form of vias in the planar structural schematic diagram, and each insulating layer and each planarization layer themselves are made transparent. Furthermore, in the stacked structure, each metal layer and conductive layer are made semi-transparent.

[0140] The following description uses the fabrication process of a display panel as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using sputtering, evaporation, or chemical vapor deposition; coating can be performed using spraying, spin coating, or inkjet printing; and etching can be performed using dry etching or wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a material fabricated on a substrate (or substrate plate) using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0141] For example, Figure 11 This is a schematic planar structure diagram of a first metal layer in a display panel, provided for at least one embodiment of this disclosure. (See diagram below.) Figure 11 As shown, the first metal layer 201 includes the first electrode C11 of the first capacitor C1 and the first electrode C21 of the second capacitor C2.

[0142] For example, in an exemplary embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be block structures, and the shape of the block structure can be polygonal. In an exemplary embodiment, at least one edge of the polygonal block structure is a broken line. For example, the polygonal block structure can be rectangular, and at least one edge of the rectangle is a broken line. In an exemplary embodiment, in the second direction Y, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be arranged sequentially.

[0143] In an exemplary embodiment, the second direction Y is substantially the same as the extension direction of the data signal line.

[0144] For example, in an exemplary embodiment, the first plate C11 of the first capacitor C1 may be provided with a first connection portion CL1. The first connection portion CL1 is configured to correspond to the subsequently formed fifteenth via. The orthographic projection of the fifteenth via on the substrate is located within the range of the orthographic projection of the first connection portion CL1 on the substrate and exposes the surface of the first connection portion CL1, so that the second electrode of the subsequently formed first transistor T1 and the second electrode of the fourth transistor T4 are connected to the first plate C11 of the first capacitor C1 through the fifteenth via and the first connection portion CL1.

[0145] For example, in an exemplary embodiment, the first electrode plate C21 of the second capacitor C2 is provided with a second connection portion CL2. The second connection portion CL2 is configured to correspond to the subsequently formed thirteenth via. The orthographic projection of the thirteenth via on the substrate is located within the range of the orthographic projection of the second connection portion CL2 on the substrate, and exposes the surface of the second connection portion CL2, so that the first electrode of the subsequently formed fifth transistor T5 is connected to the first electrode plate C21 of the second capacitor C2 through the thirteenth via and the second connection portion CL2.

[0146] For example, such as Figure 11 As shown, taking the Mth row and Nth column sub-pixel as an example: In the second direction Y, the main body of the first plate C11 of the first capacitor C1 in the Mth row can be located on the side of the first plate C21 of the second capacitor C2 of the same sub-pixel near the M+1th row sub-pixel; In the first direction X, at least a part of the structure of the first plate C11 of the first capacitor C1 is located on the side of the first plate C21 of the second capacitor C2 of the same sub-pixel near the N-1th column sub-pixel.

[0147] For example, the process of forming the first metal layer is as follows: depositing a first metal thin film on a substrate, and patterning the first metal thin film using a patterning process to form a pattern for the first metal layer, such as... Figure 11 As shown, Figure 11 This is a schematic diagram of the planar structure of the three sub-pixels after the formation of the first metal layer. The first metal layer can be called the first gate metal (GATE1) layer.

[0148] For example, Figure 12 This is a schematic planar structure diagram of a second metal layer in a display panel, provided for at least one embodiment of this disclosure. (See diagram below.) Figure 12 As shown, the second metal layer 202 includes the second electrode C12 of the first capacitor C1, the second electrode C22 of the second capacitor C2, the first substructure EM11 of the first light emission control line, the first substructure EM21 of the second light emission control line, the bottom gate T1gb of the first transistor T1, the bottom gate T2gb of the second transistor T2, the bottom gate T4gb of the fourth transistor T4, and the first repair line RP.

[0149] For example, in an exemplary embodiment, in the second direction Y, within the same sub-pixel, the bottom gate T1gb of the first transistor T1 and the bottom gate T2gb of the second transistor T2 can be located on opposite sides of the first substructure EM21 of the second light-emitting control line. The bottom gate T1gb of the first transistor T1 can be located between the first substructure EM21 of the second light-emitting control line and the second plate C12 of the first capacitor C1. The second plate C22 of the second capacitor C2 and the bottom gate T4gb of the fourth transistor T4 can be located on the side of the second plate C12 of the first capacitor C1 away from the first substructure EM21 of the second light-emitting control line. For example, in the same sub-pixel, the bottom gate T2gb of the second transistor T2, the first substructure EM21 of the second light-emitting control line, the bottom gate T1gb of the first transistor T1, the second plate C12 of the first capacitor C1, the second plate C22 of the second capacitor C2, and the first substructure EM11 of the first light-emitting control line can be arranged sequentially along the second direction Y.

[0150] For example, in an exemplary embodiment, the first substructure EM11 of the first light-emitting control line and the first substructure EM21 of the second light-emitting control line can be strip-shaped or zigzag-shaped, and the main body can extend along the first direction X.

[0151] For example, the first substructure EM11 of the first light-emitting control line is configured as a shielding layer for the fifth transistor T5, shielding the channel of the fifth transistor T5 and ensuring the electrical performance of the metal-oxide-semiconductor fifth transistor T5. In an exemplary embodiment, the signals of the first substructure EM11 of the first light-emitting control line and the subsequently formed second substructure EM12 of the first light-emitting control line can be the same, that is, the first substructure EM11 of the first light-emitting control line and the subsequently formed second substructure EM12 of the first light-emitting control line are connected in parallel and connected to the same signal source, so that the first substructure EM11 of the first light-emitting control line can serve as the bottom gate electrode (i.e., the bottom control electrode) of the fifth transistor T5, and the second substructure EM12 of the first light-emitting control line can serve as the top gate electrode (i.e., the top control electrode) of the fifth transistor T5, forming a double-gate structure fifth transistor T5.

[0152] For example, the first substructure EM21 of the second light-emitting control line is configured as a shielding layer for the sixth transistor T6, shielding the channel of the sixth transistor T6 and ensuring the electrical performance of the metal-oxide-semiconductor sixth transistor T6. In an exemplary embodiment, the signals of the first substructure EM21 of the second light-emitting control line and the subsequently formed second substructure EM22 of the second light-emitting control line can be the same, that is, the first substructure EM21 of the second light-emitting control line and the subsequently formed second substructure EM22 of the second light-emitting control line are connected in parallel and connected to the same signal source, so that the first substructure EM21 of the second light-emitting control line can serve as the bottom gate electrode (i.e., the bottom control electrode) of the sixth transistor T6, and the second substructure EM22 of the second light-emitting control line can serve as the top gate electrode (i.e., the top control electrode) of the sixth transistor T6, forming a double-gate structure sixth transistor T6.

[0153] For example, in an exemplary embodiment, the bottom gate T1gb of the first transistor T1 can be strip-shaped or zigzag-shaped, and its main body can extend along the first direction X. The bottom gate T1gb of the first transistor T1 is configured as a shielding layer of the first transistor T1, shielding the channel of the first transistor T1 and ensuring the electrical performance of the oxide first transistor T1. In an exemplary embodiment, the signal of the bottom gate T1gb of the first transistor T1 can be the same as that of the subsequently formed first reset control line Reset1, and it can be connected in parallel with the top gate T1gt of the subsequently formed first transistor T1. Both are connected to the same signal source, so that the bottom gate T1gb of the first transistor T1 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the first transistor T1, forming a dual-gate structure first transistor T1.

[0154] For example, in an exemplary embodiment, the bottom gate T2gb of the second transistor T2 can be a strip structure or a zigzag structure extending along the first direction X. In an exemplary embodiment, the bottom gate T2gb of the second transistor T2 can be an island structure, configured as a shielding layer of the second transistor T2, shielding the channel of the second transistor T2 and ensuring the electrical performance of the oxide second transistor T2. In an exemplary embodiment, the signal of the bottom gate T2gb of the second transistor T2 and the subsequently formed second reset control line Reset2 can be the same, that is, the bottom gate T2gb of the second transistor T2 is connected to the subsequently formed second reset control line Reset2 and is connected in parallel with the top gate T2gt of the subsequently formed second transistor T2. Both are connected to the same signal source, so that the bottom gate T2gb of the second transistor T2 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the second transistor T2, forming a dual-gate structure of the second transistor T2.

[0155] For example, in an exemplary embodiment, the bottom gate T4gb of the fourth transistor T4 can be a strip structure or a zigzag structure extending along the first direction X. In an exemplary embodiment, the bottom gate T4gb of the fourth transistor T4 can be an island structure, configured as a shielding layer of the fourth transistor T4 to shield the channel of the fourth transistor T4 and ensure the electrical performance of the oxide fourth transistor T4. In an exemplary embodiment, the signal of the bottom gate T4gb of the fourth transistor T4 can be the same as that of the subsequently formed scan signal line Gate, that is, the bottom gate T4gb of the fourth transistor T4 is connected to the subsequently formed scan signal line Gate and is connected in parallel with the subsequently formed top gate T4gt of the fourth transistor T4. Both are connected to the same signal source, so that the bottom gate T4gb of the fourth transistor T4 can serve as the bottom gate electrode (i.e., the bottom control electrode) of the fourth transistor T4, forming a dual-gate structure fourth transistor T4.

[0156] For example, Figure 13 This is a schematic diagram of the structure of a first metal layer and a second metal layer stack provided in at least one embodiment of the present disclosure. In an exemplary embodiment, such as... Figure 13 As shown, the outline of the second plate C12 of the first capacitor C1 can be consistent with the outline of the first plate C11 of the first capacitor C1, and the outline of the second plate C22 of the second capacitor C2 can be consistent with the outline of the first plate C21 of the second capacitor C2. For example, the outlines of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 can be polygons (such as rectangles, and at least one edge of the rectangle is a broken line). In an exemplary embodiment, the orthographic projection of the second plate C12 of the first capacitor C1 onto the substrate overlaps with the orthographic projection of the first plate C11 of the first capacitor C1 onto the substrate. Similarly, the orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate overlaps with the orthographic projection of the first plate C21 of the second capacitor C2 onto the substrate. For example, the orthographic projection of the second plate C12 of the first capacitor C1 onto the substrate may be within the range of the orthographic projection of the first plate C11 of the first capacitor C1 onto the substrate, and the orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate may be within the range of the orthographic projection of the first plate C21 of the second capacitor C2 onto the substrate. In this exemplary embodiment, the first plate C11 and the second plate C12 of the first capacitor C1 constitute the first capacitor C1, and the first plate C21 and the second plate C22 of the second capacitor C2 constitute the second capacitor C2.

[0157] In an exemplary embodiment, the second plate C22 of the second capacitor C2 can block the channel of the third body tube T3, thereby ensuring the electrical performance of the oxide third body tube T3.

[0158] For example, the process of forming the second metal layer is as follows: on the substrate on which the aforementioned pattern is formed, a first insulating layer thin film and a second metal thin film are sequentially deposited; the second metal thin film is patterned using a patterning process to form a first insulating layer covering the first metal layer, and a pattern of the second metal layer disposed on the first insulating layer. Figure 12 and Figure 13 This is a planar structural diagram of the three sub-pixels after the formation of the second metal layer. In an exemplary embodiment, the second metal layer 202 may be referred to as the second gate metal (GATE2) layer.

[0159] For example, Figure 14 This is a schematic planar structure diagram of a semiconductor layer pattern in a display panel, provided for at least one embodiment of the present disclosure. For example... Figure 14 As shown, the pattern of semiconductor layer 203 in at least some sub-pixels includes at least: active layer AT1 of the first transistor T1 to active layer AT6 of the sixth transistor T6.

[0160] For example, in an exemplary embodiment, in the same sub-pixel, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6 can be interconnected. For example, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6 can be an interconnected integral structure.

[0161] For example, in an exemplary embodiment, within the same sub-pixel, in the first direction X, the active layer AT1 of the first transistor T1 and the active layer AT4 of the fourth transistor T4 may be located on the same side of the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6; in the second direction Y, the active layer AT2 of the second transistor T2 and the active layer AT3 of the third transistor T3 are located on opposite sides of the active layer AT6 of the sixth transistor T6, the active layer AT4 of the fourth transistor T4 and the active layer AT5 of the fifth transistor T5 are located on the same side of the active layer AT6 of the sixth transistor T6, and the active layer AT1 of the first transistor T1 and the active layer AT2 of the second transistor T2 are located on the same side of the active layer AT3 of the third transistor T3.

[0162] For example, in an exemplary embodiment, taking the sub-pixel of the Mth row and Nth column as an example: In the first direction X, the active layer of the first transistor T1 and the active layer AT4 of the fourth transistor T4 can be located on the side away from the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6; In the second direction Y, the active layer AT4 of the fourth transistor T4 can be located on the side away from the active layer AT1 of the first transistor T1, the active layer AT6 of the sixth transistor T6 can be located on the side away from the active layer AT3 of the third transistor T3, the active layer AT2 of the second transistor T2 can be located on the side close to the active layer AT6 of the sixth transistor T6, and the active layer AT5 of the fifth transistor T5 can be located on the side away from the active layer AT6 of the sixth transistor T6.

[0163] For example, in an exemplary embodiment, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6 can be in the shape of an "I" or a strip.

[0164] For example, in an exemplary embodiment, the active layer of at least some transistors includes a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region AT31 of the active layer AT3 of the third transistor T3 can serve as the second region AT52 of the active layer AT5 of the fifth transistor T5, the second region AT32 of the active layer AT3 of the third transistor T3 can serve as the first region AT61 of the active layer AT6 of the sixth transistor T6, the second region AT62 of the active layer AT6 of the sixth transistor T6 can serve as the second region AT22 of the active layer AT2 of the second transistor T2, and the first region AT11 and the second region AT12 of the active layer AT1 of the first transistor T1, the first region AT21 of the active layer AT2 of the second transistor T2, the first region AT41 and the second region AT42 of the active layer AT4 of the fourth transistor T4, and the first region AT51 of the active layer AT5 of the fifth transistor T5 can be individually configured.

[0165] For example, in an exemplary embodiment, the semiconductor layer can be a metal oxide, i.e., the first transistor T1 to the sixth transistor T6 are all metal oxide thin-film transistors. In an exemplary embodiment, the metal oxide can be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), and lanthanum copper sulfide oxide (LaCuOS). In some possible implementations, the metal oxide semiconductor layer can be indium gallium zinc oxide (IGZO), which has a high electron mobility.

[0166] For example, the process of forming a semiconductor layer pattern includes: sequentially depositing a second insulating layer thin film and a semiconductor thin film on a substrate on which the aforementioned pattern is formed; patterning the semiconductor thin film using a patterning process to form a second insulating layer covering the substrate and a semiconductor layer pattern disposed on the second insulating layer. Figure 14 This is a planar structure diagram of the three sub-pixels after the semiconductor layer is formed.

[0167] For example, Figure 15 This is a schematic diagram of the structure of the stacked first metal layer, second metal layer, and semiconductor layer provided in at least one embodiment of the present disclosure, as shown below. Figure 15 As shown, the region where the first substructure EM11 of the first light-emitting control line overlaps with the active layer AT5 of the fifth transistor T5 can serve as the bottom gate of the fifth transistor T5. The region where the first substructure EM21 of the second light-emitting control line overlaps with the active layer AT6 of the sixth transistor T6 can serve as the bottom gate of the sixth transistor T6. The region where the second plate C22 of the second capacitor C2 overlaps with the active layer AT3 of the third transistor T3 can serve as a light-shielding layer for the third transistor T3. The region where the semiconductor layer 203 overlaps with the active layer AT1 of the first transistor T1 can serve as the channel of the first transistor T1. The region where the semiconductor layer 203 overlaps with the active layer AT2 of the second transistor T2 can serve as the channel of the second transistor T2. The region where the semiconductor layer 203 overlaps with the active layer AT4 of the fourth transistor T4 can serve as the channel of the fourth transistor T4.

[0168] For example, Figure 16 This is a schematic planar structure diagram of a third metal layer in a display panel, provided for at least one embodiment of this disclosure. (See diagram below.) Figure 16As shown, the pattern of the third metal layer 204 includes at least: a second substructure of the first light-emitting control line EM12, a second substructure of the second light-emitting control line EM22, the top gate T1gt of the first transistor T1, the top gate T2gt of the second transistor T2, the top gate T3gt of the third transistor T3, and the top gate T4gt of the fourth transistor T4.

[0169] For example, in an exemplary embodiment, both the first light-emitting control line second substructure EM12 and the second light-emitting control line second substructure EM22 are zigzag or strip-shaped extensions of the main body along the first direction X. In the same sub-pixel row, in the second direction Y, the top gate T1gt of the first transistor T1 and the top gate T2gt of the second transistor T2 can be located on opposite sides of the second light-emitting control line second substructure EM22, the top gate T3gt of the third transistor T3 can be located on the side of the top gate T1gt of the first transistor T1 away from the second light-emitting control line second substructure EM22, and the top gate T4gt of the fourth transistor T4 can be located on the side of the top gate T3gt of the third transistor T3 away from the second light-emitting control line second substructure EM22; the first light-emitting control line second substructure EM12 is on the side of the top gate T4gt of the fourth transistor T4 away from the second light-emitting control line second substructure EM22; in the first direction X, the top gate T4gt of the fourth transistor T4 and the top gate T4gt of the first transistor T1 are located on opposite sides of the second light-emitting control line second substructure EM22. 1gt can be located on the same side of the top gate T3gt of the third transistor T3 and the top gate T2gt of the second transistor T2; taking the Mth row and Nth column sub-pixel as an example: in the second direction Y, the top gate T1gt of the first transistor T1 can be located on the side of the second substructure EM22 of the second light-emitting control line away from the M+1th row sub-pixel, the top gate T2gt of the second transistor T2 can be located on the side of the second substructure EM22 of the second light-emitting control line close to the M+1th row sub-pixel, the top gate T3gt of the third transistor T3 can be located on the side of the top gate T1gt of the first transistor T1 away from the M+1th row sub-pixel, and the top gate T4gt of the fourth transistor T4 can be located on the side of the top gate T3gt of the third transistor T3 away from the M+1th row sub-pixel; in the first direction X, the top gate T4gt of the fourth transistor T4 and the top gate T1gt of the first transistor T1 can be located on the side of the top gate T3gt of the third transistor T3 and the top gate T2gt of the second transistor T2 close to the N-1th column sub-pixel.

[0170] For example, Figure 17This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, and a third metal layer provided in at least one embodiment of the present disclosure. In an exemplary embodiment, the region where the second substructure EM22 of the second light-emitting control line overlaps with the active layer AT6 of the sixth transistor T6 can serve as the top gate T6gt of the sixth transistor T6. In an exemplary embodiment, the orthographic projection of the second substructure EM22 of the second light-emitting control line on the substrate at least partially overlaps with the orthographic projection of the first substructure EM21 of the second light-emitting control line on the substrate. For example, the orthographic projection of the second substructure EM22 of the second light-emitting control line on the substrate can be located within the range of the orthographic projection of the first substructure EM21 of the second light-emitting control line on the substrate, which can save space on the display substrate and improve the utilization rate of the display substrate space. The region where the second substructure EM12 of the first light-emitting control line overlaps with the active layer AT5 of the fifth transistor T5 can serve as the top gate T5gt of the fifth transistor T5. In an exemplary embodiment, the orthographic projection of the second substructure EM12 of the first light-emitting control line on the substrate at least partially overlaps with the orthographic projection of the first substructure EM11 of the first light-emitting control line on the substrate. For example, the orthographic projection of the second substructure EM12 of the first light-emitting control line on the substrate may be located within the range of the orthographic projection of the first substructure EM11 of the first light-emitting control line on the substrate, which can save space on the display substrate and improve the utilization rate of the display substrate space.

[0171] For example, in an exemplary embodiment, the orthographic projection of the top gate T1gt of the first transistor T1 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate; the orthographic projection of the top gate T2gt of the second transistor T2 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate; the orthographic projection of the top gate T3gt of the third transistor T3 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT3 of the third transistor T3 onto the substrate; and the orthographic projection of the top gate T4gt of the fourth transistor T4 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT4 of the fourth transistor T4 onto the substrate.

[0172] For example, in an exemplary embodiment, after the pattern of the third metal layer is formed, the third metal layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the third metal layer forms the channel region of the first transistor T1 to the sixth transistor T6. The semiconductor layer in the region not shielded by the third metal layer is conducted, that is, the first and second regions of the active layer AT1 of the first transistor T1 to the first and second regions of the active layer AT6 of the sixth transistor T6 are all conducted.

[0173] For example, the process of forming the third metal layer includes: sequentially depositing a third insulating film and a third metal film on a substrate on which the aforementioned pattern is formed; patterning the third metal film using a patterning process to form a third insulating layer covering the semiconductor layer, and a pattern of the third metal layer disposed on the third insulating layer. In an exemplary embodiment, the third metal layer may be referred to as the third gate metal (GATE3) layer.

[0174] For example, in embodiments of this disclosure, the partial overlap of element A and element B can mean that a portion of element A overlaps with element B, a portion of element B overlaps with element A, or a portion of element A overlaps with a portion of element B. Element A and element B are two different elements.

[0175] For example, Figure 18 This is a schematic planar structure diagram of a fourth insulating layer in a display panel according to at least one embodiment of the present disclosure, wherein the fourth insulating layer 206 is represented by a via on the fourth insulating layer. Figure 19 This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, and a fourth insulating layer provided in at least one embodiment of the present disclosure.

[0176] For example, such as Figure 18 and Figure 19 As shown, at least some of the vias in the sub-pixels include: the tenth via V10, the eleventh via V11, the twelfth via V12, the thirteenth via V13, the fifteenth via V15, the sixteenth via V16, and the seventeenth via V17.

[0177] For example, combining Figure 18 and Figure 19 As shown, in an exemplary embodiment, the orthogonal projection of the tenth via V10 onto the substrate lies within the range of the orthogonal projection of the bottom gate T1gb of the first transistor T1 onto the substrate. The fourth, third, and second insulating layers, as well as the subsequently formed fifth insulating layer, within the tenth via V10 are etched away, exposing the surface of the bottom gate T1gb of the first transistor T1. The tenth via V10 is configured to allow the subsequently formed first reset control line Reset1 to connect to the bottom gate T1gb of the first transistor T1 through the tenth via V10.

[0178] For example, combining Figure 18 and Figure 19As shown, in an exemplary embodiment, the orthogonal projection of the eleventh via V11 onto the substrate lies within the orthogonal projection of the bottom gate T2gb of the second transistor T2 onto the substrate. The fourth, third, and second insulating layers, as well as the subsequently formed fifth insulating layer, within the eleventh via V11 are etched away, exposing the surface of the bottom gate T2gb of the second transistor T2. The eleventh via V11 is configured to allow the subsequently formed second reset control line Reset2 to connect to the bottom gate T2gb of the second transistor T2 through the eleventh via V11.

[0179] For example, combining Figure 18 and Figure 19 As shown, in an exemplary embodiment, the orthogonal projection of the twelfth via V12 onto the substrate lies within the orthogonal projection of the bottom gate T4gb of the fourth transistor T4 onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the subsequently formed fifth insulating layer within the twelfth via V12 are etched away, exposing the surface of the bottom gate T4gb of the fourth transistor T4. The twelfth via V12 is configured to allow the subsequently formed scan signal line Gate to be connected to the bottom gate T4gb of the fourth transistor T4 through the twelfth via V12.

[0180] For example, combining Figure 18 and Figure 19 As shown, in an exemplary embodiment, the orthogonal projection of the thirteenth via V13 onto the substrate is located within the range of the orthogonal projection of the first electrode C21 of the second capacitor C2 onto the substrate (the orthogonal projection of the thirteenth via V13 onto the substrate may be located within the range of the orthogonal projection of the second connection portion CL2 onto the substrate). The fourth insulating layer, the third insulating layer, the second insulating layer, the first insulating layer, and the subsequently formed fifth insulating layer within the thirteenth via V13 are etched away, exposing the surface of the first electrode C21 of the second capacitor C2. The thirteenth via V13 is configured to allow the subsequently formed sixth connection electrode to be connected to the first electrode C21 of the second capacitor C2 through the thirteenth via V13.

[0181] For example, combining Figure 18 and Figure 19 As shown, in an exemplary embodiment, the orthographic projection of the fifteenth via V15 onto the substrate lies within the orthographic projection of the first electrode C11 of the first capacitor C1 onto the substrate. The fourth, third, second, and first insulating layers, as well as the subsequently formed fifth insulating layer, within the fifteenth via V15 are etched away, exposing the surface of the first electrode C11 of the first capacitor C1. The fifteenth via V15 is configured to allow the second electrode of the subsequently formed fourth transistor T4 to be connected to the first electrode C11 of the first capacitor C1 through the fifteenth via V15.

[0182] For example, combining Figure 18 and Figure 19 As shown, in an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate lies within the orthographic projection of the second electrode C12 of the first capacitor C1 onto the substrate. The fourth, third, and second insulating layers, as well as the subsequently formed fifth insulating layer, within the sixteenth via V16 are etched away, exposing the surface of the second electrode C12 of the first capacitor C1. The sixteenth via V16 is configured to allow the second electrode of the subsequently formed third transistor T3 (which is also the first electrode of the sixth transistor T6) to be connected to the second electrode C12 of the first capacitor C1 through the sixteenth via V16.

[0183] For example, combining Figure 18 and Figure 19 As shown, in an exemplary embodiment, the orthogonal projection of the seventeenth via V17 onto the substrate lies within the orthogonal projection of the second electrode C22 of the second capacitor C2 onto the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer, and the subsequently formed fifth insulating layer within the seventeenth via V17 are etched away, exposing the surface of the second electrode C22 of the second capacitor C2. The seventeenth via V17 is configured to allow the second electrode of the subsequently formed third transistor T3 (which is also the first electrode of the sixth transistor T6) to be connected to the second electrode C22 of the second capacitor C2 through this via.

[0184] For example, the process of forming the pattern of the fourth insulating layer includes: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed; patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third metal layer; and having multiple vias on the fourth insulating layer, such as... Figure 18 As shown, Figure 18 This is a planar structure diagram of a sub-pixel after the fourth insulating layer is formed.

[0185] For example, Figure 20 This is a schematic planar structure diagram of a fifth insulating layer in a display panel provided in at least one embodiment of the present disclosure, wherein the fifth insulating layer is represented by a via on the fifth insulating layer. Figure 21 This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, and a fifth insulating layer provided for at least one embodiment of this disclosure.

[0186] For example, such as Figure 20 and Figure 21 As shown, at least some of the vias in the sub-pixels include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a fourteenth via V14, an eighteenth via V18, and a nineteenth via V19.

[0187] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The fifth, fourth, and third insulating layers within the first via V1 are etched away, exposing the surface of the first region AT11 of the active layer AT1 of the first transistor T1. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the active layer AT1 of the first transistor T1 through the first via V1.

[0188] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The fifth, fourth, and third insulating layers within the second via V2 are etched away, exposing the surface of the second region AT12 of the active layer AT1 of the first transistor T1. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the active layer AT1 of the first transistor T1 through the via.

[0189] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate. The fifth, fourth, and third insulating layers within the third via V3 are etched away, exposing the surface of the first region AT21 of the active layer AT2 of the second transistor T2. The third via V3 is configured to allow the first electrode of the subsequently formed second transistor T2 to be connected to the active layer AT2 of the second transistor T2 through the via.

[0190] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthogonal projection of the fourth via V4 onto the substrate lies within the orthogonal projection range of the second region AT22 of the active layer AT2 of the second transistor T2 (which is also the second region AT62 of the active layer AT6 of the sixth transistor T6) onto the substrate. The fifth, fourth, and third insulating layers within the fourth via V4 are etched away, exposing the surface of the second region AT22 of the active layer AT2 of the second transistor T2 (which is also the second region AT62 of the active layer AT6 of the sixth transistor T6). The fourth via V4 is configured to connect the second electrode of the subsequently formed second transistor T2 to the active layer AT2 of the second transistor T2 through the via, and to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer AT6 of the sixth transistor T6 through the via.

[0191] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate lies within the orthographic projection of the active layer AT3 of the third transistor T3 onto the substrate. The fifth, fourth, and third insulating layers within the fifth via V5 are etched away, exposing the surface of the second region AT32 of the active layer AT3 of the third transistor T3 (which is also the first region AT61 of the active layer AT6 of the sixth transistor T6). The fifth via V5 is configured to connect the second electrode of the subsequently formed third transistor T3 to the active layer AT3 of the third transistor T3 through the via, and to connect the first electrode of the subsequently formed sixth transistor T6 to the active layer AT6 of the sixth transistor T6 through the via.

[0192] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthogonal projection of the sixth via V6 onto the substrate lies within the orthogonal projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The fifth, fourth, and third insulating layers within the sixth via V6 are etched away, exposing the first region AT41 of the active layer AT4 of the fourth transistor T4. The sixth via V6 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the active layer AT4 of the fourth transistor T4 through this via.

[0193] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthogonal projection of the seventh via V7 onto the substrate lies within the orthogonal projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The fifth, fourth, and third insulating layers within the seventh via V7 are etched away, exposing the second region AT42 of the active layer AT4 of the fourth transistor T4. The seventh via V7 is configured to allow the second electrode of the subsequently formed fourth transistor T4 to be connected to the active layer AT4 of the fourth transistor T4 through this via.

[0194] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the active layer AT5 of the fifth transistor T5 onto the substrate. The fifth, fourth, and third insulating layers within the eighth via V8 are etched away, exposing the surface of the first region AT51 of the active layer AT5 of the fifth transistor T5. The eighth via V8 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the active layer AT5 of the fifth transistor T5 through this via.

[0195] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the substrate lies within the orthogonal projection of the top gate T3gt of the third transistor T3 onto the substrate. The fifth and fourth insulating layers within the ninth via V9 are etched away, exposing the surface of the top gate T3gt of the third transistor T3. The ninth via V9 is configured to allow the second terminal of the subsequently formed fourth transistor T4 to be connected to the top gate T3gt of the third transistor T3 through this via.

[0196] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthogonal projection of the fourteenth via V14 onto the substrate lies within the orthogonal projection of the top gate T4gt of the fourth transistor T4 onto the substrate. The fourth and fifth insulating layers within the fourteenth via V14 are etched away, exposing the surface of the top gate T4gt of the fourth transistor T4. The fourteenth via V14 is configured to allow the subsequently formed scan signal line Gate to be connected to the top gate T4gt of the fourth transistor T4 through this via.

[0197] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthographic projection of the eighteenth via V18 onto the substrate lies within the range of the orthographic projection of the top gate T1gt of the first transistor T1 onto the substrate. The fourth and fifth insulating layers within the eighteenth via V18 are etched away, exposing the surface of the top gate T1gt of the first transistor T1. The eighteenth via V18 is configured to allow the subsequently formed first reset control line Reset1 to connect to the top gate T1gt of the first transistor T1 through this via.

[0198] For example, such as Figure 20 and Figure 21 As shown, in an exemplary embodiment, the orthogonal projection of the nineteenth via V19 onto the substrate lies within the range of the orthogonal projection of the top gate T2gt of the second transistor T2 onto the substrate. The fourth and fifth insulating layers within the nineteenth via V19 are etched away, exposing the surface of the top gate T2g of the second transistor T2. The nineteenth via V19 is configured to allow the subsequently formed second reset control line Reset2 to connect to the top gate T2gt of the second transistor T2 through this via.

[0199] For example, the process of forming the pattern of the fifth insulating layer includes: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed; patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third metal layer; and providing multiple vias on the fifth insulating layer, such as... Figure 20 As shown, Figure 20This is a planar structure diagram of a sub-pixel after the fourth insulating layer is formed.

[0200] For example, in another embodiment, the fourth and fifth insulating layers can be formed by the same deposition process, that is, the vias in the fourth and fifth insulating layers can be vias of different depths on the same insulating layer to form a connection channel.

[0201] For example, Figure 22 This is a schematic diagram of the planar structure of the first conductive layer in a display panel according to at least one embodiment of the present disclosure. Figure 23 This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, and a first conductive layer provided for at least one embodiment of the present disclosure.

[0202] For example, combining Figure 22 and Figure 23 As shown, the first conductive layer 208 includes at least: a first high-voltage power supply signal line VDD1, a scan signal line Gate, a first reset control line Reset1, a first initialization signal line Vinit11, a second reset control line Reset2, a second initialization signal line Vinit21, a first low-voltage power supply signal line VSS1, a first connection electrode L1, a second connection electrode L2, a third connection electrode L3, a fourth connection electrode L4, and a first fan-out data line FIP H.

[0203] For example, combining Figure 22 and Figure 23 As shown, in an exemplary embodiment, the main body of the first high-voltage power signal line VDD1, the scan signal line Gate, the first reset control line Reset1, the first initialization signal line Vinit11, the second reset control line Reset2, the second initialization signal line Vinit21, the first low-voltage power signal line VSS1, and the first fan-out data line FIP H is a strip-shaped structure or a broken line structure extending along the first direction X. In the same row of sub-pixels, the first high-voltage power signal line VDD1, the scan signal line Gate, the first reset control line Reset1, the first initialization signal line Vinit11, the second reset control line Reset2, the second initialization signal line Vinit21, the first low-voltage power signal line VSS1, and the first fan-out data line FIP H are arranged sequentially at intervals in the second direction Y.

[0204] It should be noted that the first direction X is the same as the extension direction of the scanning signal line.

[0205] For example, combining Figure 22 and Figure 23As shown, in an exemplary embodiment, within the same sub-pixel, in the second direction Y, the first connecting electrode L1 and the third connecting electrode L3 are located between the first reset control line Reset1 and the scan signal line Gate, the second connecting electrode L2 is located between the first initialization signal line Vinit11 and the second reset control line Reset2, and the fourth connecting electrode L4 is located on the side of the scan signal line Gate away from the first reset control line Reset1. In the first direction X, the first connecting electrode L1 and the fourth connecting electrode L4 may be located on the same side of the third connecting electrode L3. Taking the Mth row and Nth column sub-pixel as an example: In the second direction Y, the scan signal line Gate can be located on the side of the first reset control line Reset1 away from the M+1th row sub-pixel, the first initialization signal line Vinit11 can be located on the side of the first reset control line Reset1 close to the M+1th row sub-pixel, the second reset control line Reset2 can be located on the side of the first initialization signal line Vinit11 close to the M+1th row sub-pixel, the second initialization signal line Vinit21 can be located on the side of the second reset control line Reset2 close to the M+1th row sub-pixel, the first connecting electrode L1 and the third connecting electrode L3 are located on the side of the first reset control line Reset1 away from the M+1th row sub-pixel, the second connecting electrode L2 can be located on the side of the first initialization signal line Vinit11 close to the M+1th row sub-pixel, and the fourth connecting electrode L4 is located on the side of the scan signal line Gate away from the M+1th row sub-pixel. In the first direction X, the first connecting electrode L1 and the fourth connecting electrode L4 are located on the side of the third connecting electrode L3 away from the N+1th column sub-pixel.

[0206] For example, combining Figure 22 and Figure 23 As shown, in an exemplary embodiment, the scan signal line Gate can be connected to the top gate T4gt of the fourth transistor T4 in a row of sub-pixels via the fourteenth via V14, and to the bottom gate T4gb of the fourth transistor T4 in the same row of sub-pixels via the twelfth via V12, thus providing scan signals to the bottom gate T4gb and top gate T4gt of multiple fourth transistors T4 in that row of sub-pixels. Within the same sub-pixel, the bottom gate T4gb and top gate T4gt of the fourth transistor T4 can be electrically connected via the scan signal line Gate, ensuring that the bottom gate T4gb and top gate T4gt of the fourth transistor T4 in the same sub-pixel have the same potential.

[0207] For example, combining Figure 22 and Figure 23As shown, in an exemplary embodiment, the first reset control line Reset1 can be connected to the top gate T1gt of the first transistor T1 in a row of sub-pixels via the eighteenth via V18 in that row of sub-pixels, and to the bottom gate T1gb of the first transistor T1 in that row of sub-pixels via the tenth via V10 in that row of sub-pixels, configured to provide a first reset control signal to the bottom gate T1gb and top gate T1gt of multiple first transistors T1 in that row of sub-pixels. Within the same sub-pixel, the bottom gate T1gb and top gate T1gt of the first transistor T1 can be electrically connected via the first reset control line Reset1, so that the bottom gate T1gb and top gate T1gt of the first transistor T1 in the same sub-pixel have the same potential.

[0208] For example, combining Figure 22 and Figure 23 As shown, in an exemplary embodiment, the first initialization signal line Vinit11 can be connected to the first region AT11 of the active layer AT1 of the first transistor T1 in that row of sub-pixels via a first via V1 in that row of sub-pixels, and is configured to provide a first initialization signal to the first transistor T1 in that row of sub-pixels. In an exemplary embodiment, the first initialization signal line Vinit11 can serve as the first electrode of the first transistor T1.

[0209] For example, combining Figure 22 and Figure 23 As shown, in an exemplary embodiment, the second reset control line Reset2 can be connected to the top gate T2gt of the second transistor T2 in a row of sub-pixels via the nineteenth via V19 in that row, and to the bottom gate T2gb of the second transistor T2 in that row via the eleventh via V11 in that row, thus providing a second reset control signal to the bottom gate T2gb and top gate T2gt of multiple second transistors T2 in that row of sub-pixels. Within the same sub-pixel, the bottom gate T2gb and top gate T2gt of the second transistor T2 can be electrically connected via the second reset control line Reset2, so that the bottom gate T2gb and top gate T2gt of the second transistor T2 in the same sub-pixel have the same potential.

[0210] For example, combining Figure 22 and Figure 23 As shown, in an exemplary embodiment, the second initialization signal line Vinit21 can be connected to the first region AT21 of the active layer AT2 of the second transistor T2 located in that row of sub-pixels via a third via V3 in that row of sub-pixels, configured to provide a second initialization signal to the second transistor T2 in that row of sub-pixels. In an exemplary embodiment, the second initialization signal line Vinit21 can serve as the first electrode of the second transistor T2.

[0211] For example, combining Figure 22 and Figure 23 As shown, in an exemplary embodiment, the first connection electrode L1 is approximately polygonal in shape. The first connection electrode L1 can be connected to the second region AT12 of the active layer AT1 of the first transistor T1 via the second via V2, and to the first electrode C11 of the first capacitor C1 via the fifteenth via V15. The second region AT12 of the active layer AT1 of the first transistor T1 and the first electrode C11 of the first capacitor C1 can be electrically connected via the first connection electrode L1, so that the second electrode of the first transistor T1 and the first electrode C11 of the first capacitor C1 in the same sub-pixel have the same potential. In an exemplary embodiment, the first connection electrode L1 can serve as the second electrode of the first transistor T1.

[0212] For example, combining Figure 22 and Figure 23 As shown, in an exemplary embodiment, the first connection electrode L1 is also connected to the second region AT42 of the active layer AT4 of the fourth transistor T4 through the seventh via V7, to the first plate C11 of the first capacitor C1 through the fifteenth via V15, and to the top gate T3gt of the third transistor T3 through the ninth via V9, so that the top gate T3gt of the third transistor T3, the first plate C11 of the first capacitor C1, and the second region AT42 of the active layer AT4 of the fourth transistor T4 in the same sub-pixel have the same potential. Since the first plate C11 of the first capacitor C1 is connected to the second region AT12 of the active layer AT1 of the first transistor T1 through the first connection electrode L1, the second region AT12 of the active layer AT1 of the first transistor T1 can have the same potential as the top gate T3gt of the third transistor T3, the first plate C11 of the first capacitor C1, and the second region AT42 of the active layer AT4 of the fourth transistor T4, that is, the first connection electrode L1 can have the same potential as the gate T3gt of the third transistor T3. In an exemplary embodiment, the first connection electrode L1 can serve as the second electrode of the fourth transistor T4.

[0213] For example, combining Figure 22 and Figure 23 As shown, in an exemplary embodiment, the second connection electrode L2 is generally zigzag-shaped, and can be connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT22 of the active layer AT2 of the second transistor T2) via the fourth via V4. In an exemplary embodiment, the second connection electrode L2 can serve as the second electrode of the sixth transistor T6 and the second electrode of the second transistor T2, and is configured to be connected to the anode connection electrode of a subsequently formed light-emitting element.

[0214] For example, combining Figure 22 and Figure 23As shown, in an exemplary embodiment, the third connection electrode L3 has a zigzag shape. The third connection electrode L3 can be connected to the second region AT32 of the active layer AT3 of the third transistor T3 (which is also the first region AT61 of the active layer AT6 of the sixth transistor T6) through the fifth via V5, to the second plate C12 of the first capacitor C1 through the sixteenth via V16, and to the second plate C22 of the second capacitor C2 through the seventeenth via V17. This ensures that the second region AT32 of the active layer AT3 of the third transistor T3 (which is also the first region AT61 of the active layer AT6 of the sixth transistor T6), the second plate C12 of the first capacitor C1, and the second plate C22 of the second capacitor C2 in the same sub-pixel have the same potential. In an exemplary embodiment, the third connection electrode L3 can serve as the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.

[0215] For example, combining Figure 22 and Figure 23 As shown, in an exemplary embodiment, the fourth connection electrode L4 is generally a block structure or a rectangular structure extending along the first direction X. The fourth connection electrode L4 can be connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the sixth via V6. In an exemplary embodiment, the fourth connection electrode L4 can serve as the first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0216] For example, combining Figure 22 and Figure 23 As shown, in an exemplary embodiment, the first high-voltage power signal line VDD1 is generally strip-shaped or zigzag-shaped extending along the first direction X. The first high-voltage power signal line VDD1 is connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 in the same sub-pixel through the eighth via V8, and to the first electrode C21 of the second capacitor C2 through the thirteenth via V13. In an exemplary embodiment, the first high-voltage power signal line VDD1 can serve as the first electrode of the fifth transistor T5. In the same sub-pixel, the first region AT51 of the active layer AT5 of the fifth transistor T5 and the first electrode C21 of the second capacitor C2 can be electrically connected through the first high-voltage power signal line VDD1, so that the first region AT51 of the active layer AT5 of the fifth transistor T5 and the first electrode C21 of the second capacitor C2 in the same sub-pixel have the same potential.

[0217] For example, in an exemplary embodiment, forming the first conductive layer 208 may include: depositing a first conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the first conductive thin film using a patterning process to form a first conductive layer disposed on a fifth insulating layer. Figure 23This is a schematic diagram of the stacked structure after the formation of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0218] For example, the display panel also includes a data writing transistor T4, a first reset transistor T1, and a second reset transistor T2. The first conductive layer 208 includes a scan signal line Gate, a first reset control line Reset1, a second reset control line Reset2, and a first connection electrode L1. The scan signal line Gate is configured to provide a control signal to the data writing transistor T4, the first reset control line Reset1 is configured to provide a control signal to the first reset transistor T1, and the second reset control line Reset2 is configured to provide a control signal to the second reset transistor T2. The data writing transistor T4 is configured to provide a data signal to the pixel circuit, the first reset transistor T1 is configured to provide a first reset signal, and the second reset transistor T2 is configured to provide an initialization voltage signal. The first connection electrode L1 is electrically connected to the gate of the driving transistor T3, the second electrode of the data writing transistor T4, and the second electrode of the first reset transistor T1.

[0219] For example, in one example, a first fan-out data line FIP H is disposed on a first conductive layer 208, and a second conductive layer 210 is provided with a second low-voltage power supply signal line VSS2 extending in a second direction Y, and at least a portion of the second low-voltage power supply signal line VSS2 covers the gate of the driving transistor T3.

[0220] For example, in one example, a first fan-out data line FIP H is disposed on a first conductive layer 208, and a second conductive layer 210 is provided with a second low-voltage power signal line VSS2 extending in a second direction Y, and at least a portion of the second low-voltage power signal line VSS2 covers the first connection electrode L1.

[0221] For example, Figure 24 This is a schematic diagram of the planar structure of a first planarization layer and a sixth insulating layer in a display panel according to at least one embodiment of the present disclosure. Figure 25 This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, and a first planarization layer provided in at least one embodiment of the present disclosure.

[0222] For example, combining Figure 24 and Figure 25 As shown, in an exemplary embodiment, the plurality of vias on the sixth insulating layer and the first planarization layer may include at least: a twenty-third via V23, a twenty-fourth via V24, and a twenty-fifth via V25.

[0223] It should be noted that, although in Figure 24 and Figure 25 It is not shown in the figure, but the sixth insulating layer and the first planarization layer also include other vias, such as vias that connect the first high voltage power signal line VDD1 and the second high voltage power signal line VDD2.

[0224] For example, combining Figure 24 and Figure 25 As shown, in an exemplary embodiment, the orthographic projection of the 23rd via V23 onto the substrate lies within the range of the orthographic projection of the fourth connection electrode L4 onto the substrate. The first planarization layer and the sixth insulating layer within the 23rd via V23 are etched away, exposing the surface of the fourth connection electrode L4. The 23rd via V23 is configured to allow subsequently formed data signal lines to be electrically connected to the fourth connection electrode L4 through this via.

[0225] For example, combining Figure 24 and Figure 25 As shown, in an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 onto the substrate lies within the range of the orthographic projection of the first low-voltage power signal line VSS1 onto the substrate. The first planarization layer and the sixth insulating layer within the twenty-fourth via V24 are etched away, exposing the surface of the first low-voltage power signal line VSS1. The twenty-fourth via V24 is configured to allow the subsequently formed second low-voltage power signal line VSS2 to connect to the first low-voltage power signal line VSS1 through this via.

[0226] For example, combining Figure 24 and Figure 25 As shown, in an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate lies within the range of the orthographic projection of the second connection electrode L2 onto the substrate. The first planarization layer and the sixth insulating layer within the 25th via V25 are etched away, exposing the surface of the second connection electrode L2. The 25th via V25 is configured to allow the anode connection electrode of a subsequently formed light-emitting element to be electrically connected to the second connection electrode L2 through this via.

[0227] For example, the pattern forming the sixth insulating layer and the first planarization layer may include: first depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, then coating a first planarization film, and using a patterning process to pattern the first planarization film and the sixth insulating film to form a sixth insulating layer covering the first conductive layer and a first planarization layer disposed on the sixth insulating layer, wherein multiple vias are provided on the sixth insulating layer and the first planarization layer. Figure 24 This is a planar structure diagram after the formation of the first planarization layer.

[0228] For example, in some implementations, the sixth insulating layer may be absent.

[0229] For example, Figure 26This is a schematic diagram of the planar structure of a second conductive layer in a display panel according to at least one embodiment of the present disclosure. Figure 27 This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, and a second conductive layer, provided for at least one embodiment of this disclosure.

[0230] For example, a first conductive layer 208 is disposed on the side of the third metal layer 204 away from the substrate, and a second conductive layer 210 is disposed on the side of the first conductive layer 208 away from the substrate. An insulating layer is disposed between the first conductive layer 208 and the second conductive layer 210, so that the first conductive layer 208 and the second conductive layer 210 are electrically connected at the electrical connection location through a via structure disposed in the insulating layer.

[0231] For example, in an exemplary embodiment, such as Figure 26 and Figure 27 As shown, the second conductive layer 210 includes at least: a data signal connection structure Data L, a second high-voltage power signal line VDD2, a first anode connection electrode ZL1, and a second low-voltage power signal line VSS2.

[0232] For example, in an exemplary embodiment, such as Figure 26 and Figure 27 As shown, the data signal connection structure Data L is a short strip extending along the second direction Y. The data signal connection structure Data L is connected to the fourth connection electrode L4 through the twenty-third via V23. Since the fourth connection electrode L4 is connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the via, the connection between the data signal line Data and the first electrode of the fourth transistor T4 is realized, and the data signal is written to the fourth transistor T4.

[0233] For example, in an exemplary embodiment, such as Figure 26 and Figure 27 As shown, the second low-voltage power signal line VSS2 is a zigzag or strip-shaped structure whose main body extends along the second direction Y. The second low-voltage power signal line VSS2 is connected to the first low-voltage power signal line VSS1 through the twenty-fourth via V24. Multiple second low-voltage power signal lines VSS2 and multiple first low-voltage power signal lines VSS1 are interconnected to form a mesh structure.

[0234] For example, the second high-voltage power signal line VDD2 and the first high-voltage power signal line VDD1 cross and are electrically connected to form a mesh structure.

[0235] For example, in an exemplary embodiment, the first anode connection electrode ZL1 can be in the shape of an "I" or a strip structure extending along the second direction Y. The first anode connection electrode ZL1 can be connected to the second connection electrode L2 through the twenty-fifth via V25. Since the second connection electrode L2 is connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT22 of the active layer AT2 of the second transistor T2) through the via, the connection between the first anode connection electrode ZL1 and the second electrode of the sixth transistor T6 and the second electrode of the second transistor T2 is realized.

[0236] For example, in an exemplary embodiment, within the same sub-pixel, the data signal connection structure Data L, the second high-voltage power signal line VDD2, and the second low-voltage power signal line VSS2 can be arranged sequentially along a first direction X. In the first direction X, the data signal connection structure Data L and the second low-voltage power signal line VSS2 can be located on opposite sides of the second high-voltage power signal line VDD2, and the first anode connection electrode ZL1 can be located between the second high-voltage power signal line VDD2 and the second low-voltage power signal line VSS2.

[0237] It should be noted that in other examples, the line at the location of the second low-voltage power signal line VSS2 can also be either the first initialization signal connection line Vinit12 or the second initialization signal connection line Vinit22. When the line is the second low-voltage power signal line VSS2, it is conductive at the location of the twenty-fourth via V24, so that the second low-voltage power signal line VSS2 is connected to the second low-voltage power signal line VSS1 through the twenty-fourth via V24. When the line is the second initialization signal connection line Vinit22, the first planarization layer also has a via structure at the location corresponding to the third via V3, and this via structure and the third via V3 are connected and conductive, so that the second initialization signal line Vinit21 and the second initialization signal connection line Vinit22 are connected to form a mesh structure, while the location of the twenty-fourth via V24 is not conductive. When the line is the first initialization signal connection line Vinit12, the first planarization layer also has a via structure at the position corresponding to the first initialization signal line Vinit12, and the via structure is conductive, so that the first initialization signal connection line Vinit12 and the first initialization signal line Vinit11 are connected to form a mesh structure, while the position of the twenty-fourth via V24 is not conductive.

[0238] For example, in one example, the first conductive layer 208 includes a first high-voltage power signal line VDD1 and a first low-voltage power signal line VSS1 extending in the first direction X; the second conductive layer 210 includes a second high-voltage power signal line VDD2 and a second low-voltage power signal line VSS2 extending in the second direction Y; the first fan-out data line may be located in the second conductive layer 210, or in the first conductive layer 208 and the second conductive layer 210.

[0239] For example, in one instance, multiple first high-voltage power signal lines VDD1 and multiple second high-voltage power signal lines VDD2 intersect and are electrically connected to form a mesh structure, and multiple first low-voltage power signal lines VSS1 and multiple second low-voltage power signal lines VSS2 intersect and are electrically connected to form a mesh structure.

[0240] For example, in one example, the first conductive layer 208 includes a first low-voltage power signal line VSS1, a first initialization signal line Vinit11, and a second initialization signal line Vinit21 extending in a first direction X; the second conductive layer 210 includes a second low-voltage power signal line VSS2, a first initialization signal connection line Vinit12, and a second initialization signal connection line Vinit22 extending in a second direction Y; a first fan-out data line FIP H is located in at least one of the first conductive layer 208 and the second conductive layer 210; the first low-voltage power signal line VSS1 and the second low-voltage power signal line VSS2 are connected, the first initialization signal line Vinit11 and the first initialization signal connection line Vinit12 are connected, and the second initialization signal line Vinit12 and the second initialization signal connection line Vinit22 are connected to form a mesh.

[0241] For example, Figure 28 This is a schematic diagram of the planar structure of a second planarization layer in a display panel according to at least one embodiment of the present disclosure. Figure 29 This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, a second conductive layer, and a second planarization layer provided for at least one embodiment of this disclosure.

[0242] For example, combining Figure 28 and Figure 29 As shown, in an exemplary embodiment, the plurality of vias on the second planarization layer 211 may include at least: a twenty-sixth via V26 and a twenty-seventh via V27.

[0243] For example, such as Figure 29As shown, the orthographic projection of the twenty-sixth via V26 on the substrate lies within the orthographic projection of the data signal connection structure Data L on the substrate, and is used to connect the data signal connection structure Data L and the subsequently formed data signal line Data. The twenty-seventh via V27 is used to electrically connect the subsequently formed second anode connection electrode ZL2 and the first anode connection electrode ZL1.

[0244] For example, such as Figure 29 As shown, the display panel includes: a substrate, and a first metal layer 201, a second metal layer 202, a semiconductor layer 203, and a third metal layer 204 sequentially stacked on the substrate. The first metal layer 201 includes a first electrode C11 of a first capacitor C1, the second metal layer 202 includes a second electrode C12 of the first capacitor C1, and the third metal layer 204 includes a gate T3gt of a driving transistor T3. The second electrode C12 of the first capacitor C1 and the gate T3gt of the driving transistor T3 are electrically connected. The display panel also includes a first fan-out data line FIP H and a first low-voltage power signal line VSS1 extending in a first direction X, and a second low-voltage power signal line VSS2 and a data signal line extending in a second direction Y. The first direction X and the second direction Y intersect. The first fan-out data line FIP H and at least one of the first low-voltage power signal lines VSS1 and VSS2 are disposed on the same layer, and the first fan-out data line FIP H is configured to connect to at least one data line.

[0245] For example, such as Figure 29 As shown, the display panel includes: a substrate; a first metal layer 201, a second metal layer 202, a semiconductor layer 203, and a third metal layer 204 sequentially stacked on the substrate; wherein, the first metal layer 201 includes a first electrode C11 of a first capacitor C2, the second metal layer 202 includes a second electrode C12 of the first capacitor C1, and the third metal layer 204 includes a gate of a driving transistor T3, the second electrode C12 of the first capacitor C1 and the gate of the driving transistor T3 are electrically connected; the display panel also includes a first fan-out data line FIP H extending in a first direction X and a second fan-out data line FIP V extending in a second direction Y, the first direction X and the second direction Y intersect, the first fan-out data line FIP H and the second fan-out data line FIP V are located in different layers, and at least one organic insulating layer is disposed between the first fan-out data line FIP H and the second fan-out data line FIP V.

[0246] For example, Figure 30 This is a schematic diagram of the planar structure of a third conductive layer in a display panel according to at least one embodiment of the present disclosure. Figure 31This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, a second conductive layer, a second planarization layer, and a third conductive layer provided for at least one embodiment of this disclosure.

[0247] For example, in an exemplary embodiment, such as Figure 30 and Figure 31 As shown, the third conductive layer 212 includes at least: a data signal line Data, a second fan-out data line FIP V, and a second anode connection electrode ZL2.

[0248] For example, in an exemplary embodiment, such as Figure 30 and Figure 31 As shown, the data signal connection structure Data L and the data signal line Data are electrically connected through the 26th via V26, and the second anode connection electrode ZL2 and the first anode connection electrode ZL1 are electrically connected through the 27th via V27. The second fan-out data line FIP V and the first fan-out data line FIP H are electrically connected.

[0249] For example, the third conductive layer 212 is disposed on the side of the second conductive layer 210 away from the substrate. The third conductive layer 212 includes a second fan-out data line FIP V and a data signal line (Data), and the second fan-out data line FIP V and the data line are arranged adjacent to each other between adjacent sub-pixels in the first direction X.

[0250] For example, in one example, the first fan-out data line FIP H is on the first conductive layer 208, the second fan-out data line FIP V is on the third conductive layer 212, and the first fan-out data line FIP H is connected to the second fan-out data line FIP V through the second conductive layer 210.

[0251] For example, in one example, there is a first planarization layer between the first conductive layer 208 and the second conductive layer 210, and a second planarization layer between the second conductive layer 210 and the third conductive layer 212.

[0252] For example, the first planarization layer and the second planarization layer are organic layers.

[0253] For example, in one example, the first fan-out data line FIP H is on the second conductive layer 210, the second fan-out data line FIP V is on the third conductive layer 212, an insulating layer is provided between the second conductive layer 210 and the third conductive layer 212, and the first fan-out data line FIP H and the second fan-out data line FIP V are electrically connected through a via structure provided in the insulating layer.

[0254] For example, Figure 32This is a schematic diagram of the planar structure of a third planarization layer in a display panel according to at least one embodiment of the present disclosure. Figure 33 This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, a second conductive layer, a second planarization layer, a third conductive layer, and a third planarization layer provided for at least one embodiment of this disclosure.

[0255] For example, combining Figure 32 and Figure 33 As shown, in an exemplary embodiment, the plurality of vias on the third planarization layer 213 may include at least: a twenty-eighth via V28.

[0256] For example, such as Figure 33 As shown, the orthographic projection of the 28th via V28 on the substrate is within the orthographic projection of the 27th via V27 on the substrate, that is, the 28th via V28 and the 27th via V27 are connected. The 28th via V28 is used to electrically connect the subsequently formed anode and the second anode connection electrode ZL2.

[0257] For example, Figure 34 This is a schematic diagram of the planar structure of the anode layer in a display panel according to at least one embodiment of the present disclosure. Figure 35 This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, a second conductive layer, a second planarization layer, a third conductive layer, a third planarization layer, and an anode layer provided for at least one embodiment of this disclosure.

[0258] For example, combining Figure 34 and Figure 35 As shown, in an exemplary embodiment, the anode layer 214 includes a plurality of anodes 2141. Each anode 2141 is electrically connected via a twenty-eighth via V28 and a second anode connection electrode ZL2.

[0259] For example, Figure 36 This is a schematic diagram of a planar structure of a pixel definition layer in a display panel, provided by at least one embodiment of the present disclosure. Figure 37 This is a schematic diagram of the stacked structure of a first metal layer, a second metal layer, a semiconductor layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, a second conductive layer, a second planarization layer, a third conductive layer, a third planarization layer, an anode layer, and a pixel definition layer provided for at least one embodiment of this disclosure.

[0260] like Figure 36 and Figure 37As shown, the area defined by the box is the area where the pixel definition layer is removed, and the other areas are the areas where the pixel definition layer is retained, with the aforementioned anode and other structures at the location of the pixel definition layer.

[0261] For example, Figure 37 The driving circuit layer is a complete structure formed by the various layers in the driving circuit layer. The driving circuit layer is provided with pixel driving circuits for multiple sub-pixels. In the direction perpendicular to the plane where the main surface of the substrate is located, the driving circuit layer includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a semiconductor layer, a third insulating layer, a third metal layer, a fourth insulating layer, a fifth insulating layer, a first conductive layer, a sixth insulating layer, a first planarization layer, a second conductive layer, a second planarization layer, a third conductive layer, a third planarization layer, an anode layer, and a pixel definition layer, which are sequentially disposed on the substrate.

[0262] For example, in an exemplary embodiment, after the driving circuit layer is fabricated, an organic light-emitting layer is formed using vapor deposition or inkjet printing, and a cathode is formed on the organic light-emitting layer; an encapsulation layer is formed, which may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to ensure that external moisture cannot enter the light-emitting structure layer.

[0263] For example, in an exemplary embodiment, the first metal layer, second metal layer, third metal layer, first conductive layer, second conductive layer, and third conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, fifth insulating layer, sixth insulating layer, first planarization layer, second planarization layer, and third planarization layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. For example, in other examples, the first planarization layer, second planarization layer, and third planarization layer can be made of organic insulating materials, such as polyimide (PI) and its derivatives, as well as polybenzoxazole, etc.

[0264] For example, in an embodiment of this disclosure, the manufacturing process of the display panel is as follows: a pixel circuit is formed on a substrate, a light-emitting element is formed on the pixel circuit, and a display substrate is obtained, thereby the pixel circuit is closer to the substrate than the light-emitting element.

[0265] For example, the materials of the first and second electrodes of the light-emitting element can be selected as needed. In some embodiments of this disclosure, the first electrode may be at least one of a transparent conductive metal oxide and silver, but the embodiments of this disclosure are not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but the embodiments of this disclosure are not limited thereto. For example, the first electrode may have a structure in which three sublayers of ITO-Ag-ITO are stacked. In some embodiments, the second electrode may be a metal with low work function, and may be at least one of magnesium and silver, but the embodiments of this disclosure are not limited thereto.

[0266] For example, Figure 38 For the above Figures 11-37 The diagram shown is a partial enlarged view of some structures within the layout structure, such as... Figure 38 As shown, the data signal line Data is located in the third conductive layer 212, and the second high-voltage power signal line VDD2 and the second low-voltage power signal line VSS2 (or the first initialization signal connection line Vinit12 and the second initialization signal connection line Vinit22) are located in the second conductive layer 210. That is, the data signal line Data is located in the third conductive layer 212, and the remaining second low-voltage power signal line VSS2, the first initialization signal connection line Vinit12, and the second initialization signal connection line Vinit22 carry DC signals and are located in the second conductive layer 210. Since the second conductive layer is closer to the bottom metal oxide thin film transistor than the third conductive layer in the film layer stack, this pixel circuit design can reduce the parasitic capacitance of each node while ensuring that the bottom metal oxide thin film transistor is completely shielded by the second conductive layer, resulting in a better light shielding effect. Moreover, the first repair line RP can be integrated so that laser irradiation can be used to repair short circuits or open circuits in the future.

[0267] For example, such as Figure 38 As shown, the first repair line RP is in the second metal layer 202, and the first conductive layer 208 includes a second connecting electrode L2. The orthographic projection of the first repair line RP on the substrate and the orthographic projection of the second connecting electrode L2 on the substrate have an overlapping portion. If a short circuit or open circuit occurs later, the second connecting electrode L2 can be irradiated with a laser to make the second connecting electrode L2 and the first repair line RP electrically connected, thereby playing a repair role.

[0268] For example, Figure 39 for Figure 38 A schematic diagram of the stacked structure of some pixel circuits and their surrounding transition areas, as shown in the figure. Figure 39As shown, the first fan-out data line FIP H in the first conductive layer 208 has a first break 215. The first break 215 is blocked by the third low-voltage power signal line VSS3 located in the second conductive layer 210 to avoid the first break 215 anechoic visualization problem, thereby avoiding the screen-off optical anechoic visualization problem and ensuring the uniformity of the display.

[0269] For example, such as Figure 39 As shown, the second fan-out data line FIP V in the third conductive layer 212 has a second break 216, which is blocked by the first fan-out data line FIP H located in the first conductive layer 208 to avoid the visual problem of the second break 216 disappearing, thereby avoiding the visual problem of optical disappearance when the screen is off and ensuring the uniformity of the display.

[0270] For example, such as Figure 39 As shown, the first fan-out data line FIP H of the first conductive layer 208 is electrically connected to the data signal line Data at the first transition position 217 through the transition holes of the first conductive layer 208 and the second conductive layer 210, as well as the transition holes of the second conductive layer 210 and the third conductive layer 212. The first fan-out data line FIP H of the first conductive layer 208 is also electrically connected to the second fan-out data line FIP V at the second transition position 218 through the transition holes of the first conductive layer 208 and the second conductive layer 210, as well as the transition holes of the second conductive layer 210 and the third conductive layer 212.

[0271] For example, a second low-voltage power supply signal line VSS2, a first initialization signal connection line Vinit12, a second initialization signal connection line Vinit22, and a second fan-out data line FIP V can be set in the second conductive layer 210 or the third conductive layer 212. Therefore, in this case, the first fan-out data line FIP H can only be set in the first conductive layer, but the second fan-out data line FIP V can be set in the second conductive layer or the third conductive layer according to the actual situation, or alternately set in the second conductive layer and the third conductive layer.

[0272] For example, Figure 40 This disclosure provides a design schematic diagram of at least one embodiment of a first fan-out data line and a second fan-out data line, as shown below. Figure 40 As shown, a vertical trace is inserted every other subpixel, for example, in Figure 40 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other.

[0273] For example, such as Figure 40As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels. In the second direction Y, the length of the first fan-out data lines FIP H increases sequentially, while the length of the fourth low-voltage power signal line VSS4 decreases sequentially. Some of the first fan-out data lines FIP H and the fourth low-voltage power signal line VSS4 are spaced apart on the same straight line.

[0274] For example, such as Figure 40 As shown, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are both disposed on the third conductive layer, the first fan-out data line FIP H and the fourth low-voltage power signal line VSS4 are both disposed on the first conductive layer, and the first fan-out data line FIP H and the second fan-out data line FIP V are electrically connected through corresponding adapter holes.

[0275] For example, the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4 intersect to form a grid structure, which can reduce the load on the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4.

[0276] For example, Figure 41 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 41 As shown, a vertical trace is inserted every other subpixel, for example, in Figure 41 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0277] For example, such as Figure 41 As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels. In the second direction Y, the length of the first fan-out data lines FIP H increases sequentially, while the length of the fourth low-voltage power signal line VSS4 decreases sequentially. Some of the first fan-out data lines FIP H and the fourth low-voltage power signal line VSS4 are spaced apart on the same straight line.

[0278] For example, such as Figure 41As shown, in the first direction X, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V, located in the middle position, are disposed in the second conductive layer. The third low-voltage power signal line VSS3 and the second fan-out data line FIP V, located on both sides, are both disposed in the third conductive layer. The first fan-out data line FIP H and the fourth low-voltage power signal line VSS4 are both disposed in the first conductive layer, and the first fan-out data line FIP H and the second fan-out data line FIP V are electrically connected through corresponding adapter holes.

[0279] For example, the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4 intersect to form a grid structure, which can reduce the load on the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4.

[0280] For example, Figure 42 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 42 As shown, a vertical trace is inserted every other subpixel, for example, in Figure 42 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0281] For example, such as Figure 42 As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels. In the second direction Y, the length of the first fan-out data lines FIP H increases sequentially, while the length of the fourth low-voltage power signal line VSS4 decreases sequentially. Some of the first fan-out data lines FIP H and the fourth low-voltage power signal line VSS4 are spaced apart on the same straight line.

[0282] For example, such as Figure 42 As shown, in the first direction X, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V, located in the middle and rightmost positions, are disposed in the second conductive layer. The third low-voltage power signal line VSS3 and the second fan-out data line FIP V, located in the leftmost position, are disposed in the third conductive layer. The first fan-out data line FIP H and the fourth low-voltage power signal line VSS4 are both disposed in the first conductive layer, and the first fan-out data line FIP H and the second fan-out data line FIP V are electrically connected through corresponding adapter holes.

[0283] For example, the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4 intersect to form a grid structure, which can reduce the load on the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4.

[0284] For example, Figure 43 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 43 As shown, three vertical traces are inserted every three subpixels. For example, in Figure 43 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0285] For example, such as Figure 43 As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels. In the second direction Y, the length of the first fan-out data lines FIP H increases sequentially, and they are electrically connected to the second fan-out data line FIP V through an adapter hole.

[0286] For example, such as Figure 43 As shown, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are both disposed on the third conductive layer, and the first fan-out data line FIP H is disposed on the first conductive layer.

[0287] For example, Figure 44 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 44 As shown, three vertical traces are inserted every three subpixels. For example, in... Figure 44 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0288] For example, such as Figure 44 As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels. In the second direction Y, the length of the first fan-out data lines FIP H increases sequentially, and they are electrically connected to the second fan-out data line FIP V through an adapter hole.

[0289] For example, such as Figure 44As shown, in the first direction X, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V located in the middle position are disposed in the second conductive layer, and the third low-voltage power signal line VSS3 and the second fan-out data line FIP V located in the left and right positions are disposed in the third conductive layer, and the first fan-out data line FIP H is disposed in the first conductive layer.

[0290] For example, Figure 45 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 45 As shown, three vertical traces are inserted every three subpixels. For example, in... Figure 45 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0291] For example, such as Figure 45 As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels. In the second direction Y, the length of the first fan-out data lines FIP H increases sequentially, and they are electrically connected to the second fan-out data line FIP V through an adapter hole.

[0292] For example, such as Figure 45 As shown, in the first direction X, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V, located in the middle and right positions, are both disposed in the second conductive layer. The third low-voltage power signal line VSS3 and the second fan-out data line FIP V, located in the left position, are disposed in the third conductive layer. The first fan-out data line FIP H is disposed in the first conductive layer.

[0293] For example, Figure 46 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 46 As shown, a vertical trace is inserted every three subpixels, for example, in Figure 46 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0294] For example, such as Figure 46As shown, in the second direction Y, a first fan-out data line FIP H is provided between adjacent sub-pixels. The first fan-out data line FIP H is electrically connected to the second fan-out data line FIP V through an adapter hole.

[0295] For example, such as Figure 46 As shown, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are disposed on the third conductive layer, and the first fan-out data line FIP H is disposed on the first conductive layer.

[0296] For example, Figure 47 This is a partially enlarged schematic diagram of a portion of a layout structure in at least one embodiment of the pixel circuit provided in this disclosure, such as... Figure 47 As shown, the data signal line Data, the second high-voltage power signal line VDD2, and the second low-voltage power signal line VSS2 (or the first initialization signal connection line Vinit12 and the second initialization signal connection line Vinit22) are all located in the third conductive layer 212. That is, the data signal line Data, the second low-voltage power signal line VSS2, the first initialization signal connection line Vinit12, and the second initialization signal connection line Vinit22 all carry DC signals and are located in the third conductive layer 212. This pixel circuit design reduces the parasitic capacitance of each node and can also integrate the first repair line RP so that laser irradiation can be used to repair short circuits or other conditions in the future.

[0297] For example, Figure 48 for Figure 47 A schematic diagram of the stacked structure of some pixel circuits and their surrounding transition areas, as shown in the figure. Figure 48 As shown, the first fan-out data line FIP H in the second conductive layer 210 has a third break 305. The third break 305 is blocked by the second low-voltage power signal line VSS2 located in the third conductive layer 212 to avoid the visual problem of the third break 305 disappearing, thereby avoiding the visual problem of optical disappearance when the screen is off and ensuring the uniformity of the display.

[0298] It should be noted that after inserting the first fan-out data line FIP H and the second fan-out data line FIP V, the density of the metal lines becomes uneven, resulting in inconsistent light reflection by the metal layer. This can cause a mura phenomenon when the display panel is off, which is the problem of image cancellation.

[0299] For example, such as Figure 48As shown, the second fan-out data line FIP V in the third conductive layer 212 has a fourth break 306, which is blocked by the first fan-out data line FIP H located in the second conductive layer 210 to avoid the problem of visual cancellation of the fourth break 306, thereby avoiding the problem of visual cancellation of optical shadows when the screen is off and ensuring the uniformity of the display.

[0300] For example, such as Figure 47 and Figure 48 As shown, the first fan-out data line FIP H of the second conductive layer 210 is electrically connected to the data signal line Data at the third transition position 307 through the transition hole of the second conductive layer 210 and the third conductive layer 212. The first fan-out data line FIP H of the second conductive layer 210 is also electrically connected to the second fan-out data line FIP V at the fourth transition position 308 through the transition hole of the second conductive layer 210 and the third conductive layer 212.

[0301] For example, such as Figure 47 and Figure 48 As shown, a second low-voltage power supply signal line VSS2, a first initialization signal connection line Vinit12, a second initialization signal connection line Vinit22, and a second fan-out data line FIP V are provided in the third conductive layer 212. Therefore, in this case, the first fan-out data line FIP H can be provided in the second conductive layer or the first conductive layer.

[0302] For example, Figure 49 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 49 As shown, a vertical trace is inserted every other subpixel, for example, in Figure 49 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0303] For example, such as Figure 49 As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels. In the second direction Y, the length of the first fan-out data lines FIP H increases sequentially, while the length of the fourth low-voltage power signal line VSS4 decreases sequentially. Some of the first fan-out data lines FIP H and the fourth low-voltage power signal line VSS4 are spaced apart on the same straight line.

[0304] For example, such as Figure 49As shown, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are both disposed on the third conductive layer, the first fan-out data line FIP H and the fourth low-voltage power signal line VSS4 are both disposed on the second conductive layer, and the first fan-out data line FIP H and the second fan-out data line FIP V are electrically connected through corresponding adapter holes.

[0305] For example, the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4 intersect to form a grid structure, which can reduce the load on the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4.

[0306] For example, Figure 50 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 50 As shown, a vertical trace is inserted every other subpixel, for example, in Figure 50 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0307] For example, such as Figure 50 As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels. In the second direction Y, the length of the first fan-out data lines FIP H increases sequentially, while the length of the fourth low-voltage power signal line VSS4 decreases sequentially. Some of the first fan-out data lines FIP H and the fourth low-voltage power signal line VSS4 are spaced apart on the same straight line.

[0308] For example, such as Figure 50 As shown, in the second direction Y, the first fan-out data line FIP H and the fourth low-voltage power signal line VSS4 located in the middle are disposed in the first conductive layer, the first fan-out data line FIP H and the fourth low-voltage power signal line VSS4 located on the lower side are both disposed in the second conductive layer, the first fan-out data line FIP H located on the upper side is disposed in the second conductive layer, the second fan-out data line FIP V and the third low-voltage power signal line VSS3 are both disposed in the third conductive layer, and the first fan-out data line FIP H and the second fan-out data line FIP V are electrically connected through corresponding adapter holes.

[0309] For example, the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4 intersect to form a grid structure, which can reduce the load on the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4.

[0310] For example, Figure 51 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 51 As shown, a vertical trace is inserted every other subpixel, for example, in Figure 51 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0311] For example, such as Figure 51 As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels. In the second direction Y, the length of the first fan-out data lines FIP H increases sequentially, while the length of the fourth low-voltage power signal line VSS4 decreases sequentially. Some of the first fan-out data lines FIP H and the fourth low-voltage power signal line VSS4 are spaced apart on the same straight line.

[0312] For example, such as Figure 51 As shown, in the second direction Y, the first fan-out data line FIP H and the fourth low-voltage power signal line VSS4 located in the middle position are disposed in the second conductive layer, the first fan-out data line FIP H and the fourth low-voltage power signal line VSS4 located on the lower side are both disposed in the first conductive layer, the first fan-out data line FIP H located on the upper side is disposed in the first conductive layer, the second fan-out data line FIP V and the third low-voltage power signal line VSS3 are both disposed in the third conductive layer, and the first fan-out data line FIP H and the second fan-out data line FIP V are electrically connected through corresponding adapter holes.

[0313] For example, the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4 intersect to form a grid structure, which can reduce the load on the third low-voltage power signal line VSS3 and the fourth low-voltage power signal line VSS4.

[0314] For example, Figure 52 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 52 As shown, three vertical traces are inserted every three subpixels. For example, in... Figure 52 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0315] For example, such as Figure 52As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels, and the length of the first fan-out data lines FIP H increases sequentially in the second direction Y.

[0316] For example, such as Figure 52 As shown, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are both disposed on the third conductive layer, and the first fan-out data line FIP H is disposed on the second conductive layer.

[0317] For example, Figure 53 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 53 As shown, three vertical traces are inserted every three subpixels. For example, in... Figure 53 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0318] For example, such as Figure 53 As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels. In the second direction Y, the length of the first fan-out data lines FIP H increases sequentially, and they are electrically connected to the second fan-out data line FIP V through an adapter hole.

[0319] For example, such as Figure 53 As shown, in the second direction Y, the first fan-out data line FIP H located in the middle position is disposed in the first conductive layer, and the first fan-out data lines FIP H located at the upper and lower positions are disposed in the second conductive layer. The third low-voltage power signal line VSS3 and the second fan-out data line FIP V are both disposed in the third conductive layer.

[0320] For example, Figure 54 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 54 As shown, three vertical traces are inserted every three subpixels. For example, in... Figure 54 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0321] For example, such as Figure 54As shown, in the second direction Y, three first fan-out data lines FIP H are arranged sequentially between adjacent sub-pixels. In the second direction Y, the length of the first fan-out data lines FIP H increases sequentially, and they are electrically connected to the second fan-out data line FIP V through an adapter hole.

[0322] For example, such as Figure 54 As shown, the first fan-out data line FIP H located in the middle is disposed on the second conductive layer, while the first fan-out data lines FIP H located at the upper and lower sides are disposed on the first conductive layer. The third low-voltage power signal line VSS3 and the second fan-out data line FIP V are both disposed on the third conductive layer.

[0323] For example, Figure 55 A schematic diagram of another design for a first fan-out data line and a second fan-out data line provided in at least one embodiment of this disclosure, as shown below. Figure 55 As shown, a vertical trace is inserted every three subpixels, for example, in Figure 55 In the middle, the vertical routing is either the second fan-out data line FIP V or the third low-voltage power signal line VSS3. In the second direction Y, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are arranged sequentially and spaced apart from each other, thereby reducing the load on the second fan-out data line FIP V.

[0324] For example, such as Figure 55 As shown, in the second direction Y, a first fan-out data line FIP H is provided between adjacent sub-pixels. The first fan-out data line FIP H is electrically connected to the second fan-out data line FIP V through an adapter hole.

[0325] For example, such as Figure 55 As shown, the third low-voltage power signal line VSS3 and the second fan-out data line FIP V are disposed on the third conductive layer, and the first fan-out data line FIP H is disposed on the second conductive layer.

[0326] For example, Figure 56 This is a schematic diagram of another pixel circuit stack-up structure provided in at least one embodiment of the present disclosure, such as... Figure 56 As shown, the main openings of the red sub-pixel R, blue sub-pixel B, and green sub-pixel G are all square, forming a single, integrated structure. The anodes of each color sub-pixel cover the second fan-out data line FIP V and the data signal line Data. The anodes corresponding to each color sub-pixel must avoid the position shown in the dashed box, specifically the position of node N4 on the second connecting electrode L2 in the circuit diagram, to reduce step differences. This area is where the laser acts when the repair function is activated; it is generally a frontal laser, so the anodes must avoid this area.

[0327] For example, such as Figure 56As shown, the anode needs to avoid the intersection of the first fan-out data line FIP H and the vertical trace.

[0328] For example, Figure 57 This is a schematic diagram of another pixel circuit stack-up structure provided in at least one embodiment of the present disclosure, such as... Figure 57 As shown, the openings of the main bodies of the red sub-pixel R, blue sub-pixel B, and green sub-pixel G are designed in a partitioned manner, avoiding the second fan-out data line FIP V and data signal line Data. Only at the partition connection points of each sub-pixel is the anode designed to cover the second fan-out data line FIP V and data signal line Data to reduce their load. The anodes corresponding to each color sub-pixel must avoid the position shown in the dashed box, that is, avoid the position of node N4 in the circuit diagram on the second connecting electrode L2, to reduce the step difference. This is also the location where the laser acts when the repair function is enabled, generally a frontal laser, so the anode needs to avoid this area.

[0329] For example, such as Figure 57 As shown, the anode needs to avoid the intersection of the first fan-out data line FIP H and the vertical trace.

[0330] For example, Figure 58 This is a schematic diagram of another pixel circuit stack-up structure provided in at least one embodiment of the present disclosure, such as... Figure 58 As shown, the red sub-pixel R, blue sub-pixel B, and green sub-pixel G have a largely partitioned opening design. This means that most openings avoid the second fan-out data line FIP V and the data signal line Data. Only at the junctions of the partitions of each sub-pixel are the openings and anodes designed to cover the second fan-out data line FIP V and the data signal line Data, thus reducing their load. The anodes for each color sub-pixel must avoid the location shown in the dashed box, specifically the location of node N4 on the second connecting electrode L2 in the circuit diagram, to reduce step differences. This is also the location where the laser acts when the repair function is enabled, typically a frontal laser, so the anode must avoid this area.

[0331] For example, such as Figure 58 As shown, the anode needs to avoid the intersection of the first fan-out data line FIP H and the vertical trace.

[0332] For example, Figure 59 This is a schematic diagram of another pixel circuit stack-up structure provided in at least one embodiment of the present disclosure, such as... Figure 59As shown, the main body of the red sub-pixel R, blue sub-pixel B, and green sub-pixel G features a largely partitioned opening design. This means that most openings avoid the second fan-out data line FIP V. Only at the junctions of the partitions of each sub-pixel are the openings and anodes designed to cover the second fan-out data line FIP V and the data signal line Data, thus increasing the pixel aperture ratio based on the partitioning. The anodes corresponding to the sub-pixels of each color must avoid the position shown in the dashed box, specifically the position of node N4 on the second connecting electrode L2 in the circuit diagram, to reduce step differences. This is also the location where the laser acts when the repair function is enabled, typically a frontal laser, so the anode needs to avoid this area.

[0333] For example, such as Figure 59 As shown, the anode needs to avoid the intersection of the first fan-out data line FIP H and the vertical trace.

[0334] For example, Figure 59 The stacked structure shown is relatively Figure 58 The proposed solution simply connects the blue sub-pixel regions while keeping the anode disconnected, thus increasing the opening area at least while increasing the current.

[0335] For example, Figure 60 This is a schematic diagram of another pixel circuit stack-up structure provided in at least one embodiment of the present disclosure, such as... Figure 60 As shown, the openings of the main bodies of the red sub-pixel R, blue sub-pixel B, and green sub-pixel G are evenly partitioned, avoiding the second fan-out data line FIP V and data signal line Data. Only at the partition connection points of each sub-pixel is the anode designed to cover the second fan-out data line FIP V and data signal line Data to reduce their load. The anodes for each color sub-pixel must avoid the position shown in the dashed box, that is, avoid the position of node N4 in the circuit diagram on the second connecting electrode L2, to reduce step difference. This is also the location where the laser acts when the repair function is enabled, generally a frontal laser, so the anode needs to avoid this area.

[0336] For example, in Figure 60In the stacked structure shown, the pixel openings of the red sub-pixel R, blue sub-pixel B, and green sub-pixel G are all designed to avoid vias. However, if the transition via located in the first planarization layer between the first conductive layer and the second conductive layer is placed below the sub-pixel opening, color deviation will easily occur. At the extreme resolution, it is impossible to completely avoid the traces on the side close to the substrate. Therefore, except for the position of the opening corresponding to the first planarization layer at the bottom, the pixel openings of the red sub-pixel R, blue sub-pixel B, and green sub-pixel G are designed to avoid other via structures. The rest of the sub-pixels of various colors emit light normally, thereby avoiding color deviation caused by vias.

[0337] For example, in Figure 60 The embodiment shown takes into account reducing the load on the second fan-out data line FIP V and the data signal line Data, and improving color shift. While satisfying the maximum possible aperture ratio, it aims to simultaneously implement irregular line avoidance and aperture avoidance design for the red sub-pixel R, blue sub-pixel B, and green sub-pixel G.

[0338] In exemplary embodiments, the sub-pixel rows and sub-pixel columns described in this disclosure can be understood as the rows and columns of pixel driving circuits in a sub-pixel. The anode in a sub-pixel is connected to the pixel driving circuit in the corresponding sub-pixel, but the position of the anode of a sub-pixel may not completely correspond to the row and column of the pixel driving circuit it is connected to. For example, the orthographic projection of the anode of the third sub-pixel on the substrate may overlap with the orthographic projection of the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel on the substrate.

[0339] The structures and fabrication processes described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced as needed. The display substrates in this disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc. This disclosure does not limit them.

[0340] At least one embodiment of this disclosure also provides a display device, which includes the display panel 400 in any of the above embodiments, for example... Figure 61 This is a block diagram of a display device provided for at least one embodiment of the present disclosure. The display device 500 can be any display device 500 that displays either moving (e.g., video) or stationary (e.g., still image) text or images.

[0341] For example, the display device 500 provided in the embodiments of this disclosure can be implemented in a variety of electronic devices, including but not limited to mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0342] For example, at least the display device disclosed herein may further include a functional component located on the side of the substrate away from the light-emitting element. For example, the functional component includes at least one of a camera module (e.g., a front-facing camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), and an infrared sensing module (e.g., an infrared sensing sensor).

[0343] In embodiments of this disclosure, components located in the same layer may be fabricated from the same film layer using the same patterning process. For example, components located in the same layer may be located on the surface of the same component away from the substrate.

[0344] In the embodiments of this disclosure, the patterning or patterning process may include only photolithography, or it may include both photolithography and etching steps, or it may include other processes such as printing or inkjet printing to form a predetermined pattern. Photolithography refers to processes including film formation, exposure, and development, using photoresist, photomasks, and exposure machines to form patterns. The appropriate patterning process can be selected based on the structure formed in the embodiments of this disclosure.

[0345] The following points need to be explained:

[0346] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0347] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0348] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0349] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A display panel, characterized in that, include: Substrate; A first metal layer, a second metal layer, a semiconductor layer, and a third metal layer are sequentially stacked on the substrate; wherein... The first metal layer includes a first electrode of a first capacitor, the second metal layer includes a second electrode of a first capacitor, and the third metal layer includes a gate of a driving transistor. The first electrode of the first capacitor and the gate of the driving transistor are electrically connected. The display panel further includes a first fan-out data line and a first low-voltage power signal line extending in a first direction, and a second low-voltage power signal line and a data signal line extending in a second direction. The first direction and the second direction intersect. The first fan-out data line and at least one of the first low-voltage power signal line and the second low-voltage power signal line are disposed on the same layer, and the first fan-out data line is configured to connect to at least one of the data signal lines.

2. The display panel according to claim 1, characterized in that, It also includes a first conductive layer and a second conductive layer, wherein the first conductive layer is disposed on the side of the third metal layer away from the substrate, the second conductive layer is disposed on the side of the first conductive layer away from the substrate, and an insulating layer is disposed between the first conductive layer and the second conductive layer.

3. The display panel according to claim 2, characterized in that, The first conductive layer includes a first high-voltage power signal line and a first low-voltage power signal line extending in the first direction; the second conductive layer includes a second high-voltage power signal line and a second low-voltage power signal line extending in the second direction, and the first fan-out data line is located in at least one of the first conductive layer and the second conductive layer.

4. The display panel according to claim 3, characterized in that, Multiple first high-voltage power signal lines and multiple second high-voltage power signal lines intersect and are electrically connected to form a mesh structure, and multiple first low-voltage power signal lines and multiple second low-voltage power signal lines intersect and are electrically connected to form a mesh structure.

5. The display panel according to claim 2, characterized in that, It also includes a data writing transistor, a first reset transistor, and a second reset transistor, wherein the first conductive layer includes a scan signal line, a first reset control line, a second reset control line, and a first connection electrode. The scan signal line is configured to provide a control signal to the data write transistor, the first reset control line is configured to provide a control signal to the first reset transistor, and the second reset control line is configured to provide a control signal to the second reset transistor. The data write transistor is configured to provide a data signal to the pixel circuit, the first reset transistor is configured to provide a first reset signal, and the second reset transistor is configured to provide an initialization voltage signal; The first connection electrode is electrically connected to the gate of the driving transistor, the second electrode of the data writing transistor, and the second electrode of the first reset transistor.

6. The display panel according to claim 5, characterized in that, The first fan-out data line is disposed on the first conductive layer, and the second conductive layer is provided with a second low-voltage power signal line extending in the second direction, and at least a portion of the second low-voltage power signal line covers the gate of the driving transistor.

7. The display panel according to claim 5, characterized in that, The first fan-out data line is disposed on the first conductive layer, and the second conductive layer is provided with a second low-voltage power signal line extending in the second direction, and at least a portion of the second low-voltage power signal line covers the first connection electrode.

8. The display panel according to claim 2, characterized in that, It also includes a third conductive layer, wherein the third conductive layer is disposed on the side of the second conductive layer away from the substrate, the third conductive layer includes a second fan-out data line and the data signal line, and the second fan-out data line and the data signal line are arranged adjacent to each other between adjacent sub-pixels in the first direction.

9. The display panel according to claim 2, characterized in that, The first conductive layer includes a first low-voltage power supply signal line, a first initialization signal line, and a second initialization signal line extending in the first direction; The second conductive layer includes a second low-voltage power supply signal line, a first initialization signal connection line, and a second initialization signal connection line extending in the second direction; The first fan-out data line is located in at least one of the first conductive layer and the second conductive layer; The first low-voltage power supply signal line and the second low-voltage power supply signal line are connected, the first initialization signal line and the first initialization signal connection line are connected, and the second initialization signal line and the second initialization signal connection line are connected to form a network.

10. The display panel according to claim 2, characterized in that, It also includes a first conductive layer, a second conductive layer and a third conductive layer stacked together, wherein the first fan-out data line is in the first conductive layer, the second fan-out data line is in the third conductive layer, and the first fan-out data line is connected to the second fan-out data line through the second conductive layer.

11. The display panel according to claim 10, characterized in that, A first planarization layer is provided between the first conductive layer and the second conductive layer, and a second planarization layer is provided between the second conductive layer and the third conductive layer.

12. The display panel according to claim 10, characterized in that, The first fan-out data line located in the first conductive layer has a first break, and the first break is blocked by a third low-voltage power signal line located in the second conductive layer.

13. The display panel according to claim 10, characterized in that, The second fan-out data line located in the third conductive layer has a second break, which is blocked by the first fan-out data line located in the first conductive layer.

14. The display panel according to claim 10, characterized in that, The first conductive layer further includes a second connecting electrode, the second conductive layer further includes a first anode connecting electrode, and the third conductive layer further includes a second anode connecting electrode. The first anode connecting electrode is electrically connected to the second connecting electrode and the second anode connecting electrode, respectively.

15. The display panel according to claim 2, characterized in that, The second metal layer further includes a first repair line, and the first conductive layer includes a second connecting electrode. The orthographic projection of the first repair line on the substrate and the orthographic projection of the second connecting electrode on the substrate have an overlapping portion.

16. The display panel according to claim 2, characterized in that, It also includes a third conductive layer disposed on the side of the second conductive layer away from the substrate, wherein the first fan-out data line is in the second conductive layer, the second fan-out data line is in the third conductive layer, an insulating layer is disposed between the second conductive layer and the third conductive layer, and the first fan-out data line and the second fan-out data line are electrically connected through a via structure disposed in the insulating layer.

17. A display panel, characterized in that, include: Substrate; A first metal layer, a second metal layer, a semiconductor layer, and a third metal layer are sequentially stacked on the substrate; wherein... The first metal layer includes a first electrode of a first capacitor, the second metal layer includes a second electrode of a first capacitor, and the third metal layer includes a gate of a driving transistor. The first electrode of the first capacitor and the gate of the driving transistor are electrically connected. The display panel further includes a first fan-out data line extending in a first direction and a second fan-out data line extending in a second direction, the first direction and the second direction intersect, the first fan-out data line and the second fan-out data line are located in different layers, and at least one organic insulating layer is provided between the first fan-out data line and the second fan-out data line.

18. The display panel according to claim 17, characterized in that, It also includes a first conductive layer and a second conductive layer, wherein the first conductive layer is disposed on the side of the third metal layer away from the substrate, the second conductive layer is disposed on the side of the first conductive layer away from the substrate, and at least a portion of at least one insulating layer is disposed between the first conductive layer and the second conductive layer.

19. The display panel according to claim 18, characterized in that, It also includes a third conductive layer, wherein the first fan-out data line is disposed on the first conductive layer, the second fan-out data line is disposed on the third conductive layer, the second conductive layer is provided with a second low-voltage power supply signal line extending in the second direction, and at least a portion of the second low-voltage power supply signal line covers the gate of the driving transistor.

20. The display panel according to claim 18, characterized in that, It also includes a third conductive layer, wherein the first fan-out data line is disposed on the first conductive layer, the second fan-out data line is disposed on the third conductive layer, the second conductive layer is provided with a second low-voltage power signal line extending in the second direction, and at least a portion of the second low-voltage power signal line covers the first connection electrode.

21. A display device, characterized in that, The display panel includes any one of claims 1-20.

Images