Display panel and electronic device

Abstract

The utility model discloses a kind of display panel and electronic device. Display panel can include multiple pixels, stage including multiple transistors, multiple clock wiring electrically connected with the stage and multiple connection wiring connecting the multiple clock wiring and the multiple transistors, the multiple transistors include: multiple first group transistors, with the pixel in the multiple pixels along the first direction is arranged in the 2N-1 (N is 1 above integer) pixel is connected;And multiple second group transistors, with the pixel in the multiple pixels along the first direction is arranged in the 2N pixel is connected, the multiple first group transistors and the multiple second group transistors are separated from each other across virtual reference line extending in the second direction crossing with the first direction.

Description

Technical Field

[0001] This utility model relates to a display panel with a reduced width of the non-display area and an electronic device. Background Technology

[0002] Multimedia electronic devices such as televisions, mobile phones, tablets, computers, navigation devices, and game consoles include display panels used to display images. Research is being conducted to reduce the size of areas within the display panel that do not display images (non-display areas or border areas) based on market demands. Utility Model Content

[0003] One object of this invention is to provide a display panel with a reduced width of the non-display area and an electronic device including the same.

[0004] The display panel according to one embodiment of the present invention may include: a plurality of pixels arranged along a first direction; a stage including a plurality of transistors that output a plurality of scan signals to the plurality of pixels; a plurality of clock wirings electrically connected to the stage; and a plurality of connection wirings connecting the plurality of clock wirings and the plurality of transistors, wherein the plurality of transistors includes: a plurality of first group transistors connected to the 2N-1th pixel (N is an integer greater than or equal to 1) arranged along the first direction; and a plurality of second group transistors connected to the 2Nth pixel arranged along the first direction, wherein the plurality of first group transistors and the plurality of second group transistors are separated from each other by a virtual reference line extending in a second direction intersecting the first direction.

[0005] The plurality of connection wirings may include: a plurality of first group connection wirings connected to the plurality of first group transistors; and a plurality of second group connection wirings connected to the plurality of second group transistors, wherein the plurality of first group connection wirings and the plurality of second group connection wirings are separated from each other by the virtual baseline.

[0006] It may be that the display panel defines a first region where the plurality of clock wirings are configured, a second region where the levels are configured, and a third region between the first region and the second region, wherein the plurality of connecting wirings have a curved shape in the third region.

[0007] The third region may include: a first boundary adjacent to the first region and extending along the first direction; and a second boundary adjacent to the second region and extending along the first direction, wherein at least one of the first group of connection wirings is aligned at the first boundary and at the second boundary, and at least another of the first group of connection wirings is different from each other at the first boundary and at the second boundary.

[0008] It is possible that the first distance between the plurality of first group connection wirings and the plurality of second group connection wirings at the first boundary is less than the second distance between the plurality of first group connection wirings and the plurality of second group connection wirings at the second boundary.

[0009] Alternatively, the plurality of clock wirings, the level, and the plurality of pixels may be arranged sequentially along the second direction, each of the plurality of clock wirings extending along the first direction, and the plurality of clock wirings being spaced apart along the second direction.

[0010] The plurality of clock wiring may include: a plurality of first group clock wirings electrically connected to the plurality of first group connecting wirings; and a plurality of second group clock wirings electrically connected to the plurality of second group connecting wirings, wherein the plurality of first group clock wirings and the plurality of second group clock wirings are arranged alternately and repeatedly along the second direction.

[0011] The plurality of clock wirings may include a first clock wiring, a second clock wiring, a third clock wiring, a fourth clock wiring, a fifth clock wiring, and a sixth clock wiring; the plurality of transistors may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor electrically connected to the first to sixth clock wirings; and the plurality of pixels may include a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel arranged sequentially along the first direction and connected to the first to sixth transistors in a one-to-one correspondence.

[0012] Alternatively, the first transistor and the second transistor may be separated by the virtual reference line, the third transistor and the fourth transistor may be separated by the virtual reference line, and the fifth transistor and the sixth transistor may be separated by the virtual reference line.

[0013] Alternatively, the first transistor, the third transistor, and the fifth transistor may be arranged sequentially in a direction away from the plurality of clock lines, and the second transistor, the fourth transistor, and the sixth transistor may be arranged sequentially in the same direction away from the plurality of clock lines.

[0014] Alternatively, the interval between the first transistor and the second transistor may be smaller than the interval between the fifth transistor and the sixth transistor.

[0015] Alternatively, the display panel may further include: voltage wiring disposed between the stage and the plurality of pixels; and a first intermediate connection wiring, a second intermediate connection wiring, a third intermediate connection wiring, a fourth intermediate connection wiring, a fifth intermediate connection wiring, and a sixth intermediate connection wiring, which are connected one-to-one with the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, respectively. The first intermediate connection wiring, the second intermediate connection wiring, the third intermediate connection wiring, the fourth intermediate connection wiring, the fifth intermediate connection wiring, and the sixth intermediate connection wiring are arranged sequentially along the first direction in the area overlapping with the voltage wiring.

[0016] Alternatively, the first transistor, the third transistor, and the fifth transistor may be arranged sequentially in the direction toward the plurality of clock wirings, and the second transistor, the fourth transistor, and the sixth transistor may be arranged sequentially in the direction toward the plurality of clock wirings.

[0017] It is possible that the interval between the first transistor and the second transistor is greater than the interval between the fifth transistor and the sixth transistor.

[0018] It is possible that, in a first mode where the display panel is driven at a first frequency, the multiple clock signals transmitted to the multiple clock wirings have different phases from each other, and in a second mode where the display panel is driven at a second frequency higher than the first frequency, a portion of the multiple clock signals have the same phase.

[0019] An electronic device according to an embodiment of the present invention includes a display panel defining a display area and a non-display area adjacent to the display area. The display panel includes: a plurality of pixels disposed in the display area; and a stage disposed in the non-display area and outputting a plurality of scan signals to the plurality of pixels. The plurality of pixels includes a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel arranged sequentially along a first direction. The stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth pixel, and a sixth transistor that correspond one-to-one with the first pixel, the second pixel, the third pixel, the fourth pixel, the fifth pixel, and the sixth pixel and output the plurality of scan signals. The first transistor and the second transistor face each other in the first direction, the third transistor and the fourth transistor face each other in the first direction, the fifth transistor and the sixth transistor face each other in the first direction, the third transistor is disposed between the first transistor and the fifth transistor, and the fourth transistor is disposed between the second transistor and the sixth transistor.

[0020] Alternatively, the display panel may further include: a plurality of clock wirings configured in the non-display area and providing a plurality of clock signals to the stage; and a first connection wiring, a second connection wiring, a third connection wiring, a fourth connection wiring, a fifth connection wiring, and a sixth connection wiring, configured in the non-display area and connected one-to-one with the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, and transmitting the plurality of clock signals, wherein the first connection wiring, the third connection wiring, and the fifth connection wiring are separated from the second connection wiring, the fourth connection wiring, and the sixth connection wiring by a virtual reference line extending in a second direction.

[0021] It may be that the display panel defines a first region where the plurality of clock wirings are configured, a second region where the levels are configured, and a third region between the first region and the second region. The third region includes: a first boundary adjacent to the first region and extending along the first direction; and a second boundary adjacent to the second region and extending along the first direction. The first connecting wiring, the second connecting wiring, the third connecting wiring, the fourth connecting wiring, the fifth connecting wiring, and the sixth connecting wiring have curved shapes in the third region.

[0022] It is possible that the first distance between the first connecting wire and the second connecting wire at the first boundary is less than the second distance between the first connecting wire and the second connecting wire at the second boundary.

[0023] It is possible that the first distance between the fifth and sixth connecting wires at the first boundary is less than the second distance between the fifth and sixth connecting wires at the second boundary.

[0024] Based on the above, the display panel may include multiple levels disposed in the non-display area, each level including multiple transistors. A portion and the remainder of the multiple transistors may be arranged facing each other. Therefore, the width of the non-display area of ​​the display panel can be reduced.

[0025] In addition, the display panel includes multiple connection lines that correspond one-to-one with multiple transistors. Some of these connection lines can be configured to be separated from each other by virtual reference lines. Therefore, the equal resistance design can be simplified, thereby reducing the width or area of ​​the equal resistance design space. Attached Figure Description

[0026] Figure 1 This is a perspective view of an electronic device according to an embodiment of the present invention.

[0027] Figure 2 This is a plan view of an electronic device according to an embodiment of the present invention.

[0028] Figure 3 This is a block diagram of an electronic device according to an embodiment of the present invention.

[0029] Figure 4 This is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0030] Figure 5 This is a block diagram illustrating a portion of the structure of a display panel according to an embodiment of the present invention.

[0031] Figure 6a This is a diagram illustrating a scanning drive circuit according to an embodiment of the present invention.

[0032] Figure 6b This is an equivalent circuit diagram of one stage according to an embodiment of the present invention.

[0033] Figure 7 This is a timing diagram illustrating the operation of a first mode level according to an embodiment of the present invention.

[0034] Figure 8 This is a timing diagram illustrating the operation of multiple clock signals in a second mode level according to an embodiment of the present invention.

[0035] Figure 9This is a diagram showing the activation state and brightness changes of a first type of scan signal and a second type of scan signal according to an embodiment of the present invention.

[0036] Figure 10 This is a diagram showing the activation state and brightness changes of a first type of scan signal and a second type of scan signal according to an embodiment of the present invention.

[0037] Figure 11 This is a plan view of a portion of a display panel according to an embodiment of the present invention.

[0038] Figure 12 This is an enlarged view of an embodiment according to the present invention. Figure 11 Plan view of area AA'.

[0039] Figure 13 This is an enlarged plan view showing a portion of a display panel according to an embodiment of the present invention.

[0040] Figure 14 According to an embodiment of the present invention, along Figure 13 The cross-sectional view of the display panel taken from I-I'.

[0041] Figure 15 According to an embodiment of the present invention, along Figure 13 The cross-sectional view of the display panel taken from section II-II'.

[0042] Figure 16 This is a plan view of a portion of a display panel according to an embodiment of the present invention.

[0043] Figure 17 This is a plan view of a portion of a display panel according to an embodiment of the present invention.

[0044] (Explanation of reference numerals in the attached diagram)

[0045] DP: Display Panel

[0046] PX: pixel

[0047] TCG1: First set of transistors

[0048] TCG2: Second set of transistors

[0049] TC1, TC2, TC3, TC4, TC5, TC6: Multiple transistors

[0050] CKL1, CKL2, CKL3, CKL4, CKL5, CKL6: First to sixth clock routing; CL1, CL2, CL3, CL4, CL5, CL6: First to sixth connection routing. Detailed Implementation

[0051] In this specification, when a constituent element (or region, layer, part, etc.) is referred to as being "on", "connected to", or "integrated with" another constituent element, it means that the constituent element can be directly configured / connected / integrated on the other constituent element, or a third constituent element can be configured between them.

[0052] The same reference numerals refer to the same constituent elements. Furthermore, in the drawings, the thickness, scale, and dimensions of the constituent elements are enlarged for the purpose of effectively illustrating the technical content. "And / or" includes all combinations that can be defined for the relevant constituent elements.

[0053] The terms "first," "second," etc., can be used to describe multiple constituent elements, but the constituent elements are not limited by these terms. These terms are used only to distinguish one constituent element from others. For example, without departing from the scope of this utility model, a first constituent element can be named a second constituent element, and similarly, a second constituent element can be named a first constituent element. Singular expressions include plural expressions unless explicitly stated otherwise in the context.

[0054] In addition, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationship between the constituent elements shown in the accompanying drawings. These terms are relative concepts and are explained based on the directions indicated in the accompanying drawings.

[0055] Terms such as “including” or “having” should be understood as indicating the presence of features, figures, steps, operations, constituent elements, components, or combinations thereof as described in the specification, and do not preclude the presence or additional possibilities of one or more other features or figures, steps, operations, constituent elements, components, or combinations thereof.

[0056] The terms "part" and "unit" refer to software or hardware components that perform a specific function. Hardware components may include, for example, FPGAs (field-programmable gate arrays) or ASICs (application-specific integrated circuits). Software components may refer to executable code and / or data used by the executable code through addressable storage media. Therefore, software components can be, for example, object-oriented software components, class components, and job components, and may include processes, functions, attributes, steps, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrangements, or variables.

[0057] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms such as those defined in commonly used dictionaries shall be interpreted as having the same meaning in the context of the related art, and shall not be construed as having overly idealized or formalistic meanings unless explicitly defined herein.

[0058] The embodiments of this utility model will now be described with reference to the accompanying drawings.

[0059] Figure 1 This is a perspective view of an electronic device DD according to an embodiment of the present invention. Figure 2 This is a plan view of an electronic device DD according to an embodiment of the present invention.

[0060] Reference Figure 1 as well as Figure 2 The electronic device DD can be a device activated by an electrical signal. The electronic device DD can be used in large electronic devices such as televisions, monitors, or external billboards, as well as in small and medium-sized electronic devices such as personal computers, laptops, personal digital terminals, car navigation units, game consoles, portable electronic devices, and cameras. Furthermore, these are presented only as examples; obviously, they can also be used in other electronic devices as long as they do not depart from the concept of this invention. Figure 1 The electronic device DD shown can be a monitor.

[0061] Electronic devices (DD) may include display panels (DP), connecting films (COF), and circuit boards (PCB).

[0062] Display panel (DP) can be a structure that substantially generates an image. A display panel (DP) can be a light-emitting display panel, such as an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micro-LED display panel, or a nano-LED display panel, but is not particularly limited thereto. Display panels (DP) can have small to medium sizes of a few inches or less (tens of inches or less). Alternatively, display panels (DP) can have large sizes of tens of inches or more.

[0063] The display panel DP can define a display area DA and a non-display area NDA. The display panel DP can display images through the display area DA. For example, the display panel DP can include multiple pixels PX, which can be configured in the display area DA. The display area DA can include a surface defined by a first direction DR1 and a second direction DR2. The display area DA can display images on a third direction DR3 that intersects the first direction DR1 and the second direction DR2. The non-display area NDA can surround the perimeter of the display area DA.

[0064] The bezel area BA of the electronic device DD can cover at least a portion of the non-display area NDA of the display panel DP. The bezel area BA can also cover the entire non-display area NDA, or only a portion of it. If the area of ​​the non-display area NDA decreases, the area of ​​the bezel area BA can also decrease accordingly.

[0065] Multiple connection films (COFs) can be provided. Each COF can be fitted with a driving circuit for driving the display panel (DP), such as a data driving circuit. Multiple COFs can be combined with the non-display area (NDA) of the display panel (DP). For example, the COFs can be attached to one side of the display panel (DP). In one embodiment of this invention, the COFs can be combined with the pad area (PDA) of the display panel (DP). The PDA can be defined within the non-display area (NDA) of the display panel (DP). The COFs and the display panel (DP) can be bonded together using an anisotropic conductive film (ACF), but are not particularly limited thereto.

[0066] Multiple circuit boards (PCBs) can be provided. Each PCB can be electrically connected to the display panel (DP) via a corresponding portion of the connecting film (COF). Chips that control the operation of the display panel (DP), such as timing controllers, can be mounted on the PCB.

[0067] Figure 2 The diagram shows 12 connecting membranes (COFs), but the present invention is not limited thereto. Figure 2 Two circuit boards (PCBs) are shown, but the present invention is not limited thereto. For example, the number of connecting films (COFs) and the number of circuit boards (PCBs) can vary depending on the resolution of the display panel (DP), the size of the display panel (DP), the specifications of the data driving circuit, and other factors.

[0068] Figure 3 This is a block diagram of an electronic device DD according to an embodiment of the present invention.

[0069] Reference Figure 2 as well as Figure 3The electronic device DD may include a display panel DP, a scan drive circuit SDC, a data drive circuit DDC, and a control circuit TC.

[0070] The display panel DP includes a display area DA for displaying images and a non-display area NDA located outside the display area DA. Multiple pixels PX can be configured in the display area DA. A scan drive circuit SDC for driving the pixels PX can be configured in the non-display area NDA.

[0071] The scan drive circuit SDC can be directly formed on the substrate layer using photolithography. For example, the scan drive circuit SDC can be formed simultaneously with the pixel circuit using the same process used to form the pixel PX.

[0072] The control circuit TC controls the scanning drive circuit SDC and the data drive circuit DDC. The control circuit TC transforms the data format of the input image signal to match the interface specifications of the data drive circuit DDC, generating image data RGB. The control circuit TC outputs the image data RGB and various control signals DCS and GCS.

[0073] The scan driver circuit SDC receives the first control signal GCS from the control circuit TC. The first control signal GCS may include a vertical start signal to initiate the operation of the scan driver circuit SDC, a clock signal to determine the timing of signal output, etc. The scan driver circuit SDC can output multiple scan signals to multiple scan lines SCL1-SCLn and SSL1-SSLn. n can be an integer greater than 2. The scan driver circuit SDC can also be called the gate driver circuit.

[0074] The data driver circuit (DDC) receives the second control signal (DCS) and image data (RGB) from the control circuit (TC). The DDC converts the RGB image data into a data signal and outputs the data signal to multiple data routes DL1-DLm. m can be an integer greater than 2. The data signal is an analog voltage corresponding to the grayscale value of the RGB image data. The DDC can be provided as a driver chip and installed on... Figure 2 The connecting film shown is either mounted on the COF, on the circuit board (PCB), or on the non-display area (NDA) of the display panel (DP).

[0075] The display panel (DP) may include multiple scan lines SCL1-SCLn, SSL1-SSLn, multiple data lines DL1-DLm, multiple lead lines RL1-RLm, and multiple pixels (PX).

[0076] Alternatively, scan lines SCL1-SCLn and SSL1-SSLn can be arranged along a first direction DR1, with each of them extending along a second direction DR2 that intersects the first direction DR1. Scan lines SCL1-SCLn and SSL1-SSLn can include a first type of scan line SCL1-SCLn and a second type of scan line SSL1-SSLn. The first type of scan line SCL1-SCLn can be referred to as a first scan line, a write scan line, or a first gate line, and the second type of scan line SSL1-SSLn can be referred to as a second scan line, an initialization scan line, a sensing scan line, or a second gate line.

[0077] Alternatively, data wiring DL1-DLm can be arranged along the second direction DR2, with each of DL1-DLm extending along the first direction DR1. Similarly, lead wiring RL1-RLm can be arranged along the second direction DR2, with each of RL1-RLm extending along the first direction DR1. Data wiring DL1-DLm and lead wiring RL1-RLm can be insulated from and intersect with scan wirings SCL1-SCLn and SSL1-SSLn.

[0078] Each pixel PX can be connected to the corresponding scan routes SCL1-SCLn, SSL1-SSLn, the corresponding data routes DL1-DLm, and the corresponding lead routes RL1-RLm. For example, the pixels PX arranged in the first row can be connected to the first first-type scan route SCL1 and the first second-type scan route SSL1, and the pixels PX arranged in the nth row can be connected to the nth first-type scan route SCLn and the nth second-type scan route SSLn. The pixels PX arranged in the first column can be connected to the first data route DL1 and the first lead route RL1, and the pixels PX arranged in the mth column can be connected to the mth data route DLm and the mth lead route RLm. However, this is just one example, and the connection relationships between pixels PX and scan routes SCL1-SCLn, SSL1-SSLn, data routes DL1-DLm, and lead routes RL1-RLm are not limited to this.

[0079] The display panel (DP) receives a first power supply voltage (ELVDD) and a second power supply voltage (ELVSS). The first power supply voltage (ELVDD) can be supplied to the pixel (PX). The display panel (DP) can also receive an initialization voltage (Vint). The initialization voltage (Vint) can be supplied to the pixel (PX).

[0080] Figure 4 This is an equivalent circuit diagram of pixel PXij according to an embodiment of the present invention.

[0081] exist Figure 4 The example shows multiple pixels PX (see reference). Figure 3 The equivalent circuit diagram of a pixel PXij in the diagram is shown below. Each of the multiple pixels PX has the same circuit structure; therefore, the specific descriptions of the remaining pixels PX are omitted by describing the circuit structure of pixel PXij. i can be an integer greater than 1 and less than n, and j can be an integer greater than 1 and less than m.

[0082] Reference Figure 4 Pixel PXij includes a light-emitting element (ED) and a pixel driving circuit (PDC). Pixel PXij can be connected to the scan wirings SCL1-SCLn and SSL1-SSLn (see reference). Figure 3 The i-th scan routing SCLi, SSLi, and data routing DL1-DLm in ) (refer to Figure 3 The j-th data routing DLj and the lead routing RL1-RLm in (refer to) Figure 3 The j-th lead routing RLj in ) . The i-th scan routing SCLi and SSLi may include the i-th first-type scan routing SCLi and the i-th second-type scan routing SSLi.

[0083] The pixel driving circuit PDC may include a first transistor TR1, a second transistor TR2, a third transistor TR3, and a capacitor Cst. The structure of the pixel driving circuit PDC according to this invention is not limited to... Figure 4 The example shown. Figure 4 The pixel driver circuit PDC shown is merely an example, and its structure can be modified. For instance, the pixel driver circuit PDC may also include at least one transistor and at least one capacitor.

[0084] In one embodiment of this invention, each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 is described as an N-type thin-film transistor. However, this is not a limitation. For example, at least any one of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may also be a P-type thin-film transistor.

[0085] Furthermore, each of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be a transistor having an oxide semiconductor layer. However, it is not particularly limited thereto. For example, at least one of the first transistor TR1, the second transistor TR2, and the third transistor TR3 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer.

[0086] The first transistor TR1 can be electrically connected between the first power supply wiring PL1 and the light-emitting element ED. The first transistor TR1 may include a gate electrode connected to the first node N1, a first electrode electrically connected to the first power supply wiring PL1, and a second electrode connected to the light-emitting element ED. The light-emitting element ED and the first transistor TR1 can be electrically connected at the second node N2. The first power supply voltage ELVDD can be provided to the pixel PXij through the first power supply wiring PL1.

[0087] The first transistor TR1 can control the amount of current flowing to the light-emitting element ED in accordance with the voltage of the first node N1. For example, the first transistor TR1 can be turned on when the voltage between the first node N1 and the second node N2 (i.e., the gate-source voltage) is higher than a threshold voltage.

[0088] The second transistor TR2 can be electrically connected between the j-th data line DLj and the first node N1. The second transistor TR2 may include a gate electrode connected to the i-th first type scan line SCLi, a first electrode connected to the j-th data line DLj, and a second electrode connected to the first node N1.

[0089] The second transistor TR2 can transmit the data voltage DS received from the j-th data line DLj to the first node N1 in response to the i-th first-type scan signal SCi provided through the i-th first-type scan line SCLi. For example, the second transistor TR2 can be turned on when the i-th first-type scan signal SCi is at a logic high level.

[0090] A third transistor TR3 may be electrically connected between the second node N2 and the j-th lead RLj. The third transistor TR3 may include a gate electrode connected to the i-th second-type scan lead SSLi, a first electrode connected to the j-th lead RLj, and a second electrode connected to the second node N2. The third transistor TR3 may turn on the second node N2 and the j-th lead RLj in response to the i-th second-type scan signal SSi provided by the i-th second-type scan lead SSLi. For example, the third transistor TR3 may be turned on when the i-th second-type scan signal SSi is logic high.

[0091] According to one embodiment of the present invention, during image display operation, the third transistor TR3 can transmit an initialization voltage Vint to the second node N2 in response to the i-th second-type scan signal SSi. That is, if the third transistor TR3 is turned on, the second electrode of the first transistor TR1 can be reset to the initialization voltage Vint.

[0092] During sensing operation, the third transistor TR3 can transmit a sensing current corresponding to the voltage of the second node N2 to the j-th lead wiring RLj in response to the i-th second-type scan signal SSi. The control circuit TC (see reference) Figure 3 It can receive the sensed current to determine the threshold voltage or mobility of the first transistor TR1, and generate compensated image data RGB (refer to...). Figure 3 ).

[0093] Capacitor Cst can be connected between the first node N1 and the second node N2. When the data voltage DS is supplied, the initialization voltage Vint can be supplied to the second node N2. At this time, the differential voltage between the data voltage DS and the initialization voltage Vint can be stored in capacitor Cst. Based on the voltage stored in capacitor Cst, the on / off state of the first transistor TR1 can be determined.

[0094] A light-emitting element (ED) can be connected between a second node N2 and a second power supply line PL2. A second power supply voltage ELVSS can be applied to the second power supply line PL2. The ED can include a first electrode (e.g., an anode), a second electrode (e.g., a cathode), and a light-emitting layer between the first and second electrodes. For example, the first electrode can be connected to the second node N2, and the second electrode can be connected to the second power supply line PL2. The ED can generate light with a predetermined brightness corresponding to the amount of current supplied from the first transistor TR1.

[0095] Figure 5 This is a block diagram illustrating a portion of the structure of a display panel DP according to an embodiment of the present invention.

[0096] Reference Figure 5 The image shows a portion of a scan drive circuit SDC and a pixel PX. The scan drive circuit SDC may include a first type scan drive circuit SCD and a second type scan drive circuit SSD. Specifically, the first type scan drive circuit SCD may include multiple first type stages SC-ST1, SC-ST2, and SC-ST3, and the second type scan drive circuit SSD may include multiple second type stages SS-ST1, SS-ST2, and SS-ST3.

[0097] According to one embodiment of the present invention, the first type-level SC-ST1, SC-ST2, and SC-ST3 can be arranged along the first direction DR1, and the second type-level SS-ST1, SS-ST2, and SS-ST3 can be arranged along the first direction DR1. Alternatively, the first type-level SC-ST1, SC-ST2, and SC-ST3 and the second type-level SS-ST1, SS-ST2, and SS-ST3 can be alternately and repeatedly arranged along the first direction DR1.

[0098] According to one embodiment of the present invention, each of the first type levels SC-ST1, SC-ST2, and SC-ST3 can be electrically connected to a plurality of first type scan cabling SCLs. Additionally, each of the second type levels SS-ST1, SS-ST2, and SS-ST3 can be electrically connected to a plurality of second type scan cabling SSLs. For example, one first type level SC-ST1 can be connected to Y first type scan cabling SCLs to output Y first type scan signals, and one second type level SS-ST1 can be connected to Y second type scan cabling SSLs to output Y second type scan signals. Y can be an integer greater than 2.

[0099] exist Figure 5 The example illustrates a Type 1 SC-ST1 electrically connected to six Type 1 Scan Cabling (SCLs) and a Type 2 SS-ST1 electrically connected to six Type 2 Scan Cabling (SSLs), but is not particularly limited thereto. For example, a Type 1 SC-ST1 may also connect more than two Type 1 Scan Cabling (SCLs), and a Type 2 SS-ST1 may connect more than two Type 2 Scan Cabling (SSLs).

[0100] According to one embodiment of the present invention, a plurality of pixels PX can be arranged in a first direction DR1 and a second direction DR2. A row of pixels PX-r arranged in the second direction DR2 (hereinafter referred to as a pixel row) can be connected to a first type level SC-ST1 and a second type level SS-ST1. Alternatively, the pixels PX may include pixels PXG1 (hereinafter referred to as a first pixel group) arranged in a Y-row in the first direction DR1, and the first pixel group PXG1 is connected to a first type level SC-ST1 and a second type level SS-ST1.

[0101] The first pixel group PXG1, comprising six pixel rows of PX-r, can be connected to the first first type level SC-ST1 and the first second type level SS-ST1. The second pixel group PXG2, comprising the following six pixel rows of PX-r, can be connected to the second first type level SC-ST2 and the second second type level SS-ST2. The third pixel group PXG3, comprising the following six pixel rows of PX-r, can be connected to the third first type level SC-ST3 and the third second type level SS-ST3.

[0102] According to one embodiment of the present invention, a level, such as a first type level SC-ST1, can control the operation of a pixel group comprising two or more pixel rows PX-r, such as a first pixel group PXG1. That is, the total number of levels can be smaller than the number of rows of pixels PX. Thus, the non-display area NDA (refer to...) Figure 3 The number of transistors, capacitors, and wiring (e.g., clock wiring) in a display panel can be reduced. As a result, the display panel (DP) can be reduced in size. Figure 2 The non-display area NDA (refer to) Figure 3 The width of ) can be reduced.

[0103] Figure 6a This illustrates a scan drive circuit SDC (refer to) according to an embodiment of the present invention. Figure 5 (The image is shown.) Figure 6b This is an equivalent circuit diagram of a stage ST[N] according to an embodiment of the present invention.

[0104] exist Figure 6a The example shows three levels ST[N-1], ST[N], and ST[N+1]. N can be an integer greater than 2. The three levels ST[N-1], ST[N], and ST[N+1] can be the first type levels SC-ST1, SC-ST2, and SC-ST3 (see reference). Figure 5 ) or second-level SS-ST1, SS-ST2, SS-ST3 (refer to Figure 5 ).

[0105] exist Figure 6b An equivalent circuit diagram of a stage ST[N] is shown as an example. The remaining stages ST[N-1], ST[N+1] also include substantially the same structure, therefore repeated descriptions are omitted. The structure of a stage ST[N] according to this invention is not limited to... Figure 6b The example shown. Figure 6b The single-stage ST[N] shown is merely an example; the circuit structure of a single-stage ST[N] can be modified and implemented.

[0106] Reference Figure 6a Levels ST[N-1], ST[N], and ST[N+1] can be referred to as the first level ST[N-1], the second level ST[N], and the third level ST[N+1], respectively. Alternatively, the second level ST[N] can be called the base level or level, the first level ST[N-1] can be called the first peripheral level, and the third level ST[N+1] can be called the second peripheral level. Hereinafter, the second level ST[N] will be referred to as level.

[0107] Level ST[N] may include the first to sixth input terminals IN1, IN2, IN3, IN4, IN5, IN6, the first to sixth clock terminals CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, the first control terminal CINa, the second control terminal CINb, the first to sixth output terminals OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, and the carry output terminal COUT.

[0108] The first input terminal IN1 of stage ST[N] can receive the carry signal CR[N-1] output from the previous stage, such as the first stage ST[N-1]. When stage ST[N] is the first stage, the first input terminal IN1 can receive the start signal output from the virtual stage preceding the first stage.

[0109] The carry signal CR[N-1] can be called the previous carry signal or the first carry signal, hereinafter referred to as the first carry signal CR[N-1]. The first stage ST[N-1] and the stage ST[N] can be electrically connected to the first carry routing CRL1, which can also be called the first peripheral carry routing. The first carry signal CR[N-1] generated in the first stage ST[N-1] can be transmitted to the stage ST[N] through the first carry routing CRL1.

[0110] The second input terminal IN2 of stage ST[N] can receive the carry signal CR[N+1] output from the next stage, such as the third stage ST[N+1]. When stage ST[N] is the last stage, the second input terminal IN2 can receive the carry signal output from the next virtual stage after the last stage.

[0111] The carry signal CR[N+1] can be called the next carry signal or the third carry signal, hereinafter referred to as the third carry signal CR[N+1]. The third stage ST[N+1] and the stage ST[N] can be electrically connected to the third carry routing CRL3, which can also be called the second peripheral carry routing. The third carry signal CR[N+1] generated in the third stage ST[N+1] can be transmitted to the stage ST[N] through the third carry routing CRL3.

[0112] It is possible that the third input terminal IN3 of stage ST[N] receives the first high voltage VDD1, and the fourth input terminal IN4 receives the second high voltage VDD2. The voltage level of the second high voltage VDD2 can be greater than the voltage level of the first high voltage VDD1, but is not particularly limited thereto. For example, the first high voltage VDD1 can be 15V, and the second high voltage VDD2 can be 25V.

[0113] It is possible that the fifth input terminal IN5 of stage ST[N] receives the supply of the first low voltage VSS1, and the sixth input terminal IN6 receives the supply of the second low voltage VSS2. The voltage levels of the first low voltage VSS1 and the second low voltage VSS2 can be the same or different from each other.

[0114] Stage ST[N] can receive the boost clock signal BCK through the first control terminal CINa and the carry clock signal CR_CK through the second control terminal CINb. Stage ST[N] can receive the first to sixth clock signals CK1, CK2, CK3, CK4, CK5, and CK6 through the first to sixth clock terminals CIN1, CIN2, CIN3, CIN4, CIN5, and CIN6. In one embodiment of this utility model, the first to sixth clock terminals CIN1, CIN2, CIN3, CIN4, CIN5, and CIN6 of each of the first stage ST[N-1] and the third stage ST[N+1] can also receive clock signals with opposite phases to the first to sixth clock signals CK1, CK2, CK3, CK4, CK5, and CK6, respectively.

[0115] The carry output terminal COUT of stage ST[N] can output the carry signal CR[N]. The carry signal CR[N] can be transmitted to the first stage ST[N-1] and the third stage ST[N+1]. The carry signal CR[N] can be called the second carry signal, hereinafter referred to as the second carry signal CR[N]. The first stage ST[N-1], stage ST[N], and third stage ST[N+1] can be electrically connected to the second carry wiring CRL2. The second carry signal CR[N] generated in stage ST[N] can be transmitted to the first stage ST[N-1] and the third stage ST[N+1] through the second carry wiring CRL2.

[0116] The first to sixth output terminals OUT1, OUT2, OUT3, OUT4, OUT5, and OUT6 of stage ST[N] can output the first to sixth scan signals SS1[N], SS2[N], SS3[N], SS4[N], SS5[N], and SS6[N], respectively. The first to sixth scan signals SS1[N], SS2[N], SS3[N], SS4[N], SS5[N], and SS6[N] can, for example, be output from the second pixel group PXG2 (see reference). Figure 5 ) Provide pixels for each of the six rows.

[0117] The first to sixth scan signals SS1[N], SS2[N], SS3[N], SS4[N], SS5[N], and SS6[N] can be transmitted via the first type of scan wiring SCLs (see reference). Figure 5 The first scan signal (or first type scan signal) is provided respectively. Alternatively, the first to sixth scan signals SS1[N], SS2[N], SS3[N], SS4[N], SS5[N], and SS6[N] can be provided via second type scan wiring SSLs (see reference). Figure 5 The second scan signal (or second type scan signal) provided by each.

[0118] Reference Figure 6b A level ST[N] can include a first node QC, a second node QB, a third node N-CQ, a fourth node NB, and multiple partition nodes Q-1 to Q-6. Specifically, the first node QC is called a Q node, the multiple partition nodes Q-1 to Q-6 are called partition Q nodes, and the second node QB is called a QB node.

[0119] In addition, a stage ST[N] may also include a first circuit S101, a second circuit S102, a third circuit S103, a fourth circuit S104, a fifth circuit S105, a sixth circuit S106, a seventh circuit S107, an eighth circuit S108, and a ninth circuit S109.

[0120] The first circuit S101 can control the voltage of the first node QC and can be called the first node control circuit. The first circuit S101 may include the first to fourth transistors T11, T12, T13, and T14.

[0121] The first transistor T11 and the second transistor T12 can be connected in series, and both transistors T11 and T12 can have a dual-gate structure. The first transistor T11 and the second transistor T12 can be connected between the first input terminal IN1 and the first node QC. Furthermore, the gate electrodes of the first transistor T11 and the second transistor T12 can both be connected to the first input terminal IN1. A fourth input terminal IN4 can be connected between the first transistor T11 and the second transistor T12. Alternatively, the first and second transistors T11 and T12 can be turned on in response to the gate on-state voltage (e.g., logic high level) of the first carry signal CR[N-1], and the second transistor T12 transmits a second high voltage VDD2 to the first node QC. The transmission of the second high voltage VDD2 to the first node QC can be referred to as pre-charging operation or boosting operation. The third transistor T13 and the fourth transistor T14 can be connected in series, and both transistors T13 and T14 can have a dual-gate structure. The third and fourth transistors T13 and T14 can be connected between the first node QC and the sixth input terminal IN6. Additionally, the gate electrodes of the third transistor T13 and the fourth transistor T14 can both be connected to the second input terminal IN2. The third and fourth transistors T13 and T14 can transmit a second low voltage VSS2 to the first node QC in response to the gate on-state voltage (e.g., a logic high level) of the third carry signal CR[N+1].

[0122] The second circuit S102 may include a first transistor T21 and a second transistor T22. The first transistor T21 and the second transistor T22 can be connected in series, and the first and second transistors T21 and T22 can be connected between the first node QC and the sixth input terminal IN6. Furthermore, the gate electrodes of the first transistor T21 and the second transistor T22 can both be connected to the second node QB. The first and second transistors T21 and T22 can transmit a second low voltage VSS2 to the first node QC in response to the voltage of the second node QB. Therefore, the second circuit S102 can be referred to as a first node stabilization circuit.

[0123] The third circuit S103 may include a first transistor T31, a second transistor T32, a third transistor T33, a fourth transistor T34, and a fifth transistor T35.

[0124] The first transistor T31 can be connected between the second node QB and the third input terminal IN3. The second transistor T32 and the third transistor T33 can be connected in series. Specifically, the gate electrodes of the second and third transistors T32 and T33 can be connected to the third input terminal IN3, and the second and third transistors T32 and T33 can be connected between the third input terminal IN3 and the gate electrode of the first transistor T31.

[0125] Alternatively, the fourth transistor T34 can be connected between the gate electrode of the first transistor T31 and the fifth input terminal IN5, and the fifth transistor T35 can be connected between the second node QB and the sixth input terminal IN6. The gate electrodes of the fourth transistor T34 and the fifth transistor T35 can be connected to the first node QC.

[0126] The second and third transistors T32 and T33, in response to the first high voltage VDD1, transfer the first high voltage VDD1 to the gate electrode of the first transistor T31. The fourth transistor T34 is controlled to operate in response to the voltage of the first node QC. If the fourth transistor T34 is turned on, the first low voltage VSS1 can be transferred to the gate electrode of the first transistor T31.

[0127] The first transistor T31 can transmit a first high voltage VDD1 to the second node QB in response to the voltage at its gate electrode. The fifth transistor T35 is controlled to operate in response to the voltage at the first node QC. If the fifth transistor T35 is turned on, a second low voltage VSS2 can be transmitted to the second node QB.

[0128] The fourth circuit S104 may include a first transistor T41, a second transistor T42, and a capacitor C4.

[0129] The first transistor T41 can be connected between the first control terminal CINa and the fourth node NB. The gate electrode of the first transistor T41 can be connected to the first node QC. The first transistor T41 is controlled to operate in response to the voltage of the first node QC. When the first transistor T41 is turned on, a logic high-level voltage can be provided to the fourth node NB.

[0130] The second transistor T42 can be connected between the fourth node NB and the sixth input terminal IN6. The gate electrode of the second transistor T42 can be connected to the second node QB. The second transistor T42 is controlled to operate in response to the voltage of the second node QB. When the second transistor T42 is turned on, a second low voltage VSS2 can be provided to the fourth node NB.

[0131] Capacitor C4 is connected between the gate electrode of the first transistor T41 and the fourth node NB. Capacitor C4 can increase the voltage of the first node QC in response to the voltage rise of the fourth node NB (boost voltage), which can be called secondary boost operation.

[0132] The fifth circuit S105 may include a first transistor T51 and a second transistor T52.

[0133] The first transistor T51 can be connected between the second control terminal CINb and the carry output terminal COUT. The gate electrode of the first transistor T51 can be connected to the first node QC. The first transistor T51 is controlled to operate in response to the voltage of the first node QC. When the first transistor T51 is turned on, a logic high level voltage of the second carry signal CR[N] can be provided to the carry output terminal COUT.

[0134] The second transistor T52 can be connected between the carry output terminal COUT and the sixth input terminal IN6. The gate electrode of the second transistor T52 can be connected to the second node QB. The second transistor T52 is controlled to operate in response to the voltage of the second node QB. When the second transistor T52 is turned on, a second low voltage VSS2 can be provided to the carry output terminal COUT.

[0135] The sixth circuit S106 can control the voltage of the third node N-CQ and can be called the third node control circuit. The sixth circuit S106 may include the first transistor T61, the second transistor T62, and the third transistor T63.

[0136] The first transistor T61 and the second transistor T62 can be connected in series, and both transistors T61 and T62 can have a dual-gate structure. The first transistor T61 and the second transistor T62 can be connected between the fourth input terminal IN4 and the third node N-CQ. Furthermore, the gate electrodes of the first transistor T61 and the second transistor T62 can both be connected to the first input terminal IN1. The first and second transistors T61 and T62 can transmit a second high voltage VDD2 to the third node N-CQ in response to the gate on-state voltage (e.g., a logic high level) of the first carry signal CR[N-1].

[0137] The third transistor T63 can be connected between the third node N-CQ and the third input terminal IN3. Additionally, the gate electrode of the third transistor T63 can be connected to the second input terminal IN2. The third transistor T63 can transmit a first high voltage VDD1 to the third node N-CQ in response to the gate on-state voltage (e.g., logic high level) of the third carry signal CR[N+1].

[0138] The seventh circuit S107 may include transistor T71. Transistor T71 may be connected between the third input terminal IN3 and the third node N-CQ. The gate electrode of transistor T71 may be connected to the fourth node NB. Transistor T71 may provide a first high voltage VDD1 to the third node N-CQ in response to the voltage of the fourth node NB.

[0139] The eighth circuit S108 may include a first transistor T81 and a second transistor T82.

[0140] The first transistor T81 and the second transistor T82 can be connected in series, and the first and second transistors T81 and T82 can be connected between the third node N-CQ and the fifth input terminal IN5. Furthermore, the gate electrodes of the first transistor T81 and the second transistor T82 can both be connected to the second node QB. The first and second transistors T81 and T82 can transmit a first low voltage VSS1 to the third node N-CQ in response to the voltage at the second node QB. Therefore, the eighth circuit S108 can be called the third node stabilization circuit.

[0141] The ninth circuit S109 may include multiple output circuits S109s. In one embodiment of this invention, one stage ST[N] outputs six scan signals, therefore the ninth circuit S109 may include six output circuits S109s. Figure 6b The example shows a first output circuit and a last output circuit (e.g., a sixth output circuit), for a total of two output circuits.

[0142] Each of the output circuits S109s may include a first transistor T91, a second transistor T92, a third transistor T93, and a capacitor C9. The first output circuit S109s will be described below; the remaining output circuits S109s have substantially the same structure, so repeated descriptions are omitted.

[0143] The first transistor T91 can be connected between the first clock terminal CIN1 and the first output terminal OUT1. The gate electrode of the first transistor T91 can be connected to the split node Q-1. The second transistor T92 can be connected between the first node QC and the split node Q-1. The gate electrode of the second transistor T92 can be connected to the third node N-CQ. The second transistor T92 can connect the first node QC and the split node Q-1, or disconnect the first node QC and the split node Q-1, in response to the voltage of the third node N-CQ.

[0144] The first transistor T91 is controlled to operate in response to the voltage of the split node Q-1. When the first transistor T91 is turned on, a logic high level voltage of the scan signal SS1[N] can be output to the first output terminal OUT1.

[0145] According to one embodiment of the present invention, transistor T71 can be turned on during the boosting sequence of the fourth node NB, thereby transmitting the first high voltage VDD1 to the third node N-CQ. During the boosting sequence of the fourth node NB, the voltage of the first node QC can be higher than the first high voltage VDD1 of the third node N-CQ. Therefore, the second transistor T92 can be turned off. The second transistor T92 can separate the first node QC and the split node Q-1 in response to the voltage of the third node N-CQ.

[0146] During signal output to the first to sixth output terminals OUT1, OUT2, OUT3, OUT4, OUT5, and OUT6, the first node QC and the splitting node Q-1 are electrically isolated from each other, and the splitting nodes Q-1 to Q-6 are also electrically isolated from each other. Therefore, even if the voltage coupling of the splitting node Q-1 changes according to the signal output to the first output terminal OUT1, the influence on other nodes can be eliminated. For example, the other nodes can be the first node QC and the other splitting nodes among the splitting nodes Q-1 to Q-6 besides the splitting node Q-1. Therefore, horizontal line defects caused by brightness differences in each line can be eliminated.

[0147] According to one embodiment of the present invention, if a second low voltage VSS2 is transmitted to the first node QC in response to the gate turn-on voltage of the third carry signal CR[N+1], then the voltage of the first node QC can be lower than the voltage of the third node N-CQ. In this case, the second transistor T92 may be turned on while the first node QC and the split node Q-1 are connected, and the split node Q-1 is discharged.

[0148] The third transistor T93 can be connected between the first output terminal OUT1 and the fifth input terminal IN5. The gate electrode of the third transistor T93 can be connected to the second node QB. The third transistor T93 is controlled to operate in response to the voltage of the second node QB. When the third transistor T93 is turned on, a first low voltage VSS1 can be provided to the first output terminal OUT1.

[0149] Capacitor C9 is connected between split node Q-1 and fourth node NB. Capacitor C9 can increase the voltage of split node Q-1 (boost voltage) in response to the voltage rise of fourth node NB. If the voltage of split node Q-1 rises, a high-voltage scan signal SS1[N] can be output without distortion.

[0150] Figure 7 This is a timing diagram illustrating the operation of a first mode MD1 according to an embodiment of the present invention. Figure 8 This is a timing diagram illustrating the operation of multiple clock signals in the second mode MD2 according to an embodiment of the present invention.

[0151] Reference Figure 1 , Figure 7 as well as Figure 8 The display panel DP can be selected to operate in either a first mode MD1 or a second mode MD2. For example, the first mode MD1 can be a general driving mode driven at a first frequency, and the second mode MD2 can be a high-frequency driving mode driven at a second frequency higher than the first frequency. For example, the first frequency can be 240Hz, and the second frequency can be 480Hz. However, the first and second frequencies described above are merely examples, and the first and second frequencies are not particularly limited to these examples.

[0152] Reference Figure 7 The example shows the first carry signal CR[N-1], the second carry signal CR[N], the third carry signal CR[N+1], the boost clock signal BCK, the carry clock signal CR_CK, and the first to sixth clock signals CK1, CK2, CK3, CK4, CK5, and CK6 under the first mode MD1.

[0153] Reference Figure 8The example shows the first carry signal CR[N-1], the second carry signal CR[N], the third carry signal CR[N+1], the boost clock signal BCKa, the carry clock signal CR_CKa, and the first to sixth clock signals CK1a, CK2a, CK3a, CK4a, CK5a, and CK6a under the second mode MD2.

[0154] Refer to together Figure 7 as well as Figure 8 In the first mode MD1, the period CY1 of the boost clock signal BCK can be longer than the period CY1a of the boost clock signal BCKA in the second mode MD2. For example, the period CY1 can be twice the period CY1a. Similarly, in the first mode MD1, the period CY2 of the carry clock signal CR_CK can be longer than the period CY2a of the carry clock signal CR_CKa in the second mode MD2. For example, the period CY2 can be twice the period CY2a. That is, the clock period can be reduced in the second mode MD2.

[0155] According to one embodiment of the present invention, for low-power driving or high-speed driving, at least a portion of multiple scan lines can be driven (e.g., activated) simultaneously. For example, two scan lines can be driven simultaneously, and the second mode MD2 can be referred to as a dual-wire gate driving mode. In one embodiment of the present invention, the first mode MD1 can be a high-resolution mode, and the second mode MD2 can be a high-scan-rate mode.

[0156] In the first mode MD1, the first to sixth clock signals CK1, CK2, CK3, CK4, CK5, and CK6 can have different phases. That is, the first to sixth clock signals CK1, CK2, CK3, CK4, CK5, and CK6 can have waveforms shifted by a predetermined interval from each other. Correspondingly, the first to sixth scan signals SS1, SS2, SS3, SS4, SS5, and SS6, which are output synchronously with the first to sixth clock signals CK1, CK2, CK3, CK4, CK5, and CK6, can also have different phases. The first to sixth scan signals SS1, SS2, SS3, SS4, SS5, and SS6 can also be referred to as the first mode scan signals.

[0157] The first to sixth scan signals SS1, SS2, SS3, SS4, SS5, and SS6 can be transmitted via the first type of scan wiring SCLs (see reference). Figure 5 The first scan signal (or first type scan signal) is provided respectively. Alternatively, the first to sixth scan signals SS1, SS2, SS3, SS4, SS5, and SS6 can be provided via second type scan wiring SSLs (see reference). Figure 5 The second scan signal (or second type scan signal) provided by each.

[0158] In the second mode MD2, some of the clock signals CK1a, CK2a, CK3a, CK4a, CK5a, and CK6a from the first to the sixth clock signals can have the same phase. For example, the waveforms of the first clock signal CK1a and the second clock signal CK2a can be identical. The third clock signal CK3a can have a waveform shifted by a predetermined time relative to the first clock signal CK1a, and the waveforms of the third clock signal CK3a and the fourth clock signal CK4a can be identical. Furthermore, the waveforms of the fifth clock signal CK5a and the sixth clock signal CK6a can be identical.

[0159] In the second mode MD2, a portion of the first to sixth scan signals SS1a, SS2a, SS3a, SS4a, SS5a, and SS6a, which are output synchronously with the first to sixth clock signals CK1a, CK2a, CK3a, CK4a, CK5a, and CK6a, can have waveforms with the same phase. For example, the first scan signal SS1a and the second scan signal SS2a can overlap each other and have substantially the same waveform. In this case, a data voltage DS (refer to...) can be provided simultaneously to a row of pixels receiving the first scan signal SS1a and a row of pixels receiving the second scan signal SS2a in the second mode MD2. Figure 4 ).

[0160] The third scan signal SS3a and the fourth scan signal SS4a can overlap each other and have substantially the same waveform. The fifth scan signal SS5a and the sixth scan signal SS6a can overlap each other and have substantially the same waveform. The first to sixth scan signals SS1a, SS2a, SS3a, SS4a, SS5a, and SS6a can also be referred to as the second mode scan signals.

[0161] The first to sixth scan signals SS1a, SS2a, SS3a, SS4a, SS5a, and SS6a can be transmitted via the first type of scan wiring SCLs (see reference). Figure 5 The first scan signal (or first type scan signal) is provided respectively. Alternatively, the first to sixth scan signals SS1a, SS2a, SS3a, SS4a, SS5a, and SS6a can be provided via second type scan wiring SSLs (see reference). Figure 5 The second scan signal (or second type scan signal) provided by each.

[0162] Figure 9 This is a diagram showing the activation state and brightness changes of a first type scan signal SC and a second type scan signal SS according to an embodiment of the present invention. Figure 10This is a diagram illustrating the activation state and brightness changes of a first-type scan signal SCa and a second-type scan signal SSa according to an embodiment of the present invention. The first-type scan signal SC and the first-type scan signal SCa can be... Figure 4 The signal provided by the i-th first-type scan wiring SCLi shown, the second-type scan signal SS and the second-type scan signal SSa can be Figure 4 The signal shown is provided by the i-th second-type scan wiring SSLi.

[0163] Reference Figure 1 , Figure 9 as well as Figure 10 The display panel (DP) can operate in a mode driven by a variable frame rate (hereinafter, mode MD3). For example, the variable frame rate can vary in various ways within the range of 1Hz to 240Hz, but is not specifically limited to this. Figure 9 The image exemplarily illustrates the brightness of the first type scan signal SC, the second type scan signal SS, and the display panel DP when driven at 240Hz. Figure 10 The image exemplarily illustrates the brightness of the first type scan signal SCa, the second type scan signal SSa, and the display panel DP when driven at 60Hz.

[0164] Reference Figure 9 as well as Figure 10 Alternatively, when driving the display panel DP at 240Hz, the first type scan signal SC includes four write cycle intervals WP and the second type scan signal SS includes four initialization cycle intervals IP during the unit time TU. Alternatively, when driving the display panel DP at 60Hz, the first type scan signal SCa includes one write cycle interval WPa and the second type scan signal SSa includes four initialization cycle intervals IP during the unit time TU.

[0165] During the write period interval WP or WPa, the first type scan signal SC or SCa can have a waveform that alternates between logic high and logic low levels. In all other intervals besides WP or WPa, the first type scan signal SC or SCa can have a logic low level. Additionally, during the initialization period interval IP, the second type scan signal SS or SSa can have a waveform that alternates between logic high and logic low levels.

[0166] Refer to together Figure 5The multiple first-type stages SC-ST1, SC-ST2, and SC-ST3 of the first-type scan drive circuit SCD that generates the first-type scan signal SC or SCa, and the multiple second-type stages SS-ST1, SS-ST2, and SS-ST3 of the second-type scan drive circuit SSD that generates the second-type scan signal SS or SSa, can be separated from each other. Therefore, the operation of the first-type scan signal SC or SCa and the operation of the second-type scan signal SS or SSa can be separated from each other. As a result, the number of initialization period intervals IP within a unit time TU can be adjusted independently of the operating frequency of the display panel DP. At this time, the difference in light waveform according to the operating frequency of the display panel DP can be reduced, and consequently, the difference in brightness according to the operating frequency of the display panel DP can be reduced. That is, the image display quality of the display panel DP can be improved.

[0167] exist Figure 7 , Figure 8 , Figure 9 as well as Figure 10 The driving modes described herein can be applied to the display panel DP in various combinations. For example, in one embodiment of this invention, the display panel DP can operate in any of the first mode MD1, the second mode MD2, and the third mode MD3. The first mode MD1 can also correspond to a mode driven at 240Hz under the third mode MD3. Alternatively, in one embodiment of this invention, the display panel DP can operate in any of the first mode MD1 and the third mode MD3. In this case, the first mode MD1 can be a general driving mode driven at a fixed frequency, and the third mode MD3 can be a variable driving mode driven at a variable frequency. Alternatively, in one embodiment of this invention, the display panel DP can operate in any of the first mode MD1 and the second mode MD2. Alternatively, in one embodiment of this invention, the display panel DP can also operate only in the first mode MD1. Alternatively, in one embodiment of this invention, the display panel DP can also operate only in the third mode MD3.

[0168] Figure 11 This is a plan view of a portion of a display panel DP according to an embodiment of the present invention.

[0169] Reference Figure 11 The display panel DP may include multiple pixels PX1, PX2, PX3, PX4, PX5, PX6, a group level GST, multiple clock wirings CKLT1, CKLT2, multiple connection wirings CLS, multiple carry clock wirings CRCKL, and multiple signal wirings SL.

[0170] Multiple pixels PX1, PX2, PX3, PX4, PX5, and PX6 can be configured in the display area DA. Pixels PX1, PX2, PX3, PX4, PX5, and PX6 can be arranged along a first direction DR1. That is, pixels PX1, PX2, PX3, PX4, PX5, and PX6 can be arranged in different rows from each other. Pixels PX1, PX2, PX3, PX4, PX5, and PX6 can include a first pixel PX1, a second pixel PX2, a third pixel PX3, a fourth pixel PX4, a fifth pixel PX5, and a sixth pixel PX6 arranged sequentially along the first direction DR1.

[0171] The first to sixth pixels, PX1, PX2, PX3, PX4, PX5, and PX6, can receive scan signals provided from a group-level GST. For example, a group-level GST includes a first-type level SC-ST and a second-type level SS-ST. The first-type level SC-ST can provide a first-type scan signal to the first-type scan wiring, and the second-type level SS-ST can provide a second-type scan signal to the second-type scan wiring.

[0172] The non-display area NDA can be divided into multiple regions. For example, the non-display area NDA may include a first non-display area NDA1, a second non-display area NDA2, a third non-display area NDA3, a fourth non-display area NDA4, and a fifth non-display area NDA5. The first to fifth non-display areas NDA1, NDA2, NDA3, NDA4, and NDA5 can be sequentially defined along a second direction DR2 towards the display area DA.

[0173] The carry clock routing CRCKL can be configured in the first non-display area NDA1. Each of the carry clock routing CRCKLs can provide... Figure 6b The wiring diagram for the carry clock signal CR_CK and the boost clock signal BCK is shown.

[0174] Clock wiring CKLT1 and CKLT2 can be configured in the first non-display area NDA1. Clock wiring CKLT1 and CKLT2 can include a first type clock wiring CKLT1 and a second type clock wiring CKLT2. For example, a portion of the first type clock wiring CKLT1 can transmit the first to sixth clock signals CK1, CK2, CK3, CK4, CK5, and CK6 (see reference) provided to the first type level SC-ST. Figure 6a The wiring of the second type clock wiring CKLT2 is part of the transmission of the first to sixth clock signals CK1, CK2, CK3, CK4, CK6 provided to the second type level SS-ST (refer to...). Figure 6a ) wiring.

[0175] The first type of clock routing CKLT1 may include a first clock routing CKL1, a second clock routing CKL2, a third clock routing CKL3, a fourth clock routing CKL4, a fifth clock routing CKL5, and a sixth clock routing CKL6. Each of the first to sixth clock routings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6 may extend along a first direction DR1, and the first to sixth clock routings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6 may be arranged along a second direction DR2. The six clock routings arranged to the right of the sixth clock routing CKL6 in the first type of clock routing CKLT1 may be oriented towards... Figure 11 The wiring for the first type level of the group level GST shown is for transmitting the clock signal.

[0176] The second non-display area NDA2 can be an area with equal resistance design. A portion of the wiring configured in the second non-display area NDA2 is shown magnified. Figure 12 The explanation for this will be given later.

[0177] Signal wiring SL can be configured in the third non-display area NDA3. Each signal wiring SL can be a wiring for transmitting power supply voltage and other signals.

[0178] A group-level GST can be configured in the fourth non-display area NDA4. The first type level SC-ST of the group-level GST may include multiple transistors TC1, TC2, TC3, TC4, TC5, and TC6 that output multiple first-type scan signals to the first through sixth pixels PX1, PX2, PX3, PX4, PX5, and PX6. The second type level SS-ST of the group-level GST may include multiple transistors TS1, TS2, TS3, TS4, TS5, and TS6 that output multiple second-type scan signals to the first through sixth pixels PX1, PX2, PX3, PX4, PX5, and PX6.

[0179] Multiple transistors TC1, TC2, TC3, TC4, TC5, and TC6 can be connected with... Figure 6b The six output circuits S109s shown correspond one-to-one with the six first transistors T91. Additionally, multiple transistors TS1, TS2, TS3, TS4, TS5, and TS6 can be coupled with… Figure 6b The six first transistors T91 of the six output circuits S109s shown are in one-to-one correspondence. The following descriptions will focus on transistors TC1, TC2, TC3, TC4, TC5, and TC6. The descriptions of transistors TS1, TS2, TS3, TS4, TS5, and TS6 are essentially the same as those below, therefore their descriptions are omitted.

[0180] The multiple transistors TC1, TC2, TC3, TC4, TC5, and TC6 may include a first transistor TC1, a second transistor TC2, a third transistor TC3, a fourth transistor TC4, a fifth transistor TC5, and a sixth transistor TC6 that correspond one-to-one with the first to sixth pixels PX1, PX2, PX3, PX4, PX5, and PX6.

[0181] According to one embodiment of the present invention, in order to reduce the width of the non-display area NDA, such as the width of the second direction DR2, the first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6 can be configured in at least two rows. For example, instead of arranging the first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6 continuously along one direction, a portion of the first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6 and the remaining portion of the first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6 can be arranged facing each other. Therefore, the width of the second direction DR2 of the non-display area NDA can be reduced.

[0182] The first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6 can be electrically connected to the first to sixth clock wirings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6. For example, the first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6 and the first to sixth clock wirings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6 can be electrically connected through the connecting wiring CLS. Therefore, the connecting wiring CLS can transmit the clock signal received from the first to sixth clock wirings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6 to the first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6.

[0183] The connection wiring CLS may include a first connection wiring CL1, a second connection wiring CL2, a third connection wiring CL3, a fourth connection wiring CL4, a fifth connection wiring CL5, and a sixth connection wiring CL6, which are connected one-to-one with the first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6.

[0184] It can be that the first connection wiring CL1 is connected between the first clock wiring CKL1 and the first transistor TC1, the second connection wiring CL2 is connected between the second clock wiring CKL2 and the second transistor TC2, the third connection wiring CL3 is connected between the third clock wiring CKL3 and the third transistor TC3, the fourth connection wiring CL4 is connected between the fourth clock wiring CKL4 and the fourth transistor TC4, the fifth connection wiring CL5 is connected between the fifth clock wiring CKL5 and the fifth transistor TC5, and the sixth connection wiring CL6 is connected between the sixth clock wiring CKL6 and the sixth transistor TC6.

[0185] The first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6 can be divided into multiple first group transistors TCG1 connected to the 2N-1th pixel (N is an integer greater than 1) of pixels PX1, PX2, PX3, PX4, PX5, and PX6 arranged along the first direction DR1, and multiple second group transistors TCG2 connected to the 2Nth pixel of pixels PX1, PX2, PX3, PX4, PX5, and PX6 arranged along the first direction DR1. The first group transistors TCG1 and the second group transistors TCG2 can be separated from each other by a virtual reference line IL extending along the second direction DR2. The virtual reference line IL can be called a reference line or an extension line, etc.

[0186] At this point, the first to sixth connection wirings CL1, CL2, CL3, CL4, CL5, and CL6 can be divided into a first group of connection wirings CLG1 connected to the first group of transistors TCG1 and a second group of connection wirings CLG2 connected to the second group of transistors TCG2. The first group of connection wirings CLG1 and the second group of connection wirings CLG2 can be configured to be separated from each other by a virtual baseline IL.

[0187] Alternatively, the first group of transistors TCG1 may include a first transistor TC1, a third transistor TC3, and a fifth transistor TC5, and the second group of transistors TC2 may include a second transistor TC2, a fourth transistor TC4, and a sixth transistor TC6. Or, the first group of connection wiring CLG1 may include a first connection wiring CL1, a third connection wiring CL3, and a fifth connection wiring CL5, and the second group of connection wiring CLG2 may include a second connection wiring CL2, a fourth connection wiring CL4, and a sixth connection wiring CL6.

[0188] The first to sixth clock wirings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6 may include multiple first-group clock wirings CKL1, CKL3, and CKL5 electrically connected to the first-group connection wiring CLG1, and multiple second-group clock wirings CKL2, CKL4, and CKL6 electrically connected to the second-group connection wiring CLG2. The first-group clock wirings CKL1, CKL3, and CKL5 and the second-group clock wirings CKL2, CKL4, and CKL6 may be arranged alternately and repeatedly along the second direction DR2.

[0189] According to one embodiment of the present invention, transistors and connection wirings CL1, CL3, and CL5 connected to the odd-numbered pixels may be configured in the upper region of the virtual baseline IL, and transistors and connection wirings CL2, CL4, and CL6 connected to the even-numbered pixels may be configured in the lower region of the virtual baseline IL.

[0190] According to one embodiment of the present invention, the first connection wiring CL1 and the second connection wiring CL2 can be separately configured above and below a virtual reference line IL. Furthermore, the first transistor TC1 connected to the first connection wiring CL1 and the second transistor TC2 connected to the second connection wiring CL2 can be configured facing each other across the virtual reference line IL. In this case, the resistance difference between the first connection wiring CL1 and the second connection wiring CL2 can be reduced to the level of the resistance difference caused by the spacing DR2 in the second direction between the first clock wiring CKL1 and the second clock wiring CKL2. That is, the resistance difference between the first connection wiring CL1 and the second connection wiring CL2 can be reduced.

[0191] Alternatively, the third connection route CL3 and the fourth connection route CL4 can also be separated by a virtual reference line IL, and the third transistor TC3 and the fourth transistor TC4 can also be configured facing each other, separated by a virtual reference line IL. Alternatively, the fifth connection route CL5 and the sixth connection route CL6 can also be separated by a virtual reference line IL, and the fifth transistor TC5 and the sixth transistor TC6 can also be configured facing each other, separated by a virtual reference line IL.

[0192] According to one embodiment of the present invention, equal resistance design can be simplified by configuring the connection lines of adjacent clock lines separated by a virtual reference line IL. For example, the equal resistance design layout of the first connection line CL1, the third connection line CL3, and the fifth connection line CL5 can be similar to the symmetrical form of the equal resistance design layout of the second connection line CL2, the fourth connection line CL4, and the sixth connection line CL6.

[0193] Furthermore, by separately configuring the first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6 with a virtual reference line IL as the reference, it is applicable to the equal resistance design for half of the six wirings, i.e., three wirings, such as the first, third, and fifth connection wirings CL1, CL3, and CL5. Therefore, the area of ​​the equal resistance design space can be reduced.

[0194] It is possible that the first transistor TC1 and the second transistor TC2 face each other on the first direction DR1, the third transistor TC3 and the fourth transistor TC4 face each other on the first direction DR1, and the fifth transistor TC5 and the sixth transistor TC6 face each other on the first direction DR1. Figure 11 The example illustrates transistors facing each other arranged in a perfectly aligned and symmetrical manner, but is not particularly limited to this. For example, the first, third, and fifth transistors TC1, TC3, and TC5 could also be shifted by the spacing between the first clock wiring CKL1 and the second clock wiring CKL2, so that they are more adjacent to the second non-display area NDA2 than the second, fourth, and sixth transistors TC2, TC4, and TC6.

[0195] Alternatively, a third transistor TC3 can be configured between the first transistor TC1 and the fifth transistor TC5, and a fourth transistor TC4 can be configured between the second transistor TC2 and the sixth transistor TC6.

[0196] The first transistor TC1, the third transistor TC3, and the fifth transistor TC5 can be arranged sequentially in a direction away from the first type of clock wiring CKLT1. Additionally, the second transistor TC2, the fourth transistor TC4, and the sixth transistor TC6 can also be arranged sequentially in a direction away from the first type of clock wiring CKLT1.

[0197] The spacing between the fifth transistor TC5 and the sixth transistor TC6 can be greater than the spacing between the third transistor TC3 and the fourth transistor TC4. The spacing between the third transistor TC3 and the fourth transistor TC4 can be greater than the spacing between the first transistor TC1 and the second transistor TC2.

[0198] That is, the first transistor TC1, the third transistor TC3, and the fifth transistor TC5 can be arranged in a stepped configuration, as can the second transistor TC2, the fourth transistor TC4, and the sixth transistor TC6. In this case, the first to sixth connection wirings CL1, CL2, CL3, CL4, CL5, and CL6 extending in the second direction DR2 in the region overlapping with the group level GST can be easily connected to the corresponding first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6.

[0199] The display panel DP may also include a first intermediate connection wiring MCL1, a second intermediate connection wiring MCL2, a third intermediate connection wiring MCL3, a fourth intermediate connection wiring MCL4, a fifth intermediate connection wiring MCL5, and a sixth intermediate connection wiring MCL6, which are connected one-to-one with the first to sixth transistors TC1, TC2, TC3, TC4, TC5, and TC6. The first to sixth intermediate connection wirings MCL1, MCL2, MCL3, MCL4, MCL5, and MCL6 may extend toward the first to sixth pixels PX1, PX2, PX3, PX4, PX5, and PX6.

[0200] Figure 12 This is an enlarged view of an embodiment according to the present invention. Figure 11 Plan view of area AA'.

[0201] Reference Figure 11 as well as Figure 12 The first to sixth connection wirings CL1, CL2, CL3, CL4, CL5, and CL6 can be electrically connected to the first to sixth clock wirings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6 in a one-to-one correspondence, extending towards the group-level GST.

[0202] Alternatively, carry clock routing CRCKL and clock routing CKLT1 and CKLT2 can be configured in the first non-display area NDA1, and group-level GST can be configured in the fourth non-display area NDA4. The first to sixth connection routings CL1, CL2, CL3, CL4, CL5, and CL6 can have a curved shape in the second non-display area NDA2. Alternatively, the first non-display area NDA1 can be referred to as the first area, the fourth non-display area NDA4 as the second area, and the second non-display area NDA2 as the third area.

[0203] The second non-display area NDA2 may include a first boundary BD1 that is adjacent to the first non-display area NDA1 and extends along the first direction DR1, and a second boundary BD2 that is adjacent to the fourth non-display area NDA4 and extends along the first direction DR1 compared to the first non-display area NDA1.

[0204] The first connection wiring CL1 may include a first input terminal CL1-I overlapping with the first boundary BD1 and a first output terminal CL1-O overlapping with the second boundary BD2. The second connection wiring CL2 may include a second input terminal CL2-I overlapping with the first boundary BD1 and a second output terminal CL2-O overlapping with the second boundary BD2. The third connection wiring CL3 may include a third input terminal CL3-I overlapping with the first boundary BD1 and a third output terminal CL3-O overlapping with the second boundary BD2.

[0205] The fourth connection wiring CL4 may include a fourth input terminal CL4-I overlapping the first boundary BD1 and a fourth output terminal CL4-O overlapping the second boundary BD2. The fifth connection wiring CL5 may include a fifth input terminal CL5-I overlapping the first boundary BD1 and a fifth output terminal CL5-O overlapping the second boundary BD2. The sixth connection wiring CL6 may include a sixth input terminal CL6-I overlapping the first boundary BD1 and a sixth output terminal CL6-O overlapping the second boundary BD2.

[0206] According to one embodiment of the present invention, when viewed in the second direction DR2, at least a portion of the first to sixth input terminals CL1-I, CL2-I, CL3-I, CL4-I, CL4-I, CL5-I and the first to sixth output terminals CL1-O, CL2-O, CL3-O, CL4-O, CL5-O, CL6-O may not be aligned. For example, when viewed in the second direction DR2, the case where the axes extending in the first direction DR1 are in the same position can be defined as aligned, and the case where the positions are different can be defined as not aligned.

[0207] For example, when viewed from the second direction DR2, if the input and output ends are aligned, the number of straight sections extending from the corresponding connection wiring in the first direction DR1 should be even. However, when viewed from the second direction DR2, if the input and output ends are not aligned, the number of straight sections extending from the corresponding connection wiring in the first direction DR1 may also be odd. That is, design freedom can be increased. In addition, since it is not necessary for the number of straight sections to be even, the width of the second direction DR2 of the second non-display area NDA2 can be further reduced.

[0208] According to one embodiment of the present invention, when viewed in the second direction DR2, the third, fourth, fifth, and sixth input terminals CL3-I, CL4-I, CL5-I, and CL6-I, and the third, fourth, fifth, and sixth output terminals CL3-O, CL4-O, CL5-O, and CL6-O are aligned; however, when viewed in the second direction DR2, the first and second input terminals CL1-I and CL2-I, and the first and second output terminals CL1-O and CL2-O, are not aligned. Therefore, the first input terminal CL1-I of the first connecting wiring CL1 that overlaps with the first boundary BD1 and the first output terminal CL1-O of the first connecting wiring CL1 that overlaps with the second boundary BD2 can be non-overlapping in the second direction DR2.

[0209] According to one embodiment of the present invention, the first distance DT1 between the first connecting wire CL1 and the second connecting wire CL2 at the first boundary BD1 can be less than the second distance DT2 between the first connecting wire CL1 and the second connecting wire CL2 at the second boundary BD2.

[0210] According to one embodiment of the present invention, at least one of the first group of connecting wires CLG1 may be aligned at the position of the first boundary BD1 and the position of the second boundary BD2, while at least another of the first group of connecting wires CLG1 may be different from each other at the position of the first boundary BD1 and the position of the second boundary BD2.

[0211] In addition, the first distance DT1 between the first group of connecting wiring CLG1 and the second group of connecting wiring CLG2 at the first boundary BD1 can be less than the second distance DT2 between the first group of connecting wiring CLG1 and the second group of connecting wiring CLG2 at the second boundary BD2.

[0212] The connection wiring connecting the second type level SS-ST and the second type clock wiring CKLT2 can also have a similar layout to the first to sixth connection wirings CL1, CL2, CL3, CL4, CL5, and CL6 in the second non-display area NDA2. That is, according to one embodiment of the present invention, the equal resistance design region of the connection wiring transmitting signals to the first type level SC-ST and the equal resistance design region of the connection wiring transmitting signals to the second type level SS-ST can overlap in the first direction DR1. Therefore, the width of the second direction DR2 of the non-display area NDA can be further reduced.

[0213] Figure 13 This is an enlarged plan view showing a portion of a display panel DP according to an embodiment of the present invention.

[0214] Reference Figure 11 as well as Figure 13 Voltage routing (VL) can be configured in the fifth non-display area NDA5. That is, voltage routing VL can be configured between the group level GST and the first to sixth pixels PX1, PX2, PX3, PX4, PX5, and PX6. Voltage routing VL can be configured with... Figure 6b The fifth input terminal IN5 shown is electrically connected to receive the first low voltage VSS1 (refer to...). Figure 6b However, this is just one example, and voltage wiring VL is not limited to this.

[0215] The first to sixth intermediate connection wirings MCL1, MCL2, MCL3, MCL4, MCL5, and MCL6 can be arranged sequentially along the first direction DR1 in the area overlapping with the voltage wiring VL. That is, the first to sixth intermediate connection wirings MCL1, MCL2, MCL3, MCL4, MCL5, and MCL6 can extend from the first, third, and fifth transistors TC1, TC3, and TC5 and the second, fourth, and sixth transistors TC2, TC4, and TC6 separated by the virtual reference line IL, and correspond to the order of the first to sixth pixels PX1, PX2, PX3, PX4, and PX6.

[0216] The signals output from transistors TC1, TC2, TC3, TC4, TC5, and TC6 (from the first to the sixth pixels) can be output to the first to sixth scan wirings SCL1, SCL2, SCL3, SCL4, SCL5, and SCL6 connected to pixels PX1, PX2, PX3, PX4, PX2, PX5, and PX6. Additionally, the signals output from transistors TS1, TS2, TS3, TS4, TS5, and TS6 (from the first to the sixth pixels) can be output to the first to sixth scan wirings SSL1, SSL2, SSL3, SSL4, SSL5, and SSL6 connected to pixels PX1, PX2, PX3, PX4, PX5, and PX6.

[0217] Figure 14 According to an embodiment of the present invention, along Figure 13 The cross-sectional view of the display panel taken from I-I'. Figure 15 According to an embodiment of the present invention, along Figure 13 The cross-sectional view of the display panel taken from section II-II'.

[0218] Reference Figure 13 , Figure 14 as well as Figure 15 The display panel DP may also include a substrate layer 110 and a circuit layer 120. Figure 13 as well as Figure 14 The structure shown is only a partial representation of the display panel DP. The display panel DP may also include light-emitting elements ED (see reference). Figure 4 The light-emitting element layer and the encapsulation layer covering it.

[0219] The substrate 110 may be a component that provides a substrate surface for configuring the circuit layer 120. The substrate 110 may have a multilayer structure or a single-layer structure. The substrate 110 may be a glass substrate, a metal substrate, a silicon substrate, or a polymer substrate, etc., but is not particularly limited thereto.

[0220] The circuit layer 120 may be disposed on the substrate layer 110. The circuit layer 120 may include a first intermediate insulating layer ILG1, a second intermediate insulating layer ILG2, and a third intermediate insulating layer ILG3. Each of the first intermediate insulating layer ILG1, the second intermediate insulating layer ILG2, and the third intermediate insulating layer ILG3 may include more than one insulating layer, and each of the more than one insulating layer may be an inorganic insulating layer or an organic insulating layer.

[0221] Voltage wiring (VL) can have a multilayer structure consisting of two or more layers. Voltage wiring (VL) may include a first wiring pattern MT1, a second wiring pattern MT2, and a third wiring pattern MT3. The first wiring pattern MT1, the second wiring pattern MT2, and the third wiring pattern MT3 can be electrically connected to each other.

[0222] Reference Figure 14 A first wiring pattern MT1 can be disposed on the substrate layer 110. A first intermediate insulating layer ILG1 can be disposed on the substrate layer 110, covering the first wiring pattern MT1. A second wiring pattern MT2 can be disposed on the first intermediate insulating layer ILG1. A second intermediate insulating layer ILG2 can be disposed on the first intermediate insulating layer ILG1, covering the second wiring pattern MT2. A third wiring pattern MT3 and the first to sixth intermediate connecting wirings MCL1, MCL2, MCL3, MCL4, MCL5, and MCL6 can be disposed on the second intermediate insulating layer ILG2. A third intermediate insulating layer ILG3 can be disposed on the second intermediate insulating layer ILG2, covering the third wiring pattern MT3 and the first to sixth intermediate connecting wirings MCL1, MCL2, MCL3, MCL4, MCL5, and MCL6.

[0223] Reference Figure 13 as well as Figure 14 The first to sixth scan wirings SCL1, SCL2, SCL3, SCL4, SCL5, and SCL6 can be connected one-to-one with the first to sixth intermediate connection wirings MCL1, MCL2, MCL3, MCL4, MCL5, and MCL6 and configured on the same layer as each other.

[0224] Reference Figure 15 From the first transistor TS1 (reference) Figure 13 The intermediate connection wiring MSL can be configured between the second intermediate insulating layer ILG2 and the third intermediate insulating layer ILG3. The first scan wiring SSL1 can be configured on a different layer than the intermediate connection wiring MSL. The intermediate connection wiring MSL can pass through the first intermediate insulating layer ILG1 and the second intermediate insulating layer ILG2 to connect to the first scan wiring SSL1.

[0225] exist Figure 15The example illustrates a first scan routing SSL1 disposed between a first intermediate insulating layer ILG1 and a substrate layer 110, but is not particularly limited thereto. For example, the first scan routing SSL1 may also be disposed between a first intermediate insulating layer ILG1 and a second intermediate insulating layer ILG2.

[0226] Figure 16 This is a plan view of a portion of a display panel DPa according to an embodiment of the present invention. Figure 16 When making an explanation, regarding the relationship with Figure 11 Components that are identical to those described in the figure are marked with the same reference numerals and the description of them is omitted.

[0227] Reference Figure 16 Alternatively, each of the first to sixth clock traces CKL1a, CKL2a, CKL3a, CKL4a, CKL5a, and CKL6a can extend along the first direction DR1, and the first to sixth clock traces CKL1a, CKL2a, CKL3a, CKL4a, CKL5a, and CKL6a can be arranged sequentially along the opposite direction of the second direction DR2. For example, the first to sixth clock traces CKL1a, CKL2a, CKL3a, CKL4a, CKL5a, and CKL6a can be arranged sequentially in a direction away from the group level GST.

[0228] The first transistor TC1a, the third transistor TC3a, and the fifth transistor TC5a can be arranged sequentially toward the first to sixth clock wirings CKL1a, CKL2a, CKL3a, CKL4a, CKL5a, and CKL6a. Similarly, the second transistor TC2a, the fourth transistor TC4a, and the sixth transistor TC6a can also be arranged sequentially toward the first to sixth clock wirings CKL1a, CKL2a, CKL3a, CKL4a, CKL5a, and CKL6a. The first to sixth transistors TS1a, TS2a, TS3a, TS4a, TS5a, and TS6a can also have the same arrangement as the first to sixth transistors TC1a, TC2a, TC3a, TC4a, TC5a, and TC6a.

[0229] The first to sixth connection wirings CL1a, CL2a, CL3a, CL4a, CL5a, and CL6a can be electrically connected to ground in a one-to-one pair with the first to sixth clock wirings CKL1a, CKL2a, CKL3a, CKL4a, CKL5a, and CKL6a, extending towards the group-level GST. Additionally, the first to sixth connection wirings CL1a, CL2a, CL3a, CL4a, CL5a, and CL6a can be electrically connected to ground in a one-to-one correspondence with the first to sixth transistors TC1a, TC2a, TC3a, TC4a, TC5a, and TC6a.

[0230] The first distance DT1a between the fifth connection wiring CL5a and the sixth connection wiring CL6a at the first boundary BD1 can be less than the second distance DT2a between the fifth connection wiring CL5a and the sixth connection wiring CL6a at the second boundary BD2.

[0231] Figure 17 This is a plan view of a portion of a display panel DPb according to an embodiment of the present invention. Figure 17 When making an explanation, regarding the relationship with Figure 11 as well as Figure 16 The same constituent elements described herein shall be marked with the same reference numerals in the accompanying drawings.

[0232] Reference Figure 17 It can be that each of the first to sixth clock wirings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6 extends along the first direction DR1, and the first to sixth clock wirings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6 are arranged sequentially along the second direction DR2.

[0233] The first transistor TC1a, the third transistor TC3a, and the fifth transistor TC5a can be arranged sequentially toward the first to sixth clock wirings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6. Similarly, the second transistor TC2a, the fourth transistor TC4a, and the sixth transistor TC6a can also be arranged sequentially toward the first to sixth clock wirings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6.

[0234] The first to sixth connection wirings CL1b, CL2b, CL3b, CL4b, CL5b, and CL6b can be electrically connected to the first to sixth clock wirings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6 in a one-to-one correspondence, extending towards the group-level GST. Additionally, the first to sixth connection wirings CL1b, CL2b, CL3b, CL4b, CL5b, and CL6b can be electrically connected to the first to sixth transistors TC1a, TC2a, TC3a, TC4a, TC5a, and TC6a in a one-to-one correspondence.

[0235] Compare Figure 16 and Figure 17 , Figure 16 The arrangement direction of the first to sixth clock wirings CKL1a, CKL2a, CKL3a, CKL4a, CKL5a, and CKL6a and Figure 17 The arrangement directions of the first to sixth clock wirings CKL1, CKL2, CKL3, CKL4, CKL5, and CKL6 can be different from each other. At this time, Figure 16 The deviation of the distance DR2 in the second direction between one end and the other end of each of the first to sixth connecting wirings CL1a, CL2a, CL3a, CL4a, CL5a, and CL6a shown can be less than [missing information]. Figure 17 The deviation of the distance DR2 in the second direction between one end and the other end of each of the first to sixth connection wirings CL1b, CL2b, CL3b, CL4b, CL5b, and CL6b shown. One end may correspond to the contact point between the connection wiring and the clock wiring, and the other end may correspond to the contact point between the connection wiring and the transistor. Therefore, according to Figure 16 In the illustrated embodiment, the area of ​​the equal resistance design region, such as the second non-display region NDA2, can be larger than... Figure 17 The area of ​​the equal resistance design region in the illustrated embodiment is further reduced.

[0236] Reference Figure 16 as well as Figure 17 In order to reduce the non-display area NDA (refer to...) Figure 2 The width of the non-display area NDA, for example, the width of the second direction DR2, can be configured with the first to sixth transistors TC1a, TC2a, TC3a, TC4a, TC5a, and TC6a in at least two rows. For example, instead of arranging the first to sixth transistors TC1a, TC2a, TC3a, TC4a, TC5a, and TC6a continuously along one direction, a portion of the first to sixth transistors TC1a, TC2a, TC3a, TC4a, TC5a, and TC6a and the remaining portions of the first to sixth transistors TC1a, TC2a, TC3a, TC4a, TC5a, and TC6a can be arranged facing each other. Therefore, the width of the second direction DR2 of the non-display area NDA can be reduced.

[0237] Furthermore, by configuring the connection routing of adjacent clock lines symmetrically with respect to a virtual reference line IL, equal-resistance design can be simplified. For example, the equal-resistance design layout of the first, third, and fifth connection routings CL1a, CL3a, and CL5a or the first, third, and fifth connection routings CL1b, CL3b, and CL5b can be similar to the symmetrical form of the equal-resistance design layout of the second, fourth, and sixth connection routings CL2a, CL4a, and CL6a or the second, fourth, and sixth connection routings CL2b, CL4b, and CL6b.

[0238] Furthermore, by separately configuring the first to sixth transistors TC1a, TC2a, TC3a, TC4a, TC5a, and TC6a with a virtual reference line IL as the reference, it is applicable to half of the six wirings, i.e., three wirings, such as the first, third, and fifth connection wirings CL1a, CL3a, and CL5a or the first, third, and fifth connection wirings CL1b, CL3b, and CL5b, with equal resistance design. Therefore, the area of ​​the equal resistance design space, such as the width of the second direction DR2, can be reduced.

[0239] Furthermore, the equal resistance design layout of the connection wiring for transmitting signals to the second type-level SS-ST can also be configured in the second non-display area NDA2. Therefore, the equal resistance design area of ​​the connection wiring for transmitting signals to the first type-level SC-ST and the equal resistance design area of ​​the connection wiring for transmitting signals to the second type-level SS-ST can overlap in the first direction DR1. Therefore, the width of the second direction DR2 of the non-display area NDA can be further reduced.

[0240] The above description refers to preferred embodiments of the present invention. However, those skilled in the art or with ordinary knowledge in the art will understand that various modifications and alterations can be made to the present invention without departing from the concept and technical scope of the present invention as set forth in the appended claims. Therefore, the technical scope of the present invention is not limited by the content described in the detailed specification, but rather by the claims.

Claims

1. A display panel, characterized in that, include: Multiple pixels, arranged along a first direction; The stage includes multiple transistors that output multiple scan signals to the multiple pixels; Multiple clock wirings are electrically connected to the stage; as well as Multiple connection lines connect the multiple clock lines and the multiple transistors. The plurality of transistors includes: a plurality of first group transistors, which are connected to the pixel arranged along the first direction at the 2N-1th position among the plurality of pixels, where N is an integer greater than or equal to 1; And a plurality of second-group transistors, connected to the 2Nth pixel among the plurality of pixels arranged along the first direction. The plurality of first groups of transistors and the plurality of second groups of transistors are separated from each other by a virtual reference line extending in a second direction intersecting the first direction.

2. The display panel according to claim 1, characterized in that, The plurality of connection wirings include: a plurality of first group connection wirings connected to the plurality of first group transistors; and a plurality of second group connection wirings connected to the plurality of second group transistors, wherein the plurality of first group connection wirings and the plurality of second group connection wirings are separated from each other by the virtual baseline.

3. The display panel according to claim 2, characterized in that, The display panel defines a first region where the plurality of clock wirings are configured, a second region where the levels are configured, and a third region between the first region and the second region. The plurality of connecting wires have a curved shape in the third region.

4. The display panel according to claim 3, characterized in that, The third region includes: a first boundary adjacent to the first region and extending along the first direction; and a second boundary adjacent to the second region and extending along the first direction. At least one of the first group of connection wirings is aligned at the first boundary and at the second boundary, and at least another of the first group of connection wirings is different from each other at the first boundary and at the second boundary.

5. The display panel according to claim 4, characterized in that, The first distance between the plurality of first group connection wirings and the plurality of second group connection wirings at the first boundary is less than the second distance between the plurality of first group connection wirings and the plurality of second group connection wirings at the second boundary.

6. The display panel according to claim 2, wherein, The plurality of clock wirings, the levels, and the plurality of pixels are arranged sequentially along the second direction. Each of the plurality of clock wirings extends along the first direction, and the plurality of clock wirings are spaced apart along the second direction.

7. The display panel according to claim 6, characterized in that, The plurality of clock wirings includes: a plurality of first group clock wirings electrically connected to the plurality of first group connecting wirings; and a plurality of second group clock wirings electrically connected to the plurality of second group connecting wirings. The plurality of first groups of clock wiring and the plurality of second groups of clock wiring are arranged alternately and repeatedly along the second direction.

8. The display panel according to claim 6, characterized in that, The plurality of clock routings includes a first clock routing, a second clock routing, a third clock routing, a fourth clock routing, a fifth clock routing, and a sixth clock routing. The plurality of transistors includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor that are electrically connected to the first through sixth clock wirings. The plurality of pixels includes a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel, which are arranged sequentially along the first direction and are connected to the first to sixth transistors in a one-to-one correspondence. The first transistor and the second transistor are separated by the virtual reference line, the third transistor and the fourth transistor are separated by the virtual reference line, and the fifth transistor and the sixth transistor are separated by the virtual reference line. The first transistor, the third transistor, and the fifth transistor are arranged sequentially in a direction away from the plurality of clock wirings. The second transistor, the fourth transistor, and the sixth transistor are arranged sequentially in a direction away from the plurality of clock wirings. The spacing between the first transistor and the second transistor is smaller than the spacing between the fifth transistor and the sixth transistor.

9. An electronic device, characterized in that, include: The display panel defines a display area and a non-display area adjacent to the display area. The display panel includes: Multiple pixels are configured in the display area; as well as A level is configured in the non-display area and outputs multiple scan signals to the multiple pixels. The plurality of pixels includes a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel arranged sequentially along a first direction. The stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor that correspond one-to-one with the first pixel, the second pixel, the third pixel, the fourth pixel, the fifth pixel, and the sixth pixel and output the plurality of scan signals. The first transistor and the second transistor face each other in the first direction, the third transistor and the fourth transistor face each other in the first direction, and the fifth transistor and the sixth transistor face each other in the first direction. The third transistor is disposed between the first transistor and the fifth transistor, and the fourth transistor is disposed between the second transistor and the sixth transistor.

10. The electronic device according to claim 9, characterized in that, The display panel also includes: Multiple clock wirings are configured in the non-display area and provide multiple clock signals to the stage; and A first connection wiring, a second connection wiring, a third connection wiring, a fourth connection wiring, a fifth connection wiring, and a sixth connection wiring are configured in the non-display area and are connected one-to-one with the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, and transmit the plurality of clock signals. The first, third, and fifth connection wirings are separated from the second, fourth, and sixth connection wirings by a virtual baseline extending in a second direction.

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