Display panel and display device

Abstract

A display panel and a display device. The display panel comprises: a substrate substrate; pixel circuits are located on the substrate substrate and comprise first pixel circuits and second pixel circuits, each pixel circuit comprises initialization circuit, the initialization circuit is configured to be electrically connected with light emitting element; an electrode layer comprising a plurality of first electrodes electrically connected with a plurality of pixel circuits; a first initialization voltage line comprising a first sub-initialization voltage line and a second sub-initialization voltage line, the first sub-initialization voltage line is electrically connected with the initialization circuit in the first pixel circuit, and the second sub-initialization voltage line is electrically connected with the initialization circuit in the second pixel circuit. At least three layers of conductive layers are arranged between the electrode layer and the substrate substrate, the first sub-initialization voltage line and the second sub-initialization voltage line are respectively located in two layers of conductive layers in the at least three layers of conductive layers, so as to realize the individual reset of the first pixel circuit and the second pixel circuit respectively belonging to different color sub-pixels.

Description

Technical Field

[0001] This disclosure relates to a display panel and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays possess advantages such as self-illumination, high color saturation, and high contrast, making them a core component of next-generation flat panel and flexible display technologies. The tandem structure employed in OLED displays improves the lifespan and brightness of the device while reducing power consumption by adding at least one light-emitting layer and a charge-generating layer. Utility Model Content

[0003] This disclosure provides a display panel and a display device. At least three conductive layers are disposed between the electrode layer and the substrate in the display panel. A first sub-initialization voltage line and a second sub-initialization voltage line are respectively located in two of the at least three conductive layers, thereby enabling individual reset of the first pixel circuit and the second pixel circuit, which belong to different color sub-pixels.

[0004] This disclosure provides a display panel, comprising: a substrate; a plurality of pixel circuits located on the substrate, the plurality of pixel circuits including at least a first pixel circuit and a second pixel circuit, each pixel circuit including an initialization circuit configured to be electrically connected to a light-emitting element; an electrode layer located on the side of the pixel circuits away from the substrate, the electrode layer including a plurality of first electrodes configured to be electrically connected to the plurality of pixel circuits; and a first initialization voltage line located on the substrate, the first initialization voltage line including a first sub-initialization voltage line and a second sub-initialization voltage line, the first sub-initialization voltage line being electrically connected to the initialization circuit in the first pixel circuit, and the second sub-initialization voltage line being electrically connected to the initialization circuit in the second pixel circuit. At least three conductive layers are disposed between the electrode layer and the substrate, the first sub-initialization voltage line and the second sub-initialization voltage line being respectively located in two of the at least three conductive layers.

[0005] For example, according to an embodiment of this disclosure, the plurality of pixel circuits further includes a third pixel circuit, the first initialization voltage line further includes a third sub-initialization voltage line, the third sub-initialization voltage line is electrically connected to the initialization circuit of the third pixel circuit, the third sub-initialization voltage line is located in the at least three conductive layers, and is located in a different layer from the first sub-initialization voltage line and the second sub-initialization voltage line.

[0006] For example, according to an embodiment of this disclosure, at least two of the first sub-initialization voltage line, the second sub-initialization voltage line, and the third sub-initialization voltage line overlap along a direction perpendicular to the substrate.

[0007] For example, according to an embodiment of this disclosure, at least two of the first sub-initialization voltage line, the second sub-initialization voltage line, and the third sub-initialization voltage line have a gap between their orthogonal projections on the substrate.

[0008] For example, according to an embodiment of this disclosure, each pixel circuit includes a plurality of transistors, each transistor including an active layer pattern; the at least three conductive layers include at least one gate conductive layer, the portion of the at least one gate conductive layer overlapping with the active layer pattern serves as the gate of at least some of the transistors; at least one of the first sub-initialization voltage line, the second sub-initialization voltage line and the third sub-initialization voltage line is located in the at least one gate conductive layer.

[0009] For example, according to an embodiment of this disclosure, the at least one gate conductive layer includes at least two gate conductive layers; two of the first sub-initialization voltage line, the second sub-initialization voltage line, and the third sub-initialization voltage line are respectively located in the two gate conductive layers.

[0010] For example, according to an embodiment of this disclosure, the first initialization voltage line, which is located outside the two gate conductive layers, is located between the two gate conductive layers and the electrode layer.

[0011] For example, according to an embodiment of this disclosure, the first pixel circuit, the second pixel circuit, and the third pixel circuit are configured to be electrically connected to three different color light-emitting elements.

[0012] For example, according to an embodiment of this disclosure, one of the first pixel circuit and the second pixel circuit is configured to be electrically connected to two different color light-emitting elements.

[0013] For example, according to an embodiment of this disclosure, each pixel circuit includes a first transistor, a second transistor, a driving transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a capacitor; the gate of the driving transistor is connected to a first node, the first electrode of the driving transistor is connected to a second node, and the second electrode of the driving transistor is connected to a third node; the first electrode of the fourth transistor is connected to a data signal terminal, the second electrode of the fourth transistor is connected to the second node, and the gate of the fourth transistor is connected to a first gate driving signal terminal; the first electrode of the fifth transistor is connected to a first power supply terminal, the second electrode of the fifth transistor is connected to the second node, and the gate of the fifth transistor is connected to an enable signal terminal; the first electrode of the second transistor is connected to the first node, the second electrode of the second transistor is connected to the third node, and the gate of the second transistor is connected to a second gate driving signal terminal. The signal terminals are as follows: the first terminal of the sixth transistor is connected to the third node, the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor, and the gate of the sixth transistor is connected to the enable signal terminal; the first terminal of the first transistor is connected to the first node, the second terminal of the first transistor is connected to the first initial signal terminal, and the gate of the first transistor is connected to the first reset signal terminal; the second terminal of the seventh transistor is connected to the second initial signal terminal, and the gate of the seventh transistor is connected to the second reset signal terminal; the initialization circuit includes the seventh transistor, and the first initialization voltage line is electrically connected to the second initial signal terminal; the gate of the eighth transistor is connected to the second reset signal terminal, the first terminal of the eighth transistor is connected to the third initial signal terminal, and the second terminal of the eighth transistor is connected to the second node; the capacitor is connected between the first power supply terminal and the first node.

[0014] For example, according to an embodiment of this disclosure, the display panel further includes: a first active layer located between the electrode layer and the substrate, wherein at least one of the at least three conductive layers is located between the first active layer and the electrode layer. The first active layer includes active layer patterns of the first transistor and the second transistor, wherein the active layer patterns of the first transistor and the second transistor in the same pixel circuit are integrally formed.

[0015] For example, according to an embodiment of this disclosure, the display panel further includes: a first active layer located between the electrode layer and the substrate, wherein at least one of the at least three conductive layers is located between the first active layer and the electrode layer. The first active layer includes a first active layer pattern of the first transistor and a second active layer pattern of the second transistor. In the same pixel circuit, the first active layer pattern and the second active layer pattern are connected through at least one of the at least three conductive layers.

[0016] For example, according to an embodiment of this disclosure, the display panel further includes: a second active layer located between the at least three conductive layers and the substrate. Each pixel circuit includes a plurality of transistors, and the second active layer includes an active layer pattern of at least a portion of the plurality of transistors; the plurality of pixel circuits are arranged in an array along a first direction and a second direction, at least one of the first initialization voltage lines extends along the first direction, and the first direction intersects the second direction; two adjacent pixel circuits arranged along the first direction include a first specific pixel circuit and a second specific pixel circuit, and the active layer patterns of the first specific pixel circuit and the second specific pixel circuit are symmetrically distributed with respect to a centerline extending along the second direction.

[0017] For example, according to an embodiment of this disclosure, the display panel further includes: a plurality of auxiliary signal lines extending along the second direction and located on the side of the first initialization voltage line away from the substrate. At least a portion of the auxiliary signal lines have their orthographic projections on the plane containing the second active layer located at the center line, and at least one of the at least a portion of the auxiliary signal lines is electrically connected to the first initialization voltage line.

[0018] For example, according to an embodiment of this disclosure, the display panel further includes: a plurality of auxiliary signal lines extending along the second direction and located on the side of the first initialization voltage line away from the substrate; a first power signal line located in one of the at least three conductive layers, at least a portion of the first power signal line extending along the first direction; a second initialization voltage line disposed in the same layer as the first power signal line and extending along the first direction; and a third initialization voltage line disposed in the same layer as the first power signal line and extending along the first direction. The orthographic projection of at least a portion of the auxiliary signal lines onto the plane containing the active layer is located at the center line, and the at least a portion of the auxiliary signal lines are electrically connected to at least one of the first initialization voltage line, the second initialization voltage line, the third initialization voltage line, and the first power signal line.

[0019] For example, according to an embodiment of this disclosure, the plurality of pixel circuits are divided into a plurality of pixel circuit groups, each pixel circuit group including four pixel circuits arranged along the first direction, two of the four pixel circuits being configured to be electrically connected to a first color light-emitting element, and the other two of the four pixel circuits being configured to be electrically connected to a second color light-emitting element and a third color light-emitting element, respectively.

[0020] For example, according to an embodiment of this disclosure, the four pixel circuits include a first sub-pixel circuit, a second sub-pixel circuit, a third sub-pixel circuit, and a fourth sub-pixel circuit arranged in sequence. The first sub-pixel circuit is electrically connected to the second color light-emitting element, the second sub-pixel circuit is electrically connected to the first color light-emitting element, the third sub-pixel circuit is electrically connected to the third color light-emitting element, and the fourth sub-pixel circuit is electrically connected to the first color light-emitting element.

[0021] For example, according to an embodiment of this disclosure, the active layer pattern of the first sub-pixel circuit and the active layer pattern of the second sub-pixel circuit are symmetrically distributed with respect to a center line extending along the second direction between them, and the active layer pattern of the third sub-pixel circuit and the active layer pattern of the fourth sub-pixel circuit are symmetrically distributed with respect to a center line extending along the second direction between them.

[0022] For example, according to an embodiment of this disclosure, the display panel further includes: an isolation structure located on the side of the at least three conductive layers away from the substrate. The display panel includes a plurality of sub-pixels, each sub-pixel including the pixel circuit and a light-emitting element electrically connected to the pixel circuit. The light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode stacked together. The electrode layer includes the first electrode of each of the plurality of sub-pixels, the first electrode being located between the light-emitting functional layer and the substrate, and the first electrode being electrically connected to the pixel circuit. The plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit including two first-color sub-pixels, one second-color sub-pixel, and one third-color sub-pixel. The isolation structure is located at least between the light-emitting areas of the first-color sub-pixels and the third-color sub-pixels, and is configured to isolate at least a portion of the light-emitting functional layer.

[0023] For example, according to an embodiment of this disclosure, the display panel further includes: a spacer located on the side of the light-emitting functional layer away from the substrate. The plurality of sub-pixels include a first pixel group and a second pixel group arranged along a first direction, the first pixel group and the second pixel group being staggered along a second direction, the first direction intersecting the second direction; the first pixel group includes second color sub-pixels and the third color sub-pixels alternately arranged along the second direction, the second pixel group includes first color sub-pixels arranged along the second direction; the spacer includes at least a sub-spacer located between the light-emitting area of ​​the second color sub-pixel and at least one of the light-emitting areas of the third color sub-pixel and the light-emitting area of ​​the first color sub-pixel, and the spacer does not overlap with the isolation structure in a direction perpendicular to the substrate.

[0024] For example, according to an embodiment of this disclosure, the display panel further includes: spacers located on the side of the light-emitting functional layer away from the substrate. The plurality of sub-pixels include a first pixel group and a second pixel group arranged along a first direction, the first pixel group and the second pixel group being staggered along a second direction, the first direction intersecting the second direction; the first pixel group includes second color sub-pixels and third color sub-pixels alternately arranged along the second direction, the second pixel group includes first color sub-pixels arranged along the second direction; the spacers include a plurality of sub-spacers, the two sub-spacers closest to the light-emitting area of ​​the same first color sub-pixel being symmetrically distributed with respect to the line connecting the center of the light-emitting area of ​​the first color sub-pixel and the center of the light-emitting area of ​​its adjacent second color sub-pixel or third color sub-pixel.

[0025] For example, according to an embodiment of this disclosure, the isolation structure includes a plurality of sub-isolation structures, and at least one sub-isolation structure is provided between the first color sub-pixel and the third color sub-pixel.

[0026] For example, according to an embodiment of this disclosure, the display panel further includes: a metal layer located between the electrode layer and the at least three conductive layers. The first electrode includes a main electrode and a connecting electrode, the connecting electrode being electrically connected to the pixel circuit; the metal layer includes a first power signal line connecting line and a transition portion, the first power signal line connecting line extending along a second direction, the first power signal line connecting line forming an opening, the transition portion being disposed within the opening; the connecting electrode of at least one color sub-pixel among the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is electrically connected to a transistor in the pixel circuit through the transition portion; in the extending direction of the connecting electrode, the size ratio of the connecting electrode to the main electrode is 0.3 to 0.6.

[0027] For example, according to an embodiment of this disclosure, the connection electrode of the first color sub-pixel extends along the second direction, and the connection electrodes of the second color sub-pixel and the third color sub-pixel extend along the first direction; along the second direction, the size ratio of the connection electrode of the first color sub-pixel to the corresponding opening is 0.25 to 0.35; along the first direction, the size ratio of the connection electrode of the second color sub-pixel to the corresponding opening is 0.45 to 0.65, and the size ratio of the connection electrode of the third color sub-pixel to the corresponding opening is 0.45 to 0.65.

[0028] For example, according to an embodiment of this disclosure, the connection electrode of the first color sub-pixel extends along the first direction, and the connection electrodes of the second color sub-pixel and the third color sub-pixel extend along the second direction; along the first direction, the size ratio of the connection electrode of the first color sub-pixel to the corresponding opening is 0.35 to 0.45; along the second direction, the size ratio of the connection electrode of the second color sub-pixel to the corresponding opening is 0.25 to 0.40, and the size ratio of the connection electrode of the third color sub-pixel to the corresponding opening is 0.25 to 0.40.

[0029] For example, according to an embodiment of this disclosure, the display panel further includes: a metal layer located between the electrode layer and the at least three conductive layers. The first electrode includes a main electrode and a connecting electrode, the connecting electrode being electrically connected to the pixel circuit; the metal layer includes a first power signal line connecting line and a transition portion, the first power signal line connecting line extending along a second direction, the first power signal line connecting line forming an opening, and the transition portion being disposed within the opening; the connecting electrode of at least one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is electrically connected to a transistor in the pixel circuit through the transition portion; the connecting electrode of the first color sub-pixel extends along the second direction, and along the second direction, the size ratio of the connecting electrode of the first color sub-pixel to the corresponding transition portion is 1.1 to 1.4; the connecting electrodes of the second color sub-pixel and the third color sub-pixel extend along the first direction, and along the first direction, the size ratio of the connecting electrode of the second color sub-pixel to the corresponding transition portion is 1.1 to 1.4, and the size ratio of the connecting electrode of the third color sub-pixel to the corresponding transition portion is 1.1 to 1.4.

[0030] For example, according to an embodiment of this disclosure, the adapter portion connected to the connection electrode of the first color sub-pixel extends along the first direction; the first power signal line connection includes two strip portions surrounding the opening and extending along the second direction, the connection electrode of the first color sub-pixel overlaps with one of the two strip portions; the width of the strip portion overlapping the connection electrode of the first color sub-pixel is less than the width of the other of the two strip portions, or the widths of the two strip portions are the same; in the first direction, the ratio of the width of the strip portion overlapping the connection electrode of the first color sub-pixel to the size of the opening is 0.15 to 0.25.

[0031] For example, according to an embodiment of this disclosure, the opening includes a partition extending along the second direction; the at least one color sub-pixel includes two different color sub-pixels, and two transition portions connected to the connection electrodes of the two different color sub-pixels are both located within the opening and are respectively located on both sides of the partition, and the two transition portions extend in different directions; the first power signal line connection includes two strip portions surrounding the opening and extending along the second direction, and in the first direction, the ratio of the width of at least one of the two strip portions to the size of the opening is 0.15 to 0.25.

[0032] For example, according to an embodiment of this disclosure, the display panel further includes: a metal layer located between the electrode layer and the at least three conductive layers. The first electrode includes a main electrode and a connecting electrode, the connecting electrode being electrically connected to the pixel circuit; the metal layer includes a first power signal line connecting line and a transition portion, the first power signal line connecting line extending along a second direction, the first power signal line connecting line including a transmission portion and a strip-shaped connecting portion located between adjacent transmission portions, the width of the strip-shaped connecting portion being smaller than the width of the transmission portion; the transition portion is disposed between adjacent transmission portions, the transition portion being located on at least one side of the strip-shaped connecting portion; the connecting electrode of at least one color sub-pixel among the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is electrically connected to a transistor in the pixel circuit through the transition portion.

[0033] For example, according to an embodiment of this disclosure, two types of transition portions are provided on both sides of the strip-shaped connecting portion. The two types of transition portions extend in different directions and are configured to be electrically connected to the connecting electrodes of two different color sub-pixels.

[0034] For example, according to an embodiment of this disclosure, the connection electrode of the at least one color sub-pixel does not overlap with the isolation structure along a direction perpendicular to the substrate.

[0035] For example, according to an embodiment of this disclosure, in a direction perpendicular to the substrate, the connection electrodes of at least two color sub-pixels do not overlap with the isolation structure.

[0036] For example, according to an embodiment of this disclosure, the connection electrodes of each color sub-pixel do not overlap with the isolation structure along a direction perpendicular to the substrate.

[0037] For example, according to an embodiment of this disclosure, the area of ​​the main electrode of the third color sub-pixel is larger than the area of ​​the main electrodes of the other color sub-pixels, and the length of the connecting electrode of the third color sub-pixel is shorter than that of the connecting electrodes of the other color sub-pixels; the connecting electrode of the third color sub-pixel does not overlap with the isolation structure along a direction perpendicular to the substrate.

[0038] For example, according to an embodiment of this disclosure, along a direction perpendicular to the substrate, the connection electrode of at least one color sub-pixel other than the third color sub-pixel overlaps with the isolation structure.

[0039] For example, according to an embodiment of this disclosure, the display panel includes a plurality of sub-pixels, each sub-pixel including the pixel circuit and a light-emitting element electrically connected to the pixel circuit. The light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode stacked together. The electrode layer includes the first electrode in each of the plurality of sub-pixels. The first electrode is located between the light-emitting functional layer and the substrate, and the first electrode is electrically connected to the pixel circuit. The second electrode includes a first sub-layer and a second sub-layer stacked together. The second sub-layer is located between the first sub-layer and the second electrode. The material of the first sub-layer includes silver, and the material of the second sub-layer includes a transparent metal oxide.

[0040] For example, according to embodiments of this disclosure, the transparent metal oxide includes indium zinc oxide.

[0041] For example, according to an embodiment of this disclosure, the plurality of sub-pixels includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; the number of light-emitting layers included in the light-emitting functional layer of the third color sub-pixel is not less than the number of light-emitting layers included in the light-emitting functional layers of the other color sub-pixels.

[0042] For example, according to an embodiment of this disclosure, the display panel further includes: an optical coupling output layer located on the side of the second electrode away from the light-emitting functional layer. The optical coupling output layer includes a first optical coupling output layer and a second optical coupling output layer stacked together, the first optical coupling output layer being located between the second optical coupling output layer and the second electrode, and the refractive index of the first optical coupling output layer being greater than the refractive index of the second optical coupling output layer.

[0043] For example, according to an embodiment of this disclosure, the display panel further includes: an encapsulation layer located on the side of the second electrode away from the light-emitting functional layer. The encapsulation layer includes a first encapsulation layer and a second encapsulation layer stacked together, the second encapsulation layer being located on the side of the first encapsulation layer away from the second electrode, and the density of the first encapsulation layer being higher than the density of the second encapsulation layer.

[0044] For example, according to an embodiment of this disclosure, the light-emitting functional layer includes a first light-emitting unit and a second light-emitting unit stacked together. The first light-emitting unit is located between the second light-emitting unit and the first electrode. The first light-emitting unit includes at least one light-emitting layer, and the second light-emitting unit includes at least one light-emitting layer. The light-emitting functional layer includes a first charge-generating layer and a second charge-generating layer stacked together between the first light-emitting unit and the second light-emitting unit. The first charge-generating layer is located between the second charge-generating layer and the substrate. The distance between the first light-emitting unit and the first electrode is a first distance L1. The distance between the interface between the first charge-generating layer and the second charge-generating layer and the first light-emitting unit is a second distance L2. The distance between the interface and the second light-emitting unit is a third distance L3. The distance between the second light-emitting unit and the second electrode is a fourth distance L4. The second distance L2 of each color sub-pixel is equal, and the fourth distance L4 of each color sub-pixel is equal.

[0045] For example, according to an embodiment of this disclosure, in the second color sub-pixel, the second distance L2 and the first distance L1 satisfy: 0.3≤L2 / L1≤0.5; in the first color sub-pixel, the second distance L2 and the first distance L1 satisfy: 0.5≤L2 / L1≤0.7; and in the third color sub-pixel, the second distance L2 and the first distance L1 satisfy: 0.6≤L2 / L1≤0.8.

[0046] For example, according to an embodiment of this disclosure, the distance between the distant surfaces of the first light-emitting unit is a fifth distance L5, where the fifth distance is the thickness of the first light-emitting unit. In the second color sub-pixel, the fifth distance L5 satisfies: 40 nm ≤ L5 ≤ 50 nm; in the first color sub-pixel, the fifth distance L5 satisfies: 30 nm ≤ L5 ≤ 40 nm; and in the third color sub-pixel, the fifth distance L5 satisfies: 15 nm ≤ L5 ≤ 25 nm.

[0047] For example, according to an embodiment of this disclosure, the distance between the mutually distant surfaces of the second light-emitting unit is a sixth distance L6, where the sixth distance is the thickness of the second light-emitting unit. In the second color sub-pixel, the sixth distance L6 satisfies: 40 nm ≤ L6 ≤ 50 nm; in the first color sub-pixel, the sixth distance L6 satisfies: 30 nm ≤ L6 ≤ 40 nm; and in the third color sub-pixel, the sixth distance L6 satisfies: 15 nm ≤ L6 ≤ 25 nm.

[0048] For example, according to an embodiment of this disclosure, the distance between the first electrode and the second electrode is an eighth distance L. In the second color sub-pixel, the fourth distance L4 and the eighth distance L satisfy: 0.10≤L4 / L≤0.15; in the first color sub-pixel, the fourth distance L4 and the eighth distance L satisfy: 0.14≤L4 / L≤0.19; in the third color sub-pixel, the fourth distance L4 and the eighth distance L satisfy: 0.17≤L4 / L≤0.22.

[0049] For example, according to an embodiment of this disclosure, the distance between the second electrode and the first light-emitting unit is a seventh distance L7, and the distance between the first electrode and the second electrode is an eighth distance L. In the second color sub-pixel, the seventh distance L7 and the eighth distance L satisfy: 0.60≤L7 / L≤0.66; in the first color sub-pixel, the seventh distance L7 and the eighth distance L satisfy: 0.63≤L7 / L≤0.70; and in the third color sub-pixel, the seventh distance L7 and the eighth distance L satisfy: 0.67≤L7 / L≤0.73.

[0050] Another embodiment of this disclosure provides a display device including any of the above-described display panels. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0052] Figure 1 This is a partial structural schematic diagram of a display panel provided according to an example embodiment of the present disclosure.

[0053] Figure 2 for Figure 1 The diagram shows the equivalent circuit of the pixel circuit in the display panel and the schematic diagram of its connection to the light-emitting elements.

[0054] Figure 3 This is a partial planar structural diagram of the second active layer in the display panel.

[0055] Figures 4 to 6 This is a partial structural diagram of the three-layer gate conductive layer in a display panel.

[0056] Figure 7 This is a schematic diagram of a via in an interlayer insulation layer.

[0057] Figure 8 This is a schematic diagram of the first active layer.

[0058] Figure 9 This is a schematic diagram of a via in a planarization layer.

[0059] Figure 10 and Figure 11 This is a schematic diagram of the two source / drain metal layers in the display panel.

[0060] Figure 12A This is a schematic diagram of the light-shielding layer in the display panel.

[0061] Figure 12B This is a schematic diagram of the stacking of at least some of the film layers included in the display panel.

[0062] Figure 13 This is a partial structural schematic diagram of a display panel provided according to another example of an embodiment of the present disclosure.

[0063] Figure 14 for Figure 13 A schematic diagram of the third gate conductive layer in the display panel shown.

[0064] Figure 15 This is a partial structural schematic diagram of a display panel provided according to another example of an embodiment of the present disclosure.

[0065] Figure 16 This is a partial structural schematic diagram of a display panel provided according to another example of an embodiment of the present disclosure.

[0066] Figures 17 to 25 for Figure 16 The diagram shows the film layers of the pixel circuit in the display panel.

[0067] Figure 26 for Figure 16 The diagram shows the overlapping relationship between the second active layer and the first electrode in the pixel circuit group of the display panel.

[0068] Figure 27 This is a schematic diagram of a partial planar structure in a display panel provided according to another example of an embodiment of the present disclosure.

[0069] Figure 28 For along Figure 27 A schematic diagram of the local cross-section structure intercepted by line AA'.

[0070] Figure 29A and Figure 29B This is a schematic diagram illustrating the relative positional relationship between a pixel unit and an isolation structure, provided according to different examples of embodiments of this disclosure.

[0071] Figure 30 For along Figure 29A The diagram shows a partial cross-sectional structure cut by the BB' line in the display panel.

[0072] Figures 31 to 38This is a schematic diagram showing the relative positional relationship between the first electrode of at least one color sub-pixel, the pixel circuit, and the signal lines in different examples.

[0073] Figure 39 and Figure 40 This is a schematic diagram showing the relative positional relationship between the first electrode of each color sub-pixel and a portion of the structure in the metal layer in different examples.

[0074] Figures 41 to 45 This is a schematic diagram illustrating the relative positional relationship of the light-emitting area, isolation structure, and spacer of a sub-pixel according to different examples of embodiments of this disclosure.

[0075] Figures 46A to 46B This is a schematic diagram showing the relative positional relationship of the light-emitting area, isolation structure, and third power signal line of a sub-pixel provided in different examples of embodiments of this disclosure.

[0076] Figure 47 and Figure 48 This is a schematic diagram illustrating the layering relationship of some film layers in a display panel provided according to different examples of embodiments of the present disclosure.

[0077] Figure 49 This is a schematic diagram of the layering relationship of some film layers in a display panel provided according to another example of an embodiment of the present disclosure.

[0078] Figure 50 for Figure 49 A schematic diagram showing the thickness of at least a portion of the film layers in the structure shown.

[0079] Figures 51 to 53 This is a schematic diagram illustrating the layering relationship of some film layers in a display panel provided according to different examples of embodiments of the present disclosure.

[0080] Figure 54 This is a schematic block diagram of a display device provided according to another embodiment of the present disclosure. Detailed Implementation

[0081] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0082] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0083] Unless otherwise specified in the following embodiments of this disclosure, the quantity of a component is implied to mean that the component may be one or more, or can be understood as at least one. "At least one" means one or more, and "more" means at least two.

[0084] This disclosure provides a display panel and a display device. The display panel includes: a substrate; a plurality of pixel circuits located on the substrate, the plurality of pixel circuits including at least a first pixel circuit and a second pixel circuit, each pixel circuit including an initialization circuit configured to be electrically connected to a light-emitting element; an electrode layer located on the side of the pixel circuits away from the substrate, the electrode layer including a plurality of first electrodes configured to be electrically connected to the plurality of pixel circuits; and a first initialization voltage line located on the substrate, the first initialization voltage line including a first sub-initialization voltage line and a second sub-initialization voltage line, the first sub-initialization voltage line being electrically connected to the initialization circuit in the first pixel circuit, and the second sub-initialization voltage line being electrically connected to the initialization circuit in the second pixel circuit. At least three conductive layers are disposed between the electrode layer and the substrate, the first sub-initialization voltage line and the second sub-initialization voltage line being respectively located in two of the at least three conductive layers.

[0085] By placing the first sub-initialization voltage line and the second sub-initialization voltage line in different conductive layers, it is possible to reset the first pixel circuit and the second pixel circuit, which belong to different color sub-pixels, separately.

[0086] The display panel and display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

[0087] Figure 1 This is a partial structural schematic diagram of a display panel provided according to an example embodiment of the present disclosure. Figure 2 for Figure 1 The diagram shows the equivalent circuit of the pixel circuit in the display panel and the schematic diagram of its connection to the light-emitting elements. Figures 3 to 12A for Figure 1 The diagram shows the layers where the pixel circuits are located in the display panel.

[0088] like Figure 1 and Figure 2 As shown, a display panel includes a substrate 01 and a plurality of pixel circuits 100, an electrode layer 2100, and a first initialization voltage line Init2 located on the substrate 01. The plurality of pixel circuits 100 include at least a first pixel circuit 110 and a second pixel circuit 120, and each pixel circuit 100 includes an initialization circuit 101 configured to be electrically connected to a light-emitting element 200.

[0089] For example, such as Figure 2 As shown, the pixel circuit 100 can be an 8T1C (i.e., eight transistors and one capacitor) pixel circuit. For example, the initialization circuit 101 includes at least one transistor, such as a seventh transistor T7. For example, under the control of the scan signal, the initialization circuit 101 writes the initial voltage provided by the initial voltage terminal Vinit2 into the light-emitting element 200.

[0090] like Figure 1 As shown, the electrode layer 2100 is located on the side of the pixel circuit 100 away from the substrate 01. The electrode layer 2100 includes a plurality of first electrodes 210, which are configured to be electrically connected to the plurality of pixel circuits 100. For example, Figure 1 The diagram schematically illustrates a pixel circuit 100 electrically connected to a first electrode 210, but is not limited thereto; the same pixel circuit 100 may be electrically connected to multiple first electrodes 210. For example, the electrode layer 2100 may be an anode layer, and the first electrode 210 may be the anode of a sub-pixel. For example, the first pixel circuit 110 and the second pixel circuit 120 may be configured to be electrically connected to light-emitting elements 200 of different colors, such as when a display panel includes sub-pixels of different colors, and the first pixel circuit 110 and the second pixel circuit 120 are pixel circuits within the sub-pixels of different colors. For example, the sub-pixels of different colors may include red sub-pixels, green sub-pixels, and blue sub-pixels. Figure 1 The schematic diagram shows that the shape of the main electrode 211 overlapping the light-emitting area in the first electrode 210 can be circular, but it is not limited to this. The shape of the first electrode 210 can also be other shapes, such as polygons. For example, Figure 1 The schematic diagram shows that the connecting electrodes 212 of the first electrode 210, which are electrically connected to the first pixel circuit 110 and the second pixel circuit 120 respectively, are all located on the same side of the main electrode 211. However, this is not a limitation; the connecting electrodes 212 of the first electrode 210, which are electrically connected to the first pixel circuit 110 and the second pixel circuit 120 respectively, can be located on different sides of the corresponding main electrode 211, as described later. Figure 26 As shown.

[0091] like Figure 1As shown, the first initialization voltage line Init2 is located on the substrate 01. The first initialization voltage line Init2 includes a first sub-initialization voltage line 311 and a second sub-initialization voltage line 312. The first sub-initialization voltage line 311 is electrically connected to the initialization circuit 101 in the first pixel circuit 110, and the second sub-initialization voltage line 312 is electrically connected to the initialization circuit 101 in the second pixel circuit 120. For example, the first sub-initialization voltage line 311 and the second sub-initialization voltage line 312 can be two voltage lines arranged in parallel, such as the first sub-initialization voltage line 311 and the second sub-initialization voltage line 312 both extending along the X direction.

[0092] like Figure 1 As shown, at least three conductive layers are disposed between the electrode layer 2100 and the substrate 01, and the first sub-initialization voltage line 311 and the second sub-initialization voltage line 312 are respectively located in two of the at least three conductive layers.

[0093] Since the activation voltages of the sub-pixels corresponding to the first pixel circuit 110 and the second pixel circuit 120 are different, by setting the first sub-initialization voltage line 311 and the second sub-initialization voltage line 312 in different conductive layers, the first pixel circuit 110 and the second pixel circuit 120 belonging to different color sub-pixels can be reset separately. This can optimize the voltage across VDD-VSS in different colors, thereby reducing power consumption and heat generation.

[0094] For example, such as Figure 1 As shown, the first sub-initialization voltage line 311 and the second sub-initialization voltage line 312 overlap along a direction perpendicular to the substrate 01, which helps to save layout space. For example, the first sub-initialization voltage line 311 and the second sub-initialization voltage line 312 partially overlap or almost completely overlap. However, this is not the only possibility; in other examples, the first sub-initialization voltage line 311 and the second sub-initialization voltage line 312 may not overlap along a direction perpendicular to the substrate 01.

[0095] In some examples, such as Figure 1 As shown, one of the first pixel circuit 110 and the second pixel circuit 120 is configured to be electrically connected to two different color light-emitting elements.

[0096] When the display panel includes three different colored light-emitting elements, one of the first pixel circuit 110 and the second pixel circuit 120 is electrically connected to the two different colored light-emitting elements, and the other of the first pixel circuit 110 and the second pixel circuit 120 is electrically connected to the one colored light-emitting element. This allows the first sub-initialization voltage line 311 and the second sub-initialization voltage line 312 to connect the three different colored sub-pixels. This not only achieves the individual reset of some different colored sub-pixels, but also helps to save layout space.

[0097] For example, such as Figure 1 As shown, in one of the pixel circuits, the first pixel circuit 110 and the second pixel circuit 120, a portion of the pixel circuit is configured to be electrically connected to a green light-emitting element, and another portion of the pixel circuit is configured to be electrically connected to a blue light-emitting element. The other pixel circuit in the first pixel circuit 110 and the second pixel circuit 120 is configured to be electrically connected to a red light-emitting element. For example, there are multiple first pixel circuits 110, some of which are electrically connected to the green light-emitting element, and another portion of which are electrically connected to the blue light-emitting element. Thus, the pixel circuits connected to both the green and blue light-emitting elements are electrically connected to a first sub-initialization voltage line, which resets the green and blue sub-pixels. The second pixel circuit 120 is electrically connected to only one color light-emitting element, such as a red light-emitting element, thereby resetting the red sub-pixel via the second sub-initialization voltage line.

[0098] This disclosure is not limited to the embodiments described herein. In other examples, the pixel circuits connected to both the red and blue light-emitting elements are electrically connected to a first sub-initialization voltage line, which resets both the red and blue sub-pixels. The second pixel circuit is electrically connected to only one color light-emitting element, such as a green light-emitting element, thereby resetting the green sub-pixel. In other examples, the pixel circuits connected to both the red and green light-emitting elements are electrically connected to a first sub-initialization voltage line, which resets both the red and green sub-pixels. The second pixel circuit is electrically connected to only one color light-emitting element, such as a blue light-emitting element, thereby resetting the blue sub-pixel.

[0099] In some examples, such as Figure 2As shown, each pixel circuit includes a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. The gate of the driving transistor T3 is connected to the first node N1, the first terminal of the driving transistor T3 is connected to the second node N2, and the second terminal of the driving transistor T3 is connected to the third node N3. The first terminal of the fourth transistor T4 is connected to the data signal terminal Data, the second terminal of the fourth transistor T4 is connected to the second node N2, and the gate of the fourth transistor T4 is connected to the first gate driving signal terminal P-Gate. The first terminal of the fifth transistor T5 is connected to the first power supply terminal VDD, the second terminal of the fifth transistor T5 is connected to the second node N2, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM. The first terminal of the second transistor T2 is connected to the first node N1. The second transistor T2 has its second terminal connected to the third node N3, and its gate connected to the second gate drive signal terminal N-Gate. The sixth transistor T6 has its first terminal connected to the third node N3, its second terminal connected to the first terminal of the seventh transistor T7, and its gate connected to the enable signal terminal EM. The first transistor T1 has its first terminal connected to the first node N1, its second terminal connected to the first initial signal terminal Vinit1, and its gate connected to the first reset signal terminal N-Reset. The seventh transistor T7 has its second terminal connected to the second initial signal terminal Vinit2, and its gate connected to the second reset signal terminal P-Reset. The initialization circuit 101 includes the seventh transistor T7, and the first initialization voltage line Init2 is electrically connected to the second initial signal terminal Vinit2. The eighth transistor T8 has its gate connected to the second reset signal terminal P-Reset, its first terminal connected to the third initial signal terminal Vinit3, and its second terminal connected to the second node N2. Capacitor C is connected between the first power supply terminal VDD and the first node N1.

[0100] Figure 3 This is a partial planar structural diagram of the second active layer in the display panel.

[0101] For example, such as Figure 3 As shown, the second active layer 410 can be formed by patterning semiconductor material. The second active layer 410 can be used to fabricate the active layer patterns of the aforementioned driving transistors T3, T4, T5, T6, T7, and T8. The second active layer 410 includes the active layer pattern (channel region) and doped region pattern (source / drain doped region) of the aforementioned transistors, and the active layer pattern and doped region pattern of the driving transistors T3, T4, T5, T6, and T7 in the same pixel circuit are integrally formed.

[0102] For example, the second active layer 410 may include a low-temperature polycrystalline silicon layer, and the source and drain regions can be conductiveized through doping to achieve electrical connections between the various structures. That is, the active layer of some of the transistors can be a monolithic pattern formed of p-silicon, and the transistors in the same pixel circuit include a doped region pattern (i.e., source and drain regions) and an active layer pattern, with the active layers of different transistors separated by doped structures. For example, the second active layer 410 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. For example, the source and drain regions can be regions doped with n-type or p-type impurities.

[0103] Figures 4 to 6 This is a partial structural diagram of the three-layer gate conductive layer in a display panel.

[0104] For example, such as Figures 4 to 6 The schematic illustration shows a display panel comprising three gate conductive layers 400, such as a first gate conductive layer 421, a second gate conductive layer 422, and a third gate conductive layer 423. However, it is not limited to this; in other examples, the display panel may include at least one gate conductive layer 400, such as one gate conductive layer, two gate conductive layers, or more gate conductive layers.

[0105] In some examples, such as Figures 1 to 6 As shown, each pixel circuit 100 includes a plurality of transistors, each transistor including an active layer pattern; at least three conductive layers include at least one gate conductive layer, the portion of the at least one gate conductive layer overlapping with the active layer pattern serving as the gate of at least a portion of the transistors.

[0106] For example, such as Figures 1 to 4 As shown, the light-emitting control signal line EM1 in the first gate conductive layer 421 is electrically connected to the enable signal terminal EM, and the overlapping portion of the light-emitting control signal line EM1 and the second active layer 410 are the gates of the fifth transistor T5 and the sixth transistor T6, respectively. For example, the overlapping portion of the capacitor plate C01 in the first gate conductive layer 421 and the second active layer 410 is the gate of the driving transistor T3. For example, the reset control signal line Reset2 in the first gate conductive layer 421 is electrically connected to the second reset signal terminal P-Reset, and the overlapping portion of the reset control signal line Reset2 and the second active layer 410 are the gates of the seventh transistor T7 and the eighth transistor T8, respectively. For example, the conductive portion L1 in the first gate conductive layer 421 is electrically connected to the first gate driving signal terminal P-Gate, and the overlapping portion of the conductive portion L1 and the second active layer 410 is the gate of the fourth transistor T4.

[0107] For example, such as Figure 4As shown, the light-emitting control signal line EM1 and the reset control signal line Reset2 extend along the X direction, and the conductive part L1 and the capacitor plate C01 are located on the side of the light-emitting control signal line EM1 away from the reset control signal line Reset2. For example, the capacitor plate C01 is located between the conductive part L1 and the light-emitting control signal line EM1.

[0108] For example, such as Figures 1 to 3 , Figure 5 As shown, the power signal line VDD in the second gate conductive layer 422, such as the second power signal line 522, is electrically connected to the first power terminal VDD. The second gate conductive layer 422 includes a first initialization voltage line Init2, such as a second sub-initialization voltage line 312, which is connected to the second terminal of the seventh transistor T7 of the second pixel circuit 120. For example, the second gate conductive layer 422 includes conductive portions L2, L3, and L4. For example, the second gate conductive layer 422 also includes a repair line Rep, which is connected to the anode. If a sub-pixel has a process problem before leaving the factory, an additional voltage can be applied to the sub-pixel through the repair line Rep to make the sub-pixel a dark spot.

[0109] For example, such as Figure 5 As shown, the second power signal line 522, the repair line Rep, and the second sub-initialization voltage line 312 all extend along the X direction, with the repair line Rep located between the second power signal line 522 and the second sub-initialization voltage line 312. For example, conductive portions L2, L3, and L4 are located between the second sub-initialization voltage line 312 and the second power signal line 522. For example, a portion of conductive portion L2 is located between conductive portions L3 and L4.

[0110] For example, such as Figures 1 to 3 , Figure 6 As shown, the third gate conductive layer 423 includes conductive portion L5 and conductive portion L6.

[0111] For example, such as Figures 4 to 6 As shown, at least one of the first sub-initialization voltage line 311 and the second sub-initialization voltage line 312 is located in at least one gate conductive layer. For example, Figures 4 to 6 The second sub-initialization voltage line 312 is schematically shown to be located in the second gate conductive layer 422, but is not limited thereto. For example, in other examples, the first sub-initialization voltage line 311 may be located in the third gate conductive layer 423.

[0112] Figure 7 This is a schematic diagram of a via in an interlayer insulation layer. Figure 8 This is a schematic diagram of the first active layer.

[0113] Figure 7The vias in the interlayer insulating layer 430 shown are not limited to vias in a single insulating layer. For example, some vias can be vias in a single insulating layer, and some vias can be vias in multiple insulating layers. For example, the interlayer insulating layer 430 is not limited to a single insulating layer. It may include at least one of the following: the insulating layer between the second active layer 410 and the first gate conductive layer 421; the insulating layer between the first gate conductive layer 421 and the second gate conductive layer 422; the insulating layer between the second gate conductive layer 422 and the third gate conductive layer 423; the insulating layer between the third gate conductive layer 423 and the first active layer 440; the insulating layer between the first active layer 440 and the first source / drain metal layer 460; and the insulating layer between the first source / drain metal layer 460 and the second source / drain metal layer 470.

[0114] For example, such as Figures 1 to 8 As shown, the portion of conductive part L3 overlapping with the first active layer 440 constitutes the first gate of the first transistor T1, and the portion of conductive part L6 overlapping with the first active layer 440 constitutes the second gate of the first transistor T1. The first transistor T1 has a top gate and a bottom gate design. For example, the portion of conductive part L4 overlapping with the first active layer 440 constitutes the first gate of the second transistor T2, and the portion of conductive part L5 overlapping with the first active layer 440 constitutes the second gate of the second transistor T2. The second transistor T2 has a top gate and a bottom gate design. However, this is not a limitation. At least one of the first transistor T1 and the second transistor T2 may include only one gate, such as the first active layer 440 of the first transistor T1 overlapping with one of the second gate conductive layer 422 and the third gate conductive layer 423, and / or the first active layer 440 of the second transistor T2 overlapping with one of the second gate conductive layer 422 and the third gate conductive layer 423.

[0115] For example, such as Figure 8 As shown, the material of the first active layer 440 includes oxide. For example, the pixel circuit provided in this disclosure can be an LTPO (LTPS low-temperature polysilicon transistor + oxide transistor) pixel circuit. For example, the first transistor T1 and the second transistor T2 can be oxide transistors. Oxide transistors have good hysteresis characteristics, low leakage current, and low mobility. Therefore, setting the first transistor T1 as an oxide transistor achieves low leakage current and ensures the stability of the potential at the control terminal of the driving transistor T3.

[0116] For example, such as Figure 8 As shown, the active layer pattern of the second transistor T2 includes a portion extending along the X direction and a portion extending along the Y direction. For example, the active layer pattern of the first transistor T1 is along the Y direction.

[0117] Figure 9 This is a schematic diagram of a via in a planarization layer. Figure 10 and Figure 11This is a schematic diagram of two source / drain metal layers in a display panel. For example, Figure 10 This is a schematic diagram of the first source / drain metal layer 460. Figure 11 This is a schematic diagram of the second source / drain metal layer 470.

[0118] For example, such as Figures 1 to 10 As shown, the first source / drain metal layer 460 includes a first initialization voltage line Init2. For example, the first sub-initialization voltage line 311 is connected to the second terminal of the seventh transistor T7 in the first pixel circuit 110. The seventh transistor T7 is electrically connected to the first sub-initialization voltage line 311 through a via in the interlayer insulating layer 430. For example, the seventh transistor T7 in the second pixel circuit 120 is electrically connected to the second sub-initialization voltage line 312 through a conductive portion L11 in the first source / drain metal layer 460. For example, the seventh transistor T7 is electrically connected to one end of the conductive portion L11 through a via in the interlayer insulating layer 430 between the second active layer 410 and the first source / drain metal layer 460, and the other end of the conductive portion L11 is electrically connected to the second sub-initialization voltage line 312 through a via in the interlayer insulating layer 430 between it and the second sub-initialization voltage line 312.

[0119] For example, such as Figures 1 to 10 As shown, the first source / drain metal layer 460 includes a power signal line VDD, such as a first power signal line 521, at least a portion of which extends in the X direction. For example, the first power signal line 521 is electrically connected to the second power signal line 522 through a via in the interlayer insulating layer 430 between it and the second power signal line 522. For example, the first power signal line 521 includes a transition portion 5210, which is electrically connected to the first electrode of the fifth transistor T5 through a via in the interlayer insulating layer 430 between it and the first electrode of the fifth transistor T5. For example, at least a portion of the transition portion 5210 extends in the Y direction. For example, the transition portion 5210 includes a portion extending in the X direction and another portion extending in the Y direction.

[0120] For example, such as Figures 1 to 10As shown, the first source-drain metal layer 460 includes a second initialization voltage line Init1, which is disposed on the same layer as the first power signal line 521 and extends along the X direction; the second initialization voltage line Init1 is connected to the first initial signal terminal Vinit1, and the second terminal of the first transistor T1 is electrically connected to the second initialization voltage line Init1 through a via in the interlayer insulating layer 430 between it and the second initialization voltage line Init1. For example, the first source-drain metal layer 460 includes a third initialization voltage line Init3, which is disposed on the same layer as the first power signal line 521 and extends along the X direction; the third initialization voltage line Init3 is electrically connected to the third initial signal terminal Vinit3, and the third initialization voltage line Init3 is connected to the first terminal of the eighth transistor T8 through a via in the interlayer insulating layer 430 between it and the second active layer 410.

[0121] For example, such as Figures 1 to 10 As shown, the first source / drain metal layer 460 includes a conductive portion L9. The eighth transistor T8 is electrically connected to one end of the conductive portion L9 through a via in the interlayer insulating layer 430 between it and the conductive portion L9. The other end of the conductive portion L9 is electrically connected to the second electrode of the fifth transistor T5 through a via in the interlayer insulating layer 430 between it and the second active layer 410.

[0122] For example, such as Figures 1 to 10 As shown, the first source / drain metal layer 460 includes a reset control signal line Reset1, which is electrically connected to the first reset signal terminal N-Reset. The bottom gate and top gate of the first transistor T1 are electrically connected to the reset control signal line Reset1 through vias in the interlayer insulating layer 430 between them and the reset control signal line Reset1.

[0123] For example, such as Figures 1 to 10 As shown, the first source / drain metal layer 460 includes a conductive portion L10. The second electrode of the sixth transistor T6 is electrically connected to the conductive portion L10 through a via in the interlayer insulating layer 430 between it and the conductive portion L10. The conductive portion L10 is electrically connected to the electrode layer 2100 through a via in the planarization layer 450 between it and the electrode layer 2100. For example, the conductive portion L10 is electrically connected to the repair line Rep through a via in the interlayer insulating layer 430 between it and the repair line Rep. For example, the conductive portion L10 is located on the side of the conductive portion L9 away from the transition portion 5210. For example, the conductive portion L9, the conductive portion L10, and the transition portion 5210 are located between the first power signal line and the third initialization voltage line Init3.

[0124] For example, such as Figures 1 to 10As shown, the first source / drain metal layer 460 includes a conductive portion L7. One end of the conductive portion L7 is electrically connected to the capacitor plate C01 through a via in the interlayer insulating layer 430 between it and the capacitor plate C01. The other end of the conductive portion L7 is electrically connected to the conductive portion L2 through a via in the interlayer insulating layer 430 between it and the conductive portion L2. The conductive portion L2 is electrically connected to the first electrode of the first transistor T1 through a via in the interlayer insulating layer 430 between it and the first electrode of the first transistor T1. For example, the conductive portion L7 may include a portion extending along the X direction and a portion extending along the Y direction.

[0125] For example, such as Figures 1 to 10 As shown, the first source / drain metal layer 460 includes a conductive portion L8. One end of the conductive portion L8 is electrically connected to the second electrode of the driving transistor T3 through a via in the interlayer insulating layer 430 between it and the second electrode of the driving transistor T3. The other end of the conductive portion L8 is electrically connected to the first electrode of the second transistor T2 through a via in the interlayer insulating layer 430 between it and the first electrode of the second transistor T2. For example, a straight line extending along the Y direction passes through the conductive portions L7 and L8.

[0126] For example, such as Figures 1 to 10 As shown, the first source / drain metal layer 460 includes a scan line Gate2, which is electrically connected to the first gate drive signal terminal P-Gate. For example, the scan line Gate2 is electrically connected to the conductive portion L1 through a via in the interlayer insulating layer 430 between it and one end of the conductive portion L1. For example, the conductive portion L1 can be L-shaped.

[0127] For example, such as Figures 1 to 10 As shown, the first source / drain metal layer 460 includes a scan line Gate1, which is electrically connected to the second gate drive signal terminal N-Gate. For example, the top gate and bottom gate of the second transistor T2 are electrically connected to the scan line Gate2 through vias in the interlayer insulating layer 430 between them and the scan line Gate2. For example, conductive portions L7 and L8 are located between the scan line Gate1 and the first power supply signal line 521.

[0128] For example, such as Figure 10 As shown, the first initialization voltage line Init2, the second initialization voltage line Init1, the reset control signal line Reset1, the scan line Gate2, the scan line Gate1, the first power signal line 521, and the third initialization voltage line Init3 are arranged sequentially in the direction indicated by the arrow in the Y direction.

[0129] For example, such as Figure 11As shown, the second source / drain metal layer 470 includes a power signal line VDD, such as a third power signal line 523, and a data line DL. For example, the third power signal line 523 is electrically connected to the first power signal line 521. For example, the third power signal line 523 and the first power signal line 521 are electrically connected through a via in the film layer between the two power signal lines. This via can be located in the bezel area or in the display surface where the sub-pixel is located, without limitation. For example, the data line DL is electrically connected to the data signal terminal Data. For example, the data line DL is electrically connected to the first electrode of the fourth transistor T4 through a via in the interlayer insulating layer 430 between it and the first electrode of the fourth transistor T4. For example, the third power signal line 523 extends along the Y direction. For example, the data line DL includes a portion extending along the Y direction and a portion extending along the X direction, characterized in that the portion extending along the X direction is electrically connected to the first electrode of the fourth transistor T4.

[0130] For example, such as Figure 1 , Figure 10 as well as Figure 11 As shown, the second source / drain metal layer 470 includes a conductive portion L12, which is overlapped with a conductive portion L10 and is electrically connected to the conductive portion L10.

[0131] Figure 12A This is a schematic diagram of the light-shielding layer in the display panel.

[0132] For example, such as Figure 12A As shown, the light-shielding layer 480 includes portions extending along the X direction and along the Y direction. For example, the light-shielding layer 480 includes a light-shielding portion 481 for blocking the active layer pattern of the driving transistor T3. For example, the light-shielding layer 480 is located between the second active layer and the substrate.

[0133] Figure 12B This is a schematic diagram of the stacking of at least some of the film layers included in the display panel.

[0134] For example, such as Figure 12B As shown, the substrate 01 is sequentially provided with a light-shielding layer 480, a second active layer 410, a first gate conductive layer 421, a second gate conductive layer 422 and a third gate conductive layer 423, an interlayer insulating layer 430, a first active layer 440, a first source / drain metal layer 460, a second source / drain metal layer 470, a planarization layer 450, a first electrode 210 of the sub-pixel, and a pixel defining layer 02. Figure 12B The pixel openings of the pixel-defining layer 02 are schematically shown. Figure 12B Some insulating layers have been omitted, such as the insulating layer between some adjacent metal layers.

[0135] For example, such as Figures 1 to 11As shown, the gate conductive layer 420 is located on the side of the second active layer 410 away from the substrate 01. The first gate conductive layer 421, the second gate conductive layer 422, and the third gate conductive layer 423 are sequentially disposed along a direction perpendicular to the substrate 01. The first gate conductive layer 421 is located between the second gate conductive layer 422 and the second active layer 410, the first active layer 440 is located between the third gate conductive layer 423 and the first source / drain metal layer 460, and the second source / drain metal layer 470 is located between the first source / drain metal layer 460 and the electrode layer 2100. For example, the conductive layer between the electrode layer 2100 and the substrate 01 may include the first gate conductive layer 421, the second gate conductive layer 422, the third gate conductive layer 423, the first source / drain metal layer 460, and the second source / drain metal layer 470. However, this is not the only possibility. In other examples, the gate conductive layer may include at least one layer, and the source / drain metal layer may include at least one layer.

[0136] Figure 13 and Figure 15 This is a partial structural schematic diagram of a display panel provided according to different examples of embodiments of the present disclosure. Figure 14 for Figure 13 A schematic diagram of the third gate conductive layer in the display panel shown.

[0137] Figure 13 The display panel shown is Figure 1 The difference in the display panel shown is that the multiple pixel circuits 100 also include a third pixel circuit 130, and the first initialization voltage line Init2 also includes a third sub-initialization voltage line 313. Figure 13 The other film layers in the display panel shown, except for the third gate conductive layer 423, can be connected with... Figures 1 to 12A The corresponding films in the display panel shown have the same characteristics, which will not be described again here.

[0138] In some examples, such as Figure 5 , Figure 10 , Figures 13 to 14 As shown, the third sub-initialization voltage line 313 is electrically connected to the initialization circuit 101 of the third pixel circuit 130. The third sub-initialization voltage line 313 is located in the above-mentioned at least three conductive layers, and is located in a different layer from the first sub-initialization voltage line 311 and the second sub-initialization voltage line 312.

[0139] In some examples, such as Figure 13 As shown, the first pixel circuit 110, the second pixel circuit 120, and the third pixel circuit 130 are configured to be electrically connected to three different color light-emitting elements. For example, the first pixel circuit 110, the second pixel circuit 120, and the third pixel circuit 130 are pixel circuits in different color sub-pixels.

[0140] Since the activation voltages of the three different color sub-pixels corresponding to the first pixel circuit, the second pixel circuit, and the third pixel circuit are different, by setting the first sub-initialization voltage line, the second sub-initialization voltage line, and the third sub-initialization voltage line in different conductive layers, the pixel circuits belonging to different color sub-pixels can be reset separately. This can optimize the voltage across VDD-VSS in different colors, thereby reducing power consumption and heat generation.

[0141] In some examples, such as Figure 5 , Figure 10 , Figures 13 to 14 As shown, at least one of the first sub-initialization voltage line 311, the second sub-initialization voltage line 312, and the third sub-initialization voltage line 313 is located in at least one gate conductive layer. For example, at least one of the first sub-initialization voltage line 311, the second sub-initialization voltage line 312, and the third sub-initialization voltage line 313 is located in at least one of the first gate conductive layer 421, the second gate conductive layer 422, and the third gate conductive layer 423.

[0142] In some examples, such as Figure 5 , Figure 10 , Figures 13 to 14 As shown, at least one gate conductive layer 420 includes at least two gate conductive layers; two of the first sub-initialization voltage line 311, the second sub-initialization voltage line 312 and the third sub-initialization voltage line 313 are respectively located in the two gate conductive layers.

[0143] For example, such as Figure 5 , Figure 13 as well as Figure 14 As shown, the second sub-initialization voltage line 312 is located in the second gate conductive layer 422, and the third sub-initialization voltage line 313 is located in the third gate conductive layer 423. However, it is not limited to this. It is also possible that the third sub-initialization voltage line 313 is located in the second gate conductive layer 422, and the second sub-initialization voltage line 312 is located in the third gate conductive layer 423; or, the second sub-initialization voltage line 312 is located in the second gate conductive layer 422, and the first sub-initialization voltage line 311 is located in the third gate conductive layer 423; or, the first sub-initialization voltage line 311 is located in the second gate conductive layer 422, and the third sub-initialization voltage line 313 is located in the third gate conductive layer 423, etc. The embodiments disclosed herein do not limit this.

[0144] In some examples, such as Figure 5 and Figure 13As shown, among the first sub-initialization voltage line 311, the second sub-initialization voltage line 312, and the third sub-initialization voltage line 313, the first initialization voltage line Init2, located outside the two gate conductive layers, is situated between the two gate conductive layers and the electrode layer 2100. For example, the first initialization voltage line Init2, located outside the two gate conductive layers, can be located in the first source / drain metal layer 460 or the second source / drain metal layer 470. For example, the first initialization voltage line Init2, located outside the two gate conductive layers, can be located in the first source / drain metal layer 460. The embodiments of this disclosure are not limited to having two source / drain metal layers; for example, the number of source / drain metal layers can be three, such as including a third source / drain metal layer located on the side of the second source / drain metal layer 470 away from the substrate 01, and the first initialization voltage line Init2, located outside the two gate conductive layers, can be located in the second source / drain metal layer 470.

[0145] This example describes a scenario where the second sub-initialization voltage line 312 is located in the second gate conductive layer 422, the third sub-initialization voltage line 313 is located in the third gate conductive layer 423, and the first sub-initialization voltage line 311 is located in the first source / drain metal layer 460. However, this is not the only example. The first sub-initialization voltage line 311, the second sub-initialization voltage line 312, and the third sub-initialization voltage line 313 can be located in any three of the following layers: the first gate conductive layer 421, the second gate conductive layer 422, the third gate conductive layer 423, the first source / drain metal layer 460, and the second source / drain metal layer 470. These can be configured according to requirements.

[0146] For example, such as Figure 13 As shown, the third sub-initialization voltage line 313 extends along the X direction.

[0147] In some examples, such as Figure 13 As shown, at least two of the first sub-initialization voltage line 311, the second sub-initialization voltage line 312, and the third sub-initialization voltage line 313 overlap along a direction perpendicular to the substrate 01.

[0148] By overlapping at least two of the first sub-initialization voltage line 311, the second sub-initialization voltage line 312, and the third sub-initialization voltage line 313, it is beneficial to save layout space.

[0149] Figure 15 The display panel shown is Figure 13 The difference in the display panel shown lies in the relative positions of the first sub-initialization voltage line 311, the second sub-initialization voltage line 312, and the third sub-initialization voltage line 313. To clearly illustrate the relative positions of the first sub-initialization voltage line 311, the second sub-initialization voltage line 312, and the third sub-initialization voltage line 313, Figure 15The pixel circuitry has been simplified, and all signal lines except for the first initialization voltage line Init2 have been omitted.

[0150] In some examples, such as Figure 15 As shown, at least two of the first sub-initialization voltage lines 311, 312, and 313 have a gap between their orthogonal projections onto the substrate 01. For example, there is a gap between the portion of the second sub-initialization voltage line 312 extending in the X direction in its orthogonal projection onto the substrate 01 and the portion of the third sub-initialization voltage line 313 extending in the X direction in its orthogonal projection onto the substrate 01. For example, there is a gap between the portion of the second sub-initialization voltage line 312 extending in the X direction in its orthogonal projection onto the substrate 01 and the portion of the first sub-initialization voltage line 311 extending in the X direction in its orthogonal projection onto the substrate 01. For example, the portions of the first sub-initialization voltage line 311 and the third sub-initialization voltage line 313 extending in the X direction in their orthogonal projections onto the substrate 01 overlap.

[0151] By setting the portions of some sub-initialization voltage lines 311, 312, and 313 that extend along the X direction to be orthographically non-overlapping, and setting the portions of other sub-initialization voltage lines that extend along the X direction to be orthographically overlapping, the initialization signal of a certain color sub-pixel can be prevented from being affected by other signals while saving layout space.

[0152] In some examples, such as Figure 1 , Figure 5 as well as Figure 8 As shown, the first active layer 440 is located between the electrode layer 2100 and the substrate 01, and at least one of the at least three conductive layers is located between the first active layer 440 and the electrode layer 2100. The first active layer 440 includes a first active layer pattern of the first transistor T1 and a second active layer pattern of the second transistor T2. In the same pixel circuit, the first active layer pattern and the second active layer pattern are connected through at least one of the at least three conductive layers. Since the resistance of the first active layer made of oxide material is greater than the resistance of the conductive layer made of metal material, connecting the first active layer pattern and the second active layer pattern through the conductive layer helps to reduce the resistance.

[0153] For example, such as Figure 1 , Figure 5 as well as Figure 8As shown, in the same pixel circuit, the first active layer pattern and the second active layer pattern are connected through the conductive portion L2 in the second gate conductive layer 422. However, this is not the only possibility. In other examples, the first active layer pattern and the second active layer pattern can also be connected through the conductive portion in the second gate conductive layer 422 and the first source / drain metal layer 460, or only through the conductive portion in the first source / drain metal layer 460.

[0154] Figure 16 This is a partial structural schematic diagram of a display panel provided according to another example of an embodiment of the present disclosure. Figures 17 to 25 for Figure 16 The diagram shows the film layers of the pixel circuit in the display panel.

[0155] Figure 16 The equivalent circuit of the pixel circuit in the display panel shown can be referenced. Figure 2 The equivalent circuit. Figures 16 to 25 The display panel shown in the example is... Figure 1 , Figures 3 to 12A The difference in the display panel shown lies in the different patterns of the second active layer 410, the three gate conductive layers 420, the first active layer 440, and the two source / drain metal layers. Figures 16 to 25 The example shown displays the light-shielding layer 480 of the display panel and Figure 12A The light-shielding layer 480 shown has the same shape, and will not be described again here.

[0156] Figure 18 The conductive portion L1 in the first gate conductive layer 421 shown is... Figure 4 The conductive portion L1 in the first gate conductive layer 421 shown has the same electrical connection function, which will not be described in detail here. Figure 18 The capacitor plate C01 in the first gate conductive layer 421 shown is... Figure 4 The capacitor plate C01 in the first gate conductive layer 421 shown has the same function, which will not be described again here. Figure 18 The light emission control signal line EM1 and the reset control signal line Reset2 in the first gate conductive layer 421 shown are... Figure 4 The light emission control signal line EM1 and the reset control signal line Reset2 in the first gate conductive layer 421 shown have the same electrical connection relationship, which will not be described again here.

[0157] Figure 19 The conductive portions L3 and L4 in the second gate conductive layer 422 shown are... Figure 5 The conductive portions L3 and L4 in the second gate conductive layer 422 shown have the same electrical connection function, which will not be described in detail here. Figure 19 The second power signal line 522 and the repair line Rep in the second gate conductive layer 422 shown are... Figure 5The second power signal line 522 and the repair line Rep in the second gate conductive layer 422 shown have the same electrical connection relationship, which will not be described again here.

[0158] Figure 16 and Figure 19 In the example shown, the initialization circuit 101 in the first pixel circuit 110 and the second pixel circuit 120 can be connected to the same first initialization voltage line Init2, but is not limited to this. Figure 16 The initialization circuit 101 in the first pixel circuit 110 and the second pixel circuit 120 shown can also be connected to different first initialization voltage lines Init2.

[0159] Figure 20 The conductive portions L5 and L6 in the third gate conductive layer 423 shown are... Figure 6 The conductive portions L5 and L6 in the third gate conductive layer 423 shown have the same electrical connection function, which will not be described in detail here.

[0160] Figure 21 The vias in the interlayer insulating layer 430 shown Figure 7 The vias in the interlayer insulation layer 430 shown have the same electrical connection function, which will not be described in detail here.

[0161] Figure 23 The vias in the planarization layer 450 shown Figure 9 The vias in the interlayer insulation layer 430 shown have the same electrical connection function, which will not be described in detail here.

[0162] Figure 24 The second initialization voltage line Init1, reset control signal line Reset1, scan line Gate2, scan line Gate1, first power signal line, and third initialization voltage line Init3 in the first source / drain metal layer 460 shown are... Figure 10 The corresponding signal lines in the first source / drain metal layer 460 shown have the same arrangement and electrical connection relationship, which will not be described again here. Figure 24 The conductive portions L7, L8, L9, L10, and L11 in the first source / drain metal layer 460 shown are... Figure 10 The corresponding signal lines in the first source / drain metal layer 460 shown have the same electrical connection relationship, which will not be described again here.

[0163] Figure 25 The third power signal line 523 and data line DL in the second source / drain metal layer 470 shown are... Figure 10 The corresponding signal lines in the second source / drain metal layer 470 shown have the same electrical connection relationship, which will not be described again here. Figure 25 The conductive portion L12 in the second source / drain metal layer 470 shown is... Figure 11The conductive portion L12 in the second source / drain metal layer 470 shown has the same electrical connection relationship, which will not be described again here.

[0164] In some examples, such as Figure 16 and Figure 22 As shown, the first active layer 440 is located between the electrode layer (not shown) and the substrate 01, and at least one of the at least three conductive layers is located between the first active layer 440 and the electrode layer. The first active layer 440 includes active layer patterns of the first transistor T1 and the second transistor T2, and the active layer patterns of the first transistor T1 and the second transistor T2 in the same pixel circuit are integrally formed. By integrally forming the active layers of the first transistor and the second transistor, it is beneficial to reduce the number of vias.

[0165] In some examples, such as Figure 16 and Figure 17 As shown, the second active layer 410 is located between the aforementioned at least three conductive layers and the substrate 01. Each pixel circuit includes multiple transistors, and the second active layer 410 includes an active layer pattern of at least some of the transistors. For example, the second active layer 410 includes an active layer pattern of driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8.

[0166] In some examples, such as Figure 16 and Figure 17 As shown, multiple pixel circuits are arranged in an array along a first direction and a second direction, and at least one of the first initialization voltage lines Init2 extends along the first direction, with the first direction intersecting the second direction. Figure 16 Only two pixel circuits arranged along the first direction are shown schematically. Other pixel circuits can refer to these two pixel circuits and are arranged in an array. For example, the first direction can be the X direction and the second direction can be the Y direction. For example, the first direction can be the row direction and the second direction can be the column direction. For example, the angle between the first direction and the second direction is 85 to 95 degrees, such as the first direction being perpendicular to the second direction. However, this is not a limitation, and the first direction and the second direction can be interchanged.

[0167] In some examples, such as Figure 16 and Figure 17As shown, two adjacent pixel circuits arranged along the first direction include a first specific pixel circuit 100-1 and a second specific pixel circuit 100-2. The active layer patterns of the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2 are symmetrically distributed with respect to the center line CL extending along the second direction. By setting the active layer patterns of the first specific pixel circuit and the second specific pixel circuit to be symmetrically distributed, it is beneficial to increase the width of the signal line that transmits the VDD signal and extends along the Y direction, and to improve the flatness of the sub-pixel arrangement. This reduces the resistance of the signal line, reduces heat generation, and improves the display uniformity of the display panel.

[0168] For example, such as Figure 16 and Figure 17 As shown, the channel regions of the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2 are symmetrically distributed with respect to the center line CL.

[0169] For example, such as Figure 17 and Figure 18 As shown, the two conductive portions L1 that overlap with the channel regions of the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2 are symmetrically distributed with respect to the center line CL. For example, the capacitor plates C01 of the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2 are symmetrically distributed with respect to the center line CL.

[0170] For example, such as Figure 17 and Figure 19 As shown, the two conductive portions L3 overlapping the first active layers 440 of the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2 are symmetrically distributed with respect to the center line CL. For example, the two conductive portions L4 overlapping the first active layers 440 of the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2 are symmetrically distributed with respect to the center line CL. For example, the two transition portions 3122 in the first initialization voltage line Init2 that are electrically connected to the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2 are symmetrically distributed with respect to the center line CL.

[0171] For example, such as Figure 17 and Figure 20 As shown, the two conductive portions L5 overlapping the first active layer 440 of the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2 are symmetrically distributed with respect to the center line CL. For example, the two conductive portions L6 overlapping the first active layer 440 of the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2 are symmetrically distributed with respect to the center line CL.

[0172] For example, such as Figure 21As shown, the vias in the interlayer insulating layer 430 are symmetrically distributed with respect to the aforementioned centerline CL.

[0173] For example, such as Figure 17 and Figure 22 As shown, the active layer patterns in the first active layer 440 of the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2 are symmetrically distributed with respect to the aforementioned center line CL.

[0174] For example, such as Figure 17 and Figure 24 As shown, two conductive portions L7 electrically connected to the first electrode of the first transistor T1 of the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2 are symmetrically distributed with respect to the center line CL. For example, two conductive portions L8 electrically connected to the first electrode of the second transistor T2 of the first and second specific pixel circuits are symmetrically distributed with respect to the center line CL. For example, two conductive portions L9 electrically connected to the eighth transistor T8 of the first and second specific pixel circuits are symmetrically distributed with respect to the center line CL. For example, two conductive portions L10 electrically connected to the second electrode of the sixth transistor T6 of the first and second specific pixel circuits are symmetrically distributed with respect to the center line CL. For example, two conductive portions L11 electrically connected to the seventh transistor T7 of the first and second specific pixel circuits are symmetrically distributed with respect to the center line CL.

[0175] For example, such as Figure 17 and Figure 25 As shown, the third power signal line 523, which is electrically connected to the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2, is symmetrically distributed with respect to the aforementioned center line CL. For example, as... Figure 17 and Figure 25 As shown, the data lines DL, which are electrically connected to the first specific pixel circuit 100-1 and the second specific pixel circuit 100-2, are symmetrically distributed relative to the aforementioned center line CL.

[0176] In some examples, such as Figure 16 , Figure 17 as well as Figure 25 As shown, the display panel also includes multiple auxiliary signal lines 510 extending along the second direction and located on the side of the first initialization voltage line Init2 away from the substrate 01. At least a portion of the auxiliary signal lines 510 have their orthogonal projections on the plane where the second active layer 410 is located at the center line CL, and at least one of the auxiliary signal lines 510 is electrically connected to the first initialization voltage line Init2.

[0177] By electrically connecting the auxiliary signal line 510 to the first initialization voltage line Init2, a mesh signal transmission line layout is formed. This helps to reduce the overall resistance of the first initialization voltage line Init2 without affecting the layout of the pixel circuit as much as possible, which helps to ensure that the signals in different positions of the display panel are basically consistent. For example, when the display panel is a medium or large-sized panel, the above mesh signal transmission line layout can avoid different voltage drops in different areas of the display panel and achieve basic consistency of signals in different positions.

[0178] For example, such as Figure 16 and Figure 25 As shown, the auxiliary signal line 510 is located in the second source / drain metal layer 470. For example, the auxiliary signal line 510 is located between two adjacent third power signal lines 523. For example, the auxiliary signal line 510 is electrically connected to the first initialization voltage through a via in the interlayer insulating layer 430 between it and the first initialization voltage line Init2.

[0179] Figure 16 Taking the first specific pixel circuit and the second specific pixel circuit connected to the same first initialization voltage line Init2 as an example, in other examples, the first specific pixel circuit and the second specific pixel circuit are connected to different first initialization voltage lines Init2, such as the first sub-initialization voltage line 311 and the second sub-initialization voltage line 312. Some of the multiple auxiliary signal lines 510 can be electrically connected to the first sub-initialization voltage line 311, and some can be electrically connected to the second sub-initialization voltage line 312; or different first initialization voltage lines Init2 include the first sub-initialization voltage line 311, the second sub-initialization voltage line 312 and the third sub-initialization voltage line 313. Some of the multiple auxiliary signal lines 510 can be electrically connected to the first sub-initialization voltage line 311, some can be electrically connected to the second sub-initialization voltage line 312 and some can be electrically connected to the third sub-initialization voltage line 313.

[0180] In some examples, such as Figure 16 and Figure 25As shown, the display panel includes: multiple auxiliary signal lines 510, a first power signal line, a second initialization voltage line, and a third initialization voltage line Init3; the auxiliary signal lines 510 extend along a second direction and are located on the side of the first initialization voltage line Init2 away from the substrate 01; the first power signal line is located in one of the at least three conductive layers, and at least a portion of the first power signal line extends along a first direction; the second initialization voltage line is disposed in the same layer as the first power signal line and extends along the first direction; the third initialization voltage line Init3 is disposed in the same layer as the first power signal line and extends along the first direction. The orthographic projection of at least a portion of the auxiliary signal lines 510 on the plane where the active layer is located is located at the center line CL, and at least a portion of the auxiliary signal lines 510 are electrically connected to at least one of the first initialization voltage line Init2, the second initialization voltage line, the third initialization voltage line Init3, and the first power signal line.

[0181] Figure 16 The auxiliary signal line 510 is schematically shown to be electrically connected to the first initialization voltage line Init2, but is not limited thereto. In other examples, the auxiliary signal line 510 may be electrically connected to the second initialization voltage line; or the auxiliary signal line 510 may be electrically connected to the third initialization voltage line Init3; or the auxiliary signal line 510 may be electrically connected to the first power signal line; or the auxiliary signal line may include two parts of the auxiliary signal line electrically connected to two of the signal lines of the first initialization voltage line Init2, the second initialization voltage line, the third initialization voltage line Init3, and the first power signal line; or the auxiliary signal line may include three parts of the auxiliary signal line electrically connected to three of the signal lines of the first initialization voltage line Init2, the second initialization voltage line, the third initialization voltage line Init3, and the first power signal line; or the auxiliary signal line may include four parts of the auxiliary signal line electrically connected to four of the signal lines of the first initialization voltage line Init2, the second initialization voltage line, the third initialization voltage line Init3, and the first power signal line respectively. The embodiments disclosed herein do not impose any limitations on this.

[0182] For example, such as Figure 16As shown, the plurality of pixel circuits may include a first specific pixel circuit 100-1 and a second specific pixel circuit 100-2 arranged alternately along a first direction. For example, when the display panel includes the first pixel circuit 110 and the second pixel circuit 120 described above, the first pixel circuit may be one of the first specific pixel circuit and the second specific pixel circuit, and the second pixel circuit may be the other of the first specific pixel circuit and the second specific pixel circuit. For example, when the display panel includes the first pixel circuit, the second pixel circuit, and the third pixel circuit described above, the four pixel circuits arranged along the first direction constitute a pixel circuit group, and the number of one of the first pixel circuit, the second pixel circuit, and the third pixel circuit in each pixel circuit group is two, and the four pixel circuits include two first specific pixel circuits and two second specific pixel circuits.

[0183] exist Figure 16 In the display panel shown, the first sub-initialization voltage line and the second sub-initialization voltage line can be set in different conductive layers to achieve individual reset of the first pixel circuit and the second pixel circuit belonging to different color sub-pixels; however, it is not limited to this, a third sub-initialization signal line can also be set, the third sub-initialization voltage line is located in a different layer from the first sub-initialization voltage line and the second sub-initialization voltage line, and the first sub-initialization voltage line, the second sub-initialization voltage line and the third sub-initialization voltage line are electrically connected to different color sub-pixels to achieve individual reset of each color sub-pixel.

[0184] Figure 26 for Figure 16 The diagram shows the overlapping relationship between the second active layer and the first electrode in the pixel circuit group of the display panel.

[0185] In some examples, such as Figure 16 and Figure 26 As shown, the multiple pixel circuits 100 are divided into multiple pixel circuit groups 1000. Each pixel circuit group 1000 includes four pixel circuits arranged along a first direction. Two of the four pixel circuits are configured to be electrically connected to a first color light-emitting element G, and the other two pixel circuits are configured to be electrically connected to a second color light-emitting element R and a third color light-emitting element B, respectively. The first color light-emitting element, the second color light-emitting element, and the third color light-emitting element are arranged in a diamond pattern, which can improve the display resolution through pixel borrowing.

[0186] For example, the first color light-emitting element G is a green light-emitting element G, the second color light-emitting element 200R is a red light-emitting element R, and the third color light-emitting element B is a blue light-emitting element B.

[0187] In some examples, such as Figure 26As shown, the four pixel circuits include a first sub-pixel circuit 1001, a second sub-pixel circuit 1002, a third sub-pixel circuit 1003, and a fourth sub-pixel circuit 1004 arranged sequentially. The first sub-pixel circuit 1001 is electrically connected to the second color light-emitting element R, the second sub-pixel circuit 1002 is electrically connected to the first color light-emitting element G, the third sub-pixel circuit 1003 is electrically connected to the third color light-emitting element B, and the fourth sub-pixel circuit 1004 is electrically connected to the first color light-emitting element G. The first, second, and third color light-emitting elements are arranged in a diamond pattern, which can improve the display resolution through pixel borrowing.

[0188] In some examples, such as Figure 26 As shown, the active layer patterns of the first sub-pixel circuit 1001 and the active layer patterns of the second sub-pixel circuit 1002 are symmetrically distributed with respect to the center line CL extending along the second direction between them, and the active layer patterns of the third sub-pixel circuit 1003 and the active layer patterns of the fourth sub-pixel circuit 1004 are symmetrically distributed with respect to the center line CL extending along the second direction between them.

[0189] For example, such as Figure 26 As shown, the active layer patterns of the pixel circuits connected to the red light-emitting element R and the green light-emitting element G are symmetrically distributed with respect to the center line CL; the active layer patterns of the pixel circuits connected to the blue light-emitting element B and the green light-emitting element G are symmetrically distributed with respect to the center line CL.

[0190] For example, such as Figure 26 As shown, the first sub-pixel circuit 1001 can be the first specific pixel circuit 100-1, the second sub-pixel circuit 1002 can be the second specific pixel circuit 100-2, the third sub-pixel circuit 1003 can be the first specific pixel circuit 100-1, and the fourth sub-pixel circuit 1004 can be the second specific pixel circuit 100-2; but not limited thereto, the positions of the first specific pixel circuit and the second specific pixel circuit can be interchanged.

[0191] In other examples, Figure 16 The auxiliary signal line 510 may not be required in the display panel shown.

[0192] Figure 27 This is a schematic diagram of a partial planar structure in a display panel provided according to another example of an embodiment of the present disclosure. Figure 28 For along Figure 27 A schematic diagram of the local cross-section structure intercepted by line AA'.

[0193] In some examples, such as Figure 27 and Figure 28As shown, the display panel further includes an isolation structure 610 located on the side of at least three conductive layers away from the substrate 01. The display panel includes a plurality of sub-pixels, each sub-pixel including a pixel circuit and a light-emitting element 200 electrically connected to the pixel circuit. The light-emitting element 200 includes a first electrode 210, a light-emitting functional layer 230, and a second electrode 220 stacked together. The electrode layer 2100 includes a first electrode 210 for each of the plurality of sub-pixels. The first electrode 210 is located between the light-emitting functional layer 230 and the substrate 01, and is electrically connected to the pixel circuit. The plurality of sub-pixels are divided into a plurality of pixel units 1010. Each pixel unit 1010 includes two first color sub-pixels 1011, one second color sub-pixel 1012, and one third color sub-pixel 1013. The isolation structure 610 is located at least between the light-emitting areas of the first color sub-pixels 1011 and the third color sub-pixels 1013, and is configured to isolate at least a portion of the light-emitting functional layer 230. For example, the first electrode 210 includes a main electrode 211 and a connecting electrode 212, which is electrically connected to the pixel circuit.

[0194] For example, such as Figure 28 As shown, the light-emitting element 200 of the sub-pixel can be an organic light-emitting element 200. The organic light-emitting element 200 adopts the tandem technology. For example, the light-emitting functional layer 230 of the sub-pixel includes two light-emitting layers and a whole-layer charge generation layer located between the two light-emitting layers. Figure 28 The diagram schematically illustrates two light-emitting layers and a charge-generating layer in the light-emitting functional layer 230. The light-emitting functional layer 230 may further include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. For example, a charge-generating layer with strong conductivity can give the light-emitting functional layer 230 advantages such as long lifetime, low power consumption, and high brightness. For example, the charge-generating layer may include an N-type charge-generating layer and a P-type charge-generating layer. For example, the material of the charge-generating layer may be a material containing phosphorothoxy groups or a material containing triazine. For example, the ratio of the electron mobility of the charge-generating layer material to the electron mobility of the electron transport layer material is 10. -2 ~10 2 .

[0195] The emitting layers of a subpixel are stacked and connected in series, with a full-layer charge generation layer, such as a P-type doped charge generation layer P-CGL and an N-type doped charge generation layer N-CGL, placed between the stacked emitting layers. Compared to a subpixel without a tandem device, the tandem device uses N / P-CGL as a heterojunction to connect the two emitting layers in series. This technology achieves dual emitting devices in series, significantly reducing the emitting current of the emitting devices at the same luminous intensity, improving the lifetime of organic light-emitting elements (OLEDs) and reducing power consumption.

[0196] The charge generation layer of adjacent sub-pixels is a continuous film layer, and there is a lateral charge migration phenomenon, which causes the display substrate to have a monochromatic color shift at low gray levels. This can easily cause crosstalk between adjacent sub-pixels, resulting in color deviation of the display substrate.

[0197] Since the third color sub-pixel 1013 has the highest turn-on voltage and the first color sub-pixel 1011 has the lowest turn-on voltage, by providing at least a portion of the light-emitting functional layer 230, such as the isolation structure 610 of the charge generation layer, between the light-emitting areas of the first color sub-pixel 1011 and the third color sub-pixel 1013, the light emission crosstalk between the first color sub-pixel 1011 and the third color sub-pixel 1013 can be reduced.

[0198] Figure 27 The first electrode 210 of a sub-pixel in a pixel unit 1010 is schematically shown. Figure 28 A portion of the film layers in a pixel circuit connected to the light-emitting element 200 of the first color sub-pixel 1011 is schematically shown, omitting other film layers between the planarization layer 450 and the substrate 01, and omitting other film layers on the side of the second electrode 220 away from the substrate 01.

[0199] In some examples, such as Figure 27 As shown, the isolation structure 610 includes multiple sub-isolation structures, and at least one sub-isolation structure is provided between the first color sub-pixel 1011 and the third color sub-pixel 1013.

[0200] For example, Figure 27 The diagram schematically shows two sub-isolation structures between the first color sub-pixel 1011 and the third color sub-pixel 1013, but it is not limited to this and can also be one sub-isolation structure or more sub-isolation structures.

[0201] For example, Figure 27 The isolation structure 610 is schematically shown to include sub-isolation structures surrounding the light-emitting area of ​​the third color sub-pixel 1013 and the light-emitting area of ​​the second color sub-pixel 1012, but is not limited thereto. In other examples, the isolation structure 610 may include only the sub-isolation structure surrounding the light-emitting area of ​​the third color sub-pixel 1013; or the isolation structure 610 may include only the sub-isolation structure surrounding the light-emitting area of ​​the first color sub-pixel 1011. In other examples, the isolation structure 610 may include sub-isolation structures surrounding the light-emitting areas of the first color sub-pixel 1011, the second color sub-pixel 1012, and the third color sub-pixel 1013.

[0202] This example does not limit the shape, number, or position of the isolation structure 610. The isolation structure 610 is at least located between the light-emitting area of ​​the first color sub-pixel 1011 and the light-emitting area of ​​the third color sub-pixel 1013.

[0203] For example, such as Figure 28 As shown, the display panel includes a pixel defining layer 02, which includes multiple pixel openings to define the light-emitting areas of multiple sub-pixels. Figure 27 The circular areas of each sub-pixel shown are the light-emitting areas defined by the openings of multiple pixels. Figure 27 The light-emitting area of ​​each sub-pixel is schematically shown to be circular, but it is not limited to this and can also be other shapes. For example, the light-emitting functional layer 230 is in contact with the first electrode 210 and the second electrode 220 on both sides of the portion located in the pixel opening, so that the first electrode 210 and the second electrode 220 can drive the light-emitting functional layer 230 to emit light.

[0204] For example, such as Figure 28 As shown, the isolation structure 610 can be a groove in the pixel-defining layer 02.

[0205] However, this is not the only example. In other examples, the isolation structure 610 may also be an opening through the pixel defining layer, or the isolation structure 610 may include an opening through the pixel defining layer and a groove in the planarization layer 450.

[0206] For example, such as Figure 27 As shown, the isolation structure 610 may surround a portion of the light-emitting area of ​​at least one of the first color sub-pixel 1011 and the third color sub-pixel 1013. For example, the isolation structure 610 surrounding the light-emitting area of ​​the same sub-pixel may include at least two portions spaced apart.

[0207] In some examples, such as Figure 27 As shown, along the direction perpendicular to the substrate 01, the connection electrode 212 of at least one color sub-pixel does not overlap with the isolation structure 610.

[0208] By setting the connection electrode 212 of at least one color sub-pixel to not overlap with the isolation structure 610, it is possible to avoid the connection electrode 212 being exposed when the isolation structure 610 is formed in the pixel defining layer, or the adverse effects caused by the small film thickness between the connection electrode 212 and the second electrode 220 in the groove.

[0209] For example, such as Figure 27 As shown, at least the connecting electrode 212 of the third color sub-pixel 1013 does not overlap with the isolation structure 610.

[0210] In some examples, such as Figure 27As shown, along the direction perpendicular to the substrate 01, the connection electrodes 212 of at least two color sub-pixels do not overlap with the isolation structure 610.

[0211] For example, such as Figure 27 As shown, the connection electrodes 212 of the third color sub-pixel 1013 and the first color sub-pixel 1011 do not overlap with the isolation structure 610. For example, the connection electrodes 212 of the third color pixel and the second color sub-pixel 1012 do not overlap with the isolation structure 610.

[0212] In some examples, such as Figure 27 As shown, along the direction perpendicular to the substrate 01, the connection electrode 212 of each color sub-pixel does not overlap with the isolation structure 610.

[0213] For example, such as Figure 27 As shown, the spacing provided in the isolation structure 610 surrounding the light-emitting area of ​​the same sub-pixel can correspond to the connection electrode 212 of the first electrode 210 of the sub-pixel, so that the isolation structure 610 avoids the first electrode 210.

[0214] Figure 29A and Figure 29B This is a schematic diagram illustrating the relative positional relationship between a pixel unit and an isolation structure, provided according to different examples of embodiments of this disclosure.

[0215] Figure 29A and Figure 29B The display panel shown in the example is... Figure 27 The difference in the display panel shown in the example is that the length of the connecting electrode 212 of the sub-pixel and the relative positional relationship between the connecting electrode 212 and the isolation structure 610 are different.

[0216] In some examples, such as Figure 29A As shown, the area of ​​the main electrode 211 of the third color sub-pixel 1013 is larger than that of the main electrode 211 of the other color sub-pixels, and the length of the connecting electrode 212 of the third color sub-pixel 1013 is shorter than that of the connecting electrode 212 of the other color sub-pixels; along the direction perpendicular to the substrate 01, the connecting electrode 212 of the third color sub-pixel 1013 does not overlap with the isolation structure 610.

[0217] The third color sub-pixel 1013 is a blue sub-pixel. By setting the connection electrode 212 of the third color sub-pixel 1013 to be shorter than the connection electrode 212 of other color sub-pixels, the connection electrode 212 of the blue sub-pixel can be avoided from overlapping with the isolation structure 610 without deliberately adjusting the position of the isolation structure 610. This not only reduces the risk of the connection electrode of the blue sub-pixel being exposed by the groove included in the isolation structure to avoid oxidation, but also makes it beneficial for the isolation structure to include deeper grooves formed in the pixel limiting layer and the planarization layer to improve the isolation effect of the light-emitting functional layer.

[0218] For example, such as Figure 29A As shown, along the direction perpendicular to the substrate 01, the connection electrode 212 of the second color sub-pixel 1012 does not overlap with the isolation structure 610.

[0219] Figure 30 For along Figure 29A The diagram shows a partial cross-sectional structure cut by the BB' line in the display panel.

[0220] In some examples, such as Figure 29A and Figure 30 As shown, along the direction perpendicular to the substrate 01, the connection electrode 212 of at least one color sub-pixel other than the third color sub-pixel 1013 overlaps with the isolation structure 610.

[0221] When the lengths of the connecting electrodes 212 of the first color sub-pixel 1011 and the second color sub-pixel 1012 are both greater than the length of the connecting electrode 212 of the third color sub-pixel 1013, the connecting electrode 212 of at least one of the first color sub-pixel 1011 and the second color sub-pixel 1012 can overlap with the isolation structure 610.

[0222] For example, such as Figure 29A As shown, along the direction perpendicular to the substrate 01, the connection electrode 212 of the first color sub-pixel 1011 overlaps with the isolation structure 610. For example, along the direction perpendicular to the substrate 01, the connection electrode 212 of the second color sub-pixel 1012 does not overlap with the isolation structure 610.

[0223] For example, such as Figure 29BAs shown, the lengths of the connection electrodes 212 of the first color sub-pixel 1011 and the third color sub-pixel 1013 are both shorter than the length of the connection electrode 212 of the second color sub-pixel 1012. Furthermore, along the direction perpendicular to the substrate 01, the connection electrodes 212 of the first color sub-pixel 1011 and the third color sub-pixel 1013 do not overlap with the isolation structure 610. This embodiment is not limited to this; the length of the connection electrode 212 of at least one color sub-pixel and the overlap relationship between the connection electrode 212 and the isolation structure 610 can be adjusted according to the requirements of the isolation structure 610 and the connection electrodes 212 of each sub-pixel.

[0224] Figures 31 to 38 This is a schematic diagram showing the relative positional relationship between the first electrode of at least one color sub-pixel, the pixel circuit, and the signal lines in different examples. Figure 39 and Figure 40 This is a schematic diagram showing the relative positional relationship between the first electrode of each color sub-pixel and a portion of the structure in the metal layer in different examples.

[0225] To clearly illustrate the positional relationships Figures 31 to 33 Only the relative positional relationship between the first electrode 210 of the first color sub-pixel 1011, the pixel circuit, and the signal lines is shown. Figures 34 to 38 Only the relative positional relationship between the first electrode 210 of the first color sub-pixel 1011 and the third color sub-pixel 1013 and the pixel circuit and signal lines is shown. Figure 39 and Figure 40 The relative positions of the first electrode 210 of each color sub-pixel, the first power signal line connection line 631, and the adapter 632 are only shown.

[0226] Figure 39 and Figure 40 The difference in the example shown is that the extension direction of the connecting electrode 212 of the sub-pixel is different. Figure 39 In the example shown, the connection electrode 212 of the first color sub-pixel 1011 extends along the first direction, and the connection electrodes 212 of the second color sub-pixel 1012 and the third color sub-pixel 1013 extend along the second direction. Figure 40 In the example shown, the connection electrode 212 of the first color sub-pixel 1011 extends along the second direction, and the connection electrodes 212 of the second color sub-pixel 1012 and the connection electrodes 212 of the third color sub-pixel 1013 extend along the first direction.

[0227] Figures 31 to 37 The second source / drain metal layer 470 in the display panel shown is... Figure 16The difference in the second source / drain metal layer 470 in the display panel shown is that the first power signal line connection in the second source / drain metal layer 470 in this example includes an opening 633, and an adapter 632 is disposed within the opening 633.

[0228] Figures 31 to 38 The pixel circuit shown can be connected to other film layers except for the second source / drain metal layer 470. Figure 16 The corresponding films shown have the same characteristics, which will not be described again here.

[0229] For example, Figure 31 The first electrode 210 of the third color sub-pixel 1013 in the example shown can be Figure 27 The first electrode 210 of the third color sub-pixel 1013 in the example shown has a relatively long length. For example, the first electrode 210 of the third color sub-pixel 1013 in this example may overlap with the isolation structure 610 or may not overlap with the isolation structure 610.

[0230] For example, such as Figure 31 As shown, the signal lines extending along the Y direction may include signal lines connected to the first initialization voltage line Init2 and signal lines connected to the second initialization voltage line Init1, but are not limited thereto. In other examples, the signal lines extending along the Y direction may include only signal lines connected to the first initialization voltage line Init2 or signal lines connected to the second initialization voltage line Init1, or may also include signal lines transmitting other signals.

[0231] Figures 32 to 38 The first electrode 210 of the third color sub-pixel 1013 in the example shown can be Figure 29A and Figure 29B The first electrode 210 of the third color sub-pixel 1013 in the example shown is relatively short. For example, the first electrode 210 of the third color sub-pixel 1013 in this example does not overlap with the isolation structure 610.

[0232] Figure 34 The first electrode 210 of the first color sub-pixel 1011 in the example shown can be Figure 27 and Figure 29A The first electrode 210 of the first color sub-pixel 1011 in the example shown has a relatively long length. For example, the first electrode 210 of the first color sub-pixel 1011 in this example may overlap with the isolation structure 610 or may not overlap with the isolation structure 610.

[0233] Figures 35 to 38 The first electrode 210 of the first color sub-pixel 1011 in the example shown can be Figure 29B The first electrode 210 of the first color sub-pixel 1011 in the example shown is relatively short. For example, the first electrode 210 of the first color sub-pixel 1011 in this example does not overlap with the isolation structure 610.

[0234] Figures 32 to 35 The overlapping relationship between the first electrode 210 of the first color sub-pixel 1011 and the third color sub-pixel 1013 and the corresponding pixel circuit and signal line is schematically shown. The overlapping relationship between the first electrode 210 of the second color sub-pixel 1012 and the corresponding pixel circuit and signal line can be referred to the overlapping relationship between the first electrode 210 of the third color sub-pixel 1013 and the corresponding pixel circuit and signal line.

[0235] In some examples, such as Figures 32 to 36 , Figure 39 As shown, the display panel includes a metal layer 630 located between the electrode layer 2100 and at least three conductive layers, namely the aforementioned second source / drain metal layer 470. The first electrode 210 includes a main electrode 211 and a connecting electrode 212, the connecting electrode 212 being electrically connected to the pixel circuit; the metal layer 630 includes a first power signal line connecting line 631, namely the aforementioned third power signal line 523, and the metal layer includes a transition portion 632, namely the aforementioned conductive portion L12. The first power signal line connecting line 631 extends along a second direction, and the first power signal line connecting line 631 forms an opening 633, within which the transition portion 632 is disposed; the connecting electrode 212 of at least one of the first color sub-pixels 1011, the second color sub-pixel 1012, and the third color sub-pixel 1013 is electrically connected to the transistor in the pixel circuit through the transition portion 632; in the extending direction of the connecting electrode 212, the size ratio of the connecting electrode 212 to the main electrode 211 is 0.3 to 0.6. For example, as Figure 34 The diagram schematically shows that the connecting electrode can extend along the X direction or along the Y direction, but is not limited thereto. In other examples, the connecting electrode can also extend along a direction that intersects both the X and Y directions.

[0236] For example, the same first power signal line connection 631 includes a plurality of openings 633 arranged along the second direction, and each opening 633 is provided with two transition portions 632 for electrical connection with the first electrodes 210 of two different color sub-pixels. For example, the shape and size of the openings 633 corresponding to the different color sub-pixels can be the same.

[0237] For example, the multiple first power signal line connection lines 631 include multiple openings 633, which are arranged in an array in the first direction and the second direction.

[0238] For example, the connection electrode 212 of each sub-pixel is electrically connected to the pixel circuit through an adapter 632.

[0239] For example, such as Figures 32 to 36 , Figure 39 As shown, in the first color sub-pixel 1011, the second color sub-pixel 1012, and the third color sub-pixel 1013, the maximum value of the ratio of the size of the connecting electrode 212 to the size of the main electrode 211 is not greater than 0.6, and the minimum value is not less than 0.3. For example, the ratio of the size of the connecting electrode 212 to the size of the main electrode 211 in different color sub-pixels can be 0.3, 0.4, 0.5, or 0.6. For example, the ratio of the size of the connecting electrode 212 to the size of the main electrode 211 in different color sub-pixels can be the same or different.

[0240] By adjusting the position of the first electrode 210 or adjusting the length of the adapter 632, the length of the connecting electrode 212 in the first electrode 210 can be reduced to avoid the first electrode 210 overlapping with the isolation structure 610.

[0241] In some examples, such as Figures 32 to 36 , Figure 39 As shown, the connecting electrode 212 of the first color sub-pixel 1011 extends along a first direction, and the connecting electrodes 212 of the second color sub-pixel 1012 and the connecting electrodes 212 of the third color sub-pixel 1013 extend along a second direction; along the first direction, the size ratio of the connecting electrode 212 of the first color sub-pixel 1011 to the corresponding opening 633 is 0.35~0.45; along the second direction, the size ratio of the connecting electrode 212 of the second color sub-pixel 1012 to the corresponding opening 633 is 0.25~0.40, and the size ratio of the connecting electrode 212 of the third color sub-pixel 1013 to the corresponding opening 633 is 0.25~0.40.

[0242] By adjusting the size relationship between the connecting electrode 212 and the opening 633 of the first power signal line connecting line 631, the length of the connecting electrode 212 in the first electrode 210 can be reduced to avoid the first electrode 210 overlapping with the isolation structure 610.

[0243] For example, such as Figures 32 to 36 , Figure 39 As shown, the ratio of the size of the connecting electrode 212 to the corresponding opening 633 of the second color sub-pixel 1012 and the ratio of the size of the connecting electrode 212 to the corresponding opening 633 of the third color sub-pixel 1013 can be the same or different.

[0244] For example, such as Figures 32 to 36 , Figure 39As shown, along the first direction, the ratio of the size of the connecting electrode 212 of the first color sub-pixel 1011 to the size of the corresponding opening 633 is 0.37~0.42, or 0.36~0.4; or 0.38~0.43; or 0.39~0.44, etc.

[0245] For example, such as Figures 32 to 36 , Figure 39 As shown, along the second direction, the ratio of the size of the connecting electrode 212 of the second color sub-pixel 1012 to the size of the corresponding opening 633 is 0.27~0.36, or 0.28~0.32; or 0.26~0.35; or 0.29~0.37, etc.

[0246] For example, such as Figures 32 to 36 , Figure 39 As shown, along the second direction, the ratio of the size of the connecting electrode 212 of the third color sub-pixel 1013 to the size of the corresponding opening 633 is 0.27~0.36, or 0.28~0.32; or 0.26~0.35; or 0.29~0.37, etc.

[0247] In some examples, such as Figure 40 As shown, the connecting electrode 212 of the first color sub-pixel 1011 extends along the second direction, and the connecting electrodes 212 of the second color sub-pixel 1012 and the connecting electrodes 212 of the third color sub-pixel 1013 extend along the first direction; along the second direction, the size ratio of the connecting electrode 212 of the first color sub-pixel 1011 to the corresponding opening 633 is 0.25~0.35; along the first direction, the size ratio of the connecting electrode 212 of the second color sub-pixel 1012 to the corresponding opening 633 is 0.45~0.65, and the size ratio of the connecting electrode 212 of the third color sub-pixel 1013 to the corresponding opening 633 is 0.45~0.65.

[0248] For example, the corresponding opening 633 mentioned above refers to the opening 633 where the adapter 632 connected to the sub-pixel's connection electrode 212 is located, such as the opening 633 that overlaps with the sub-pixel's connection electrode 212.

[0249] For example, such as Figure 40 As shown, the ratio of the size of the connecting electrode 212 to the corresponding opening 633 of the second color sub-pixel 1012 and the ratio of the size of the connecting electrode 212 to the corresponding opening 633 of the third color sub-pixel 1013 can be the same or different.

[0250] For example, such as Figure 40 As shown, along the second direction, the ratio of the size of the connecting electrode 212 of the first color sub-pixel 1011 to the size of the corresponding opening 633 is 0.28~0.30, or 0.26~0.32, or 0.27~0.33, etc.

[0251] For example, such as Figure 40 As shown, along the first direction, the ratio of the size of the connecting electrode 212 of the second color sub-pixel 1012 to the size of the corresponding opening 633 is 0.5~0.6, or 0.48~0.62, or 0.46~0.64, or 0.55~0.61, etc.

[0252] For example, such as Figure 40 As shown, along the first direction, the ratio of the size of the connecting electrode 212 of the third color sub-pixel 1013 to the size of the corresponding opening 633 is 0.5~0.6, or 0.48~0.62, or 0.46~0.64, or 0.55~0.61, etc.

[0253] In some examples, such as Figure 40 As shown, the connecting electrode 212 of the first color sub-pixel 1011 extends along a second direction, and the size ratio of the connecting electrode 212 of the first color sub-pixel 1011 to the corresponding transition portion 632 along the second direction is 1.1 to 1.4; the connecting electrodes 212 of the second color sub-pixel 1012 and the connecting electrodes 212 of the third color sub-pixel 1013 extend along a first direction, and the size ratio of the connecting electrode 212 of the second color sub-pixel 1012 to the corresponding transition portion along the first direction is 1.1 to 1.4, and the size ratio of the connecting electrode 212 of the third color sub-pixel 1013 to the corresponding transition portion is 1.1 to 1.4.

[0254] The aforementioned corresponding adapter 632 refers to the sub-pixel connection electrode 212 being electrically connected to the pixel circuit through the adapter 632, such as the sub-pixel connection electrode 212 overlapping with the adapter 632.

[0255] For example, the size ratio of the connecting electrode 212 to the corresponding adapter 632 of each color sub-pixel can be the same or different.

[0256] For example, the size ratio of the connecting electrode 212 of the first color sub-pixel 1011 to the corresponding transition portion 632 is 1.1, 1.2, 1.3, or 1.4. For example, the size ratio of the connecting electrode 212 of the second color sub-pixel 1012 to the corresponding transition portion 632 is 1.1, 1.2, 1.3, or 1.4. For example, the size ratio of the connecting electrode 212 of the third color sub-pixel 1013 to the corresponding transition portion 632 is 1.1, 1.2, 1.3, or 1.4.

[0257] At least one of the following settings—the dimensional relationship between the connecting electrode 212 and the main electrode 211, the dimensional relationship between the connecting electrode 212 and the opening 633, and the dimensional relationship between the connecting electrode 212 and the adapter 632—can result in a smaller size for the connecting electrode 212, so that the connecting electrode 212 does not overlap with the isolation structure 610. This ensures that the pixel circuit and the anode transmission signal are the same in each sub-pixel, and guarantees the effect of the light-emitting functional layer in each color sub-pixel being isolated by the isolation structure, thus avoiding abnormal leakage or crosstalk.

[0258] For example, such as Figure 33 As shown, by increasing the length of the adapter 632, it is beneficial to avoid the overlap between the light-emitting area of ​​the sub-pixel and the opening 633, which would affect the flatness of the light-emitting functional layer 230 in the light-emitting area and cause color shift problems.

[0259] In some examples, such as Figure 35 and Figure 36 As shown, the adapter portion 632 connected to the connection electrode 212 of the first color sub-pixel 1011 extends along a first direction; the first power signal line connection line 631 includes two strip portions 634 surrounding the opening 633 and extending along a second direction, the connection electrode 212 of the first color sub-pixel 1011 overlaps with one of the two strip portions 634; the width of the strip portion 634 overlapping with the first color sub-pixel 1011 is less than the width of the other of the two strip portions 634, or the widths of the two strip portions 634 are the same; in the first direction, the ratio of the width of the strip portion 634 overlapping with the connection electrode 212 of the first color sub-pixel 1011 to the size of the opening 633 is 0.15 to 0.25.

[0260] By setting the width of the strip portion 634 that overlaps with the connection electrode 212 of the first color sub-pixel 1011 to be smaller, it is beneficial to reduce the length of the connection electrode 212 of the first color sub-pixel 1011 while minimizing the overlap between the light-emitting area of ​​the first color sub-pixel 1011 and the opening 633, which would affect the flatness of the light-emitting functional layer 230 in the light-emitting area and cause color shift problems.

[0261] For example, such as Figure 35 and Figure 36 As shown, the strip 634 can be a portion divided by dashed lines.

[0262] For example, such as Figure 35 and Figure 36 As shown, in the first direction, the ratio of the width of the strip portion 634 overlapping with the connecting electrode 212 of the first color sub-pixel 1011 to the size of the opening 633 is 0.17~0.2, or 0.16~0.23, or 0.18~0.22, or 0.19~0.24, etc.

[0263] For example, both of the above-mentioned strip portions 634 are portions surrounding the opening 633 in the first power signal line connection line 631, and the two strip portions 634 are an integral structure.

[0264] In some examples, such as Figure 37 As shown, the opening 633 includes a partition 635 extending in a second direction. At least one color sub-pixel includes two different color sub-pixels. Two types of transition portions 632 connected to the connection electrodes 212 of the two different color sub-pixels are located in the opening 633 and are located on both sides of the partition 635. The two types of transition portions 632 extend in different directions. The first power signal line connection line 631 includes two strip portions 634 surrounding the opening 633 and extending in a second direction. In the first direction, the ratio of the width of at least one of the two strip portions 634 to the size of the opening 633 is 0.15 to 0.25.

[0265] When the separator 635 is provided, by making the width of the strip 634 smaller, it is beneficial to reduce the length of the connecting electrode 212 that overlaps with the strip 634, while minimizing the overlap between the light-emitting area of ​​the sub-pixel and the opening 633, which would affect the flatness of the light-emitting functional layer 230 within the light-emitting area and cause color shift problems. Furthermore, by reducing the width of the strip 634 while providing the separator 635, it is beneficial to increase the area of ​​the first power signal line connection 631 and reduce resistance.

[0266] For example, such as Figure 37 As shown, the widths of the two strip portions 634 can be the same or different. When the widths of the two strip portions 634 are different, the ratio of the width of the strip portion 634 overlapping with the connecting electrode 212 to the size of the opening 633 is 0.15 to 0.25.

[0267] For example, such as Figure 37 As shown, the two strip sections 634 and the separator section 635 are both parts of the first power signal line connection line 631, and the two strip sections 634 and the separator section 635 are an integrated structure.

[0268] For example, such as Figure 37 As shown, the two different color sub-pixels can be a first color sub-pixel 1011 and a third color sub-pixel 1013, or a first color sub-pixel 1011 and a second color sub-pixel 1012. For example, the adapter 632 connected to the connection electrode 212 of the first color sub-pixel 1011 extends in the X direction, and the adapter 632 connected to the connection electrode 212 of the third color sub-pixel 1013 extends in the Y direction.

[0269] In some examples, such as Figure 38As shown, the first power signal line connection line 631 includes a transmission section 636 and a strip-shaped connection section 637 located between adjacent transmission sections 636. The width of the strip-shaped connection section 637 is smaller than the width of the transmission section 636. A transition section 632 is provided between adjacent transmission sections 636, and the transition section 632 is located on at least one side of the strip-shaped connection section 637. The connection electrode 212 of at least one color sub-pixel among the first color sub-pixel 1011, the second color sub-pixel 1012, and the third color sub-pixel 1013 is electrically connected to the transistor in the pixel circuit through the transition section 632.

[0270] By providing the strip-shaped connecting portion 637, the strip-shaped portion 634 at the edge of the first power signal line connecting line is omitted. This helps to avoid the risk of short circuits in the vias that electrically connect the connecting electrode 212 to the pixel circuit, while also reducing the length of the connecting electrode 212 of the sub-pixel. Furthermore, by replacing the strip-shaped portion 634 with the strip-shaped connecting portion 637, the overlap between the light-emitting area of ​​the sub-pixel and the strip-shaped portion 634 can be avoided, thus preventing it from affecting the flatness of the light-emitting functional layer 230 within the light-emitting area.

[0271] In some examples, such as Figure 38 As shown, two types of adapters 632 are provided on both sides of the strip-shaped connecting portion 637. The two types of adapters 632 extend in different directions and are configured to be electrically connected to the connecting electrodes 212 of two different color sub-pixels.

[0272] By setting the extension direction of the transition portions 632 on both sides of the strip-shaped connecting portion 637, it is beneficial to further reduce the length of the connecting electrode 212 of the sub-pixel.

[0273] For example, such as Figure 38 As shown, the strip-shaped connecting portion 637 and the transmission portion 636 are alternately arranged along the second direction. For example, the transmission portion 636 and the strip-shaped connecting portion 637 are integrated into one structure.

[0274] Figure 39 and Figure 40 The first power signal line connection 631 is schematically shown. Figure 36 The first power signal line connection 631 shown has the same structural features, but is not limited thereto. Figure 39 and Figure 40 The first power signal line connection 631 shown can also be connected to... Figures 31 to 36 The first power signal line connection 631 shown has the same structural features.

[0275] Figures 41 to 45 This is a schematic diagram illustrating the relative positional relationship of the light-emitting area, isolation structure, and spacer of a sub-pixel according to different examples of embodiments of this disclosure.

[0276] Figures 41 to 45The display panel shown in the example is... Figure 27 The difference in the display panel shown lies in the placement of the spacers. Figures 41 to 45 The isolation structure 610 in the display panel shown in the example can be configured with... Figure 27 The settings for the isolation structure 610 in the panel shown in the example are the same, but they can also be different. Figures 41 to 45 The arrangement of subpixels in the display panel shown can be compared with... Figure 27 The arrangement of subpixels in the display panel shown is the same, so it will not be described again here.

[0277] Figure 41 The display panel shown in the example is... Figure 42 The difference in the display panels shown in the examples lies in the position of the spacers. Figure 42 The display panel shown is Figure 43 The difference between the display panels shown lies in the position of the isolation structure 610 and the size of the spacer. Figure 42 , Figure 44 as well as Figure 45 The difference lies in the location of the isolation structure 610.

[0278] In some examples, such as Figures 41 to 45 As shown, the display panel also includes a spacer 620 located on the side of the light-emitting functional layer 230 away from the substrate 01. For example, the isolation structure 610 can be a recess in the pixel defining layer, and the spacer 620 can be a support structure provided on the side of the pixel defining layer away from the substrate 01, or it can be a protrusion in the pixel defining layer. The spacer is used to support the fine metal mask.

[0279] In some examples, such as Figures 41 to 45 As shown, the plurality of sub-pixels includes a first pixel group 1100 and a second pixel group 1200 arranged along a first direction. The first pixel group 1100 and the second pixel group 1200 are staggered along a second direction, and the first direction intersects the second direction. The first pixel group 1100 includes second color sub-pixels 1012 and third color sub-pixels 1013 alternately arranged along the second direction, and the second pixel group 1200 includes first color sub-pixels 1011 arranged along the second direction. For example, the same third color sub-pixel 1013 is surrounded by four first color sub-pixels 1011, and the same second color sub-pixel 1012 is surrounded by four first color sub-pixels 1011.

[0280] In some examples, such as Figure 41As shown, the spacer 620 includes at least one sub-spacer 621 located between the light-emitting area of ​​the second color sub-pixel 1012 and the light-emitting area of ​​the third color sub-pixel 1013 and the light-emitting area of ​​the first color sub-pixel 1011. Along a direction perpendicular to the substrate 01, the spacer does not overlap with the isolation structure 610. By setting the spacer to not overlap with the isolation structure, it is beneficial to avoid the grooves included in the isolation structure affecting the support effect of the spacer on the fine metal mask (FMM).

[0281] For example, Figure 41 The diagram schematically shows a spacer located between the second color sub-pixel 1012 and the third color sub-pixel 1013. However, it is not limited to this; by adjusting the position of the isolation structure 610, the spacer can also be positioned between the first color sub-pixel 1011 and the third color sub-pixel 1013.

[0282] In some examples, such as Figures 42 to 45 As shown, the spacer 620 includes a plurality of sub-spacers 621. The two sub-spacers 621 closest to the light-emitting area of ​​the same first color sub-pixel 1011 are symmetrically distributed with respect to the line CL0 connecting the center of the light-emitting area of ​​the first color sub-pixel 1011 and the center of the light-emitting area of ​​the adjacent second color sub-pixel 1012 or third color sub-pixel 1013. By setting at least part of the notch of the isolation structure around the pixel opening to face the spacer, such as directly opposite the spacer, it is beneficial to avoid the grooves included in the isolation structure from affecting the support effect of the spacer on the photomask.

[0283] For example, such as Figure 42 , Figure 44 , Figure 45 As shown, when a sub-isolation structure 610 is set between the second color sub-pixel 1012 and other color sub-pixels, or when no isolation structure 610 is set between the first color sub-pixel 1011 or the third color sub-pixel 1013 and the second color sub-pixel 1012, the size of the sub-spacer 621 can be set to be larger to improve the support effect on the fine metal mask.

[0284] For example, such as Figure 43 As shown, when an isolation structure 610 is set between any two color sub-pixels, the size of the sub-spacer 621 can be reduced and the number of sub-spacers 621 can be increased to ensure the support effect for the fine metal mask.

[0285] Figures 46A to 46B This is a schematic diagram showing the relative positional relationship of the light-emitting area, isolation structure, and third power signal line of a sub-pixel provided in different examples of embodiments of this disclosure. Figure 46A and Figure 46B The differences in the examples shown include the different number of signal lines extending along the Y direction. Figure 46A In the example shown, in addition to two data lines, there are two signal lines between two adjacent third power signal lines 523. These two signal lines can be connected to the initialization signal line or the power supply terminal VSS. Figure 46B In the example shown, in addition to two data lines, there are three signal lines between two adjacent third power signal lines 523. These three signal lines can be connected to the initialization signal line or the power supply terminal VSS.

[0286] Figures 46A to 46B The display panel shown is Figure 27 The difference in the display panel shown is that the isolation structure 610 surrounding the light-emitting area of ​​at least one sub-pixel can be a closed ring structure, and the second electrode of the sub-pixel is continuous at at least part of the edge of the ring structure.

[0287] For example, such as Figure 46A and Figure 46B As shown, when the length of the connecting electrode of the third color sub-pixel 1013 is short, the sub-isolation structure surrounding the third color sub-pixel 1013 in the isolation structure 610 can be a closed ring structure, and the ring structure does not overlap with the connecting electrode of the third color sub-pixel 1013.

[0288] For example, such as Figure 46A As shown, when the length of the connecting electrode of the second color sub-pixel 1012 is relatively long, the isolation structure 610 can be a non-closed ring structure. The opening of the non-closed ring structure is opposite to the connecting electrode to avoid the connecting electrode from overlapping with the isolation structure.

[0289] For example, such as Figure 46B As shown, when the length of the connecting electrode of the second color sub-pixel 1012 is relatively long, the isolation structure 610 can be a closed ring structure, which overlaps with the connecting electrode.

[0290] For example, such as Figure 46A and Figure 46B As shown, a sub-pixel with a larger main electrode can have a larger light-emitting area, and the length of the connecting electrode of a sub-pixel with a larger light-emitting area is less than the length of the connecting electrode of a sub-pixel with a smaller light-emitting area.

[0291] Figure 47 and Figure 48 This is a schematic diagram illustrating the layering relationship of some film layers in a display panel provided according to different examples of embodiments of the present disclosure.

[0292] In some examples, such as Figure 47 and Figure 48As shown, the second electrode 220 includes a first sub-layer 221 and a second sub-layer 222 stacked together. The second sub-layer 222 is located between the first sub-layer 221 and the second electrode 220. The material of the first sub-layer 221 includes silver, and the material of the second sub-layer 222 includes a transparent metal oxide. This is beneficial for improving transmittance.

[0293] In some examples, such as Figure 47 and Figure 48 As shown, the transparent metal oxides include indium zinc oxide (IZO).

[0294] For example, the second electrode 220 can be a cathode, which can be made of a material with a low work function. This makes it easier for electrons from the cathode to be injected into the target film layer (e.g., an electron injection layer). In this way, electrons in the cathode can effectively migrate to the light-emitting layer under the drive of the electric field, thereby recombine with holes in the anode to emit light. In addition, the cathode also needs to have good light transmittance and conductivity.

[0295] In some examples, such as Figure 47 and Figure 48 As shown, the light-emitting functional layer 230 of each sub-pixel includes a first light-emitting unit 231 and a second light-emitting unit 232 stacked together. The first light-emitting unit 231 is located between the second light-emitting unit 232 and the first electrode 210. The first light-emitting unit 231 includes at least one light-emitting layer, and the second light-emitting unit 232 includes at least one light-emitting layer.

[0296] In some examples, such as Figure 47 and Figure 48 As shown, taking the first color sub-pixel 1011 as green sub-pixel G, the second color sub-pixel 1012 as red sub-pixel R, and the third color sub-pixel 1013 as blue sub-pixel B as an example, the number of light-emitting layers included in the light-emitting functional layer 230 of the third color sub-pixel 1013 is not less than the number of light-emitting layers included in the light-emitting functional layer 230 of the other color sub-pixels.

[0297] For example, such as Figure 47 and Figure 48 As shown, each light-emitting unit of the third color sub-pixel 1013 includes two light-emitting layers, each light-emitting unit of the first color sub-pixel 1011 includes one light-emitting layer, and each light-emitting unit of the second color sub-pixel 1012 includes one light-emitting layer.

[0298] For example, such as Figure 47 and Figure 48As shown, the first light-emitting unit 231 of the red sub-pixel includes a light-emitting layer R-EML1, and the second light-emitting unit 232 of the red sub-pixel includes a light-emitting layer R-EML2; the first light-emitting unit 231 of the green sub-pixel includes a light-emitting layer G-EML1, and the second light-emitting unit 232 of the green sub-pixel includes a light-emitting layer G-EML2; the first light-emitting unit 231 of the blue sub-pixel includes light-emitting layers B-EML1 and B-EML2, and the second light-emitting unit 232 of the blue sub-pixel includes light-emitting layers B-EML3 and B-EML4.

[0299] For example, Figure 47 and Figure 48 As shown, an auxiliary layer is provided between the light-emitting layer in each light-emitting unit and the first electrode 210. For example, a first auxiliary layer is provided between the light-emitting layer in the first light-emitting unit 231 of each sub-pixel and the first electrode 210, and a second auxiliary layer is provided between the light-emitting layer in the second light-emitting unit 232 of each sub-pixel and the first light-emitting unit 231. For example, the light-emitting functional layer 230 includes the aforementioned first and second auxiliary layers.

[0300] For example, such as Figure 47 and Figure 48 As shown, a hole injection layer HIL and a first hole transport layer HTL1 are disposed between the first auxiliary layer and the first electrode 210, and a second hole transport layer HTL2 is disposed between the second auxiliary layer and the first light-emitting unit 231.

[0301] The first and second auxiliary layers mentioned above are used to reduce the transmission barrier of holes from the adjacent hole transport layer to the light-emitting layer.

[0302] Figure 47 and Figure 48 The difference in the example shown is the number of auxiliary layers included in the green sub-pixel. Figure 47 In the example shown, each light-emitting unit of the green sub-pixel includes an auxiliary layer. Figure 48 In the example shown, each light-emitting unit of the green sub-pixel includes two auxiliary layers.

[0303] For example, such as Figure 47 As shown, the first auxiliary layer disposed between the first light-emitting unit 231 of the green sub-pixel and the first hole transport layer HTL1 includes an auxiliary layer G-Prime1, and the second auxiliary layer disposed between the second light-emitting unit 232 of the green sub-pixel and the second hole transport layer HTL2 includes an auxiliary layer G-Prime2.

[0304] For example, such as Figure 48As shown, the first auxiliary layer between the first light-emitting unit 231 of the green sub-pixel and the first hole transport layer HTL1 includes auxiliary layer G-Prime1 and auxiliary layer G-Prime2, and the second auxiliary layer between the second light-emitting unit 232 of the green sub-pixel and the second hole transport layer HTL2 includes auxiliary layer G-Prime3 and auxiliary layer G-Prime4.

[0305] For example, such as Figure 47 and Figure 48 As shown, the first auxiliary layer disposed between the first light-emitting unit 231 of the red sub-pixel and the first hole transport layer HTL1 includes an auxiliary layer R-Prime1, and the second auxiliary layer disposed between the second light-emitting unit 232 of the red sub-pixel and the second hole transport layer HTL2 includes an auxiliary layer R-Prime2. For example, the first auxiliary layer disposed between the first light-emitting unit 231 of the blue sub-pixel and the first hole transport layer HTL1 includes an auxiliary layer B-Prime1, and the second auxiliary layer disposed between the second light-emitting unit 232 of the blue sub-pixel and the second hole transport layer HTL2 includes an auxiliary layer B-Prime2.

[0306] For example, the auxiliary layer included in the green subpixel may be composed of one or two materials from the green light-emitting layer connected thereto, and at least includes the hole-type host material from the green light-emitting layer.

[0307] For example, such as Figure 47 and Figure 48 As shown, the light-emitting functional layer 230 also includes a charge generation layer CGL, such as a P-type charge generation layer P-CGL and an N-type charge generation layer N-CGL, i.e., a first charge generation layer N-CGL and a second charge generation layer P-CGL. The first charge generation layer is located between the second charge generation layer and the substrate 01. The light-emitting functional layer 230 also includes a first electron transport layer ETL1 and a first hole blocking layer HBL1 located between the charge generation layer CGL and the first light-emitting unit 231. For example, the light-emitting functional layer 230 also includes an electron injection layer EIL, a second electron transport layer ETL2, and a second hole blocking layer HBL2 located between the second electrode 220 and the second light-emitting unit 232.

[0308] In some examples, such as Figure 47 and Figure 48 As shown, the display panel also includes an optical coupling output layer 710, located on the side of the second electrode 220 away from the light-emitting functional layer 230. The optical coupling output layer 710 includes a first optical coupling output layer 711 and a second optical coupling output layer 712 stacked together. The first optical coupling output layer 711 is located between the second optical coupling output layer 712 and the second electrode 220. The refractive index of the first optical coupling output layer 711 is greater than the refractive index of the second optical coupling output layer 712, which is beneficial for improving the optical coupling effect.

[0309] In some examples, such as Figure 47 and Figure 48 As shown, the display panel also includes an encapsulation layer 720 located on the side of the second electrode 220 away from the light-emitting functional layer 230. The encapsulation layer 720 includes a first encapsulation layer 721 and a second encapsulation layer 722 stacked together. The second encapsulation layer 722 is located on the side of the first encapsulation layer 721 away from the second electrode 220. The density of the first encapsulation layer 721 is higher than that of the second encapsulation layer 722.

[0310] In some examples, such as Figure 47 and Figure 48 As shown, the distance between the first light-emitting unit 231 and the first electrode 210 is the first distance L1; the distance between the interface between the first charge-generating layer and the second charge-generating layer and the first light-emitting unit 231 is the second distance L2; the distance between the interface between the first charge-generating layer and the second charge-generating layer and the second light-emitting unit 232 is the third distance L3; and the distance between the second light-emitting unit 232 and the second electrode 220 is the fourth distance L4. The second distance L2 is equal for all color sub-pixels, and the fourth distance L4 is equal for all color sub-pixels. This is beneficial for improving production efficiency and reducing costs.

[0311] In some examples, such as Figure 47 and Figure 48 As shown, in the second color sub-pixel 1012, the second distance L2 and the first distance L1 satisfy: 0.3≤L2 / L1≤0.5; in the first color sub-pixel 1011, the second distance L2 and the first distance L1 satisfy: 0.5≤L2 / L1≤0.7; in the third color sub-pixel 1013, the second distance L2 and the first distance L1 satisfy: 0.6≤L2 / L1≤0.8.

[0312] For example, in the carrier transport path of the first light-emitting unit 231, the transport distance of holes is a first distance L1, and the transport distance of electrons is L2; ​​in the carrier transport path of the second light-emitting unit 232, the transport distance of holes is L3, and the transport distance of electrons is L4. The hole transport paths and electron transport paths of the three different color sub-pixels satisfy the above three relationships.

[0313] Currently, hole transport materials have a higher hole mobility than electron transport materials, resulting in better hole injection and transport performance compared to electron injection and transport. This imbalance between holes and electrons negatively impacts device efficiency and lifetime. Increasing the thickness of hole transport materials, such as by increasing the hole transport distance L1, can help match the electron injection and transport rates.

[0314] In the three different color sub-pixels mentioned above, the energy level difference between the hole transport material and the auxiliary layer is not the same, and the energy level difference between the auxiliary layer and the light-emitting layer is different. Therefore, the thickness of the hole transport material is different in the different color sub-pixels.

[0315] For example, in the second color sub-pixel 1012, the second distance L2 and the first distance L1 satisfy: 0.35≤L2 / L1≤0.4, or 0.37≤L2 / L1≤0.45, etc.; in the first color sub-pixel 1011, the second distance L2 and the first distance L1 satisfy: 0.57≤L2 / L1≤0.65, or 0.55≤L2 / L1≤0.6, etc.; in the third color sub-pixel 1013, the second distance L2 and the first distance L1 satisfy: 0.65≤L2 / L1≤0.7, or 0.68≤L2 / L1≤0.75, etc. This embodiment of the disclosure will not list the specific numerical ranges of the relationships satisfied by the second distance L2 and the first distance L1 in different color sub-pixels; the values ​​of each relationship can be any values ​​from the above-mentioned relationships.

[0316] In some examples, such as Figure 47 and Figure 48 As shown, the distance between the distant surfaces of the first light-emitting unit 231 is the fifth distance L5, which is the thickness of the first light-emitting unit 231. In the second color sub-pixel 1012, the fifth distance L5 satisfies: 40 nm ≤ L5 ≤ 50 nm; in the first color sub-pixel 1011, the fifth distance L5 satisfies: 30 nm ≤ L5 ≤ 40 nm; and in the third color sub-pixel 1013, the fifth distance L5 satisfies: 15 nm ≤ L5 ≤ 25 nm.

[0317] In some examples, such as Figure 47 and Figure 48 As shown, the distance between the distant surfaces of the second light-emitting unit 232 is the sixth distance L6, which is the thickness of the second light-emitting unit 232. In the second color sub-pixel 1012, the sixth distance L6 satisfies: 40 nm ≤ L6 ≤ 50 nm; in the first color sub-pixel 1011, the sixth distance L6 satisfies: 30 nm ≤ L6 ≤ 40 nm; and in the third color sub-pixel 1013, the sixth distance L6 satisfies: 15 nm ≤ L6 ≤ 25 nm.

[0318] By setting the thickness of the first light-emitting unit 231 of different color sub-pixels to be different, that is, the thickness of the light-emitting layer in the first light-emitting unit 231 of different color sub-pixels is different, and setting the thickness of the second light-emitting unit 232 of different color sub-pixels to be different, that is, the thickness of the light-emitting layer in the second light-emitting unit 232 of different color sub-pixels is different, it is beneficial to optimize device efficiency and lifespan.

[0319] For example, in the second color sub-pixel 1012, the fifth distance L5 satisfies: 42 nm ≤ L5 ≤ 45 nm, or 43 nm ≤ L5 ≤ 48 nm, etc.; in the first color sub-pixel 1011, the fifth distance L5 satisfies: 33 nm ≤ L5 ≤ 37 nm, or 32 nm ≤ L5 ≤ 35 nm, etc.; in the third color sub-pixel 1013, the fifth distance L5 satisfies: 13 nm ≤ L5 ≤ 20 nm, or 17 nm ≤ L5 ≤ 22 nm, etc. This embodiment of the present disclosure will not list the specific numerical ranges of the fifth distance L5 in different color sub-pixels; the values ​​of each relation can be any value from the above relations.

[0320] For example, in the same color sub-pixel, the thickness of the first light-emitting unit 231 and the thickness of the second light-emitting unit 232 can be the same or different.

[0321] For example, the distance between the distant surfaces of the second light-emitting unit 232 is the sixth distance L6, which is the thickness of the second light-emitting unit 232. In the second color sub-pixel 1012, the sixth distance L6 satisfies: 42 nm ≤ L6 ≤ 45 nm, or 43 nm ≤ L6 ≤ 48 nm, etc.; in the first color sub-pixel 1011, the sixth distance L6 satisfies: 34 nm ≤ L6 ≤ 38 nm, or 32 nm ≤ L6 ≤ 35 nm, etc.; in the third color sub-pixel 1013, the sixth distance L6 satisfies: 18 nm ≤ L6 ≤ 22 nm, or 16 nm ≤ L6 ≤ 20 nm, etc. This embodiment of the present disclosure will not list the specific numerical ranges of the sixth distance L6 in different color sub-pixels; the values ​​of each relation can be any values ​​in the above relations.

[0322] In some examples, such as Figure 47 and Figure 48 As shown, the distance between the first electrode 210 and the second electrode 220 is the eighth distance L. In the second color sub-pixel 1012, the fourth distance L4 and the eighth distance L satisfy: 0.10≤L4 / L≤0.15; in the first color sub-pixel 1011, the fourth distance L4 and the eighth distance L satisfy: 0.14≤L4 / L≤0.19; in the third color sub-pixel 1013, the fourth distance L4 and the eighth distance L satisfy: 0.17≤L4 / L≤0.22.

[0323] In some examples, such as Figure 47 and Figure 48As shown, the distance between the second electrode 220 and the first light-emitting unit 231 is the seventh distance L7, and the distance between the first electrode 210 and the second electrode 220 is the eighth distance L. In the second color sub-pixel 1012, the seventh distance L7 and the eighth distance L satisfy: 0.60≤L7 / L≤0.66; in the first color sub-pixel 1011, the seventh distance L7 and the eighth distance L satisfy: 0.63≤L7 / L≤0.70; in the third color sub-pixel 1013, the seventh distance L7 and the eighth distance L satisfy: 0.67≤L7 / L≤0.73.

[0324] By adjusting the relationship between the thicknesses of each film layer to regulate the microcavity structure formed between the first electrode 210 and the second electrode 220, the light-emitting area is located in the microcavity enhancement region, thereby optimizing the emitted spectrum and improving the light extraction efficiency.

[0325] For example, in the second color sub-pixel 1012, the fourth distance L4 and the eighth distance L satisfy: 0.11≤L4 / L≤0.13, or 0.12≤L4 / L≤0.14, etc.; in the first color sub-pixel 1011, the fourth distance L4 and the eighth distance L satisfy: 0.15≤L4 / L≤0.18, or 0.16≤L4 / L≤0.17, etc.; in the third color sub-pixel 1013, the fourth distance L4 and the eighth distance L satisfy: 0.18≤L4 / L≤0.2, or 0.19≤L4 / L≤0.21, etc. This embodiment of the disclosure will not list the specific numerical ranges of the relationships satisfied by the fourth distance L4 and the eighth distance L in different color sub-pixels; the values ​​of each relationship can be any values ​​from the above relationships.

[0326] For example, in the second color sub-pixel 1012, the seventh distance L7 and the eighth distance L satisfy: 0.62≤L7 / L≤0.65, or 0.61≤L7 / L≤0.64, etc.; in the first color sub-pixel 1011, the seventh distance L7 and the eighth distance L satisfy: 0.64≤L7 / L≤0.65, or 0.66≤L7 / L≤0.68, etc.; in the third color sub-pixel 1013, the seventh distance L7 and the eighth distance L satisfy: 0.68≤L7 / L≤0.72, or 0.69≤L7 / L≤0.7, etc. This embodiment of the disclosure will not list the specific numerical ranges of the relationships satisfied by the seventh distance L7 and the eighth distance L in different color sub-pixels; the values ​​of each relationship can be any values ​​from the above-mentioned relationships.

[0327] For example, such as Figure 47 and Figure 48 As shown, the first electrode 210 can be an anode, and the second electrode 220 can be a cathode. To ensure that the light-emitting device can emit light effectively, the anode can be made of a material with a high work function, so that the holes in the anode can effectively migrate to the light-emitting layer under the drive of the electric field, and thus recombine with the electrons of the cathode to emit light.

[0328] Figure 49 This is a schematic diagram of the layering relationship of some film layers in a display panel provided according to another example of an embodiment of the present disclosure. Figure 50 for Figure 49 A schematic diagram showing the thickness of at least a portion of the film layers in the structure shown.

[0329] Figure 49 The display panel shown is Figure 47 The difference in the display panel shown is that each light-emitting unit of the green sub-pixel includes two light-emitting layers. Figure 49 The display panel shown is Figure 47 Except for the number of light-emitting layers in the green sub-pixels, the other film layers in the display panel shown have the same characteristics, which will not be described in detail here.

[0330] For example, such as Figure 49 As shown, the green sub-pixel includes an emissive layer G-EML1, an emissive layer G-EML2, an emissive layer G-EML3, and an emissive layer G-EML4.

[0331] For example, such as Figure 49 and Figure 50 As shown, the first electrode 210 includes three film layers, such as indium tin oxide (ITO), silver (Ag) and indium tin oxide (ITO) respectively, with thicknesses of 10 angstroms, 100 angstroms and 10 angstroms respectively.

[0332] For example, such as Figure 49 and Figure 50 As shown, the hole injection layer HIL has a thickness of 100 angstroms. For example, the first hole transport layer HTL1 has a thickness of 180 angstroms.

[0333] For example, such as Figure 49 and Figure 50 As shown, the thickness of the auxiliary layer R-Prime1 for the red subpixel is 320 angstroms, the thickness of the auxiliary layer G-Prime1 for the green subpixel is 100 angstroms, and the thickness of the auxiliary layer B-Prime1 for the blue subpixel is 60 angstroms. For example, the thickness of the emitting layer R-EML1 for the red subpixel is 450 angstroms, the thickness of the emitting layer G-EML1 for the green subpixel is 50 angstroms, the thickness of the emitting layer G-EML2 for the green subpixel is 300 angstroms, the thickness of the emitting layer B-EML1 for the blue subpixel is 50 angstroms, and the thickness of the emitting layer B-EML2 for the blue subpixel is 150 angstroms.

[0334] For example, such as Figure 49 and Figure 50As shown, the thickness of the first hole blocking layer HBL1 is 50 angstroms, the thickness of the first charge generation layer N-CGL is 180 angstroms, the thickness of the second charge generation layer P-CGL is 90 angstroms, and the thickness of the second hole transport layer HTL2 is 340 angstroms.

[0335] For example, such as Figure 49 and Figure 50 As shown, the thickness of the auxiliary layer R-Prime2 for the red subpixel is 320 angstroms, the thickness of the auxiliary layer G-Prime2 for the green subpixel is 100 angstroms, and the thickness of the auxiliary layer B-Prime2 for the blue subpixel is 60 angstroms. For example, the thickness of the emitting layer R-EML2 for the red subpixel is 450 angstroms, the thickness of the emitting layer G-EML3 for the green subpixel is 50 angstroms, the thickness of the emitting layer G-EML4 for the green subpixel is 300 angstroms, the thickness of the emitting layer B-EML3 for the blue subpixel is 50 angstroms, and the thickness of the emitting layer B-EML4 for the blue subpixel is 150 angstroms.

[0336] For example, such as Figure 49 and Figure 50 As shown, the thickness of the second hole blocking layer HBL2 is 50 angstroms. For example, the thickness of the second electron transport layer ETL2 is 300 angstroms. For example, the thickness of the electron injection layer EIL is 10 angstroms. For example, the thickness of the first sublayer 221 is 10~100 angstroms, and the thickness of the second sublayer 222 is 100~3000 angstroms. For example, the thickness of the first optical coupling output layer 711 is 400 angstroms, and the thickness of the second optical coupling output layer 712 is 450 angstroms.

[0337] Figure 49 and Figure 50 The film thickness relationship shown is applicable to Figure 48 The display panel shown. For example, Figure 48 The thickness of the G-Prime4 in the display panel shown can be... Figure 49 The thickness of the G-EML3 shown is the same. Figure 48 The thickness of G-Prime2 in the display panel shown can be... Figure 49 The thickness of G-EML1 shown is the same.

[0338] Figures 51 to 53 This is a schematic diagram illustrating the layering relationship of some film layers in a display panel provided according to different examples of embodiments of the present disclosure.

[0339] Figure 51 The display panel shown is Figure 48 The difference between the display panels shown is that the number of auxiliary layers for the green sub-pixels is different, and the first light-emitting unit of the blue sub-pixels only includes one light-emitting layer. Figure 51 The display panel shown has other films besides the aforementioned film layers and Figure 48The characteristics of the corresponding film layers in the display panel shown are the same, and will not be described again here.

[0340] Figure 52 The display panel shown is Figure 51 The difference in the display panels shown lies in the number of light-emitting layers included in the different light-emitting units of the blue sub-pixels. For example, as... Figure 52 As shown, the first light-emitting unit of the blue sub-pixel includes two light-emitting layers, such as light-emitting layer B-EML1 and light-emitting layer B-EML2, and the second light-emitting unit of the blue sub-pixel includes one light-emitting layer, such as light-emitting layer B-EML3.

[0341] Figure 53 The display panel shown contains only one light-emitting unit for each color sub-pixel, and does not include the charge generation layer (CGL). For example, as... Figure 53 As shown, the red sub-pixel includes one emissive layer, such as the emissive layer R-EML; the green sub-pixel includes one emissive layer, such as the emissive layer G-EML; and the blue sub-pixel includes two emissive layers, such as the emissive layer B-EML1 and the emissive layer B-EML2.

[0342] For example, the N-type charge generation layer NCGL may include a material with the structure shown in the following formula.

[0343] .

[0344] A represents alkyl or aryl, B represents phenylene or naphthylene, and p is a non-negative integer.

[0345] For example, the hole transport layer described above may include a material with the structure shown in the formula below.

[0346] .

[0347] For example, the aforementioned hole-blocking layer may include a material with the structure shown in the formula below.

[0348] .

[0349] For example, the aforementioned electron transport layer may include a material with the structure shown in the formula below.

[0350] .

[0351] For example, the electron blocking layer in a second color subpixel, such as a red subpixel, comprises a material with a structure as shown in the formula below.

[0352] .

[0353] For example, the electron blocking layer in the first color sub-pixel, such as the green sub-pixel, comprises a material with the structure shown in the formula below.

[0354] .

[0355] For example, the electron blocking layer in a third color subpixel, such as a blue subpixel, comprises a material with a structure as shown in the formula below.

[0356] .

[0357] For example, the N-type host material of the luminescent layer of the second color sub-pixel includes a material with the structure shown in the formula below.

[0358] .

[0359] For example, the P-type host material of the luminescent layer of the second color sub-pixel includes a material with the structure shown in the following formula.

[0360] .

[0361] For example, the H1 type body material of the luminescent layer of the third color sub-pixel includes a material with the structure shown in the following formula.

[0362] .

[0363] For example, the H2 type host material of the luminescent layer of the third color sub-pixel includes a material with the structure shown in the following formula.

[0364] .

[0365] For example, the H-shaped body material of the first color sub-pixel includes a material with the structure shown in the following formula.

[0366] .

[0367] For example, the thermally activated delayed fluorescence (TADF) material of the first color subpixel includes a material with the structure shown in the formula below.

[0368] .

[0369] For example, the doping material (D) of the first color sub-pixel includes a material with the structure shown in the formula below.

[0370] .

[0371] The above R1-R37 groups may be the same as or different from each other, and each group is independent of the following: hydrogen, deuterium, halogen group, nitrile group, nitro group, hydroxyl group, carbonyl group, ester group, imide group, amino group, substituted or unsubstituted silyl group, substituted or unsubstituted boron group, substituted or unsubstituted alkyl group, substituted or unsubstituted cycloalkyl group, substituted or unsubstituted alkoxy group, substituted or unsubstituted aryloxy group, substituted or unsubstituted alkylthio group, substituted or unsubstituted arylthio group, substituted or unsubstituted alkylsulfonyl group, substituted or unsubstituted arylsulfonyl group, substituted or unsubstituted alkenyl group, etc. Substituted or unsubstituted aralkyl, substituted or unsubstituted arene, substituted or unsubstituted alkylaryl, substituted or unsubstituted alkylamine, substituted or unsubstituted aralkylamine, substituted or unsubstituted heteroarylamine, substituted or unsubstituted arylamine, substituted or unsubstituted arylheteroarylamine, substituted or unsubstituted arylphosphine, substituted or unsubstituted phosphine oxide, substituted or unsubstituted aryl, or substituted or unsubstituted heterocyclic group; substituted or unsubstituted aryl-substituted or unsubstituted heteroaryl with 6 to 30 carbon atoms.

[0372] Ar0 to Ar12 may be the same as or different from each other, and each is independently hydrogen, deuterium, aryl group with 6 to 30 substituted or unsubstituted carbon atoms, or heterocyclic group with 6 to 30 substituted or unsubstituted carbon atoms.

[0373] L to L2 are independently selected from single bonds; C6-C60 arylene groups; fluorene groups; C2-C60 heterocyclic groups containing at least one heteroatom selected from the group consisting of O, N, S, Si and P; C3-C60 aliphatic rings; and combinations thereof.

[0374] m, n, a, and q are either the same or different from each other, and are all non-negative integers.

[0375] X1 and X2 are O, S, CR'R'', and NR', respectively; R' and R'' are independently hydrogen, deuterium, substituted or unsubstituted alkyl, substituted or unsubstituted cycloalkyl, substituted or unsubstituted aryl with 6 to 30 carbon atoms, or substituted or unsubstituted heterocyclic with 6 to 30 carbon atoms.

[0376] X and Y are selected from one of C, N, B, P, P=O, and Si.

[0377] Ra, Rb, and Rc are each independently selected from hydrogen atoms, deuterium atoms, cyano groups, substituted or unsubstituted aryl or heteroaryl groups, substituted or unsubstituted alkyl groups, and substituted or unsubstituted aromatic or heterocyclic groups fused with adjacent aromatic or heterocyclic groups.

[0378] The Za, Zb, and Zc rings are each independently an aromatic hydrocarbon ring with 6 to 50 substituted or unsubstituted carbon atoms, or a heterocycle with 5 to 50 substituted or unsubstituted carbon atoms.

[0379] Ar13 is bonded to the Za ring or the Zb ring to form a substituted or unsubstituted heterocycle, or not a substituted or unsubstituted heterocycle. Ar14 is bonded to the Za ring or the Zc ring to form a substituted or unsubstituted heterocycle, or not a substituted or unsubstituted heterocycle. Ar13 and Ar14 that do not form the substituted or unsubstituted heterocycle are independently substituted or unsubstituted alkyl groups with 1 to 50 carbon atoms, substituted or unsubstituted alkenyl groups with 2 to 50 carbon atoms, substituted or unsubstituted alkynyl groups with 2 to 50 carbon atoms, substituted or unsubstituted cycloalkyl groups with 3 to 50 cyclic carbon atoms, substituted or unsubstituted aryl groups with 6 to 50 cyclic carbon atoms, or substituted or unsubstituted heterocyclic groups with 5 to 50 cyclic atoms.

[0380] Figure 54 This is a schematic block diagram of a display device provided according to another embodiment of the present disclosure. Figure 54 As shown, an embodiment of this disclosure provides a display device including any of the above-described display panels.

[0381] For example, the display panel provided in this embodiment can be an organic light-emitting diode (OLED) display panel. For example, the display panel may or may not have a color filter layer.

[0382] For example, the display device also includes a cover plate located on the light-emitting side of the display substrate.

[0383] The following points need to be explained:

[0384] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0385] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0386] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display panel, characterized in that, include: Substrate; Multiple pixel circuits are located on the substrate, the multiple pixel circuits include at least a first pixel circuit and a second pixel circuit, each pixel circuit includes an initialization circuit, the initialization circuit being configured to be electrically connected to a light-emitting element; An electrode layer is located on the side of the pixel circuit away from the substrate, and the electrode layer includes a plurality of first electrodes configured to be electrically connected to the plurality of pixel circuits; A first initialization voltage line is located on the substrate. The first initialization voltage line includes a first sub-initialization voltage line and a second sub-initialization voltage line. The first sub-initialization voltage line is electrically connected to the initialization circuit in the first pixel circuit, and the second sub-initialization voltage line is electrically connected to the initialization circuit in the second pixel circuit. The electrode layer and the substrate are provided with at least three conductive layers, and the first sub-initialization voltage line and the second sub-initialization voltage line are respectively located in two of the at least three conductive layers.

2. The display panel according to claim 1, characterized in that, The plurality of pixel circuits further includes a third pixel circuit, and the first initialization voltage line further includes a third sub-initialization voltage line. The third sub-initialization voltage line is electrically connected to the initialization circuit of the third pixel circuit. The third sub-initialization voltage line is located in the at least three conductive layers and is located in a different layer from the first sub-initialization voltage line and the second sub-initialization voltage line.

3. The display panel according to claim 2, characterized in that, Along a direction perpendicular to the substrate, at least two of the first sub-initialization voltage line, the second sub-initialization voltage line, and the third sub-initialization voltage line overlap.

4. The display panel according to claim 2, characterized in that, At least two of the first sub-initialization voltage line, the second sub-initialization voltage line, and the third sub-initialization voltage line have a gap between their orthogonal projections on the substrate.

5. The display panel according to claim 2, characterized in that, Each pixel circuit includes multiple transistors, and each transistor includes an active layer pattern; The at least three conductive layers include at least one gate conductive layer, and the portion of the at least one gate conductive layer that overlaps with the active layer pattern serves as the gate of at least a portion of the transistors; At least one of the first sub-initialization voltage line, the second sub-initialization voltage line, and the third sub-initialization voltage line is located in the at least one gate conductive layer.

6. The display panel according to claim 5, characterized in that, The at least one gate conductive layer includes at least two gate conductive layers; The first sub-initialization voltage line, the second sub-initialization voltage line, and the third sub-initialization voltage line are each located in two gate conductive layers.

7. The display panel according to claim 6, characterized in that, The first initialization voltage line, which is located outside the two gate conductive layers among the first sub-initialization voltage line, the second sub-initialization voltage line, and the third sub-initialization voltage line, is located between the two gate conductive layers and the electrode layer.

8. The display panel according to claim 2, characterized in that, The first pixel circuit, the second pixel circuit, and the third pixel circuit are configured to be electrically connected to three different color light-emitting elements.

9. The display panel according to claim 1, characterized in that, One of the first pixel circuit and the second pixel circuit is configured to be electrically connected to two different color light-emitting elements.

10. The display panel according to claim 1, characterized in that, Each pixel circuit includes a first transistor, a second transistor, a driving transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a capacitor; The gate of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the second node, and the second electrode of the driving transistor is connected to the third node; The first terminal of the fourth transistor is connected to the data signal terminal, the second terminal of the fourth transistor is connected to the second node, and the gate of the fourth transistor is connected to the first gate drive signal terminal. The first terminal of the fifth transistor is connected to the first power supply terminal, the second terminal of the fifth transistor is connected to the second node, and the gate of the fifth transistor is connected to the enable signal terminal. The first terminal of the second transistor is connected to the first node, the second terminal of the second transistor is connected to the third node, and the gate of the second transistor is connected to the second gate drive signal terminal. The first terminal of the sixth transistor is connected to the third node, the second terminal of the sixth transistor is connected to the first terminal of the seventh transistor, and the gate of the sixth transistor is connected to the enable signal terminal. The first terminal of the first transistor is connected to the first node, the second terminal of the first transistor is connected to the first initial signal terminal, and the gate of the first transistor is connected to the first reset signal terminal. The second terminal of the seventh transistor is connected to the second initial signal terminal, the gate of the seventh transistor is connected to the second reset signal terminal, the initialization circuit includes the seventh transistor, and the first initialization voltage line is electrically connected to the second initial signal terminal; The gate of the eighth transistor is connected to the second reset signal terminal, the first terminal of the eighth transistor is connected to the third initial signal terminal, and the second terminal of the eighth transistor is connected to the second node; The capacitor is connected between the first power supply terminal and the first node.

11. The display panel according to claim 10, characterized in that, Also includes: A first active layer is located between the electrode layer and the substrate, and at least one of the at least three conductive layers is located between the first active layer and the electrode layer. The first active layer includes active layer patterns of the first transistor and the second transistor, and the active layer patterns of the first transistor and the second transistor in the same pixel circuit are integrated patterns.

12. The display panel according to claim 10, characterized in that, Also includes: A first active layer is located between the electrode layer and the substrate, and at least one of the at least three conductive layers is located between the first active layer and the electrode layer. The first active layer includes a first active layer pattern of the first transistor and a second active layer pattern of the second transistor. In the same pixel circuit, the first active layer pattern and the second active layer pattern are connected through at least one of the at least three conductive layers.

13. The display panel according to claim 1, characterized in that, Also includes: The second active layer is located between the at least three conductive layers and the substrate. Each pixel circuit includes multiple transistors, and the second active layer includes an active layer pattern of at least some of the multiple transistors. The plurality of pixel circuits are arranged in an array along a first direction and a second direction, at least one of the first initialization voltage lines extends along the first direction, and the first direction intersects the second direction; Two adjacent pixel circuits arranged along the first direction include a first specific pixel circuit and a second specific pixel circuit, and the active layer patterns of the first specific pixel circuit and the second specific pixel circuit are symmetrically distributed with respect to the center line extending along the second direction.

14. The display panel according to claim 13, characterized in that, Also includes: Multiple auxiliary signal lines extend along the second direction and are located on the side of the first initialization voltage line away from the substrate. Wherein, at least a portion of the auxiliary signal lines are projected onto the plane of the second active layer at the center line, and at least one of the at least a portion of the auxiliary signal lines is electrically connected to the first initialization voltage line.

15. The display panel according to claim 13, characterized in that, Also includes: Multiple auxiliary signal lines extend along the second direction and are located on the side of the first initialization voltage line away from the substrate. A first power signal line is located in one of the at least three conductive layers, and at least a portion of the first power signal line extends along the first direction. The second initialization voltage line is disposed on the same layer as the first power signal line and extends along the first direction; The third initialization voltage line is disposed on the same layer as the first power signal line and extends along the first direction; Wherein, at least a portion of the auxiliary signal lines are projected onto the plane where the active layer is located at the center line, and the at least a portion of the auxiliary signal lines are electrically connected to at least one of the first initialization voltage line, the second initialization voltage line, the third initialization voltage line, and the first power signal line.

16. The display panel according to claim 13, characterized in that, The plurality of pixel circuits are divided into a plurality of pixel circuit groups, each pixel circuit group including four pixel circuits arranged along the first direction, two of the four pixel circuits being configured to be electrically connected to a first color light-emitting element, and the other two of the four pixel circuits being configured to be electrically connected to a second color light-emitting element and a third color light-emitting element, respectively.

17. The display panel according to claim 16, characterized in that, The four pixel circuits include a first sub-pixel circuit, a second sub-pixel circuit, a third sub-pixel circuit, and a fourth sub-pixel circuit arranged in sequence. The first sub-pixel circuit is electrically connected to the second color light-emitting element, the second sub-pixel circuit is electrically connected to the first color light-emitting element, the third sub-pixel circuit is electrically connected to the third color light-emitting element, and the fourth sub-pixel circuit is electrically connected to the first color light-emitting element.

18. The display panel according to claim 17, characterized in that, The active layer patterns of the first sub-pixel circuit and the active layer patterns of the second sub-pixel circuit are symmetrically distributed with respect to the center line extending along the second direction between them, and the active layer patterns of the third sub-pixel circuit and the active layer patterns of the fourth sub-pixel circuit are symmetrically distributed with respect to the center line extending along the second direction between them.

19. The display panel according to claim 1, characterized in that, Also includes: An isolation structure is located on the side of the at least three conductive layers away from the substrate. The display panel includes a plurality of sub-pixels, each sub-pixel including the pixel circuit and a light-emitting element electrically connected to the pixel circuit. The light-emitting element includes a first electrode, a light-emitting functional layer and a second electrode stacked together. The electrode layer includes the first electrode of each of the plurality of sub-pixels. The first electrode is located between the light-emitting functional layer and the substrate, and the first electrode is electrically connected to the pixel circuit. The plurality of sub-pixels are divided into a plurality of pixel units, each pixel unit including two first color sub-pixels, one second color sub-pixel and one third color sub-pixel; The isolation structure is located at least between the light-emitting regions of the first color sub-pixel and the third color sub-pixel, and is configured to isolate at least a portion of the light-emitting functional layer.

20. The display panel according to claim 19, characterized in that, Also includes: The spacer is located on the side of the light-emitting functional layer away from the substrate. The plurality of sub-pixels include a first pixel group and a second pixel group arranged along a first direction, the first pixel group and the second pixel group being staggered along a second direction, and the first direction intersecting the second direction; The first pixel group includes second color sub-pixels and the third color sub-pixels arranged alternately along the second direction, and the second pixel group includes first color sub-pixels arranged along the second direction; The spacer includes at least one sub-spacer located between the light-emitting area of ​​the second color sub-pixel and the light-emitting area of ​​the third color sub-pixel and the light-emitting area of ​​the first color sub-pixel, and the spacer does not overlap with the isolation structure in a direction perpendicular to the substrate.

21. The display panel according to claim 19, characterized in that, Also includes: The spacer is located on the side of the light-emitting functional layer away from the substrate. The plurality of sub-pixels include a first pixel group and a second pixel group arranged along a first direction, the first pixel group and the second pixel group being staggered along a second direction, and the first direction intersecting the second direction; The first pixel group includes second color sub-pixels and the third color sub-pixels arranged alternately along the second direction, and the second pixel group includes first color sub-pixels arranged along the second direction; The spacer includes multiple sub-spacers, with the two sub-spacers closest to the light-emitting area of ​​the same first color sub-pixel being symmetrically distributed with respect to the line connecting the center of the light-emitting area of ​​the first color sub-pixel and the center of the light-emitting area of ​​the adjacent second or third color sub-pixel.

22. The display panel according to claim 19, characterized in that, The isolation structure includes multiple sub-isolation structures, and at least one sub-isolation structure is provided between the first color sub-pixel and the third color sub-pixel.

23. The display panel according to claim 19, characterized in that, Also includes: A metal layer is located between the electrode layer and the at least three conductive layers; The first electrode includes a main electrode and a connecting electrode, wherein the connecting electrode is electrically connected to the pixel circuit; The metal layer includes a first power signal line connection and a transition portion. The first power signal line connection extends along a second direction and is arranged to form an opening. The transition portion is provided inside the opening. The connection electrode of at least one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is electrically connected to the transistor in the pixel circuit through the adapter; In the extending direction of the connecting electrode, the size ratio of the connecting electrode to the main electrode is 0.3 to 0.

6.

24. The display panel according to claim 23, characterized in that, The connection electrode of the first color sub-pixel extends along the second direction, and the connection electrodes of the second color sub-pixel and the third color sub-pixel extend along the first direction, which intersects with the second direction; Along the second direction, the ratio of the size of the connection electrode of the first color sub-pixel to the size of the corresponding opening is 0.25 to 0.35; Along the first direction, the ratio of the size of the connecting electrode of the second color sub-pixel to the size of the corresponding opening is 0.45 to 0.65, and the ratio of the size of the connecting electrode of the third color sub-pixel to the size of the corresponding opening is 0.45 to 0.

65.

25. The display panel according to claim 23, characterized in that, The connection electrode of the first color sub-pixel extends along a first direction, and the connection electrodes of the second color sub-pixel and the third color sub-pixel extend along a second direction, wherein the first direction intersects the second direction; Along the first direction, the ratio of the size of the connection electrode of the first color sub-pixel to the size of the corresponding opening is 0.35 to 0.45; Along the second direction, the ratio of the size of the connecting electrode of the second color sub-pixel to the size of the corresponding opening is 0.25 to 0.40, and the ratio of the size of the connecting electrode of the third color sub-pixel to the size of the corresponding opening is 0.25 to 0.

40.

26. The display panel according to claim 19, characterized in that, Also includes: A metal layer is located between the electrode layer and the at least three conductive layers; The first electrode includes a main electrode and a connecting electrode, wherein the connecting electrode is electrically connected to the pixel circuit; The metal layer includes a first power signal line connection and a transition portion. The first power signal line connection extends along a second direction and is arranged to form an opening. The transition portion is provided inside the opening. The connection electrode of at least one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is electrically connected to the transistor in the pixel circuit through the adapter; The connecting electrode of the first color sub-pixel extends along the second direction, and the ratio of the size of the connecting electrode of the first color sub-pixel to the size of the corresponding transition part along the second direction is 1.1 to 1.

4. The connecting electrode of the second color sub-pixel and the connecting electrode of the third color sub-pixel extend along a first direction. Along the first direction, the size ratio of the connecting electrode of the second color sub-pixel to the corresponding transition part is 1.1 to 1.4, and the size ratio of the connecting electrode of the third color sub-pixel to the corresponding transition part is 1.1 to 1.

4.

27. The display panel according to claim 26, characterized in that, The adapter portion connected to the connection electrode of the first color sub-pixel extends along the first direction; The first power signal line connection includes two strip-shaped portions surrounding the opening and extending along the second direction, and the connection electrode of the first color sub-pixel overlaps with one of the two strip-shaped portions; The width of the stripe overlapping the connection electrode of the first color sub-pixel is less than the width of the other of the two stripes, or the widths of the two stripes are the same; In the first direction, the ratio of the width of the strip overlapping the connection electrode of the first color sub-pixel to the size of the opening is 0.15 to 0.

25.

28. The display panel according to claim 26, characterized in that, The opening includes a partition extending along the second direction; The at least one color sub-pixel includes two different color sub-pixels, and the two transition portions connected to the connection electrodes of the two different color sub-pixels are both located inside the opening and are located on both sides of the partition, and the two transition portions extend in different directions; The first power signal line connection includes two strips that surround the opening and extend in the second direction. In the first direction, the width of at least one of the two strips is 0.15 to 0.25 times the size of the opening.

29. The display panel according to claim 19, characterized in that, Also includes: A metal layer is located between the electrode layer and the at least three conductive layers; The first electrode includes a main electrode and a connecting electrode, wherein the connecting electrode is electrically connected to the pixel circuit; The metal layer includes a first power signal line connection and a transition portion. The first power signal line connection extends along a second direction and includes a transmission portion and a strip-shaped connection portion located between adjacent transmission portions. The width of the strip-shaped connection portion is smaller than the width of the transmission portion. The connecting section is provided between the adjacent transmission sections, and the connecting section is located on at least one side of the strip-shaped connecting section; The connection electrode of at least one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is electrically connected to the transistor in the pixel circuit through the adapter.

30. The display panel according to claim 29, characterized in that, Two types of transition portions are provided on both sides of the strip-shaped connecting portion. The two types of transition portions extend in different directions and are configured to be electrically connected to the connecting electrodes of two different color sub-pixels.

31. The display panel according to claim 22, 25 or 29, characterized in that, Along a direction perpendicular to the substrate, the connection electrode of the at least one color sub-pixel does not overlap with the isolation structure.

32. The display panel according to claim 31, characterized in that, Along a direction perpendicular to the substrate, the connection electrodes of at least two color sub-pixels do not overlap with the isolation structure.

33. The display panel according to claim 32, characterized in that, Along the direction perpendicular to the substrate, the connection electrodes of each color sub-pixel do not overlap with the isolation structure.

34. The display panel according to claim 31, characterized in that, The area of ​​the main electrode of the third color sub-pixel is larger than that of the main electrodes of the other color sub-pixels, and the length of the connecting electrode of the third color sub-pixel is shorter than that of the connecting electrode of the other color sub-pixels. Along a direction perpendicular to the substrate, the connection electrode of the third color sub-pixel does not overlap with the isolation structure.

35. The display panel according to claim 34, characterized in that, Along a direction perpendicular to the substrate, the connection electrode of at least one color sub-pixel other than the third color sub-pixel overlaps with the isolation structure.

36. The display panel according to claim 1, characterized in that, The display panel includes a plurality of sub-pixels, each sub-pixel including the pixel circuit and a light-emitting element electrically connected to the pixel circuit. The light-emitting element includes a first electrode, a light-emitting functional layer and a second electrode stacked together. The electrode layer includes the first electrode in each of the plurality of sub-pixels. The first electrode is located between the light-emitting functional layer and the substrate, and the first electrode is electrically connected to the pixel circuit. The second electrode includes a first sub-layer and a second sub-layer stacked together, with the second sub-layer located between the first sub-layer and the second electrode. The material of the first sub-layer includes silver, and the material of the second sub-layer includes a transparent metal oxide.

37. The display panel according to claim 36, characterized in that, The transparent metal oxide includes indium zinc oxide.

38. The display panel according to claim 36, characterized in that, The plurality of sub-pixels includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; The number of light-emitting layers in the light-emitting functional layer of the third color sub-pixel is not less than the number of light-emitting layers in the light-emitting functional layers of other color sub-pixels.

39. The display panel according to claim 36, characterized in that, Also includes: The optically coupled output layer is located on the side of the second electrode away from the light-emitting functional layer. The optical coupling output layer includes a first optical coupling output layer and a second optical coupling output layer stacked together. The first optical coupling output layer is located between the second optical coupling output layer and the second electrode. The refractive index of the first optical coupling output layer is greater than that of the second optical coupling output layer.

40. The display panel according to claim 36, characterized in that, Also includes: The encapsulation layer is located on the side of the second electrode away from the light-emitting functional layer. The encapsulation layer includes a first encapsulation layer and a second encapsulation layer stacked together. The second encapsulation layer is located on the side of the first encapsulation layer away from the second electrode, and the density of the first encapsulation layer is higher than that of the second encapsulation layer.

41. The display panel according to claim 36, characterized in that, The plurality of sub-pixels includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; The light-emitting functional layer includes a first light-emitting unit and a second light-emitting unit stacked together. The first light-emitting unit is located between the second light-emitting unit and the first electrode. The first light-emitting unit includes at least one light-emitting layer, and the second light-emitting unit includes at least one light-emitting layer. The light-emitting functional layer includes a first charge-generating layer and a second charge-generating layer disposed between the first light-emitting unit and the second light-emitting unit and stacked thereon, wherein the first charge-generating layer is located between the second charge-generating layer and the substrate. The distance between the first light-emitting unit and the first electrode is the first distance L1, the distance between the interface between the first charge-generating layer and the second charge-generating layer and the first light-emitting unit is the second distance L2, the distance between the interface and the second light-emitting unit is the third distance L3, and the distance between the second light-emitting unit and the second electrode is the fourth distance L4. The second distance L2 of each color sub-pixel is equal, and the fourth distance L4 of each color sub-pixel is equal.

42. The display panel according to claim 41, characterized in that, In the second color sub-pixel, the second distance L2 and the first distance L1 satisfy: 0.3≤L2 / L1≤0.5; in the first color sub-pixel, the second distance L2 and the first distance L1 satisfy: 0.5≤L2 / L1≤0.7; in the third color sub-pixel, the second distance L2 and the first distance L1 satisfy: 0.6≤L2 / L1≤0.

8.

43. The display panel according to claim 41, characterized in that, The distance between the distant surfaces of the first light-emitting unit is the fifth distance L5, which is the thickness of the first light-emitting unit. In the second color sub-pixel, the fifth distance L5 satisfies: 40 nm ≤ L5 ≤ 50 nm; in the first color sub-pixel, the fifth distance L5 satisfies: 30 nm ≤ L5 ≤ 40 nm; in the third color sub-pixel, the fifth distance L5 satisfies: 15 nm ≤ L5 ≤ 25 nm.

44. The display panel according to claim 41, characterized in that, The distance between the distant surfaces of the second light-emitting unit is the sixth distance L6, which is the thickness of the second light-emitting unit. In the second color sub-pixel, the sixth distance L6 satisfies: 40 nm ≤ L6 ≤ 50 nm; in the first color sub-pixel, the sixth distance L6 satisfies: 30 nm ≤ L6 ≤ 40 nm; in the third color sub-pixel, the sixth distance L6 satisfies: 15 nm ≤ L6 ≤ 25 nm.

45. The display panel according to claim 41, characterized in that, The distance between the first electrode and the second electrode is the eighth distance L. In the second color sub-pixel, the fourth distance L4 and the eighth distance L satisfy: 0.10≤L4 / L≤0.15; in the first color sub-pixel, the fourth distance L4 and the eighth distance L satisfy: 0.14≤L4 / L≤0.19; in the third color sub-pixel, the fourth distance L4 and the eighth distance L satisfy: 0.17≤L4 / L≤0.

22.

46. ​​The display panel according to claim 41, characterized in that, The distance between the second electrode and the first light-emitting unit is a seventh distance L7, and the distance between the first electrode and the second electrode is an eighth distance L. In the second color sub-pixel, the seventh distance L7 and the eighth distance L satisfy: 0.60≤L7 / L≤0.66; in the first color sub-pixel, the seventh distance L7 and the eighth distance L satisfy: 0.63≤L7 / L≤0.70; in the third color sub-pixel, the seventh distance L7 and the eighth distance L satisfy: 0.67≤L7 / L≤0.

73.

47. A display device, characterized in that, Includes the display panel as described in any one of claims 1-46.

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