A package structure of a power management chip

Abstract

The application relates to the technical field of power supply, in particular to a packaging structure of a power management chip. The packaging structure of the power management chip comprises a packaging body, high-voltage pins and low-voltage pins, the high-voltage pins and the low-voltage pins are arranged on opposite sides of the packaging body, a heat conduction layer is arranged on the top and / or bottom of the packaging body and is used for heat dissipation, and the heat conduction layer is arranged in a suspended mode or a grounded mode. The packaging structure of the power management chip improves the voltage resistance, safety and heat dissipation performance of the power management chip.

Description

Technical Field

[0001] This application relates to the field of power technology, and in particular to a packaging structure for a power management chip. Background Technology

[0002] In isolated converters such as flyback converters and LLC resonant converters, power management chips typically need to process both high-voltage and low-voltage signals simultaneously. High-voltage signals include the drain voltage of the primary-side power switch and the input voltage of the high-voltage startup circuit, while low-voltage signals include the output voltage feedback signal, the chip's supply voltage, drive signals, and compensation signals. Accordingly, the power management chip's package structure needs to include multiple high-voltage pins and multiple low-voltage pins to achieve electrical connections between the chip's internal and external circuits.

[0003] However, existing packaging structures are limited by the physical spacing between high-voltage and low-voltage pins due to the side dimensions of the package. Within this limited package area, it is difficult to establish sufficient creepage distance between the high-voltage and low-voltage pins. This results in high voltages (e.g., hundreds of volts of DC bus voltage or switching node voltage) on the high-voltage pins potentially causing surface discharge or breakdown through the insulating medium between the pins when the power management chip operates in high-voltage input scenarios (such as flyback converters with a wide input voltage range). This can damage circuit components on the low-voltage pins and even lead to system failure. Simultaneously, high-frequency switching noise from the high-voltage side can easily couple to the low-voltage side through parasitic capacitance between the pins, affecting the accuracy of the feedback signal and the stability of chip control, thereby reducing the overall reliability and safety of the power management chip.

[0004] Furthermore, with the increasing integration and power density of power management chips, the heat dissipation problem of these chips is becoming increasingly prominent. Utility Model Content

[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide a packaging structure for a power management chip that improves the chip's voltage resistance, safety, and heat dissipation performance.

[0006] To achieve the above objectives, this application provides a packaging structure for a power management chip, including... Package; High-voltage pins and low-voltage pins are respectively disposed on opposite sides of the package body; the high-voltage pins include SW pins and HV pins, the SW pins are used to connect one end of the primary winding of the transformer, and the HV pins are used to connect the DC input bus and the other end of the primary winding of the transformer; A thermally conductive layer is disposed on the top and / or bottom of the package for heat dissipation; The heat-conducting layer is either suspended or grounded; The package includes an insulating substrate, on which a first region, a second region, and a third region are disposed that are isolated from each other. The first region carries the primary-side switching transistor, and the SW pin is electrically connected to the drain of the primary-side switching transistor; The second region carries the startup module, and the HV pin is electrically connected to the startup module; The third region carries the control module, which is electrically connected to the gate and source of the primary-side switching transistor, the startup module, and the low-voltage pin.

[0007] Furthermore, when the thermal conductive layer is grounded, the distance between the thermal conductive layer and the high-voltage pin is greater than the distance between the thermal conductive layer and the low-voltage pin.

[0008] Furthermore, the low-voltage pin includes a VDD pin, a GND pin, and an FB pin. The VDD pin is a power supply pin, the GND pin is a ground pin, and the FB pin is used for output voltage feedback.

[0009] Furthermore, the low-voltage pin also includes at least one of a DMG pin, a CS pin, and a COMP pin; the DMG pin is used for primary-side resonance detection and / or input voltage detection, the CS pin is used for primary-side current detection, and the COMP pin is used for output error voltage compensation.

[0010] Furthermore, the low-voltage pin includes a VDD pin, a GND pin, and a COMP pin. The VDD pin is a power supply pin, the GND pin is a ground pin, and the COMP pin is used for output error voltage compensation.

[0011] Furthermore, the low-voltage pin also includes at least one of the following: a DMG pin, a GATEA pin, a BO pin, and a CS pin; the DMG pin is used for primary-side resonance detection, the GATEA pin is used to drive the ZVS switch, the BO pin is used for input voltage sampling, and the CS pin is used for primary-side current detection.

[0012] Furthermore, conductive adhesive is applied to the first and second regions, and the SW pin is connected to the drain of the primary-side switching transistor through the conductive adhesive, while the HV pin is connected to the startup module through the conductive adhesive.

[0013] Furthermore, the control module is connected to the gate and source of the primary-side switching transistor, the startup module, and the low-voltage pin via bonding wires.

[0014] Furthermore, the primary-side switching transistor and the starting module are manufactured using a high-voltage process, while the control module is manufactured using a low-voltage process.

[0015] Compared with the prior art, the packaging structure of the power management chip proposed in this application has the following advantages: The power management chip packaging structure of this application increases the creepage distance and improves withstand voltage performance and safety by setting high-voltage pins and low-voltage pins on opposite sides of the package. At the same time, the high-voltage signal path and the low-voltage signal path are far apart, reducing parasitic capacitance coupling between pins and preventing high-frequency switching noise from coupling to the low-voltage pin, thus improving control accuracy. Furthermore, by setting a heat-conducting layer that can be suspended or grounded, heat dissipation and electromagnetic shielding requirements are taken into account.

[0016] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the application circuit of an exemplary power management chip; Figure 2 This is a schematic diagram of the packaging structure of the power management chip in Embodiment 1 of this application; Figure 3 This is a schematic diagram of the packaging structure of the power management chip in Embodiment 2 of this application; Figure 4 This is a schematic diagram of the packaging structure of the power management chip in Embodiment 3 of this application; Figure 5 This is a schematic diagram of the packaging structure of the power management chip in Embodiment 4 of this application; Figure 6 This is a schematic diagram of the internal structure of the power management chip package according to Embodiment 5 of this application; Figure 7 This is a schematic diagram of the internal structure of the power management chip package according to Embodiment 6 of this application; In the figure: 10-Power management chip, 100-Package, 101-First side, 102-Second side, 103-Heat conductive layer, 104-Insulating substrate, 105-First region, 106-Second region, 107-Third region. Detailed Implementation

[0018] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0019] It should be understood that the steps described in the method embodiments of this application may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this application is not limited in this respect.

[0020] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0021] It should be noted that the terms "one" and "multiple" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "Multiple" should be understood as two or more.

[0022] Terminology Explanation: A power management chip is a control chip used in isolated converters (such as flyback converters and LLC resonant converters). It integrates control logic, drive circuits, and necessary functional modules to control the power switching transistors and regulate the output voltage. Figure 1 An exemplary application circuit diagram of a power management chip 10 is shown, such as... Figure 1 As shown, the power management chip 10 includes several pins, including high-voltage pins and low-voltage pins.

[0023] High-voltage pins refer to the pins in a power management chip used to connect high-voltage signals (such as DC input bus voltage, drain voltage of power switching transistors, etc.). Their normal operating voltage is typically in the tens to hundreds of volts range. High-voltage pins include the HV pin and the SW pin. The HV pin is used to connect to the DC input bus, enabling high-voltage startup. The SW pin is used to connect to the transformer and the drain of the primary-side power transistor, enabling switching node voltage detection and energy transfer.

[0024] Low-voltage pins refer to pins in power management chips used to connect low-voltage signals (such as supply voltage, ground, feedback signals, detection signals, etc.), and their normal operating voltage is typically in the range of several volts to tens of volts. Low-voltage pins may include one or more of the following: VDD pin, GND pin, CS pin, FB pin, COMP pin, and DMG pin.

[0025] The VDD pin is the power supply pin, used to connect to an external power supply; the GND pin is the ground pin; the CS pin is used for primary-side current detection; the FB pin is used for output voltage feedback, and its output feedback voltage is used to characterize the difference between the output voltage and the reference voltage; the COMP pin is the compensation pin, used to connect the compensation resistor and compensation capacitor to achieve output error voltage compensation; the DMG pin is used for primary-side resonance detection and / or input voltage detection. The HV pin is connected to the DC input bus (typically several hundred volts), the SW pin is connected to the primary winding of transformer T1 and the drain of the primary-side power transistor U1, the VDD pin is connected to the external power supply capacitor C1, the GND pin is connected to system ground, the CS pin is connected to the sampling resistor R2, the FB pin is connected to the secondary output of transformer T through the feedback network, the COMP pin is connected to the compensation network consisting of the second capacitor C2 and the fifth resistor R5, and the DMG pin is connected to the auxiliary winding.

[0026] In addition, the low-voltage pins may include a GATEA pin and / or a BO pin; the GATEA pin is used to drive the ZVS (zero voltage turn-on) switch in the chip application circuit, and is suitable for power supply circuits configured with ZVS switches; the BO pin is an input voltage sampling pin, used to sample the DC input bus voltage.

[0027] Understandable Figure 1 The pin types and functional definitions of the power management chip 10 shown are merely examples. In practical applications, the types and quantities of pins can be increased, decreased, or replaced according to actual application requirements. This application does not limit this.

[0028] Example 1 One embodiment of this application provides a packaging structure for a power management chip. Figure 2 This is a schematic diagram of the packaging structure of the power management chip in Embodiment 1 of this application, as shown below. Figure 2 As shown, the package structure of the power management chip in this application includes: The package 100 is generally rectangular and has opposing first sides 101 and second sides 102.

[0029] The high-voltage pin and the low-voltage pin are respectively located on opposite sides of the package 100. Specifically, the high-voltage pin is located on the first side 101 of the package 100, and the low-voltage pin is located on the second side 102 of the package 100.

[0030] For example, the high-voltage pins include an HV pin and an SW pin. The SW pin is typically used to connect one end of the primary winding of the transformer, and the HV pin is used to connect the DC input bus to the other end of the primary winding of the transformer. In this embodiment, the high-voltage pins are not specifically limited.

[0031] For example, the low-voltage pins include the VDD pin, the GND pin, and the FB pin. The VDD pin is the power supply pin, the GND pin is the ground pin, and the FB pin is used for output voltage feedback. In this embodiment, the low-voltage pins are not specifically limited.

[0032] In some other embodiments, the first side 101 and the second side 102 of the package 100 may also be provided with one or more NC pins (unused pins). The NC pins are not connected to any functional modules inside the package 100, but are only used for structural filling or as spares.

[0033] In other implementations, additional high-voltage or low-voltage pins can be added or replaced according to the application requirements of the actual power management chip. For example, for low-voltage pins, any one or more of the DMG pin, CS pin, GATEA pin, BO pin, and COMP pin can be replaced or added.

[0034] In this embodiment, the high-voltage pin and the low-voltage pin are respectively disposed on opposite sides of the package 100, which significantly increases the physical distance between the high-voltage pin and the low-voltage pin and the creepage distance along the surface of the package.

[0035] A thermally conductive layer 103 is provided on the top and / or bottom surfaces of the package 100.

[0036] The thermal conductive layer 103 is used to dissipate the heat generated during chip operation, thereby reducing the chip junction temperature. The thermal conductive layer 103 can be floating, i.e., not connected to any potential; or it can be grounded.

[0037] When the thermal conductive layer 103 is grounded, the distance between the thermal conductive layer 103 and the high-voltage pins (HV pin, SW pin) is greater than the distance between the thermal conductive layer 103 and the low-voltage pins (VDD pin, GND pin, FB pin). This retains the advantages of the thermal conductive layer in heat dissipation and electromagnetic interference suppression, while ensuring sufficient insulation distance between the high-voltage pins and the ground plane, preventing high voltage on the high-voltage pins from being discharged or discharged through the thermal conductive layer.

[0038] The thermally conductive layer 103 can be made of copper foil, aluminum foil, graphite sheet, or other materials with good thermal conductivity. The thermally conductive layer 103 can be bonded to the top and / or bottom surfaces of the package 100 using thermally conductive adhesive, or it can be formed by sputtering or electroplating a metal layer onto the surface of the package 100. The thickness of the thermally conductive layer 103 can be set according to actual heat dissipation requirements; for example, the thickness of the thermally conductive layer 103 ranges from 0.05 mm to 0.5 mm.

[0039] In this embodiment of the application, the package includes an insulating substrate, on which a first region, a second region, and a third region are disposed, which are isolated from each other; the first region carries a primary-side switching transistor, and the SW pin is electrically connected to the drain of the primary-side switching transistor; the second region carries a startup module, and the HV pin is electrically connected to the startup module; the third region carries a control module, and the control module is electrically connected to the gate and source of the primary-side switching transistor, the startup module, and the low-voltage pin, respectively.

[0040] In this embodiment, by placing the high-voltage pins (HV pin, SW pin) and the low-voltage pins (VDD pin, GND pin, FB pin) on opposite sides of the package 100, the creepage distance between the high-voltage pins and the low-voltage pins is increased, the risk of high-voltage signals breaking down to the low-voltage side along the surface of the package is reduced, and the voltage withstand performance and safety of the chip are improved.

[0041] In this embodiment, by physically separating the high-voltage signal path from the low-voltage signal path, parasitic capacitance coupling between pins is reduced, making it difficult for high-frequency switching noise to couple to low-voltage signal terminals such as the FB pin through parasitic paths. This ensures the accuracy of the feedback signal and improves the stability of the chip's control over the output voltage.

[0042] In this embodiment, the heat-conducting layer 103 can be either suspended or grounded, thus balancing the needs of heat dissipation and electromagnetic shielding. When the heat-conducting layer 103 is suspended, it does not have any additional impact on the withstand voltage of the high-voltage pin; when grounded, it can also serve as an electromagnetic shielding layer to suppress high-frequency noise radiation.

[0043] Example 2 One embodiment of this application provides a packaging structure for a power management chip. Figure 3 This is a schematic diagram of the packaging structure of the power management chip in Embodiment 2 of this application, as shown below. Figure 3 As shown, the difference between Embodiment 2 and Embodiment 1 is that the low-voltage pin also includes a DMG pin, a COMP pin, and a CS pin.

[0044] In this embodiment of the application, the high-voltage pin includes an HV pin and an SW pin, which are disposed on the first side 101 of the package 100.

[0045] In this embodiment, the low-voltage pins also include a DMG pin, a COMP pin, and a CS pin, which are disposed on the second side 102 of the package 100. The specific arrangement order of each pin can be adjusted according to actual application requirements. The CS pin is used for primary-side current detection, the COMP pin is used for output error voltage compensation, and the DMG pin is used for primary-side resonance detection and / or input voltage detection.

[0046] The functions of the remaining low-voltage pins are the same as in Example 1, and will not be repeated here.

[0047] It is understandable that the DMG pin, COMP pin, and CS pin can be selectively configured, either partially or entirely, depending on the specific needs of the chip. For example, only the DMG pin might be configured.

[0048] In Embodiment 2 of this application, the low-voltage pins are configured together (VDD, GND, DMG, COMP, CS, FB) to accommodate power management chips that require simultaneous output voltage feedback, primary-side current detection, output error voltage compensation, and resonant state monitoring. The physical isolation between the high-voltage and low-voltage pins is not affected by the increase in the number of low-voltage pins. Different numbers and functions of low-voltage pins can be flexibly arranged on the same side of the package, enabling the package structure to be compatible with chips with various functional combinations and providing excellent platform reuse capabilities.

[0049] Example 3 One embodiment of this application provides a packaging structure for a power management chip. Figure 4 This is a schematic diagram of the packaging structure of the power management chip in Embodiment 3 of this application, as shown below. Figure 4 As shown, the difference between Embodiment 3 and Embodiment 1 is that the low-voltage pin does not have an FB pin, but instead has a COMP pin. Furthermore, the low-voltage pin may also include a GATEA pin, a DMG pin, and a CS pin.

[0050] In this embodiment of the application, the high voltage pin still includes the HV pin and the SW pin, which are disposed on the first side 101 of the package 100.

[0051] In this embodiment, the low-voltage pins, in addition to the VDD and GND pins, mainly include the COMP pin, which is used for output error voltage compensation. This is suitable for power management chips with output error voltage compensation.

[0052] In this embodiment, the low-voltage pin also includes a GATEA pin, a DMG pin, and a CS pin; the GATEA pin is used to drive the ZVS switch in the chip application circuit. The SW pin is connected to the drain of the primary-side power transistor. The DMG pin is used for primary-side resonance detection and / or input voltage detection. Exemplarily, the DMG pin can be connected to the auxiliary winding of the transformer via a resistor divider network to detect the primary-side resonance state; alternatively, the DMG pin can be connected to the DC input bus via a resistor divider network to detect the input voltage value.

[0053] The CS pin is used for primary-side current sensing. For example, the CS pin is connected to a sampling resistor, and the voltage across the sampling resistor reflects the magnitude of the primary-side current. This voltage signal is input to the CS module inside the chip to control the on-time of the primary-side power transistor, thereby achieving cycle-by-cycle current limiting and overcurrent protection.

[0054] The low-voltage pins VDD, GND, COMP, GATEA, DMG, and CS are all located on the second side 102 of the package 100.

[0055] The GATEA, DMG, and CS pins can be selectively configured in some or all of them, depending on the specific needs of the chip. For example, only the DMG pin may be configured.

[0056] In Embodiment 3 of this application, while keeping the high-voltage pins unchanged, the low-voltage pins include VDD, GND, GATEA, DMG, COMP, and CS, which can adapt to power management chips with rich functions such as output error voltage compensation, primary-side current detection, and primary-side resonance detection. The layout of the high-voltage and low-voltage pins located on opposite sides of the package effectively avoids the problem of insufficient spacing between high and low voltage pins due to insufficient space on the sides of the package when the total number of pins is large. This allows the package structure to be suitable for chip products with higher functional integration but equally stringent voltage withstand requirements.

[0057] Example 4 One embodiment of this application provides a packaging structure for a power management chip. Figure 5 This is a schematic diagram of the packaging structure of the power management chip in Embodiment 4 of this application, as shown below. Figure 5 As shown, the difference between Embodiment 4 and Embodiment 3 is that the low-voltage pin does not include the GATEA pin, but instead has a BO pin.

[0058] In this embodiment of the application, the high-voltage pin includes an HV pin and an SW pin, which are disposed on the first side 101 of the package 100.

[0059] The low-voltage pins include VDD pin, GND pin, DMG pin, COMP pin, CS pin, and BO pin, which are located on the second side 102 of the package 100.

[0060] In this embodiment, the BO pin is an input voltage sampling pin used to sample the DC input bus voltage. Exemplarily, the BO pin is connected to the DC input bus via a resistor divider network. The sampled voltage signal is input to the chip's internal circuitry to implement functions such as input undervoltage protection, input overvoltage protection, or adjusting chip operating parameters based on the input voltage. The DMG pin is used for primary-side resonance detection, the CS pin for primary-side current detection, and the COMP pin for output error voltage compensation.

[0061] It should be noted that, in this application, the low-voltage pins on the actual power management chip include, but are not limited to, the VDD pin, GND pin, DMG pin, COMP pin, CS pin, BO pin, FB pin and GATEA pin mentioned above. Other pins used to connect low-voltage signals can also be used as low-voltage pins.

[0062] In Embodiment 4 of this application, the low-voltage pins are configured as VDD, GND, DMG, COMP, CS, and BO, which can adapt to power management chips that require independent input voltage sampling functions, such as applications that need to simultaneously implement input undervoltage protection, input overvoltage protection, and primary-side resonance detection. The independent BO pin allows input voltage sampling and primary-side resonance detection to be performed independently, without the need for time-division multiplexing via the DMG pin. This package structure, through physical isolation between the high-voltage and low-voltage sides, ensures that chips with independent input voltage sampling functions still maintain sufficient creepage distance between the high-voltage start-up pins and switching node pins and the low-voltage sampling pins.

[0063] Example 5 One embodiment of this application provides a packaging structure for a power management chip. Figure 6 This is a schematic diagram of the internal structure of the power management chip package according to Embodiment 5 of this application, as shown below. Figure 6 As shown, the internal layout structure illustrated in this embodiment is suitable for... Figure 2 The pin configuration shown in Embodiment 1 is that the high-voltage side consists of HV and SW pins, and the low-voltage side consists of VDD, GND, and FB pins. Of course, the low-voltage side can also be replaced with VDD, GND, and COMP pins. This embodiment further describes in detail the device partitioning layout structure inside the package based on Embodiment 1 above.

[0064] In this embodiment of the application, the power management chip package structure includes an insulating substrate 104, on which a first region 105, a second region 106, and a third region 107 are disposed, which are isolated from each other. The first region 105, the second region 106, and the third region 107 are electrically isolated from each other by an isolation groove or an insulating material on the surface of the insulating substrate 104.

[0065] The first region 105 carries the primary-side switch U1, which can be a power MOSFET. Conductive adhesive is applied to the surface of the first region 105, and the SW pin is connected to the drain of the primary-side switch U1 via the conductive adhesive, achieving a low-impedance electrical connection between the SW pin and the drain of the primary-side switch U1. The gate and source of the primary-side switch U1 are connected to the control module U3 via bonding wires.

[0066] The second region 106 houses the startup module U2, which enables high-voltage startup. Conductive adhesive is applied to the surface of the second region 106, and the HV pin is connected to the startup module U2 via this adhesive, achieving a low-impedance electrical connection between the HV pin and the startup module U2. The startup module U2 is connected to the control module U3 via bonding wires, and the HV pin charges the VDD pin for startup through both the startup module U2 and the control module U3.

[0067] The third region 107 carries the control module U3, which controls the primary-side switch U1 based on the feedback signal from the FB pin. The control module U3 is connected to the gate and source of the primary-side switch U1, the startup module U2, and each low-voltage pin (VDD pin, GND pin, FB pin) via bonding wires.

[0068] For example, the control module U3 is connected to the VDD pin via a bonding wire to power the chip; connected to the GND pin via a bonding wire to ground the chip; and connected to the FB pin via a bonding wire to receive the output voltage feedback signal.

[0069] In this embodiment, the bonding wire is gold wire, copper wire, or aluminum wire.

[0070] In other variations, the bonding wires may also be made of copper sheets, aluminum strips, or other types of conductive connecting strips.

[0071] In a preferred embodiment of this invention, the primary-side switch U1 and the startup module U2 are fabricated using a high-voltage process (such as BCD or high-voltage CMOS), while the control module U3 is fabricated using a low-voltage process (such as standard CMOS). Since the first region 105, the second region 106, and the third region 107 are isolated from each other on the insulating substrate 104, different regions can accommodate devices fabricated using different processes, thereby reducing the manufacturing difficulty and cost of a single chip simultaneously supporting both high and low voltage processes.

[0072] In this embodiment, a thermally conductive layer 103 is disposed on the top and / or bottom surface of the package 100. The thermally conductive layer 103 covers at least a portion of the third region 107 and is used to dissipate heat generated during the operation of the control module U3. The thermally conductive layer 103 can be suspended or grounded. When the thermally conductive layer 103 is grounded, the spacing between the thermally conductive layer 103 and the high-voltage pins (HV pin, SW pin) is greater than the spacing between the thermally conductive layer 103 and the low-voltage pins (VDD pin, GND pin, FB pin).

[0073] In a preferred embodiment of this example, the conductive adhesive laid in the first region 105 and the second region 106 is silver paste or solder paste, and the thickness of the conductive adhesive ranges from 0.01 mm to 0.1 mm.

[0074] In a preferred embodiment of this example, the bonding wire between the control module U3 and each low-voltage pin is a gold wire, copper wire, or aluminum wire, and the diameter of the bonding wire ranges from 0.015 mm to 0.05 mm.

[0075] In Embodiment 5 of this application, by carrying the primary-side switch U1, the startup module U2, and the control module U3 on three mutually isolated areas on the insulating substrate 104, the high-voltage devices such as the primary-side switch U1 and the startup module U2 are further physically isolated from the low-voltage device, the control module U3, thus meeting the packaging requirements of power management chips that integrate power switches and high-voltage startup modules and have a small number of pins.

[0076] In Embodiment 5 of this application, conductive adhesive is used to connect the SW pin to the drain of U1 and the HV pin to U2, so that the high voltage and high current path has low impedance characteristics, reducing conduction loss and parasitic inductance; by using bonding wire to connect the gate / source of U3 to U1, U2 and each low voltage pin, the transmission path of the control signal is short and direct.

[0077] In Embodiment 5 of this application, high-voltage devices and low-voltage devices are carried and isolated in separate packages, so that U1 and U2 can be manufactured using high-voltage processes and U3 can be manufactured using low-voltage processes. After different regions carry devices of different processes, they are packaged and integrated, which reduces the manufacturing difficulty and cost of a single chip that needs to be compatible with both high and low voltage processes.

[0078] Example 6 One embodiment of this application provides a packaging structure for a power management chip. Figure 7 This is a schematic diagram of the internal structure of the power management chip package according to Embodiment 6 of this application. The internal layout structure shown in this embodiment is applicable to... Figure 3 The pin configuration of Embodiment 2 shown is as follows: Figure 7As shown, the high-voltage side consists of the HV and SW pins, while the low-voltage side consists of the VDD, GND, DMG, COMP, CS, and FB pins. This embodiment, based on Embodiment 2 above, further details the internal device partitioning layout structure of the package.

[0079] In this embodiment, the package 100 of the power management chip includes an insulating substrate 104, on which are disposed mutually isolated first regions 105, second regions 106, and third regions 107. The first region 105 carries the primary-side switching transistor U1, with its SW pin connected to the drain of U1 via conductive adhesive. The gate and source of U1 are connected to the control module U3 via bonding wires. The second region 106 carries the startup module U2, with its HV pin connected to it via conductive adhesive. The startup module U2 is connected to the control module U3 via bonding wires. The third region 107 carries the control module U3, which is connected to the DMG pin, COMP pin, CS pin, FB pin, VDD pin, and GND pin via bonding wires.

[0080] In this embodiment, the CS pin is connected to the control module U3 through the conductive adhesive of the third region 107. The control module U3 is also connected to the DMG pin, COMP pin, VDD pin, GND pin and FB pin through bonding wires.

[0081] In this embodiment, the primary-side current detection signal input at the CS pin is transmitted to the control module U3 to control the on-time of the primary-side switch U1. The control module U3 also integrates a feedback control loop; the feedback signal input at the FB pin is transmitted to the feedback control loop to control the turn-on of the primary-side switch U1. The control module U3 also integrates a compensation circuit; the compensation resistor and compensation capacitor connected to the COMP pin are used to compensate for the output error voltage.

[0082] In this embodiment, the primary-side switch U1 is a power MOSFET. Its drain is connected to the SW pin via conductive adhesive, its source is connected to the source detection terminal of the control module U3 via a bonding wire, and its gate is connected to the drive output terminal of the control module U3 via a bonding wire. Based on the feedback signal from the FB pin and the current detection signal from the CS pin, the control module U3 outputs a PWM control signal to the gate of the primary-side switch U1 via its drive output terminal, thereby controlling the turn-on and turn-off of the primary-side switch U1.

[0083] In this embodiment, the isolation between the first region 105, the second region 106 and the third region 107 on the insulating substrate 104 can be achieved by: forming an isolation groove on the surface of the insulating substrate 104, the depth of which is greater than the thickness of the conductive adhesive; or by coating the surface of the insulating substrate 104 with an insulating material (such as polyimide or epoxy resin) to electrically isolate the different regions.

[0084] In Embodiment 6 of this application, multiple low-voltage pins, such as DMG pin, COMP pin, CS pin, and FB pin, are all located on the second side 102 of the package body 100. Combined with the mutually isolated three-region layout on the insulating substrate 104, this package structure can be adapted to power management chips with a larger number of low-voltage pins and more complex functions.

[0085] In Embodiment 6 of this application, the package structure combines a multi-pin configuration with a three-region partitioned layout, enabling a power management chip that integrates a switching transistor and a startup module internally, and requires external connection to a sampling resistor, compensation network, feedback network, and auxiliary winding, to achieve fan-out of all functional pins while ensuring high and low voltage isolation.

[0086] The above description is merely a partial embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

[0087] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in sequential order. Multitasking and parallel processing may be advantageous in certain environments. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this application. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0088] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A packaging structure for a power management chip, characterized in that, include: Package; High-voltage pins and low-voltage pins are respectively disposed on opposite sides of the package body; the high-voltage pins include SW pins and HV pins, the SW pins are used to connect one end of the primary winding of the transformer, and the HV pins are used to connect the DC input bus and the other end of the primary winding of the transformer; A thermally conductive layer is disposed on the top and / or bottom of the package for heat dissipation; the thermally conductive layer is either suspended or grounded. The package includes an insulating substrate, on which a first region, a second region, and a third region are disposed that are isolated from each other. The first region carries the primary-side switching transistor, and the SW pin is electrically connected to the drain of the primary-side switching transistor; The second region carries the startup module, and the HV pin is electrically connected to the startup module; The third region carries the control module, which is electrically connected to the gate and source of the primary-side switching transistor, the startup module, and the low-voltage pin.

2. The packaging structure of the power management chip according to claim 1, characterized in that, When the thermal conductive layer is grounded, the distance between the thermal conductive layer and the high-voltage pin is greater than the distance between the thermal conductive layer and the low-voltage pin.

3. The packaging structure of the power management chip according to claim 1, characterized in that, The low-voltage pins include a VDD pin, a GND pin, and an FB pin. The VDD pin is the power supply pin, the GND pin is the ground pin, and the FB pin is used for output voltage feedback.

4. The packaging structure of the power management chip according to claim 3, characterized in that, The low-voltage pin also includes at least one of a DMG pin, a CS pin, and a COMP pin; the DMG pin is used for primary-side resonance detection and / or input voltage detection, the CS pin is used for primary-side current detection, and the COMP pin is used for output error voltage compensation.

5. The packaging structure of the power management chip according to claim 1, characterized in that, The low-voltage pins include a VDD pin, a GND pin, and a COMP pin. The VDD pin is the power supply pin, the GND pin is the ground pin, and the COMP pin is used for output error voltage compensation.

6. The packaging structure of the power management chip according to claim 5, characterized in that, The low-voltage pin also includes at least one of the following: DMG pin, GATEA pin, BO pin, and CS pin; the DMG pin is used for primary-side resonance detection, the GATEA pin is used to drive an external ZVS switch, the BO pin is used for input voltage sampling, and the CS pin is used for primary-side current detection.

7. The packaging structure of the power management chip according to claim 1, characterized in that, The first and second regions are covered with conductive adhesive. The SW pin is connected to the drain of the primary-side switching transistor through the conductive adhesive, and the HV pin is connected to the startup module through the conductive adhesive.

8. The packaging structure of the power management chip according to claim 7, characterized in that, The control module is connected to the gate and source of the primary-side switching transistor, the startup module, and the low-voltage pin via bonding wires.

9. The packaging structure of the power management chip according to claim 1, characterized in that, The primary-side switching transistor and the starting module are manufactured using a high-voltage process, while the control module is manufactured using a low-voltage process.

Images