A double-sided heat dissipation power module with low parasitic inductance
Patent Information
- Application Number
- CN202522251825.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-24
- Publication Date
- 2026-09-08
- Estimated Expiration
- 2035-10-24
AI Technical Summary
通常采用引线键合的方式来实现芯片与芯片之间、芯片与基板之间的电气连接，存在较大的寄生参数，如寄生电感，较大的寄生参数会导致模块在运行过程中出现电压过冲、电压震荡等可靠性问题，并且多芯片并联模块的布局，杂感分布不均也会引起均流问题，大大限制了SiC模块的高频性能
[0030] (1) By symmetrically and uniformly arranging multiple SiCMOSFET power chips on opposite substrates, combined with the design of the first substrate, second substrate, metal connection components, and terminal layout, the mutual inductance between adjacent parallel circulating current loops of the power module cancels out, significantly reducing the parasitic inductance of the power module and reducing module heat loss. At the same time, the opposite first and second substrates increase the heat dissipation path, improving the module's heat dissipation capacity. Further multi-chip symmetrical arrangement design reduces module size and weight, and increases power density;
Smart Images
Figure CN224734168U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor power device technology, and in particular to a double-sided heat dissipation power module with low parasitic inductance. Background Technology
[0002] Power modules are power electronic devices widely used in various power equipment, such as communication equipment, electric vehicles, and power supply equipment. Their basic principle is to use high-frequency switching to control the power supply, thereby controlling voltage and current. However, traditional silicon-based power modules are increasingly unable to meet the demands of high-power applications for high temperature and high power density. In contrast, SiC power modules, due to their low switching losses, high switching speed, and high-temperature resistance, can significantly improve efficiency and reduce energy consumption, contributing to system miniaturization, high efficiency, and low weight.
[0003] SiC power modules typically employ a multi-chip parallel configuration to meet high-power applications. Wire bonding is commonly used to achieve electrical connections between chips and between chips and the substrate, which introduces significant parasitic parameters, such as parasitic inductance. These large parasitic parameters can lead to reliability issues during module operation, such as voltage overshoot and voltage oscillation. Furthermore, the uneven distribution of stray inductance in the multi-chip parallel module layout can cause current sharing problems, significantly limiting the high-frequency performance of SiC modules. In addition, in traditional packaging, single-sided substrate heat dissipation cannot simultaneously meet the requirements of high power density and high heat dissipation capacity. At high temperatures, the module's performance and reliability degrade, thus affecting system lifespan. In contrast, double-sided heat dissipation modules provide two heat dissipation paths for the SiC chips, improving both power electrical and thermal performance. Utility Model Content
[0004] The purpose of this utility model patent is to provide a low parasitic inductance double-sided heat dissipation power module, comprising a substrate assembly (1), a chip assembly (2), a metal connection assembly (3), bonding wires (4), and terminals (5); wherein,
[0005] The substrate assembly (1) includes a first substrate (11) and a second substrate (12), the second substrate (12) being located above the first substrate (11); the first substrate (11) and the second substrate (12) are provided with the metal connection assembly (3) and the chip assembly (2) in the height direction, and the metal connection assembly (3) and the chip assembly (2) are located between the first substrate (11) and the second substrate (12); the first substrate (11) includes a first conductive layer (111), a first ceramic layer (112) and a first heat dissipation layer (113), the first... The conductive layer (111) is used to connect to the chip assembly (2) and form a circuit between the first substrate (11) and the second substrate (12); the first heat dissipation layer (113) is used to connect to the copper base plate or the first heat sink (56); the second substrate (12) includes a second conductive layer (121), a second ceramic layer (122), and a second heat dissipation layer (123). The second conductive layer (121) is connected to the chip assembly (2) through a metal connection assembly (3) to form a circuit, and the second heat dissipation layer (123) is used to connect to the second heat sink (57).
[0006] The chip assembly (2) is disposed on the upper surface of the first substrate (11) and includes multiple parallel upper bridge arm chips (21) and multiple parallel lower bridge arm chips (22). The upper bridge arm chips (21) are arranged in parallel on one side of the first substrate (11); the lower bridge arm chips (22) are arranged in parallel on the other side of the first substrate (11) corresponding to the upper bridge arm chips (21), so that the chip assembly is arranged in parallel and mirror symmetrical distribution.
[0007] All terminals in each upper bridge arm chip (21) and all terminals in each lower bridge arm chip (22) are arranged along the long side of the first substrate;
[0008] The metal connection components (3) are all disposed between the first substrate (11) and the second substrate (12) for connecting the second substrate (12) with the source stage of the chip assembly (2), the upper surface of the first substrate (11) and the lower surface of the second substrate (12);
[0009] The terminal (5) includes a positive terminal (51), a negative terminal (52), an AC terminal (53), a gate control terminal (54), and a Kelvin source control terminal (55), all of which are laid on the upper surface of the first substrate (11).
[0010] Specifically, the first conductive layer (111) is divided into a first power circuit region (1111), a Kelvin source circuit region (1112), a gate circuit region (1113), and an NTC placement region (1114). The first power circuit region (1111), the Kelvin source circuit region (1112), the gate circuit region (1113), and the NTC placement region (1114) are divided into multiple independent circuits. The second conductive layer (121) contains multiple second power circuit regions (1211), and the second power circuit regions (1211) are divided into multiple independent circuits (1211-A~1211-F).
[0011] Furthermore, the terminals include a positive terminal (51), a negative terminal (52), an AC terminal (53), two gate control terminals (54), and two Kelvin source control terminals (55), wherein,
[0012] The positive terminal (51) and the negative terminal (52) are respectively connected to the first conductive layer (111) on the first substrate (11) to form a circuit; the positive terminal (51) and the negative terminal (52) are arranged at a height interval; the positive terminal (51) and the negative terminal (52) have a partial area overlap when projected onto the first substrate (11).
[0013] The AC terminal (53) is connected to the first conductive layer (111) on the upper surface of the first substrate (11), extends from the side of the first substrate (11), and is on the other side corresponding to the positive terminal (51) and the negative terminal (52);
[0014] Two gate control terminals (54) are respectively connected to the gate circuit region (1113) on the first substrate (11).
[0015] Two Kelvin source control terminals (55) are respectively connected to the Kelvin source circuit region (1112) on the first substrate (11), and each gate control terminal (54) and each Kelvin source control terminal (55) are arranged in parallel and close to each other, and extend from the opposite long edge of the first substrate (11) along the height direction.
[0016] Specifically, the upper bridge arm chip (21) includes parallel MOS transistor chips (M1~M8), and the lower bridge arm chip (22) includes parallel MOS transistor chips (M9~M16), wherein,
[0017] The positive terminal of the chip assembly is simultaneously led out from the drain of the MOS transistor chip (M1~M8);
[0018] The AC terminals of the chip assembly are simultaneously led out from the source of the MOS transistor chip (M1~M8) and the drain of the MOS transistor chip (M9~M16);
[0019] The negative terminal of the chip assembly is simultaneously led out from the source of the MOS transistor chip (M9~M16).
[0020] Specifically, the bonding wire (4) is used to connect the gate of the chip assembly (2) and the gate circuit region (1113) on the upper surface of the first substrate (11), as well as the Kelvin source of the chip assembly (2) and the Kelvin source circuit region (1112) on the upper surface of the first substrate.
[0021] Specifically, the metal connection assembly (3) includes a chip connection block (31) and a substrate connection block (32), wherein
[0022] The chip connection block (31) connects the first conductive layer (111) of the first substrate (11) to the source electrode on the upper surface of the chip assembly (2) in the height direction;
[0023] The substrate connecting block (32) connects the first conductive layer (111) on the first substrate (11) and the second conductive layer (121) on the second substrate (12) in the height direction.
[0024] Furthermore, the thickness of the chip connector block (31) is less than that of the substrate connector block (32).
[0025] Furthermore, the two gate control terminals (54) include a first gate control terminal (541) and a second gate control terminal (542) disposed on the first substrate (11), wherein the first gate control terminal (541) corresponds to the gate of the MOS transistor chip (M1~M8), and the second gate control terminal (542) corresponds to the MOS die (M9~M16).
[0026] The two Kelvin source control terminals (55) include a first Kelvin source control terminal (551) and a second Kelvin source control terminal (552) disposed on the first substrate (11), wherein the first Kelvin source control terminal (551) corresponds to the Kelvin source of the MOS transistor chip (M1~M8), and the second Kelvin source control terminal (552) corresponds to the MOS transistor chip (M9~M16).
[0027] The first gate control terminal (541) and the first Kelvin source control terminal (551) are designed to be parallel and adjacent to each other, extending from the opposite long edge of the first substrate (11) along the height direction;
[0028] The second gate control terminal (542) and the second Kelvin source control terminal (552) are designed to be parallel and adjacent to each other, extending from the opposite long edge of the first substrate (11) along the height direction.
[0029] Compared with the prior art, the low parasitic inductance double-sided heat dissipation power module of this utility model has the following advantages:
[0030] (1) By symmetrically and uniformly arranging multiple SiCMOSFET power chips on opposite substrates, combined with the design of the first substrate, second substrate, metal connection components, and terminal layout, the mutual inductance between adjacent parallel circulating current loops of the power module cancels out, significantly reducing the parasitic inductance of the power module and reducing module heat loss. At the same time, the opposite first and second substrates increase the heat dissipation path, improving the module's heat dissipation capacity. Further multi-chip symmetrical arrangement design reduces module size and weight, and increases power density;
[0031] (2) The chips are symmetrically arranged along the first substrate and electrically connected through the conductive layer of the second substrate, eliminating the traditional wire bonding process, improving reliability, and further reducing the parasitic inductance of the power module. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of the internal structure of a low parasitic inductance double-sided heat dissipation power module according to Embodiment 1;
[0033] Figure 2 This is a schematic diagram of the external structure of a low parasitic inductance double-sided heat dissipation power module according to Embodiment 1;
[0034] Figure 3 This is a distribution diagram of the first conductive layer on the first substrate in Example 1;
[0035] Figure 4 This is a distribution diagram of the second conductive layer on the second substrate in Example 1;
[0036] Figure 5 This is a schematic diagram of the connection between the chip and the terminal in Example 1;
[0037] Figure 6 This is a schematic diagram of the circuit distribution of the first conductive layer in Example 1;
[0038] Figure 7 This is a schematic diagram of the adjacent circulating current loop of a low parasitic inductance double-sided heat dissipation power module in Example 1.
[0039] Figure 8 This is a cross-sectional schematic diagram of the first substrate in Example 1;
[0040] Figure 9This is a cross-sectional schematic diagram of the second substrate in Example 1;
[0041] Figure 10 This is an exploded view of a low parasitic inductance double-sided heat dissipation power module according to Example 1. Detailed Implementation
[0042] The specific embodiments of this utility model patent will be further described in detail below with reference to the accompanying drawings.
[0043] Example 1
[0044] like Figure 1 and Figure 2 as well as Figure 10 As shown, a low parasitic inductance double-sided heat dissipation power module includes a substrate assembly 1, a chip assembly 2, a metal connection assembly 3, bonding wires 4, and terminals 5; wherein,
[0045] like Figure 1 As shown, the substrate assembly 1 includes a first substrate 11 and a second substrate 12, with the second substrate 12 located above the first substrate 11; as Figure 3 As shown, the first substrate 11 and the second substrate 12 are provided with the metal connection component 3 and the chip component 2 in the height direction, and the metal connection component 3 and the chip component 2 are located between the first substrate 11 and the second substrate 12; Figure 8 As shown, the first substrate 11 includes a first conductive layer 111, a first ceramic layer 112, and a first heat dissipation layer 113. The first conductive layer 111 is used to connect with the chip assembly 2 and form a circuit between the first substrate 11 and the second substrate 12; the first heat dissipation layer 113 is used to connect to a copper base plate or a first heat sink 56; as shown Figure 4 and Figure 9 As shown, the second substrate 12 includes a second conductive layer 121, a second ceramic layer 122, and a second heat dissipation layer 123. The second conductive layer 121 is connected to the chip assembly 2 through a metal connection assembly 3 to form a circuit. The second heat dissipation layer 123 is used to connect the second heat sink 57.
[0046] like Figure 5 and Figure 6 As shown, the chip assembly 2 is disposed on the upper surface of the first substrate 11 and includes multiple parallel upper bridge arm chips 21 and multiple parallel lower bridge arm chips 22. The upper bridge arm chips 21 are arranged in parallel on one side of the first substrate 11; the lower bridge arm chips 22 are arranged in parallel on the other side of the first substrate 11 corresponding to the upper bridge arm chips 21, so that the chip assembly is arranged in parallel and mirror symmetrical distribution to reduce loop noise.
[0047] All terminals in each upper bridge arm chip 21 and all terminals in each lower bridge arm chip 22 are arranged along the long side of the first substrate; the arrangement of all terminals along the long side of the first substrate increases the overlap area of the current loop path and reduces noise.
[0048] The metal connection components 3 are all disposed between the first substrate 11 and the second substrate 12, and are used to connect the second substrate 12 with the source stage of the chip assembly 2, the upper surface of the first substrate 11 and the lower surface of the second substrate 12.
[0049] like Figure 1 As shown, the terminal 5 includes a positive terminal 51, a negative terminal 52, an AC terminal 53, a gate control terminal 54, and a Kelvin source control terminal 55, all of which are laid on the upper surface of the first substrate 11.
[0050] Specifically, in this embodiment, such as Figure 3 As shown, the first conductive layer 111 is divided into a first power circuit region 1111, a Kelvin source circuit region 1112, a gate circuit region 1113, and an NTC placement region 1114. The first power circuit region 1111, Kelvin source circuit region 1112, gate circuit region 1113, and NTC placement region 1114 are further divided into multiple independent circuits; for example... Figure 4 As shown, the second conductive layer 121 includes a plurality of second power circuit regions 1211, which are divided into multiple independent circuits 1211-A to 1211-F.
[0051] Furthermore, the terminals include a positive terminal 51, a negative terminal 52, an AC terminal 53, two gate control terminals 54, and two Kelvin source control terminals 55, wherein,
[0052] like Figure 1 and Figure 7 As shown, the positive terminal 51 and the negative terminal 52 are respectively connected to the first conductive layer 111 on the first substrate 11 to form a circuit; the positive terminal 51 and the negative terminal 52 are arranged at intervals along the height; the positive terminal 51 and the negative terminal 52 have a partial area overlap when projected onto the first substrate 11.
[0053] The AC terminal 53 is connected to the first conductive layer 111 on the upper surface of the first substrate 11, extends from the side of the first substrate 11, and is on the other side corresponding to the positive terminal 51 and the negative terminal 52.
[0054] Two gate control terminals 54 are respectively connected to the gate circuit region 1113 on the first substrate 11;
[0055] Two Kelvin source control terminals 55 are respectively connected to the Kelvin source circuit region 1112 on the first substrate 11, and each gate control terminal 54 and each Kelvin source control terminal 55 are arranged in parallel and close to each other, and extend from the opposite long edge of the first substrate 11 along the height direction.
[0056] Specifically, the upper bridge arm chip 21 includes parallel MOS transistor chips M1~M8, and the lower bridge arm chip 22 includes parallel MOS transistor chips M9~M16, wherein...
[0057] The positive terminal of the chip assembly is simultaneously led out from the drain of the MOS transistor chips M1~M8;
[0058] The AC terminals of the chip assembly are simultaneously led out from the source of the MOS transistor chips M1~M8 and the drain of the MOS transistor chips M9~M16;
[0059] The negative terminal of the chip assembly is simultaneously led out from the source of the MOS transistor chips M9~M16.
[0060] In this embodiment, the bonding wire 4 is used to connect the gate of the chip assembly 3 and the gate circuit region 1113 on the upper surface of the first substrate 11, and the Kelvin source of the chip assembly 2 and the Kelvin source circuit region 1112 on the upper surface of the first substrate.
[0061] Specifically, the metal connection assembly 3 includes a chip connection block 31 and a substrate connection block 32, wherein
[0062] The chip connection block 31 connects the first conductive layer 111 of the first substrate 11 to the source electrode on the upper surface of the chip assembly 3 in the height direction;
[0063] The substrate connecting block 32 connects the first conductive layer 111 on the first substrate 11 and the second conductive layer 121 on the second substrate 12 in the height direction.
[0064] Furthermore, in this embodiment, the thickness of the chip connector block 31 is smaller than that of the substrate connector block 32, which facilitates the mounting of the second substrate and enables electrical connection with the second conductive layer on the second substrate.
[0065] Furthermore, the two gate control terminals 54 include a first gate control terminal 541 and a second gate control terminal 542 disposed on the first substrate 11, wherein the first gate control terminal 541 corresponds to the gate of the MOS transistor chips M1~M8, and the second gate control terminal 542 corresponds to the MOS transistor chips M9~M16.
[0066] The two Kelvin source control terminals 55 include a first Kelvin source control terminal 551 and a second Kelvin source control terminal 552 disposed on the first substrate 11, wherein the first Kelvin source control terminal 551 corresponds to the Kelvin source of the MOS transistor chips M1~M8, and the second Kelvin source control terminal 552 corresponds to the MOS transistor chips M9~M16.
[0067] The first gate control terminal 541 and the first Kelvin source control terminal 551 are designed to be parallel and adjacent to each other, extending from the opposite long edge of the first substrate 11 along the height direction;
[0068] The second gate control terminal 542 and the second Kelvin source control terminal 552 are designed to be parallel and adjacent to each other, extending from the opposite long edge of the first substrate 11 along the height direction.
[0069] Working principle: This application relates to a double-sided heat dissipation power module with multiple chips arranged in parallel, including a substrate assembly, a chip assembly, a metal connection assembly, bonding wires, and terminals. The substrate assembly includes a first substrate and a second substrate. The metal connection assembly and the chip assembly are disposed on the first substrate and the second substrate in the height direction. The chip assembly is connected to the upper surface of the first substrate, and the metal connection assembly is connected to the chip assembly and the lower surface of the second substrate. The chip assembly contains at least 20 individual chips. The terminals are connected to the upper surface of the first substrate and extend from both ends. The first terminal and the second terminal are stacked along the height direction.
[0070] The current flows from the DC+ terminal → first substrate conductive layer → upper bridge arm chip → second substrate conductive layer → metal connection layer → first substrate conductive layer → AC terminal to form DC+ → AC current, and then from the AC terminal → first substrate conductive layer → lower bridge arm chip → second substrate conductive layer → metal connection layer → first substrate conductive layer → DC- terminal. The chip terminals are arranged along the length of the first substrate, and multiple power areas are arranged on the first and second substrates, which effectively reduces the circulating current area, reduces parasitic inductance, and thus reduces switching energy loss, further improving the module's thermal performance.
Claims
1. A low parasitic inductance double-sided heat dissipation power module, characterized in that, It includes a substrate assembly (1), a chip assembly (2), a metal connection assembly (3), bonding wires (4), and terminals (5); wherein, The substrate assembly (1) includes a first substrate (11) and a second substrate (12), the second substrate (12) being located above the first substrate (11); the first substrate (11) and the second substrate (12) are provided with the metal connection assembly (3) and the chip assembly (2) in the height direction, and the metal connection assembly (3) and the chip assembly (2) are located between the first substrate (11) and the second substrate (12); the first substrate (11) includes a first conductive layer (111), a first ceramic layer (112) and a first heat dissipation layer (113), the first... The conductive layer (111) is used to connect to the chip assembly (2) and form a circuit between the first substrate (11) and the second substrate (12); the first heat dissipation layer (113) is used to connect to the copper base plate or the first heat sink (56); the second substrate (12) includes a second conductive layer (121), a second ceramic layer (122), and a second heat dissipation layer (123). The second conductive layer (121) is connected to the chip assembly (2) through a metal connection assembly (3) to form a circuit, and the second heat dissipation layer (123) is used to connect to the second heat sink (57). The chip assembly (2) is disposed on the upper surface of the first substrate (11) and includes multiple parallel upper bridge arm chips (21) and multiple parallel lower bridge arm chips (22). The upper bridge arm chips (21) are arranged in parallel on one side of the first substrate (11); the lower bridge arm chips (22) are arranged in parallel on the other side of the first substrate (11) corresponding to the upper bridge arm chips (21), so that the chip assembly is arranged in parallel and mirror symmetrical distribution. All terminals in each upper bridge arm chip (21) and all terminals in each lower bridge arm chip (22) are arranged along the long side of the first substrate; The metal connection components (3) are all disposed between the first substrate (11) and the second substrate (12) for connecting the second substrate (12) with the source stage of the chip assembly (2), the upper surface of the first substrate (11) and the lower surface of the second substrate (12); The terminal (5) includes a positive terminal (51), a negative terminal (52), an AC terminal (53), a gate control terminal (54), and a Kelvin source control terminal (55), all of which are laid on the upper surface of the first substrate (11).
2. The low parasitic inductance double-sided heat dissipation power module as described in claim 1, characterized in that, The first conductive layer (111) is divided into a first power circuit region (1111), a Kelvin source circuit region (1112), a gate circuit region (1113), and an NTC placement region (1114). The first power circuit region (1111), the Kelvin source circuit region (1112), the gate circuit region (1113), and the NTC placement region (1114) are divided into multiple independent circuits. The second conductive layer (121) contains multiple second power circuit regions (1211). The second power circuit regions (1211) are divided into multiple independent circuits (1211-A~1211-F).
3. The low parasitic inductance double-sided heat dissipation power module as described in claim 2, characterized in that, The terminals include a positive terminal (51), a negative terminal (52), an AC terminal (53), two gate control terminals (54), and two Kelvin source control terminals (55), wherein, The positive terminal (51) and the negative terminal (52) are respectively connected to the first conductive layer (111) on the first substrate (11) to form a circuit; the positive terminal (51) and the negative terminal (52) are arranged at a height interval; the positive terminal (51) and the negative terminal (52) have a partial area overlap when projected onto the first substrate (11). The AC terminal (53) is connected to the first conductive layer (111) on the upper surface of the first substrate (11), extends from the side of the first substrate (11), and is on the other side corresponding to the positive terminal (51) and the negative terminal (52); Two gate control terminals (54) are respectively connected to the gate circuit region (1113) on the first substrate (11). Two Kelvin source control terminals (55) are respectively connected to the Kelvin source circuit region (1112) on the first substrate (11), and each gate control terminal (54) and each Kelvin source control terminal (55) are arranged in parallel and close to each other, and extend from the opposite long edge of the first substrate (11) along the height direction.
4. A low parasitic inductance double-sided heat dissipation power module as described in claim 3, characterized in that, The upper bridge arm chip (21) includes parallel MOS transistor chips (M1~M8), and the lower bridge arm chip (22) includes parallel MOS transistor chips (M9~M16), wherein, The positive terminal of the chip assembly is simultaneously led out from the drain of the MOS transistor chip (M1~M8); The AC terminals of the chip assembly are simultaneously led out from the source of the MOS transistor chip (M1~M8) and the drain of the MOS transistor chip (M9~M16); The negative terminal of the chip assembly is simultaneously led out from the source of the MOS transistor chip (M9~M16).
5. A low parasitic inductance double-sided heat dissipation power module as described in claim 2, characterized in that, The bonding wire (4) is used to connect the gate of the chip assembly (2) and the gate circuit region (1113) on the upper surface of the first substrate (11), as well as the Kelvin source of the chip assembly (2) and the Kelvin source circuit region (1112) on the upper surface of the first substrate.
6. A low parasitic inductance double-sided heat dissipation power module as described in claim 1, characterized in that, The metal connection assembly (3) includes a chip connection block (31) and a substrate connection block (32), wherein The chip connection block (31) connects the first conductive layer (111) of the first substrate (11) to the source electrode on the upper surface of the chip assembly (2) in the height direction; The substrate connecting block (32) connects the first conductive layer (111) on the first substrate (11) and the second conductive layer (121) on the second substrate (12) in the height direction.
7. A low parasitic inductance double-sided heat dissipation power module as described in claim 6, characterized in that, The thickness of the chip connector (31) is less than that of the substrate connector (32).
8. A low parasitic inductance double-sided heat dissipation power module as described in claim 4, characterized in that, The two gate control terminals (54) include a first gate control terminal (541) and a second gate control terminal (542) disposed on the first substrate (11), wherein the first gate control terminal (541) corresponds to the gate of the MOS transistor chip (M1~M8) and the second gate control terminal (542) corresponds to the MOS die (M9~M16). The two Kelvin source control terminals (55) include a first Kelvin source control terminal (551) and a second Kelvin source control terminal (552) disposed on the first substrate (11), wherein the first Kelvin source control terminal (551) corresponds to the Kelvin source of the MOS transistor chip (M1~M8), and the second Kelvin source control terminal (552) corresponds to the MOS transistor chip (M9~M16). The first gate control terminal (541) and the first Kelvin source control terminal (551) are designed to be parallel and adjacent to each other, extending from the opposite long edge of the first substrate (11) along the height direction; The second gate control terminal (542) and the second Kelvin source control terminal (552) are designed to be parallel and adjacent to each other, extending from the opposite long edge of the first substrate (11) along the height direction.