Chip package structure

Abstract

The application discloses a chip packaging structure and belongs to the technical field of semiconductors. The chip packaging structure comprises a first heat dissipation fin, a chip bonded to one side of the first heat dissipation fin, a rewiring structure located on the side of the chip away from the first heat dissipation fin, wherein the rewiring structure comprises a heat dissipation circuit in contact with the chip, and a first heat dissipation structure located on the side of the rewiring structure away from the chip and in contact with the heat dissipation circuit. The application can reduce thermal resistance and improve heat dissipation efficiency.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a chip packaging structure. Background Technology

[0002] With the continuous increase in power density and miniaturization requirements of electronic devices, the heat generated by chips during operation has gradually become a key bottleneck restricting performance, stability, and lifespan. Related packaging structures typically employ single-sided heat dissipation (such as top or bottom heat dissipation), relying on heat sinks or heat sinks to conduct heat unidirectionally to the external environment. However, this approach faces problems such as excessively high thermal resistance and low heat dissipation efficiency in high-power scenarios. Utility Model Content

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a chip packaging structure that can reduce thermal resistance and improve heat dissipation efficiency.

[0004] In a first aspect, this application provides a chip packaging structure, including: First heat sink; The chip is bonded to one side of the first heat sink; A redistribution structure is located on the side of the chip away from the first heat sink, and the redistribution structure includes heat dissipation lines that are in contact with the chip. The first heat dissipation structure is located on the side of the redistribution structure opposite to the chip and is in contact with the heat dissipation line.

[0005] According to the chip packaging structure of this application, by attaching one side of the chip to the first heat sink, the chip dissipates heat through the first heat sink. A redistribution structure is provided on the other side of the chip. The redistribution structure includes heat dissipation lines that contact the chip. A first heat dissipation structure that contacts the heat dissipation lines is provided on the redistribution structure, so that the chip also dissipates heat through the heat dissipation lines and the first heat dissipation structure, thereby achieving double-sided heat dissipation of the chip, effectively reducing thermal resistance and improving heat dissipation efficiency.

[0006] According to one embodiment of this application, the chip packaging structure further includes: The second heat dissipation structure is located on the periphery of the chip and between the first heat sink and the heat dissipation line, respectively contacting the first heat sink and the heat dissipation line.

[0007] According to one embodiment of this application, the rewiring structure includes a plurality of wiring layers stacked together, the wiring layers including the heat dissipation lines; The heat dissipation lines in adjacent wiring layers are in contact with each other, the heat dissipation lines in the bottom wiring layer are in contact with the chip and the second heat dissipation structure respectively, and the heat dissipation lines in the top wiring layer are in contact with the first heat dissipation structure.

[0008] According to one embodiment of this application, the chip packaging structure further includes: A first encapsulation layer is disposed around the periphery of the chip and covers the first heat sink; a second heat dissipation structure penetrates the first encapsulation layer and contacts the first heat sink and the heat dissipation line respectively; An insulating protective layer covers the first encapsulation layer and the rewiring structure; The second encapsulation layer covers the insulating protective layer; the first heat dissipation structure penetrates the second encapsulation layer and the insulating protective layer, and is in contact with the heat dissipation line.

[0009] According to one embodiment of this application, the lateral dimension of the second heat dissipation structure is not less than 50 μm.

[0010] According to one embodiment of this application, the second heat dissipation structure includes a heat dissipation column, which may be a copper column or a diamond / copper composite material column.

[0011] According to one embodiment of this application, the chip packaging structure further includes: The second heat sink covers the first heat dissipation structure.

[0012] According to one embodiment of this application, the chip and the first heat sink are bonded together with a die adhesive having a thermal conductivity of 50 W / m℃ to 150 W / m℃.

[0013] According to one embodiment of this application, the rewiring structure further includes conductive lines electrically connected to the chip; The chip packaging structure also includes: The pin is located on the side of the redistribution structure opposite to the chip and is electrically connected to the conductive line; The pads cover the pins.

[0014] According to one embodiment of this application, the conductive line and the heat dissipation line are disposed on the same layer, and the pin is disposed on the same layer as the first heat dissipation structure.

[0015] According to one embodiment of this application, the first heat sink comprises a copper plate or a diamond / copper composite material plate; and / or, The first heat dissipation structure includes a metal structure; and / or, The heat dissipation circuit includes metal circuitry.

[0016] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects: By attaching one side of the chip to a first heat sink, the chip dissipates heat through the first heat sink. A redistribution structure is set on the other side of the chip. The redistribution structure includes heat dissipation lines that contact the chip. A first heat dissipation structure that contacts the heat dissipation lines is also set on the redistribution structure. The chip dissipates heat through the heat dissipation lines and the first heat dissipation structure, thus achieving double-sided heat dissipation of the chip, effectively reducing thermal resistance and improving heat dissipation efficiency.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the chip packaging structure provided in the embodiments of this application; Figure 2 This is a top view of the chip packaging structure provided in the embodiments of this application; Figure 3 This is a bottom view of the chip packaging structure provided in the embodiments of this application; Figure 4 This is one of the structural schematic diagrams in the method for fabricating the chip packaging structure provided in the embodiments of this application; Figure 5 This is the second schematic diagram of the structure in the method for preparing the chip packaging structure provided in the embodiments of this application; Figure 6 This is the third schematic diagram of the structure in the method for fabricating the chip packaging structure provided in the embodiments of this application; Figure 7 This is the fourth schematic diagram of the structure in the method for preparing the chip packaging structure provided in the embodiments of this application; Figure 8 This is the fifth structural schematic diagram in the method for preparing the chip packaging structure provided in the embodiments of this application.

[0019] Figure label: 1. First heat sink 2. Chip 3. Rewiring structure 3. Heat dissipation line 31. Conductive line 32. First heat dissipation structure 4. Second heat dissipation structure 5. First encapsulation layer 6. Insulating protective layer 7. Second encapsulation layer 8. Second heat sink 9. Pin 10. Pad 11. Detailed Implementation

[0020] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0021] The chip packaging structure provided in the embodiments of this application is described below with reference to the accompanying drawings.

[0022] Figure 1 This is a schematic diagram of the chip packaging structure provided in an embodiment of this application.

[0023] like Figure 1 As shown, this application embodiment provides a chip packaging structure 100 including a first heat sink 1, a chip 2, a redistribution structure 3, and a first heat dissipation structure 4.

[0024] The lateral dimension of the first heat sink 1 can be the same as the lateral dimension of the chip package structure 100, or the lateral dimension of the first heat sink 1 can be slightly smaller than the lateral dimension of the chip package structure 100, such as... Figure 2 As shown. The lateral dimension refers to the size of the lateral cross-section. For example, if both the first heat sink 1 and the chip package structure 100 have rectangular lateral cross-sections, the lateral dimension can include the length, width, and / or area of ​​the lateral cross-section. In this embodiment, the lateral dimension of the first heat sink 1 is set to be relatively large to improve its heat dissipation efficiency.

[0025] Chip 2 is bonded to one side of the first heat sink 1. The back side of chip 2 is bonded to the first heat sink 1, and the heat generated by chip 2 can be dissipated through the first heat sink 1.

[0026] The number of chips 2 can be one or more. In the case where the chip package structure includes multiple chips 2, each chip 2 is respectively bonded to one side of the first heat sink 1. The heat generated by the multiple chips 2 can be dissipated through the first heat sink 1.

[0027] The rewiring structure 3 is located on the side of the chip 2 away from the first heat sink 1, and includes a heat dissipation line 31 that contacts the chip 2. The rewiring structure 3 is located on the front side of the chip 2. The front side of the chip 2 has a PAD, and the heat dissipation line 31 can contact the PAD on the front side of the chip 2.

[0028] The redistribution structure 3 may include at least one heat dissipation line 31. When the redistribution structure 3 includes multiple heat dissipation lines 31, these lines may be disposed in the same layer or located in different film layers. Heat dissipation lines 31 in adjacent film layers may contact each other to form a heat dissipation path. The heat dissipation line 31 closest to the chip 2 in the heat dissipation path is in contact with the front surface of the chip 2.

[0029] In the case where the chip package structure 100 includes multiple chips 2, a redistribution structure 3 is provided on the front side of each chip 2, and a heat dissipation line 31 can be provided in each redistribution structure 3. The number, size, and shape of the heat dissipation lines 31 in different redistribution structures 3 can be the same or different.

[0030] The first heat dissipation structure 4 is located on the side of the redistribution structure 3 opposite to the chip 2 and is in contact with the heat dissipation line 31. The front side of the chip 2 is connected to the first heat dissipation structure 4 through the heat dissipation line 31. The heat generated by the chip 2 can also be dissipated through the heat dissipation line 31 and the first heat dissipation structure 4.

[0031] In the case where the redistribution structure 3 includes multiple overlapping wiring layers, the first heat dissipation structure 4 is in contact with the heat dissipation line 31 in the topmost wiring layer among the multiple wiring layers. The number of first heat dissipation structures 4 can be one or more. One first heat dissipation structure 4 may be in contact with multiple heat dissipation lines 31 respectively, or multiple first heat dissipation structures 4 may be in contact with corresponding multiple heat dissipation lines 31.

[0032] This embodiment sets up a bidirectional heat conduction path. The first heat sink 1 on the back of the chip 2 constitutes the back heat conduction path, and the heat dissipation line 31 and the first heat dissipation structure 4 on the front of the chip 2 constitute the front heat conduction path. The heat of the chip 2 is simultaneously discharged from the top and bottom of the chip package structure 100, which significantly reduces thermal resistance and improves heat dissipation efficiency, thereby improving system reliability.

[0033] In some embodiments, the chip package structure 100 further includes: The second heat dissipation structure 5 is located on the periphery of the chip 2 and between the first heat sink 1 and the heat dissipation line 31, respectively contacting the first heat sink 1 and the heat dissipation line 31.

[0034] The second heat dissipation structure 5 extends longitudinally, so that the two ends of the second heat dissipation structure 5 are respectively in contact with the first heat sink 1 and the heat dissipation line 31.

[0035] The number of second heat dissipation structures 5 can be one or more. When the chip package structure 100 includes multiple second heat dissipation structures 5, the multiple second heat dissipation structures 5 are located on the periphery of the chip 2, and each second heat dissipation structure 5 is in contact with the first heat sink 1 and the heat dissipation line 31. Multiple second heat dissipation structures 5 can be in contact with one heat dissipation line 31, or multiple second heat dissipation structures 5 can be in contact with multiple heat dissipation lines 31 respectively.

[0036] In this embodiment, a second heat dissipation structure 5 is provided to connect the front heat conduction path and the back heat conduction path of chip 2, thereby further improving heat dissipation efficiency.

[0037] In some embodiments, the rewiring structure 3 includes multiple wiring layers stacked together, and each wiring layer includes a heat dissipation line 31. The heat dissipation lines 31 in adjacent wiring layers are in contact with each other, the heat dissipation lines 31 in the bottom wiring layer are in contact with the chip 2 and the second heat dissipation structure 5 respectively, and the heat dissipation lines 31 in the top wiring layer are in contact with the first heat dissipation structure 4.

[0038] Each wiring layer may include at least one heat dissipation line 31. Multiple wiring layers are stacked, and the heat dissipation lines 31 in adjacent wiring layers are in contact with each other, so that the heat dissipation lines 31 in the stacked wiring layers are sequentially in contact with each other to form a heat dissipation path. The heat dissipation lines 31 closer to chip 2 in the heat dissipation path (i.e., the heat dissipation lines 31 in the bottom wiring layer) are in contact with the front side of chip 2 and the second heat dissipation mechanism 5, respectively. The heat dissipation lines 31 closer to the first heat dissipation structure 4 in the heat dissipation path (i.e., the heat dissipation lines 31 in the top wiring layer) are in contact with the first heat dissipation structure 4, so as to connect the front heat conduction path and the back heat conduction path of chip 2, thereby further improving the heat dissipation efficiency.

[0039] In some embodiments, the chip package structure 100 further includes: The first encapsulation layer 6 is disposed around the periphery of the chip 2 and covers the first heat sink 1; the second heat dissipation structure 5 penetrates the first encapsulation layer 6 and contacts the first heat sink 1 and the heat dissipation line 31 respectively. An insulating protective layer 7 covers the first encapsulation layer 6 and the rewiring structure 3; The second encapsulation layer 8 covers the insulating protective layer 7; the first heat dissipation structure 4 penetrates the second encapsulation layer 8 and the insulating protective layer 7, and contacts the heat dissipation line 31.

[0040] The first encapsulation layer 6 is used for protection and insulation. The material of the first encapsulation layer 6 may include resin, etc.

[0041] The insulating protective layer 7 is used to protect the wiring in the rewiring structure 3. The material of the insulating protective layer 7 may include PI (polyimide), etc.

[0042] The second encapsulation layer 8 is used to ensure the product's airtightness, thereby protecting its internal circuitry. The material of the second encapsulation layer 8 may include resin, etc.

[0043] In some embodiments, the lateral dimension of the second heat dissipation structure 5 is not less than 50 μm. The lateral dimension refers to the size of the lateral cross-section of the second heat dissipation structure 5. For example, the lateral cross-section of the second heat dissipation structure 5 is circular, and the lateral dimension of the second heat dissipation structure 5 is its diameter.

[0044] When the chip package structure 100 includes multiple second heat dissipation structures 5, the lateral dimensions of the multiple second heat dissipation structures 5 may be the same or different.

[0045] In this embodiment, the lateral dimension of the second heat dissipation structure 5 can be set to be larger, so as to increase the heat conduction channel of the second heat dissipation structure 5 and further improve the heat dissipation efficiency.

[0046] In some embodiments, the second heat dissipation structure 5 includes a heat dissipation column, which may be a copper column or a diamond / copper composite material column.

[0047] During the fabrication process, after forming the first encapsulation layer 6, laser drilling can be performed in the first encapsulation layer 6, and heat dissipation material can be filled into the holes to form a columnar second heat dissipation structure 5. Copper and diamond / copper composite materials are both highly thermally conductive materials. The second heat dissipation structure 5 uses copper pillars or diamond / copper composite pillars, which can improve heat dissipation efficiency.

[0048] In some embodiments, the chip package structure 100 further includes: The second heat sink 9 covers the first heat dissipation structure 4.

[0049] The second heat sink 9 is located on the side of the first heat dissipation structure 4 away from the first heat sink 1, and the second heat sink 9 is in contact with the first heat dissipation structure 4. The second heat sink 9 can completely cover the surface of the first heat dissipation structure 4 away from the first heat sink 1, so as to further improve the heat dissipation efficiency.

[0050] In some embodiments, the second heat sink 9 may include a tin sheet or the like.

[0051] In some embodiments, the chip 2 and the first heat sink 1 are bonded together with a bonding adhesive with a thermal conductivity of 50 W / m℃ to 150 W / m℃.

[0052] The adhesive has a thermal conductivity of 50 W / m℃ to 150 W / m℃, giving it high thermal conductivity. Chip 2 is bonded to the first heat sink 1 using this high thermal conductivity adhesive, effectively improving heat dissipation efficiency.

[0053] In the case where the chip package structure 100 includes multiple chips 2, each chip 2 is bonded to the first heat sink 1 by adhesive, thereby reducing the package area.

[0054] In some embodiments, the redistribution structure 3 further includes a conductive line 32 electrically connected to the chip 2, the conductive line 32 being used to transmit signals. The front side of the chip 2 has a PAD, and the conductive line 32 can contact the PAD on the front side of the chip 2. It should be noted that the PAD connected to the conductive line 32 is different from the PAD connected to the heat dissipation line 31.

[0055] The rewiring structure 3 may include at least one conductive line 32. When the rewiring structure 3 includes multiple conductive lines 32, the multiple conductive lines 32 may be disposed in the same layer or located in different film layers. For example, the rewiring structure 3 may include at least one wiring layer, and each wiring layer may include at least one conductive line 32. When the rewiring structure 3 includes multiple wiring layers, the multiple wiring layers are stacked, and the conductive lines 32 in adjacent wiring layers are electrically connected, such that the conductive lines 32 in the stacked wiring layers are sequentially electrically connected.

[0056] It should be noted that the thickness of the rewiring structure 3 is set according to the actual needs of the product. For products with high reliability requirements, the thickness of the rewiring structure 3 can be 5~10μm; for products with high density requirements, the thickness of the rewiring structure 3 can be 2~5μm, combined with fine linewidth; for products with high power requirements, the thickness of the rewiring structure 3 can be 50μm or more, combined with heat dissipation structure.

[0057] In some embodiments, the chip package structure 100 further includes: Pin 10 is located on the side of the redistribution structure 3 away from chip 2 and is electrically connected to conductive line 32. Pad 11 covers pin 10.

[0058] In the case where the redistribution structure 3 includes multiple overlapping wiring layers, pin 10 is electrically connected to the conductive line 32 in the topmost wiring layer. The material of pin 10 may include a metal such as copper.

[0059] The pad 11 is located on the side of the pin 10 away from the first heat sink 1, and the pad 11 is electrically connected to the pin 10. The material of the pad 11 may include metals such as tin.

[0060] In some embodiments, the conductive line 32 and the heat dissipation line 31 are disposed on the same layer, that is, the conductive line 32 and the heat dissipation line 31 can be formed in the same process, and the conductive line 32 and the heat dissipation line 31 are made of the same material. The pin 10 is disposed on the same layer as the first heat dissipation structure 4, that is, the pin 10 and the first heat dissipation structure 4 can be formed in the same process, and the pin 10 and the first heat dissipation structure 4 are made of the same material. The pad 11 is disposed on the same layer as the second heat sink 9, that is, the pad 11 and the second heat sink 9 can be formed in the same process, and the pad 11 and the second heat sink 9 are made of the same material.

[0061] In some embodiments, the first heat sink 1 includes a copper plate or a diamond / copper composite material plate. Both copper and diamond / copper composite materials are highly thermally conductive. Using a copper plate or a diamond / copper composite material plate for the first heat sink 1 can improve heat dissipation efficiency.

[0062] In some embodiments, the first heat dissipation structure 5 includes a metal structure. The metal may include copper or the like. Metals have good thermal conductivity, and the use of a metal structure in the first heat dissipation structure 5 can improve heat dissipation efficiency.

[0063] In some embodiments, the heat dissipation line 31 includes a metal line. The metal may include copper or the like. Metals have good thermal conductivity, and using a metal line in the heat dissipation line 31 can improve heat dissipation efficiency.

[0064] In summary, according to the chip packaging structure 100 provided in the embodiments of this application, by attaching one side of the chip 2 to the first heat sink 1, the chip 2 dissipates heat through the first heat sink 1. A redistribution structure 3 is provided on the other side of the chip 2. The redistribution structure 3 includes a heat dissipation line 31 that contacts the chip 2. A first heat dissipation structure 4 that contacts the heat dissipation line 31 is provided on the redistribution structure 3, so that the chip 2 also dissipates heat through the heat dissipation line 31 and the first heat dissipation structure 5. This achieves double-sided heat dissipation of the chip 2, effectively reducing thermal resistance, improving heat dissipation efficiency, and reducing packaging thickness and size. It is suitable for high-power scenarios such as power supply products, 5G communication, and AI chips.

[0065] Accordingly, this application also provides a method for preparing a chip packaging structure, which can prepare the chip packaging structure in the above embodiments.

[0066] The method for fabricating the chip packaging structure provided in this application may include the following steps: (1) Combination Figure 4 As shown, a first heat sink 1 is provided.

[0067] (2) Use high thermal conductivity adhesive to attach the back of chip 2 to the first heat sink 1.

[0068] (3) Apply a lamination or PI to protect the front side of the chip 2 to prevent epoxy resin from flowing onto the surface of the chip 2 during encapsulation. This step also helps to alleviate the damage to the chip caused by reliability stress.

[0069] (4) Combination Figure 5 As shown, the first encapsulation forms the first encapsulation layer 6, which provides protection and insulation for subsequent steps.

[0070] (5) Drill holes in the first encapsulation layer 6 and fill the holes with heat dissipation material to form the second heat dissipation structure 5.

[0071] (6) Combination Figure 6 and Figure 7 As shown, according to product requirements, a redistribution structure 3 containing heat dissipation lines 31 and conductive lines 32 is formed on the front side of chip 2 through exposure and development, and is connected out for the required functions. An insulating protective layer 7 is formed on the redistribution structure 3.

[0072] (7) Combination Figure 8 As shown, a second encapsulation is performed to form a second encapsulation layer 6, which ensures the airtightness of the product and protects its internal circuitry.

[0073] (8) Combination Figure 1 As shown, a second heat dissipation structure 1 and a pin 10 are formed, and the heat dissipation line 31 and the conductive line 32 in the redistribution structure 3 are respectively led out. Tin is plated on the surface of the second heat dissipation structure 1 and the pin 10 to form a second heat sink 9 and a pad 11 respectively.

[0074] (9) Cut to form the final product.

[0075] According to the chip packaging structure fabrication method provided in this application, one side of the chip is bonded to a first heat sink, allowing the chip to dissipate heat through the first heat sink. A redistribution structure is set on the other side of the chip. The redistribution structure includes heat dissipation lines that contact the chip, and a first heat dissipation structure that contacts the heat dissipation lines is set on the redistribution structure. This allows the chip to dissipate heat through the heat dissipation lines and the first heat dissipation structure, achieving double-sided heat dissipation of the chip. This effectively reduces thermal resistance, improves heat dissipation efficiency, and reduces package thickness and size. Moreover, the fabrication process is simple, enhances structural reliability, and is suitable for high-power applications such as power supply products, 5G communication, and AI chips.

[0076] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0077] In the description of this application, "multiple" means two or more.

[0078] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0079] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that, include: First heat sink; The chip is bonded to one side of the first heat sink; A redistribution structure is located on the side of the chip away from the first heat sink, and the redistribution structure includes heat dissipation lines that are in contact with the chip. The first heat dissipation structure is located on the side of the redistribution structure opposite to the chip and is in contact with the heat dissipation line.

2. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes: The second heat dissipation structure is located on the periphery of the chip and between the first heat sink and the heat dissipation line, respectively contacting the first heat sink and the heat dissipation line.

3. The chip packaging structure according to claim 2, characterized in that, The rewiring structure includes multiple wiring layers stacked together, and the wiring layers include the heat dissipation lines; The heat dissipation lines in adjacent wiring layers are in contact with each other, the heat dissipation lines in the bottom wiring layer are in contact with the chip and the second heat dissipation structure respectively, and the heat dissipation lines in the top wiring layer are in contact with the first heat dissipation structure.

4. The chip packaging structure according to claim 2, characterized in that, The chip packaging structure also includes: A first encapsulation layer is disposed around the periphery of the chip and covers the first heat sink; a second heat dissipation structure penetrates the first encapsulation layer and contacts the first heat sink and the heat dissipation line respectively; An insulating protective layer covers the first encapsulation layer and the rewiring structure; The second encapsulation layer covers the insulating protective layer; the first heat dissipation structure penetrates the second encapsulation layer and the insulating protective layer, and is in contact with the heat dissipation line.

5. The chip packaging structure according to claim 2, characterized in that, The lateral dimension of the second heat dissipation structure is not less than 50 μm; and / or, The second heat dissipation structure includes heat dissipation columns, which may be copper columns or diamond / copper composite material columns.

6. The chip packaging structure according to claim 1, characterized in that, The chip packaging structure also includes: The second heat sink covers the first heat dissipation structure.

7. The chip packaging structure according to claim 1, characterized in that, The chip is bonded to the first heat sink using adhesive with a thermal conductivity of 50 W / m℃ to 150 W / m℃.

8. The chip packaging structure according to claim 1, characterized in that, The redistribution structure also includes conductive lines electrically connected to the chip; The chip packaging structure also includes: The pin is located on the side of the redistribution structure opposite to the chip and is electrically connected to the conductive line; The pads cover the pins.

9. The chip packaging structure according to claim 8, characterized in that, The conductive lines are arranged on the same layer as the heat dissipation lines, and the pins are arranged on the same layer as the first heat dissipation structure.

10. The chip packaging structure according to any one of claims 1-9, characterized in that, The first heat sink comprises a copper plate or a diamond / copper composite material plate; and / or, The first heat dissipation structure includes a metal structure; and / or, The heat dissipation circuit includes metal circuitry.

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