Package structure, semiconductor device, and power module

Abstract

The utility model relates to a semiconductor packaging technical field especially relates to a kind of packaging body structure, semiconductor device and power module, packaging body structure includes substrate assembly, including substrate, and the first metal layer and the second metal layer on the substrate;Chip, is located on the first metal layer, and chip is electrically connected with the second metal layer by conductive connecting piece;Plastic package, covers chip and substrate assembly;Buffer layer, at least part is located chip surface and the connecting interface of plastic package, and buffer layer is formed by imide or amide imide material solidification or pre-crosslinking formation.The utility model can improve the connection strength of chip surface and plastic package, while also reduce the stress suffered by chip surface, solve the problem of chip surface and plastic package delamination.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a package structure, semiconductor device and power module. Background Technology

[0002] To meet the application requirements of high power density and high current, the packaging solution of automotive-grade power modules is gradually evolving towards injection molding, and the power connection method of chips has also undergone significant changes, resulting in varying degrees of improvement in key performance indicators such as heat resistance, current carrying capacity and reliability of power modules.

[0003] However, in power modules, the differences in the coefficients of thermal expansion of materials such as the molding compound, chip, and metal connectors can lead to excessive local stress on the chip surface and insufficient connection strength between the chip surface and the molding compound. This can cause delamination at the interface between the chip surface and the molding compound. If the delamination continues to extend to the vicinity of the signal lines, it may break the signal lines. Furthermore, moisture can easily accumulate at the delamination points during product use. Moisture accumulated on the chip surface may cause electrochemical corrosion, short circuits, and other failures, ultimately leading to the failure of the power module and severely affecting the reliability and lifespan of the product.

[0004] To address the delamination problem between the chip surface and the molding compound, the main focus is on improving the connection strength between the chip surface and the molding compound. Traditional solutions mostly include using new molding compounds, optimizing the injection molding process, or improving the plasma treatment process before injection molding. However, these methods have significant limitations. They can only improve the connection strength unilaterally, but cannot effectively reduce the stress on the chip surface. In practical applications, the stress on the chip surface is often still greater than the improved connection strength, making the improvement effect on the chip delamination problem negligible, or even ineffective. Utility Model Content

[0005] This invention provides a package structure, a semiconductor device, and a power module to solve the technical problem of delamination at the interface between the chip surface and the molding compound.

[0006] This utility model provides a package structure, the package structure comprising:

[0007] The substrate assembly includes a first metal layer and a second metal layer;

[0008] A chip is disposed on the first metal layer, and the chip is electrically connected to the second metal layer through a conductive connector;

[0009] A molding compound that encapsulates the chip and the substrate assembly;

[0010] A buffer layer, at least partially located at the interface between the chip surface and the molding compound, is formed by curing or pre-crosslinking an imide or amide-imide material.

[0011] In one embodiment of the present invention, the buffer layer covers at least the upper surface where the chip and the encapsulation are connected.

[0012] In one embodiment of the present invention, the modulus of the material of the buffer layer is less than the modulus of the material of the encapsulation body, wherein the modulus is the elastic modulus, flexural modulus, or tensile modulus.

[0013] In one embodiment of this utility model,

[0014] The buffer layer is formed on the chip surface by coating.

[0015] Alternatively, the buffer layer is formed on the chip surface by a mounting method, and the mounted buffer layer includes an adhesive backing and a polymer film formed on the upper surface of the adhesive backing. The adhesive backing is made of silicone-based material, and the polymer film is a polymer film containing imide functional groups or amide-imide functional groups.

[0016] In one embodiment of the present invention, the dielectric strength of the buffer layer is greater than 100V / μm.

[0017] In one embodiment of this utility model, the chip is a transistor or a diode, and the outer surface of the chip has a metal plating layer, which is gold, palladium or silver; the molding compound is made of epoxy, anhydride or silicone material.

[0018] In one embodiment of this utility model, the conductive connector is a metal pad, a bonding wire, or a metal clip.

[0019] In one embodiment of the present invention, a connection layer is provided between the chip and the connection interface of the first metal layer and the conductive connector, and the connection layer is sintered silver, sintered copper or solder.

[0020] This invention also provides a semiconductor device, including the package structure described in any of the preceding claims.

[0021] This utility model also provides a power module, including the semiconductor device described above.

[0022] The beneficial effects of this utility model are as follows: by setting a buffer layer at the interface between the chip surface and the molding compound, and the buffer layer is formed by curing or pre-crosslinking of imide or amide-imide materials, the connection strength between the chip and the molding compound can be significantly improved, while reducing the packaging stress on the chip surface and solving the delamination problem between the chip surface and the molding compound. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0024] In the attached diagram:

[0025] Figure 1 This is a cross-sectional schematic diagram of the encapsulation structure provided in an embodiment of the present invention;

[0026] Figure 2 A cross-sectional schematic diagram of the encapsulation structure provided in another embodiment of this utility model;

[0027] Figure 3 A cross-sectional schematic diagram of the encapsulation structure provided in another embodiment of this utility model;

[0028] Figure 4 This is a schematic diagram of the chip electrical connection during the packaging process of a package structure provided in an embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of plasma treatment during the encapsulation process of the encapsulation structure provided in an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of the coating of a buffer layer during the encapsulation process of the encapsulation structure provided in an embodiment of the present invention;

[0031] Figure 7 This is a schematic diagram of the buffer layer after it has been laid out during the encapsulation process of an embodiment of the present invention.

[0032] Figure 8 This is a schematic diagram of the curing buffer layer during the encapsulation process of the encapsulation structure provided in an embodiment of the present invention;

[0033] Figure 9 This is a schematic diagram of the encapsulation process of the encapsulation body structure provided in an embodiment of the present invention;

[0034] Figure 10 A schematic diagram of the chip connecting to the metal pad during the packaging process of the package structure provided in another embodiment of this utility model;

[0035] Figure 11 A schematic diagram of the mounting of a buffer layer during the encapsulation process of the encapsulation structure provided in another embodiment of this utility model;

[0036] Figure 12This is a schematic diagram of the chip electrical connection during the packaging process of the package structure provided in another embodiment of the present invention;

[0037] Figure 13 A schematic diagram of the encapsulation process for the encapsulation structure provided in another embodiment of this utility model;

[0038] Figure 14 This is a schematic diagram of a mounting buffer layer provided for another embodiment of the present invention.

[0039] The attached figures are labeled as follows:

[0040] 100 - Substrate; 10 - First metal layer; 20 - Second metal layer; 30 - Chip;

[0041] 40 - Conductive connector; 41 - Connecting substrate; 42 - Metal pad; 421 - First metal pad; 422 - Second metal pad;

[0042] 50 - Connector Layer;

[0043] 60 - Buffer layer; 61 - Adhesive backing; 62 - Polymer film;

[0044] 70 - Molded body;

[0045] 201-Plasma chamber; 301-Spraying device; 302-Spraying material; 401-Curing oven. Detailed Implementation

[0046] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0047] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0048] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present invention.

[0049] Please see Figure 1 , Figure 1 This is a cross-sectional schematic diagram of the encapsulation structure provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the package structure includes a substrate assembly, a chip 30, a molding compound 70, and a buffer layer 60. The substrate assembly includes a substrate 100 and a first metal layer 10 and a second metal layer 20 disposed on the substrate 100. The chip 30 is disposed on the first metal layer 10 and is electrically connected to the second metal layer 20 through a conductive connector 40. The molding compound 70 covers the chip 30 and the substrate assembly. The buffer layer 60 is at least partially located at the interface between the surface of the chip 30 and the molding compound 70. The buffer layer 60 is formed by curing or pre-crosslinking an imide or amide-imide material.

[0050] Specifically, the first metal layer 10 and the second metal layer 20 etched on the substrate 100 can be located on the same plane or on different planes. The substrate 100 can be, for example, an AMB substrate (Active Metal Brazing substrate) or a DBC substrate (Direct Bonding Copper ceramic substrate), etc., and there is no specific limitation. The first metal layer 10 serves as a carrier platform for the chip 30, providing stable mechanical support and electrical connection paths. The second metal layer 20 is electrically connected to the chip 30 through conductive connectors 40, which can realize signal expansion, current splitting, etc., and ensure the electrical performance and signal integrity of the package structure.

[0051] Chip 30 is disposed on the first metal layer 10, and chip 30 is electrically connected to the second metal layer 20 through conductive connector 40, ensuring a stable electrical connection between chip 30 and external circuit. Molded enclosure 70 covers chip 30 and substrate assembly, serving to encapsulate, block moisture, provide protection, and provide electrical insulation.

[0052] A buffer layer 60 is disposed at the interface between the chip 30 surface and the molding compound 70. The buffer layer 60 is formed by curing an imide-based or amide-imide-based material, which improves the adhesion strength between the chip 30 surface and the molding compound 70, reduces the stress on the chip 30 surface, and solves the delamination problem between the chip 30 surface and the molding compound 70. The buffer layer 60 formed by imide-based or amide-imide-based materials has good thermal stability, electrical insulation, chemical resistance, and moisture resistance, making it suitable for the packaging protection of power electronic products.

[0053] The material of the buffer layer 60 is an imide or amide-imide material, specifically including precursors, semi-mers, polymers, and copolymers of imides and amide-imides, such as polyimide materials and polyamide-imide materials, that is, materials containing imide functional groups or amide-imide functional groups in their molecules.

[0054] During the operation of chip 30, due to the different coefficients of thermal expansion of materials such as molding compound 70, chip 30, and conductive connector 40, chip 30 and molding compound 70 will undergo varying degrees of thermal expansion and contraction with temperature changes. Without the buffer layer 60, this mismatch in coefficients of thermal expansion would lead to significant stress at the interface, resulting in delamination at the interface between the chip 30 surface and molding compound 70. Imidide or amide-imide materials have low elastic modulus and good flexibility. A buffer layer 60 is formed at the interface between the chip 30 surface and molding compound 70, effectively absorbing and dispersing the stress caused by the difference in coefficients of thermal expansion between the chip 30 and molding compound 70. Furthermore, the buffer layer 60 can form a good bond with the chip 30 surface and molding compound 70, enhancing the bonding strength at the interface and reducing interface defects and microcracks.

[0055] In some embodiments, the buffer layer 60 covers at least the upper surface where the chip 30 connects to the molding compound 70. Specifically, since the upper surface of the chip 30 is typically used for electrical connections with other components, the buffer layer 60 covering the connection between the upper surface of the chip 30 and the molding compound 70 can absorb and disperse stress, preventing stress concentration in weak areas such as the edges or corners of the chip 30. Furthermore, the adhesive force between the buffer layer 60 and both the chip 30 and the molding compound 70 helps to fix the position of the chip 30, preventing displacement or tilting during packaging and use, and ensuring accurate connection between the chip 30 and external circuitry. Because the buffer layer 60 enhances the adhesive force between the chip 30 and the molding compound 70 and reduces the stress on the chip 30, delamination between the chip 30 and the molding compound 70 can be avoided at locations on the upper surface of the chip 30 commonly used for electrical connections with other components.

[0056] It should be noted that the modulus of the material of the buffer layer 60 is lower than that of the material of the molding compound 70. This modulus is the elastic modulus, flexural modulus, or tensile modulus. Imidides or amide-imides are commonly used for insulation and are not typically used as stress-absorbing materials. However, they are used here because imides or amide-imides have lower moduli (elastic modulus, flexural modulus, or tensile modulus) than the material of the molding compound 70, typically ranging from 2 to 5 GPa at room temperature. Therefore, the stress in direct contact with the chip 30 surface is lower than that of the molding compound 70, allowing it to buffer and absorb stress. Simultaneously, the material of the buffer layer 60 has good thermal stability and electrical insulation, and excellent connectivity, enabling it to simultaneously connect the chip 30 surface and the molding compound 70, thus enhancing the adhesion between the chip 30 and the molding compound 70.

[0057] In the above embodiments, regarding the electrical insulation of the buffer layer 60, the dielectric strength of the buffer layer 60 is greater than 100V / μm. The buffer layer 60, made of imide or amide-imide materials, can withstand the high-voltage operating conditions of the chip 30, preventing electrical breakdown at the chip 30 and thus preventing the product's electrical function from failing. Regarding the thermal stability of the buffer layer 60, after the buffer layer 60 covers the upper surface of the chip 30, it does not affect the heat generated by the chip 30 to be conducted to the molding compound 70, and it can meet the automotive-grade application requirements of the product, is not easily thermally decomposed or aged, and ensures stable thermal, mechanical, and electrical properties.

[0058] In the above embodiments, chip 30 is a transistor or a diode. For example, chip 30 can be a silicon-based insulated gate bipolar transistor, a silicon carbide-based metal oxide semiconductor field-effect transistor, or a diode.

[0059] Understandably, the outer surface of chip 30 has a metal plating layer, which can be gold, palladium or silver, and the metal plating layer serves to protect chip 30.

[0060] In the above embodiments, the material of the encapsulating body 70 is epoxy, anhydride or silicone, and there is no specific limitation. Any material that can perform the functions of encapsulation, moisture barrier and protection is acceptable.

[0061] It should be noted that a connection layer 50 is provided between the chip 30 and the connection interface of the first metal layer 10 and the conductive connector 40. The connection layer 50 is sintered silver, sintered copper or solder. The connection layer 50 serves to provide mechanical support, conduct electricity and heat.

[0062] In the above embodiments, the conductive connector 40 is a metal pad 42, a bonding wire, or a metal clip. Specifically, it is explained below:

[0063] like Figure 1As shown, the conductive connector 40 is a metal pad 42. Specifically, a first metal pad 421, a second metal pad 422, and a connecting substrate 41 are provided. The first side of the chip 30 is disposed on the first metal layer 10 through a connecting layer 50. The opposite sides of the first metal pad 421 are connected to the second side (facing away from the first side) of the chip 30 and the connecting substrate 41 through the connecting layer 50, respectively. The opposite sides of the second metal pad 422 are connected to the second metal layer 20 and the connecting substrate 41 through the connecting layer 50, respectively. Electrical connection is achieved through the connecting substrate 41, the first metal pad 421, and the second metal pad 422. A buffer layer 60 is disposed on the surface of the chip 30, and a molding compound 70 covers the substrate assembly and the chip 30.

[0064] like Figure 2 As shown, the conductive connector 40 is a bonding wire, which can be made of aluminum wire, copper wire, aluminum-magnesium wire, aluminum-clad copper wire, etc., as long as it can transmit current; there are no specific limitations. The first side of the chip 30 is disposed on the first metal layer 10 through the connecting layer 50. The second side of the chip 30 (facing away from the first side) is connected to the second metal layer 20 through the bonding wire. The two ends of the bonding wire are respectively connected to the chip 30 and the second metal layer 20. The buffer layer 60 is disposed on the surface of the chip 30, and the molding compound 70 covers the substrate assembly and the chip 30.

[0065] like Figure 3 As shown, the conductive connector 40 is a metal clip. The first side of the chip 30 is disposed on the first metal layer 10 through the connecting layer 50. The second side of the chip 30 (facing away from the first side) is connected to the second metal layer 20 through the metal clip. The two ends of the metal clip are connected to the chip 30 and the second metal layer 20 respectively through the connecting layer 50. The buffer layer 60 is disposed on the surface of the chip 30. The molding compound 70 covers the substrate assembly and the chip 30.

[0066] In some embodiments, the buffer layer 60 is formed on the surface of the chip 30 by coating. This is described in detail below:

[0067] This embodiment uses the conductive connector 40 as an example of a metal pad 42. The encapsulation process of the package structure is as follows: Figure 4 As shown, the power and signal connections of chip 30 are first made. Chip 30 is connected to the first metal layer 10 through connection layer 50. First metal pad 421 is connected to chip 30 through connection layer 50. Second metal pad 422 is connected to the second metal layer 20 through connection layer 50. Connection substrate 41 is connected to the first metal pad 421 and the second metal pad 422 through connection layer 50 respectively.

[0068] Next, it is moved into the plasma chamber 201 for plasma treatment, such as... Figure 5As shown, the gas used for plasma treatment in the plasma chamber 201 can be nitrogen, argon, nitrogen-hydrogen mixture, etc., without limitation, as long as it can play a role in surface cleaning, activation, and roughening.

[0069] Then, a buffer layer 60 is coated on the surface of chip 30, such as... Figure 6 As shown. The coating process can be atomized spraying, jetting, dot coating, dip coating, spin coating, etc., without limitation, as long as it serves to coat the buffer layer 60 material onto the surface of the chip 30. The spraying device 301 can be a solenoid valve, piezoelectric valve, air valve, etc., without specific limitations, as long as it serves to quantitatively transfer the buffer layer 60 material to the surface of the chip 30.

[0070] The spray material 302 sprayed from the spraying device 301 is an imide or amide-imide material used in the buffer layer 60, and the spray material 302 also contains solvents for dissolving and dispersing the imide or amide-imide material, as well as other additives such as stabilizers, buffers, catalysts, etc.

[0071] This embodiment uses a spraying method as an example. The spraying process can be carried out in an atmospheric environment, but the relative humidity of the environment needs to be controlled, for example, the relative humidity should not exceed 20%, 40%, 50%, 70%, etc. There are no restrictions here, and the selection can be made according to the physical properties of the buffer layer 60 material. The coating amount can be adjusted and selected according to the actual situation, for example, it can be adjusted according to the thickness after coating, or the thickness after curing, or the coating weight.

[0072] like Figure 7 As shown, the applied buffer layer 60 will spread and cover the surface of the chip 30, but it is not limited to covering only the surface of the chip 30. It can also cover other components, such as the first metal layer 10, the metal pad 42, the connecting layer 50, the second metal layer 20, etc., which are not limited here.

[0073] like Figure 8 As shown, this is the curing process of buffer layer 60, which involves evaporating the solvent in the buffer layer 60 material solution, causing the buffer layer 60 material to undergo a polymerization reaction at high temperature. The curing process can be divided into two-step curing (pre-curing and post-curing), or three-step curing (pre-curing, intermediate curing, and post-curing), or more steps. The curing oven 401 can be filled with nitrogen or evacuated to prevent oxidation of the product during the curing process.

[0074] To prevent the surface of the buffer layer 60 material solution from curing before the interior is fully cured during the curing process, the curing temperature of the preceding step is set lower than that of the subsequent step. In this embodiment, the pre-curing temperature is 40℃~100℃, the intermediate curing temperature is 100℃~180℃, and the post-curing temperature is 200℃~300℃. The curing time, heating rate, and cooling rate mainly depend on the type of buffer layer 60 material solution, the amount applied, the production cycle limitations imposed on the product, and the capacity of the curing oven 401 itself, and are not limited here.

[0075] like Figure 9 As shown, this is the final molding process, forming a molded body 70 that encapsulates the chip 30 and the substrate assembly.

[0076] In other embodiments, the buffer layer 60 is formed on the surface of the chip 30 by a mounting method. This will be described in detail below:

[0077] like Figure 10 As shown, the chip 30 and metal pad 42 are first installed, completing part of the power and signal connection process. The first side of the chip 30 is connected to the first metal layer 10 through the connection layer 50, the first metal pad 421 is connected to the second side of the chip 30 through the connection layer 50, and the second metal pad 422 is connected to the second metal layer 20 through the connection layer 50. Then, the buffer layer 60 is attached to the upper surface of the chip 30, as shown. Figure 11 As shown; then, the remaining power connection process continues, that is, the connection substrate 41 is connected to the first metal pad 421 and the second metal pad 422 respectively through the connection layer 50, as shown. Figure 12 As shown; finally, a molding process is performed to form a molded body 70, as shown. Figure 13 As shown. During the mounting process, the buffer layer 60 can be manually mounted or picked up and mounted using a pick-and-place machine, thus transferring the buffer layer 60 to the surface of the chip 30. After the buffer layer 60 is mounted onto the surface of the chip 30, air bubbles need to be removed, i.e., the air between the buffer layer 60 and the chip 30 needs to be expelled. This can be achieved by methods such as applying pressure or scraping the surface of the buffer layer 60.

[0078] like Figure 14 As shown, the mounting buffer layer 60 includes an adhesive backing 61 and a polymer film 62 formed on the upper surface of the adhesive backing 61. The material of the adhesive backing 61 is silicone-based, and the polymer film 62 is a polymer film containing imide functional groups or amide-imide functional groups. The thicknesses of the adhesive backing 61 and the polymer film 62 can be defined according to product requirements. For example, the thickness of the polymer film 62 can be 5µm, 10µm, 15µm, 30µm, etc., and the thickness of the adhesive backing 61 can be 20µm, 30µm, 50µm, etc., and are not limited here.

[0079] This invention also provides a semiconductor device, including the package structure described in any of the preceding claims.

[0080] This utility model also provides a power module, including the semiconductor device described above.

[0081] In summary, the package structure, semiconductor device, and power module provided by this utility model, by setting a buffer layer 60 at the connection interface between the chip 30 surface and the molding compound 70, and the buffer layer 60 being formed by curing or pre-crosslinking of imide or amide-imide materials, can significantly improve the connection strength between the chip 30 and the molding compound 70, while reducing the packaging stress on the chip 30 surface and solving the delamination problem between the chip 30 surface and the molding compound 70.

[0082] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A package structure, characterized in that, include: A substrate assembly includes a substrate and a first metal layer and a second metal layer disposed on the substrate; A chip is disposed on the first metal layer, and the chip is electrically connected to the second metal layer through a conductive connector; A molding compound that encapsulates the chip and the substrate assembly; A buffer layer, at least partially located at the interface between the chip surface and the molding compound, is formed by curing or pre-crosslinking an imide or amide-imide material.

2. The encapsulation structure according to claim 1, characterized in that, The buffer layer covers at least the upper surface where the chip connects to the molding compound.

3. The encapsulation structure according to claim 1 or 2, characterized in that, The modulus of the material of the buffer layer is less than the modulus of the material of the encapsulation, and the modulus is the elastic modulus, flexural modulus, or tensile modulus.

4. The encapsulation structure according to claim 1, characterized in that, The buffer layer is formed on the chip surface by coating. Alternatively, the buffer layer is formed on the chip surface by a mounting method, and the mounted buffer layer includes an adhesive backing and a polymer film formed on the upper surface of the adhesive backing, wherein the adhesive backing is made of a silicone-based material.

5. The encapsulation structure according to claim 1, characterized in that, The dielectric strength of the buffer layer is greater than 100V / μm.

6. The encapsulation structure according to claim 1, characterized in that, The chip is a transistor or a diode, and the outer surface of the chip has a metal plating layer, which is gold, palladium or silver; the molding compound is made of epoxy, acid anhydride or silicone material.

7. The encapsulation structure according to claim 1, characterized in that, The conductive connector is a metal pad, bonding wire, or metal clip.

8. The encapsulation structure according to claim 1 or 7, characterized in that, A connection layer is provided between the chip and the connection interface of the first metal layer and the conductive connector, respectively. The connection layer is sintered silver, sintered copper or solder.

9. A semiconductor device, characterized in that, Includes the package structure as described in any one of claims 1-8.

10. A power module, characterized in that, Including the semiconductor device as described in claim 9.

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