Chip multi-station test board

CN224745085UActive Publication Date: 2026-09-11SEMITEK INSTR LTD
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Patent Information

Application Number
CN202522024286.3
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-09-20
Publication Date
2026-09-11
Estimated Expiration
2035-09-20

AI Technical Summary

Technical Problem

[0003]现有的芯片检测设备,具有以下技术问题:不同的芯片封装规格不同,造成尺寸以及端子的数量和分布均不同,单一测试基台难以满足多个不同封装规格芯片的试验检测需求;在对不同封装规格的芯片进行检测试验时,也因端子的数量和分布不同而导致插接定位困难,影响测试效率的同时容易损伤端子;测试基台的测试插座脆弱易损,若因定位错误或芯片在插接或测试过程中发生移位,也会对测试基台的测试插座造成不可逆损伤

Benefits of technology

(1)本申请提供的芯片多工位试验台,通过连接板连接芯片与测试基台,连接板上设置的第一连接部能够适配多种不同封装规格芯片的端子;连接板上设置的第一定位销与测试基台上设置的第一定位孔可拆卸插接,在连接板连接测试基台时可同时起到定位与限位作用,有助于插接时快速精确定位,且能够避免因定位错误或测试中移位导致的测试基台损伤。

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Abstract

This utility model relates to a multi-station chip testing platform, comprising: a connecting plate having a first connecting portion thereon, the upper end of which is inserted into a chip; the distribution density of the first connecting portion is adapted to the distribution density of connection points, resulting in a large distribution range; a test base having multiple second connecting portions thereon, which are inserted into the lower ends of the first connecting portions; the distribution density of the second connecting portions is adapted to the distribution density of the first connecting portions, resulting in a large distribution range; a test panel disposed on the test base and having multiple test interfaces, which are electrically connected to the second connecting portions; and a positioning and locking mechanism comprising a first positioning pin and a first positioning hole, the first positioning pin being disposed on the connecting plate and the first positioning hole being disposed on the test base, the two being inserted into each other. This application connects the chip and the test base via a connecting plate, the connecting plate being adaptable to chips of different package specifications, and the test base being able to accommodate multiple connecting plates for simultaneous testing; the positioning and locking mechanism simultaneously serves as a positioning and limiting mechanism.
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Description

Technical Field

[0001] This utility model relates to the field of chip testing equipment technology, and in particular to a chip multi-station test bench. Background Technology

[0002] Chip testing equipment is needed when inspecting and testing the chip itself, or when using the chip as a controller to inspect and test various devices and components.

[0003] Existing chip testing equipment has the following technical problems: different chip package specifications result in different sizes and varying numbers and distributions of terminals, making it difficult for a single test base to meet the testing needs of multiple chips with different package specifications; when testing chips with different package specifications, the different number and distribution of terminals also lead to difficulties in insertion and positioning, affecting testing efficiency and easily damaging the terminals; the test sockets of the test base are fragile and easily damaged, and if positioning errors occur or the chip shifts during insertion or testing, irreversible damage can be caused to the test sockets of the test base.

[0004] In summary, there is an urgent need for a chip testing experimental device that can simultaneously adapt to chips with multiple packaging specifications, and can quickly locate, stably insert, and protect the chip and the test base. Utility Model Content

[0005] To address the aforementioned problems, this invention provides a multi-station chip testing platform.

[0006] The technical solution adopted in this utility model is as follows: A multi-station chip testing platform, comprising: At least one connection board, an array of multiple first connection parts are arranged on the connection board, the first connection parts pass through the connection board, the upper end of the first connection part is configured to be detachably plugged into the connection point of the chip, the distribution density of the first connection parts is adapted to the distribution density of the connection points, and the distribution range of the first connection parts is larger than the distribution range of the connection points. The test base has multiple second connection parts arranged in an array. The second connection parts are configured to be detachably plugged into the lower end of the first connection parts. The distribution density of the second connection parts is adapted to the distribution density of the first connection parts, and the distribution range of the second connection parts is larger than the distribution range of the first connection parts. The test panel has multiple test interfaces; the test panel is mounted on the test base and is electrically connected to at least part of the second connection part. The positioning and locking mechanism includes a first positioning pin and a first positioning hole. The first positioning pin is configured to be detachably inserted into the first positioning hole. Multiple first positioning pins are spaced apart along the circumferential direction of the connecting plate on the outer edge of the connecting plate. Multiple first positioning holes are spaced apart on the test base. The distribution positions of the first positioning holes are adapted to the distribution positions of the first positioning pins. The number and distribution area of ​​the first positioning holes are greater than the number and distribution area of ​​the first positioning pins. When each first positioning pin is inserted into a first positioning hole, each first connecting part is inserted into a second connecting part in a corresponding manner.

[0007] In one possible implementation, The first positioning hole protrudes from the test base, and a first limiting boss is provided circumferentially on its lower outer side wall; multiple placement holes are arranged circumferentially on the upper side wall of the first positioning hole, and a sphere is placed in the placement hole, the diameter of the sphere being no larger than the diameter of the placement hole. It also includes a limiting ring, which is sleeved outside the first positioning hole. A second limiting boss is provided circumferentially on the upper part of the inner sidewall of the limiting ring. The inner sidewall of the second limiting boss is slidably connected to the outer sidewall of the first positioning hole, and / or the inner sidewall of the limiting ring is slidably connected to the outer sidewall of the first limiting boss, and the sliding axis coincides with the axis of the first positioning hole. The second limiting boss is provided circumferentially on the upper part of the inner sidewall of the limiting ring, and the sidewall of the second limiting boss abuts against the outer sidewall of the first positioning hole. The distance between the inner sidewall of the limiting ring and the outer sidewall of the first positioning hole is less than the diameter of the sphere. It also includes a spring, which is sleeved on the outer wall of the first positioning hole and located between the first limiting boss and the second limiting boss. The two ends of the spring are respectively pressed against the upper edge of the first limiting boss and the lower edge of the second limiting boss. When the spring is in its original state, the side wall of the second limiting boss covers at least a portion of the area of ​​the placement hole. When the spring is in its maximum compressed state, the side wall of the second limiting boss does not cover the placement hole, and the upper edge of the limiting ring is located between the upper edge and the lower edge of the placement hole. A limiting groove and a third limiting boss are sequentially provided on the side wall of the first positioning pin at the end that is detachably inserted into the first positioning hole, along the insertion direction. Both the limiting groove and the third limiting boss are arranged circumferentially along the outer wall of the first positioning pin. The cross-sectional shapes of the third limiting boss and the limiting groove, which are parallel to the circumferential direction of the first positioning pin, are trapezoidal with an outward convexity and an inward concavity, respectively. When the first positioning pin is inserted into the first positioning hole, the side wall of the third limiting boss abuts against the inner side wall of the first positioning hole, and the sphere is at least partially located in the limiting groove.

[0008] In one possible implementation, It also includes heat dissipation components, which include heat exchange plates and heat dissipation fins. The heat exchange plate is provided with a first heat exchange surface and a second heat exchange surface that are opposite to each other. The first heat exchange surface is attached to one side of the heat dissipation fins and fixedly connected. The shape of the second heat exchange surface is adapted to the connecting plate. Multiple second positioning pins are arranged in a circumferential array along the edge of the second heat exchange surface. The connecting plate is provided with a second positioning hole at a corresponding position on the upper side of the first connecting part. When the second positioning pin is inserted into the corresponding second positioning hole, the second heat exchange surface contacts the top cover of the chip inserted into the first connection part.

[0009] In the above possible implementations, further, The connecting plate has a first hinge part on one side of the upper end of the first connecting part, and a first fastening part on the other side opposite to the first connecting part; It also includes a pressure plate, which is provided with a second hinge and a second fastening part. The second hinge is hinged to the first hinge, and the second fastening part is detachably connected to the first fastening part. The side of the pressure plate facing the upper end of the first connecting part is the pressure surface, and the side facing away from the cover is the third heat exchange surface. When the chip is inserted into the first connecting part and the second fastening part is connected to the first fastening part, the pressure surface covers the top cover of the chip and is in contact with and abuts against at least a portion of the top cover. When the second positioning pin is inserted into the corresponding second positioning hole, the second heat exchange surface covers the third heat exchange surface and is in contact with and abuts against at least a portion of the third heat exchange surface.

[0010] Furthermore, Multiple elastic sections are provided at the third heat exchange surface, and the elastic sections protrude from the third heat exchange surface in an arch shape.

[0011] In one possible implementation, It also includes a component panel with multiple component interfaces; the component panel is disposed on the connecting plate and electrically connected to the upper end of at least a portion of the first connecting part.

[0012] The technical solution provided in this application has at least the following technical effects or advantages: (1) The chip multi-station test bench provided in this application connects the chip and the test base through a connecting plate. The first connecting part on the connecting plate can be adapted to the terminals of chips with different package specifications. The first positioning pin on the connecting plate and the first positioning hole on the test base can be detachably inserted. When the connecting plate is connected to the test base, it can play the role of positioning and limiting at the same time, which helps to quickly and accurately position during insertion and can avoid damage to the test base caused by positioning errors or displacement during testing.

[0013] (2) The chip multi-station test bench provided in this application can be connected to multiple connection boards to realize the synchronous testing of multiple chips, especially multiple chips with different packaging specifications; and multiple chips can be connected to a single connection board at the same time to realize parallel testing and experimentation of different chips. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments of this application or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of the chip multi-station test bench provided in Example 1; Figure 2 for Figure 1 A magnified schematic diagram of the structure of the first magnified region; Figure 3 This is a schematic diagram of the structure of the chip multi-station test bench provided in Example 2; Figure 4 This is a schematic diagram of the heat sink in Example 2; Figure 5 This is a schematic diagram of the chip multi-station test bench provided in Example 3 without heat sinks installed; Figure 6 This is a schematic diagram of the chip multi-station test bench provided in Example 3, with heat sinks installed.

[0016] In the picture: 1-Connecting plate; 2-First connecting part; 3-Test base; 4-Second connecting part; 5-Test panel; 501-Test interface; 6-First positioning pin; 601-Limiting groove; 602-Third limiting boss; 7-First positioning hole; 701-First limiting boss; 702-Sphere; 8-Limiting ring; 801-Second limiting boss; 9-Spring; 10-Heat exchange plate; 11-Heat dissipation fin assembly; 12-Second positioning pin; 13-Second positioning hole; 14-First hinge part; 15-First fastening part; 16-Pressure plate; 1601-Second hinge part; 1602-Second fastening part; 1603-Elastic part; 17-Component panel; 1701-Component interface; 18-Chip; A-First magnification area. Detailed Implementation

[0017] The specific implementation of the present invention will now be described with reference to the accompanying drawings.

[0018] Example 1 like Figures 1-2As shown, this embodiment provides a chip multi-station test bench, which includes: At least one connecting plate 1 is provided, and multiple first connecting parts 2 are arrayed on the connecting plate 1. The first connecting parts 2 pass vertically through the connecting plate 1. The upper end of the first connecting part 2 is configured to be detachably plugged into the connection point of the chip 18. The upper end of the first connecting part 2 is located at the top surface of the connecting plate 1, and the lower end of the first connecting part 2 is located at the bottom surface of the connecting plate 1. In this embodiment, the upper end of the first connecting part 2 is specifically a socket, and the lower end of the first connecting part 2 is specifically a pin. The distribution density of the first connecting parts 2 is adapted to the distribution density of the connection points, and the distribution range of the first connecting parts 2 is larger than the distribution range of the connection points. The test base 3 has a plurality of second connecting parts 4 arranged in an array on its top surface. The second connecting parts 4 are arranged perpendicular to the top surface of the test base 3. The second connecting parts 4 are configured to be detachably plugged into the lower end of the first connecting parts 2. In this embodiment, the second connecting parts 4 are specifically plug holes adapted to the above-mentioned pins. The distribution density of the second connecting parts 4 is adapted to the distribution density of the first connecting parts 2, and the distribution range of the second connecting parts 4 is larger than the distribution range of the first connecting parts 2. The test panel 5 is provided with multiple test interfaces 501. The test panel 5 is disposed on the test base 3 and electrically connected to at least part of the second connection part 4. The test interfaces 501 are specifically PCIe interfaces, USB interfaces, etc., which can be flexibly set according to actual test requirements, and will not be described in detail here. The positioning and locking mechanism includes a first positioning pin 6 and a first positioning hole 7. The first positioning pin 6 is configured to be detachably inserted into the first positioning hole 7. A plurality of first positioning pins 6 are spaced apart along the circumferential direction of the connecting plate 1 at the outer edge of the bottom surface of the connecting plate 1 and perpendicular to the bottom surface of the connecting plate 1. A plurality of first positioning holes 7 are spaced apart at the top surface of the test base 3 and perpendicular to the top surface of the test base 3. The distribution position of the first positioning holes 7 is adapted to the distribution position of the first positioning pins 6. The number and distribution area of ​​the first positioning holes 7 are greater than the number and distribution area of ​​the first positioning pins 6. When each first positioning pin 6 is inserted into a first positioning hole 7, each first connecting part 2 is inserted into the second connecting part 4 in a one-to-one correspondence.

[0019] Specifically, in this embodiment, a connection board 1 is provided, which directly supports the chip 18 and connects the chip 18 to the test base 3. The distribution density of the first connection parts 2 on the connection board 1 matches that of the chip 18, so that each pin of the chip 18 corresponds to and is inserted into the first connection part 2. The number and distribution range of the first connection parts 2 are greater than the number and distribution range of the pins of the chip under test 18, thereby adapting to chips 18 with different package specifications and sizes. Moreover, multiple chips 18 can be inserted into a single connection board 1 at the same time, realizing parallel testing and experimentation of different chips 18. The second connection part 4 provided on the test base 3 is used for... The second connecting part 4 is inserted into the first connecting part 2, and the distribution density of the second connecting part 4 is adapted to the first connecting part 2 on the connecting plate 1 to ensure that each pin of the chip 18 is connected to the test base 3. The number and distribution range of the second connecting part 4 are greater than the number and distribution range of the first connecting part 2 on a single connecting plate 1, thereby achieving the technical effect of simultaneously inserting multiple connecting plates 1 so that multiple chips 18 can be tested at the same time. The first positioning pin 6 cooperates with the first positioning hole 7 to achieve both positioning and limiting functions, which helps to quickly and accurately position during insertion and can avoid damage to the test base 3 caused by positioning errors or displacement during testing.

[0020] Figure 2 It indicates Figure 1 The enlarged structural diagram of the first enlarged region A in the middle, combined with Figure 2 As can be seen, regarding the aforementioned positioning and locking mechanism, more specifically, The first positioning hole 7 protrudes from the test base 3, and a first limiting boss 701 is provided circumferentially on its lower outer side wall; a plurality of placement holes are arranged circumferentially on the upper side wall of the first positioning hole 7, and a ball 702 is placed in the placement hole, the diameter of the ball 702 being no larger than the diameter of the placement hole. It also includes a limiting ring 8, which is sleeved outside the first positioning hole 7 and slidably connected to the first positioning hole 7, with the sliding axis coinciding with the axis of the first positioning hole 7; a second limiting boss 801 is provided circumferentially on the upper part of the inner sidewall of the limiting ring 8, the inner sidewall of the second limiting boss 801 is slidably connected to the outer sidewall of the first positioning hole 7, and / or, the inner sidewall of the limiting ring 8 is slidably connected to the outer sidewall of the first limiting boss 701, and the sliding axis coincides with the axis of the first positioning hole 7; the distance between the inner sidewall of the limiting ring 8 and the outer sidewall of the first positioning hole 7 is less than the diameter of the sphere 702; It also includes a spring 9, which is sleeved on the outer wall of the first positioning hole 7 and located between the first limiting boss 701 and the second limiting boss 801. The two ends of the spring 9 are respectively pressed against the upper edge of the first limiting boss 701 and the lower edge of the second limiting boss 801. The spring 9 has an original state and a maximum compression state. When the spring 9 is in the original state, that is, in the state where it is not compressed by external force, the side wall of the second limiting boss 801 covers at least a part of the area of ​​the placement hole. When the spring 9 is in the maximum compression state, the side wall of the second limiting boss 801 does not cover the placement hole, and the upper edge of the limiting ring 8 is located between the upper edge and the lower edge of the placement hole. At the side wall of the first positioning pin 6 and the first positioning hole 7 that are detachably connected, a limiting groove 601 and a third limiting boss 602 are sequentially provided along the insertion direction. The limiting groove 601 and the third limiting boss 602 are both arranged circumferentially along the outer wall of the first positioning pin 6. The cross-sectional shapes of the third limiting boss 602 and the limiting groove 601, which are parallel to the circumference of the first positioning pin 6, are trapezoidal with an outward convex shape and an inward concave shape, respectively. When the first positioning pin 6 is inserted into the first positioning hole 7, the side wall of the third limiting boss 602 abuts against the inner side wall of the first positioning hole 7, and the sphere 702 is at least partially located in the limiting groove 601.

[0021] like Figure 1 As shown, the first limiting boss 701 restricts the movement of the limiting ring 8 and cooperates with the second limiting boss 801 to support the spring 9. Before the first positioning pin 6 is inserted into the first positioning hole 7, the limiting ring 8 is pressed down until the spring 9 is in its maximum compressed state. At this time, the ball 702 is freed from the restriction of the second limiting boss 801 on the limiting ring 8 and can move freely in the placement hole. Then, the first positioning pin 6 is inserted, and the third limiting boss 602 on the first positioning pin 6 first pushes the ball 702 back into the limiting hole. Then, the limiting groove 601 moves to the corresponding position of the ball 702. When the limiting ring 8 is released, the spring 9 returns to its original state after the external force is removed, pushing the limiting ring 8 upward to reset. During the reset process of the limiting ring 8, the second boss presses a part of the ball 702 into the limiting groove 601. At this time, the ball 702 is simultaneously in the placement hole and the limiting groove 601, realizing the limitation between the first positioning hole 7 and the first positioning pin 6. Afterwards, unless the limiting ring 8 is pressed down again and the second limiting boss 801 is moved to give the ball 702 enough room to move, the ball 702 will not be able to move, so that the first positioning pin 6 cannot be loosened or pulled out of the first positioning hole 7.

[0022] Through the above technical solution, this embodiment achieves rapid positioning and limiting when the connecting plate 1 and the test base 3 are plugged in, and the limiting is very firm. It will not shift during the detection and testing of the chip 18, thus avoiding damage to the test base 3.

[0023] like Figure 1 As shown, in a preferred embodiment of this invention, It also includes a component panel 17, on which a plurality of component interfaces 1701 are provided; the component panel 17 is disposed on the connecting plate 1 and electrically connected to the upper end of at least a portion of the first connecting part 2.

[0024] Specifically, in this preferred embodiment, the test panel 5 on the test base 3 faces the test system, while the component panel 17 on the connection board 1 faces the chip under test 18. Their different functions together constitute an efficient and flexible system. By setting up the component panel 17 and its component interface 1701, functional modules not originally included in the package can be added to the chip under test 18 via a rear-mount connection. This allows for simultaneous testing of multiple desired added functions on the original chip 18 without the need for specially designed chips 18 with different packages.

[0025] Example 2 like Figures 3-4 As shown, this embodiment provides a chip multi-station testing platform, whose structure is basically the same as that of Embodiment 1, except that: It also includes a heat dissipation component, which includes a heat exchange plate 10 and a heat dissipation fin assembly 11. The heat exchange plate 10 is provided with a first heat exchange surface and a second heat exchange surface that are opposite to each other. The first heat exchange surface is attached to one side of the heat dissipation fin assembly 11 and fixedly connected. The shape of the second heat exchange surface is adapted to the connecting plate 1. Multiple second positioning pins 12 are arranged in a circumferential array along the edge of the second heat exchange surface. The connecting plate 1 is provided with a second positioning hole 13 at a corresponding position on the upper side of the first connecting part 2. When the second positioning pin 12 is inserted into the corresponding second positioning hole 13, the second heat exchange surface contacts the top cover of the chip 18 inserted into the first connecting part 2.

[0026] Specifically This embodiment adds a heat sink to the basis of embodiment 1, which can ensure the test effect when facing high-specification chips 18 with high integration, high power consumption and high heat generation; the heat exchange plate 10 plays a direct heat exchange role with the chip 18, and the heat dissipation fin group 11 plays a timely role in dissipating the heat accumulated after heat exchange by the heat exchange plate 10; the second heat exchange surface of the heat exchange plate 10 fully covers the top surface of the connecting plate 1, so that the single or multiple chips 18 of different specifications inserted into the connecting plate 1 can all receive a good heat dissipation effect. The second positioning pin 12 and the second positioning hole 13 provided in this embodiment have the same structure as the first positioning pin 6 and the first positioning hole 7 in embodiment 1, and the operation method is also basically the same.

[0027] Example 3 like Figures 5-6 As shown, this embodiment provides a chip multi-station testing platform, whose structure is basically the same as that of Embodiment 2, except that: The connecting plate 1 is provided with a first hinge part 14 on one side of the upper end of the first connecting part 2, and a first fastening part 15 is provided on the other side opposite to the first connecting part 2. It also includes a pressure plate 16, on which a second hinge part 1601 and a second fastening part 1602 are provided. The second hinge part 1601 is hinged to the first hinge part 14, and the second fastening part 1602 is detachably connected to the first fastening part 15. The side of the pressure plate 16 facing the upper end of the first connecting part 2 is the pressure surface, and the side facing away from the cover surface is the third heat exchange surface. When the chip 18 is inserted into the first connecting part 2 and the second fastening part 1602 is connected to the first fastening part 15, the pressure surface covers the top cover of the chip 18 and is attached to and abuts against at least a portion of the top cover; and when the second positioning pin 12 is inserted into the corresponding second positioning hole 13, the second heat exchange surface covers the third heat exchange surface and is attached to and abuts against at least a portion of the third heat exchange surface. Multiple elastic parts 1603 are provided at the third heat exchange surface, and the elastic parts 1603 protrude from the third heat exchange surface in an arch shape.

[0028] Specifically This embodiment includes a pressure plate 16 to restrict the movement of the chip 18 on the connecting plate 1, preventing the chip 18 from being displaced by external forces and damaging its pins and the first connecting part 2. The pressure plate 16 is hinged to the first hinge part 14 on the connecting plate 1 via the second hinge part 1601, and is fastened to the first fastening part 15 on the connecting plate 1 via the second fastening part 1602. This allows for easy replacement of different test chips 18 at any time. The lever effect formed between the second fastening part 1602, the second hinge part 1601, and the chip 18 is the main source of pressure exerted by the pressure plate 16 on the chip 18.

[0029] In this embodiment, the pressure plate 16 serves as a medium between the heat sink and the chip 18. By closely adhering to and pressing against the top cover of the chip 18 and the heat exchange plate 10, it achieves sufficient heat conduction and ensures the heat dissipation effect of the heat sink.

[0030] The elastic part 1603 is provided so that when the heat exchange plate 10 presses down on the pressure plate 16, the elastic part 1603 first contacts the heat exchange plate 10 and undergoes elastic deformation under pressure. Its elastic deformation makes the pressure plate 16 and the top cover of the chip 18 more tightly pressed together and the contact is more sufficient. While improving the fixing effect, it reduces the gap between the heat exchange plate 10 and the pressure plate 16, and between the pressure plate 16 and the top cover of the chip 18, further improving the heat exchange efficiency and effect.

[0031] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of this application.

Claims

1. A multi-station chip testing platform, characterized in that, include: At least one connecting plate (1) is provided with an array of multiple first connecting parts (2), the first connecting parts (2) pass through the connecting plate (1), the upper end of the first connecting parts (2) is configured to be detachably plugged into the connection point of the chip, the distribution density of the first connecting parts (2) is adapted to the distribution density of the connection point, and the distribution range of the first connecting parts (2) is greater than the distribution range of the connection point. The test base (3) has multiple second connection parts (4) arranged in an array on it. The second connection parts (4) are configured to be detachably plugged into the lower end of the first connection part (2). The distribution density of the second connection parts (4) is adapted to the distribution density of the first connection part (2). The distribution range of the second connection parts (4) is greater than the distribution range of the first connection part (2). The test panel (5) is provided with multiple test interfaces (501); the test panel (5) is disposed on the test base (3) and electrically connected to at least part of the second connection part (4); The positioning and locking mechanism includes a first positioning pin (6) and a first positioning hole (7). The first positioning pin (6) is configured to be detachably inserted into the first positioning hole (7). A plurality of first positioning pins (6) are spaced apart along the circumferential direction of the connecting plate (1) on the outer edge of the connecting plate (1). A plurality of first positioning holes (7) are spaced apart on the test base (3). The distribution position of the first positioning holes (7) is adapted to the distribution position of the first positioning pins (6). The number and distribution area of ​​the first positioning holes (7) are greater than the number and distribution area of ​​the first positioning pins (6). When each of the first positioning pins (6) is inserted into a first positioning hole (7), each of the first connecting parts (2) is inserted into the second connecting part (4) in a corresponding manner.

2. The chip multi-station test bench according to claim 1, characterized in that, The first positioning hole (7) protrudes from the test base (3), and a first limiting boss (701) is provided circumferentially on its lower outer side wall; a plurality of placement holes are arranged circumferentially on the upper side wall of the first positioning hole (7), and a sphere (702) is placed in the placement hole, the diameter of the sphere (702) is not greater than the diameter of the placement hole; It also includes a limiting ring (8), which is sleeved outside the first positioning hole (7). The upper part of the inner sidewall of the limiting ring (8) is provided with a second limiting boss (801) along the circumferential direction. The inner sidewall of the second limiting boss (801) is slidably connected to the outer sidewall of the first positioning hole (7), and / or, the inner sidewall of the limiting ring (8) is slidably connected to the outer sidewall of the first limiting boss (701), and the sliding axis coincides with the axis of the first positioning hole (7); the distance between the inner sidewall of the limiting ring (8) and the outer sidewall of the first positioning hole (7) is less than the diameter of the sphere (702). It also includes a spring (9), which is sleeved on the outer wall of the first positioning hole (7) and located between the first limiting boss (701) and the second limiting boss (801). The two ends of the spring (9) are respectively pressed against the upper edge of the first limiting boss (701) and the lower edge of the second limiting boss (801). When the spring (9) is in its original state, the side wall of the second limiting boss (801) covers at least a portion of the area of ​​the placement hole. When the spring (9) is in its maximum compression state, the side wall of the second limiting boss (801) does not cover the placement hole, and the upper edge of the limiting ring (8) is located between the upper edge and the lower edge of the placement hole. A limiting groove (601) and a third limiting boss (602) are sequentially provided on the side wall of the first positioning pin (6) and the first positioning hole (7) along the insertion direction. The limiting groove (601) and the third limiting boss (602) are both arranged circumferentially along the outer wall of the first positioning pin (6). The cross-sectional shapes of the third limiting boss (602) and the limiting groove (601) parallel to the circumferential direction of the first positioning pin (6) are respectively convex and concave trapezoidal. When the first positioning pin (6) is inserted into the first positioning hole (7), the side wall of the third limiting boss (602) abuts against the inner side wall of the first positioning hole (7), and the sphere (702) is at least partially located in the limiting groove (601).

3. The chip multi-station test bench according to claim 1, characterized in that, It also includes a heat dissipation component, which includes a heat exchange plate (10) and a heat dissipation fin assembly (11). The heat exchange plate (10) is provided with a first heat exchange surface and a second heat exchange surface that are opposite to each other. The first heat exchange surface is attached to and fixedly connected to one side of the heat dissipation fin assembly (11). The shape of the second heat exchange surface is adapted to the connecting plate (1). Multiple second positioning pins (12) are arranged in a circumferential array at the edge of the second heat exchange surface. The connecting plate (1) is provided with a second positioning hole (13) at a corresponding position on the upper side of the first connecting part (2). When the second positioning pin (12) is inserted into the corresponding second positioning hole (13), the second heat exchange surface contacts the top cover of the chip inserted into the first connecting part (2).

4. The chip multi-station test bench according to claim 3, characterized in that, The connecting plate (1) is provided with a first hinge part (14) on one side of the upper end of the first connecting part (2), and a first fastening part (15) is provided on the other side opposite to the first hinge part (2). It also includes a pressure plate (16), on which a second hinge part (1601) and a second fastening part (1602) are provided. The second hinge part (1601) is hinged to the first hinge part (14), and the second fastening part (1602) is detachably connected to the first fastening part (15). The side of the pressure plate (16) facing the upper end of the first connecting part (2) is the pressure surface, and the side facing away from the cover is the third heat exchange surface. When the chip is inserted into the first connecting part (2) and the second fastening part (1602) is connected to the first fastening part (15), the pressure surface covers the top cover of the chip and is attached to and abuts against at least a portion of the top cover; and when the second positioning pin (12) is inserted into the corresponding second positioning hole (13), the second heat exchange surface covers the third heat exchange surface and is attached to and abuts against at least a portion of the third heat exchange surface.

5. A chip multi-station testing platform according to claim 4, characterized in that, The third heat exchange surface is provided with a plurality of elastic parts (1603), and the elastic parts (1603) protrude from the third heat exchange surface in an arch shape.

6. The chip multi-station test bench according to claim 1, characterized in that, It also includes a component panel (17) on which a plurality of component interfaces (1701) are provided; the component panel (17) is disposed on the connecting plate (1) and electrically connected to the upper end of at least a portion of the first connecting part (2).