A low-dropout protection circuit

Abstract

The utility model discloses a kind of low voltage drop protection circuits, comprising: power supply, current limiting circuit, main circuit, first ORING circuit and super capacitor, power supply one-way connection main circuit, another road is connected current limiting circuit and first ORING circuit in turn, first ORING circuit is connected with main circuit, one end of super capacitor is connected between current limiting circuit and first ORING circuit, the other end of super capacitor is grounded, to solve the problem caused by diode voltage drop in prior art, by adopting first ORING circuit to improve power efficiency, reach low-cost scheme, applicable to few peripheral circuits, the occasion of which power time demand is not high, first ORING circuit can also be optimized core power technology for the condition of more peripheral circuits, increase second ORING circuit, can be individually powered for core, further improve capacitor capacity utilization, can use smaller capacitor to meet design requirements.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, specifically to a low voltage drop protection circuit. Background Technology

[0002] In existing hardware power-saving technologies, most adopt methods such as... Figure 5 In this topology, supercapacitor C1 is charged via diode D1 and current-limiting resistor R1 when power is on. When power is off, supercapacitor C1 supplies power to the main circuit via diode D2 to complete a short-term power supply after power failure. This scheme is widely used, but it still has limitations. Since the unidirectional conduction function is completed by the diode, it is inevitably affected by the diode's forward voltage drop, which makes the supply voltage during power failure lower than the normal voltage during power-on. The actual supply voltage during power failure will be reduced by the voltage drop of the two diodes. Even if Schottky diodes are used, there will still be a voltage drop of nearly 0.5V. In some applications, the core power supply has relatively strict voltage range requirements, and the voltage drop caused by the diode will seriously affect the power supply time. Furthermore, using resistor current limiting will cause the supercapacitor to have an excessively long charging time at the end of the charging process, which will affect the actual use.

[0003] In addition, in most power-saving applications, the components requiring power protection are mostly the core and storage, while peripheral circuits do not need power protection. Figure 5 Existing power protection technologies cannot protect the core and storage separately, resulting in low utilization of the charge stored in the supercapacitor and significant waste of supercapacitor capacity. Utility Model Content

[0004] To address the above problems, this utility model provides a low voltage drop protection circuit to improve power protection efficiency.

[0005] This utility model is achieved through the following technical solution: A low voltage drop protection circuit includes: a power supply, a current limiting circuit, a main circuit, a first ORING circuit, and a supercapacitor. One power supply is connected to the main circuit, and the other is connected sequentially to the current limiting circuit and the first ORING circuit. The first ORING circuit is connected to the main circuit. One end of the supercapacitor is connected between the current limiting circuit and the first ORING circuit, and the other end of the supercapacitor is grounded.

[0006] In some embodiments, the low voltage drop protection circuit further includes: a peripheral circuit and a second ORING circuit, wherein: The second ORING circuit is provided between the power supply, the current limiting circuit, and the main circuit, and the peripheral circuit is provided between the power supply and the second ORING circuit.

[0007] In some embodiments, the first ORING circuit includes: MOSFET Q2, transistor Q4, and transistor Q6, wherein: The drain of the MOS transistor Q2 is connected to the emitter of the transistor Q6 and the core storage of the main circuit, respectively. The source of the MOS transistor Q2 is connected to the emitter of the transistor Q4. The gate of the MOS transistor Q2 is connected to the collector of the transistor Q6 and is connected to a first resistor. The base of the transistor Q4 is connected to the base of the transistor Q6 and is connected to a second resistor. The collector of the transistor Q4 is connected to a third resistor.

[0008] In some embodiments, the second ORING circuit includes: MOSFET Q1, transistor Q3, and transistor Q5, wherein: The drain of the MOSFET Q1 is connected to the emitter of the transistor Q5. The source of the MOSFET Q1 is connected to the emitter of the transistor Q3 and the power supply. The gate of the MOSFET Q1 is connected to the collector of the transistor Q5 and is connected to a fourth resistor. The base of the transistor Q3 is connected to the base of the transistor Q5 and is connected to a fifth resistor. The collector of the transistor Q3 is connected to a sixth resistor.

[0009] In some embodiments, the current limiting circuit includes an electronic load switch.

[0010] In some embodiments, the current limiting circuit further includes a DC-DC chip.

[0011] In some embodiments, MOSFETs Q1 and Q2 are channel MOSFETs with low drain-source resistance.

[0012] In some embodiments, transistors Q3, Q4, Q5, and Q6 are PNP transistors.

[0013] In some embodiments, the electronic load switch uses an external pull-down resistor connected to the SET pin to control the constant current value.

[0014] In some embodiments, the DC-DC chip integrates a built-in power MOSFET and uses FB feedback to adjust the voltage range and maximum current.

[0015] Compared with the prior art, this application has at least the following advantages or beneficial effects: This application discloses a low-voltage-drop protection circuit, comprising: a power supply, a current-limiting circuit, a main circuit, a first ORING circuit, and a supercapacitor. One power supply is connected to the main circuit, and the other is sequentially connected to the current-limiting circuit and the first ORING circuit. The first ORING circuit is connected to the main circuit. One end of the supercapacitor is connected between the current-limiting circuit and the first ORING circuit, and the other end of the supercapacitor is grounded. This addresses the problem caused by diode voltage drop in the prior art. By employing the first ORING circuit, the power protection efficiency is improved, achieving a low-cost solution suitable for applications with few external circuits and low power protection time requirements.

[0016] In a further technical approach, the core power protection technology is optimized for cases with many peripheral circuits by adding a second ORING circuit, which can perform power protection on the core separately, further improving capacitor utilization and allowing smaller capacitors to meet design requirements.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0018] The present application will be described in more detail below based on embodiments and with reference to the accompanying drawings.

[0019] Figure 1 A schematic diagram of an exemplary low-voltage drop protection circuit according to an embodiment of this application is shown; Figure 2 A schematic diagram of an exemplary low-voltage drop protection circuit according to an embodiment of this application is shown; Figure 3 This paper illustrates an exemplary low-voltage-drop protection circuit employing an electronic load switch current-limiting implementation as proposed in one embodiment of this application. Figure 4 This illustration shows an exemplary low-dropout protection circuit employing a current-limiting implementation using a DC-DC power chip (BUCK type) according to an embodiment of this application. Figure 5 This application illustrates a general power-saving technology solution in the prior art proposed in one embodiment of the present application. Detailed Implementation

[0020] The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] In view of the existing technology Figure 5 The power protection technology cannot protect the core and storage separately, resulting in low utilization of the charge stored in the supercapacitor and significant waste of supercapacitor capacity. Furthermore, the resistance value of the current-limiting resistor is also difficult to select. If the resistance value is too large, the charging time will be too long; if the resistance value is too small, the starting inrush current will be too large. The selection range is quite strict.

[0022] This utility model provides a low voltage drop protection circuit, see reference. Figure 1 The diagram shows a low voltage drop protection circuit. Figure 1 The system includes: a power supply, a current limiting circuit, a main circuit, a first ORING circuit, and a supercapacitor. One power supply is connected to the main circuit, and the other is connected to the current limiting circuit and the first ORING circuit in sequence. The first ORING circuit is connected to the main circuit. One end of the supercapacitor is connected between the current limiting circuit and the first ORING circuit, and the other end of the supercapacitor is grounded.

[0023] In this application, the problem of diode voltage drop caused by existing technology is reduced by design optimization using a first ORING circuit and a current limiting circuit to power the core and storage of the main circuit. This application achieves a low-cost solution that is suitable for occasions with few external circuits and low power-saving time requirements. The first ORING circuit solves the voltage drop problem of traditional power-saving circuits.

[0024] In cases where there are special requirements and the control core still needs to operate normally for a period of time after a power outage, this topology can be used. Figure 2 As shown, power preservation measures are implemented for all circuits after the power supply.

[0025] See Figure 2 The diagram shows another low-voltage-drop protection circuit. Figure 2 The low voltage drop protection circuit also includes: peripheral circuits and a second ORING circuit, wherein: A second ORING circuit is set between the power supply, the current limiting circuit, and the main circuit, and the peripheral circuit is set between the power supply and the second ORING circuit.

[0026] Figure 2 In the system, the external power supply is divided into two power circuits. One power circuit supplies power to the peripheral circuits, and the other enters the internal power circuit through the second ORING circuit. This circuit is also divided into two circuits. One circuit charges the C1 supercapacitor through the current limiting circuit, and the other directly supplies power to the core and storage of the main circuit. After the external power supply of the system is lost, the supercapacitor C1 supplies power to the core and storage through the first ORING circuit. Since the first ORING circuit is reverse cut off, the energy stored in the C1 capacitor can be used for almost all the required purposes.

[0027] In this embodiment, the topology is modified to separate the peripheral circuits from the core and its surrounding circuits for partial power protection. Simultaneously, the current limiting scheme is optimized, and a constant current charging method is used to charge the supercapacitor. This is the core power protection technology topology of this application, and the components used are compared to... Figure 1 This is more suitable for situations with more peripheral circuits. In most applications, after an auxiliary power undervoltage fault occurs, only the main circuit core needs to record the fault information, or wirelessly upload the fault information. At this time, the peripheral circuits do not need to work. Figure 2 The topology can provide power protection for the core of the main circuit separately, further improving the utilization rate of capacitor capacity and allowing the use of smaller capacitors to meet design requirements.

[0028] In some implementations, the first ORING circuit includes: MOSFET Q2, transistor Q4, and transistor Q6, wherein: The drain of MOSFET Q2 is connected to the emitter of transistor Q6 and the core memory of the main circuit. The source of MOSFET Q2 is connected to the emitter of transistor Q4. The gate of MOSFET Q2 is connected to the collector of transistor Q6 and is connected to a first resistor. The base of transistor Q4 is connected to the base of transistor Q6 and is connected to a second resistor. The collector of transistor Q4 is connected to a third resistor.

[0029] In some implementations, the second ORING circuit includes: MOSFET Q1, transistor Q3, and transistor Q5, wherein: The drain of MOSFET Q1 is connected to the emitter of transistor Q5. The source of MOSFET Q1 is connected to the emitter of transistor Q3 and the power supply. The gate of MOSFET Q1 is connected to the collector of transistor Q5 and is connected to a fourth resistor. The base of transistor Q3 is connected to the base of transistor Q5 and is connected to a fifth resistor. The collector of transistor Q3 is connected to a sixth resistor.

[0030] In a specific implementation: See Figure 3 This application provides an exemplary low-voltage-drop protection circuit that employs an electronic load switch current-limiting implementation.

[0031] Figure 3 The small and medium boxes 1 can correspond to Figure 2 The second ORING circuit in the diagram, indicated by box 2, corresponds to... Figure 2 The current limiting circuit and C1 in the diagram, as indicated by box 3, can be identified. Figure 2 The first ORING circuit in the circuit.

[0032] Figure 3In the circuit, the second ORING circuit consists of Q1, Q3, Q5, R3, R4, and R5. Pin 3 of Q1 is connected to the power supply and pin 3 of Q3. Pin 2 of Q1 is connected to the structure inside the small box 2 and pin 3 of Q5. Q3 and Q5 are symmetrically arranged. Pin 1 of Q3 and Q5 are connected to each other and connected to R4. Pin 2 of Q3 is connected to R3. Pin 1 of Q5 is connected to R5. Pin 1 of Q1 is connected between R5 and pin 2 of Q3. The unconnected ends of R3, R4, and R5 are connected to the power supply and ground in the structure inside the small box 2, respectively.

[0033] Within the structure marked in small box 2, pin 5 of electronic load switch U1 can be connected to Q3 and Q5 and one end of C1 respectively, and then connected to the structure marked in small box 3. Pin 4 of electronic load switch U1 is connected to R1 and then connected between Q1 and Q3. Pin 3 of electronic load switch U1 is connected to R2 and then grounded. The other end of C1 is grounded. Pin 2 of electronic load switch U1 is grounded. Pin 1 of electronic load switch U1 is connected to the positive terminal of C2, and the negative terminal of C2 is grounded.

[0034] Within the structure marked in small box 3, the first ORING circuit consists of Q2, Q4, Q6, R6, R7, and R8. Pin 3 of Q2 is connected to pin 3 of Q4, the positive terminal of C2, and pin 1 of the electronic load switch U1. Pin 2 of Q1 is connected to the core storage of the main circuit and pin 3 of Q6. Q4 and Q6 are symmetrically arranged, and pin 1 of Q4 and Q6 are connected to each other and connected to R7. Pin 2 of Q4 is connected to R6, and pin of Q6 is connected to R8. Pin 1 of Q1 is connected between pin 2 of R8 and pin of Q6. The unconnected ends of R6, R7, and R8 are connected to the core storage of the main circuit and ground in the structure marked in small box 2.

[0035] Figure 3 In the process, after the power supply is turned on, Q3 and Q1 are turned on. The emitter voltage of Q5 will be slightly less than the emitter voltage of Q3. Since the base voltages of Q3 and Q5 are equal after Q3 is saturated, the EC voltage of Q5 will be slightly less than the EC voltage drop during saturation, keeping the gate voltage of Q1 low and Q1 on. Because the internal resistance of the MOSFET is small, the voltage drop is much smaller than that of the diode. Therefore, the voltage after Q1 is not much different from the power supply voltage. One loop supplies the internal circuit, and the other loop charges the supercapacitor through the current limiting circuit. The current limiting circuit provides two solutions. Figure 3 An electronic load switch is used as a current limiting device. The electronic load switch chip can control the constant current value through an external pull-down resistor connected to the SET pin. When the external power supply fails, the supercapacitor supplies power to the inner loop circuit through a similar Q2 circuit. Due to the failure of the external power supply, Q3 stops working, the base voltage of Q5 drops until Q5 is turned on, raising the gate voltage of Q1 and turning off Q1, so that the C1 supercapacitor only supplies power to the core circuit.

[0036] In some implementations, U1 is a commonly used electronic switch with current limiting function, and the withstand voltage and maximum current are determined according to the specific circumstances.

[0037] In this embodiment, the electronic load switch changes linearly and generates heat in high power supply voltage applications. Therefore, it is suitable for applications with lower power supply voltages, and it has fewer components, a simple circuit, and low cost.

[0038] See Figure 4 This application provides an exemplary low-voltage-drop protection circuit that employs a DC-DC power chip (BUCK type) current-limiting implementation method.

[0039] Figure 4 The small and medium boxes 1 can correspond to Figure 2 The second ORING circuit in the diagram, indicated by box 2, corresponds to... Figure 2 The current limiting circuit and C1 in the diagram, as indicated by box 3, can be identified. Figure 2 The first ORING circuit in the circuit.

[0040] In the attached diagram, the specific structures of the first and second ringing circuits are similar. In this embodiment, a DC-DC power supply chip (BUCK type) is used as... Figure 2 The current limiting circuit in the diagram has specific connections, which will not be described in detail here.

[0041] Appendix Figure 4 The constant current section of the Chinese solution is slightly different. It uses a DC-DC chip for constant current, where R6 has a small resistance value, and the values ​​of R2 and R3 should be much larger than R6, so that the current in this circuit is much smaller than the capacitor charging current. When the charging current increases, the voltage drop across R6 increases until the voltage at the FB pin (pin 5) reaches the reference, and this current will be maintained for charging to achieve the constant current effect. Since the resistance of R6 is very small, the voltage drop generated by the supercapacitor supplying power across R6 after the power supply is turned off can also be ignored.

[0042] Among them, the appendix Figure 4 The U1 is a commonly used DC-DC power chip (BUCK type), which integrates a built-in power MOSFET and supports FB feedback to adjust the output. The specific voltage range and maximum current are determined according to the actual circuit used.

[0043] In this embodiment, a wider range of power supply voltages is applied, and the heat generation is better at slightly higher power supply voltages. Figure 4 The electronic load switch scheme is described.

[0044] It should be noted that this application Figure 3 and Figure 4 In response to Figure 2 Detailed design, remove Figure 3 With appendix Figure 4The small box 1 marked in the text can be used as an attachment. Figure 2 Detailed design.

[0045] In some preferred embodiments, considering the large parameter errors caused by the discreteness of transistor manufacturing processes, Q3 and Q5 are grouped together, and Q4 and Q6 are grouped together. Each group preferably uses a dual-diode integrated chip to ensure that the transistor parameters within a group are relatively similar.

[0046] In summary, the low voltage drop protection circuit provided in this application solves the voltage drop problem of traditional power protection circuits through the first ORING circuit, while completing local power protection by improving the second ORING circuit, and proposing two constant current schemes for different application scenarios.

[0047] Using the improved solution of this application, the voltage drop caused by the unidirectional conducting device in the power protection circuit can be significantly reduced. After testing, the actual power protection supply voltage is only about 120mV lower than the power supply voltage, which greatly improves the power protection capability. The constant current circuit enables the supercapacitor to charge linearly, making the charging process uniform and improving the end charging efficiency. The optimized topology can realize local power supply of the system, further improving the power protection efficiency.

[0048] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A low-dropout protection circuit, characterized by, include: The system includes a power supply, a current limiting circuit, a main circuit, a first ORING circuit, and a supercapacitor. One power supply is connected to the main circuit, and the other is connected to the current limiting circuit and the first ORING circuit in sequence. The first ORING circuit is connected to the main circuit. One end of the supercapacitor is connected between the current limiting circuit and the first ORING circuit, and the other end of the supercapacitor is grounded.

2. A low-dropout protection circuit according to claim 1, wherein Also includes: The peripheral circuit and the second ORING circuit, wherein: The second ORING circuit is provided between the power supply, the current limiting circuit, and the main circuit, and the peripheral circuit is provided between the power supply and the second ORING circuit.

3. A low-dropout protection circuit according to claim 2, wherein, The first ORING circuit includes: MOSFET Q2, transistor Q4, and transistor Q6, wherein: The drain of the MOS transistor Q2 is connected to the emitter of the transistor Q6 and the core storage of the main circuit, respectively. The source of the MOS transistor Q2 is connected to the emitter of the transistor Q4. The gate of the MOS transistor Q2 is connected to the collector of the transistor Q6 and is connected to a first resistor. The base of the transistor Q4 is connected to the base of the transistor Q6 and is connected to a second resistor. The collector of the transistor Q4 is connected to a third resistor.

4. A low-dropout protection circuit according to claim 2, wherein The second ORING circuit includes: MOSFET Q1, transistor Q3, and transistor Q5, wherein: The drain of the MOSFET Q1 is connected to the emitter of the transistor Q5. The source of the MOSFET Q1 is connected to the emitter of the transistor Q3 and the power supply. The gate of the MOSFET Q1 is connected to the collector of the transistor Q5 and is connected to a fourth resistor. The base of the transistor Q3 is connected to the base of the transistor Q5 and is connected to a fifth resistor. The collector of the transistor Q3 is connected to a sixth resistor.

5. A low-dropout protection circuit according to claim 2, wherein The current limiting circuit includes an electronic load switch.

6. A low-dropout protection circuit according to claim 2, wherein The current limiting circuit also includes a DC-DC chip.

7. A low-dropout protection circuit according to claim 4, wherein The MOSFETs Q1 and Q2 are channel MOSFETs with low drain-source resistance.

8. A low-dropout protection circuit according to claim 4, wherein, Transistors Q3, Q4, Q5, and Q6 are PNP type transistors.

9. A low-dropout protection circuit according to claim 5, wherein, The electronic load switch uses an external pull-down resistor connected to the SET pin to control the constant current value.

10. A low voltage drop protection circuit according to claim 6, characterized in that, The DC-DC chip integrates a built-in power MOSFET and uses FB feedback to adjust the voltage range and maximum current.

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