A discrete logic circuit for a small timing switch

Abstract

This utility model relates to a discrete logic circuit for a small timer switch, belonging to the field of logic control circuit technology. It includes a crystal oscillator, a frequency divider, a D flip-flop a, a binary counter, a multi-input AND gate, a three-position selector switch, an OR gate, a D flip-flop b, and a reset button. The crystal oscillator is divided to a 1Hz second pulse to drive the binary counter. The multi-input AND gate accurately decodes 3600 seconds and 7200 seconds. The three-position selector switch enables control of three operating modes: 1 hour, 2 hours, or normally open. Advantages include a novel structure, timing accuracy far exceeding traditional RC timing circuits based on a crystal oscillator time base, strong electromagnetic interference resistance of the digital logic circuit, use of standard discrete components eliminating the need for a dedicated control chip, compact circuit structure, small PCB area, making it particularly suitable for portable devices, extremely low static power consumption of the discrete logic components, making it particularly suitable for battery-powered or energy-efficient applications, and good long-term operational stability.

Description

Technical Field

[0001] This utility model belongs to the field of logic control circuit technology, specifically relating to a discrete logic circuit for a small timer switch. This discrete logic circuit achieves precise timing control based on pure hardware logic and is suitable for applications such as USB Type-C small power switches and charger timing control. Background Technology

[0002] With the rapid development of small electronic devices, the demand for timed switching control circuits is increasing. In applications such as smartphone chargers, power supply control for small electronic products, and time management for children's devices, reliable timed control circuits are needed to achieve automatic power-off functionality. Traditional timed control solutions mainly rely on microcontrollers (MCUs) or complex digital chips, which suffer from high power consumption, poor interference immunity, and relatively high cost.

[0003] Existing timing control circuits mostly employ analog solutions such as the 555 timer and RC oscillator circuits. While these circuits are simple, their timing accuracy is low, their long-term stability is poor, and they struggle to achieve precise control across various timing modes. The drift problem of analog timing circuits is particularly pronounced in applications requiring longer timing periods such as 1 hour or 2 hours.

[0004] On the other hand, most existing digital logic timing circuits are complex in design, requiring a large number of logic gates or dedicated timing control chips. This not only increases circuit complexity and cost but also makes the circuits bulky, making it difficult to meet the application requirements of miniaturized devices. Moreover, existing solutions lack optimized designs for small timing switch applications, and have shortcomings in interface adaptation, mode selection, and status display.

[0005] Therefore, it is necessary to propose a timing control circuit based on discrete logic devices to solve the technical problems of low accuracy, poor stability, large size and high power consumption in existing timing control circuits, and to provide a highly reliable, low-power and miniaturized logic control solution for small timing switch applications. Summary of the Invention

[0006] This invention provides a discrete logic circuit for a small timer switch to solve the problems of low accuracy, poor stability, large size and high power consumption of existing timer control circuits.

[0007] The technical solution adopted by this utility model includes a crystal oscillator, a frequency divider, a D flip-flop a, a binary counter, a multi-input AND gate, a three-position selector switch, an OR gate, a D flip-flop b, and a reset button. The output of the crystal oscillator is connected to the oscillation input of the frequency divider. The high-order division output of the frequency divider is connected to the clock input of the D flip-flop a. The 1Hz second pulse output of the D flip-flop a is connected to the clock input of the binary counter. Multiple outputs of the binary counter are respectively connected to the inputs of the multi-input AND gate. The three positions of the three-position selector switch are respectively connected to the outputs of different timing decoding channels of the multi-input AND gate and the ground terminal; the common terminal is connected to one input of the OR gate. The output of the OR gate is connected to the clock input of the D flip-flop b. Each output of the reset button is respectively connected to the reset input of the frequency divider, the reset input of the D flip-flop a, the clear input of the binary counter, and the reset input of the D flip-flop b.

[0008] The oscillation frequency of the crystal oscillator is 32.768 kHz.

[0009] The frequency divider is a multi-stage frequency divider circuit that divides 32.768kHz to 1Hz.

[0010] The binary counter is a 13-bit counter with a counting range of 0-8191 seconds, meeting the timing requirements of 1 hour and 2 hours.

[0011] The multi-input AND gate includes at least two four-input AND gates, which are used to decode 3600-second and 7200-second count values, respectively, corresponding to 1-hour and 2-hour timing lengths. The four input terminals of each AND gate are connected to different combinations of output bits of the binary counter to form several timing decoding channels, which are used to generate decoding pulses when the corresponding count is reached, so as to achieve accurate decoding of specific count values.

[0012] The three-position selector switch can be set to 1 hour, 2 hours, or normally open mode. When it is in the normally open position, the corresponding input is grounded and suppressed, or the door does not generate a timed trigger.

[0013] The data terminal of the D flip-flop b is fixed at a high level so that the timing end signal is set and held at its Q terminal when triggered. The output timing control signal is used to drive an external level conversion circuit to control the high-side switch to realize the function of a small timing switch.

[0014] The reset button is used to clear the count and release the latch to restart the timing.

[0015] This invention also includes an LED running indicator, whose input terminal is connected to the 1Hz second pulse output terminal of the D trigger a, for periodically flashing during timing.

[0016] This invention also includes an LED status indicator, whose input terminal is connected to the Q terminal of the D flip-flop b, for keeping it constantly lit when the timing ends.

[0017] The advantages of this invention are: novel structure, pure hardware logic control, no risk of software failure, and good long-term working stability; based on a crystal oscillator time base, the timing accuracy is much higher than that of traditional RC timing circuits; the digital logic circuit has strong anti-electromagnetic interference capability and can still work stably in complex electromagnetic environments; it uses standard discrete components, eliminating the need for dedicated control chips, resulting in low mass production costs; the circuit structure is compact, with a small PCB area, making it particularly suitable for portable device applications; and the discrete logic devices have extremely low static power consumption, making them particularly suitable for battery-powered applications or applications with high energy-saving requirements. Attached Figure Description

[0018] Figure 1 This is the circuit schematic diagram of this utility model; Figure 2 This is a schematic diagram of the application of this utility model to a small timer switch. Detailed Implementation

[0019] The preferred embodiments of this utility model will be described in detail below with reference to the accompanying drawings. It should be understood that conventional techniques and components known to those skilled in the art will not be elaborated upon in this specification. The scope of protection of this utility model should be determined by the claims, and not limited to the following embodiments.

[0020] The system includes a crystal oscillator 1, a frequency divider 2, a D flip-flop a3, a binary counter 4, a multi-input AND gate 5, a three-position selector switch 6, an OR gate 7, a D flip-flop b8, and a reset button 9. The output of the crystal oscillator 1 is connected to the oscillation input of the frequency divider 2. The high-order division output of the frequency divider 2 is connected to the clock input of the D flip-flop a3. The 1Hz second pulse output of the D flip-flop a3 is connected to the clock input of the binary counter 4. The multiple outputs of the binary counter 4 are connected to the inputs of the multi-input AND gate 5. The three positions of the three-position selector switch 6 are connected to the outputs of different timing decoding channels and the ground terminal of the multi-input AND gate 5, respectively. The common terminal is connected to one input of the OR gate 7. The output of the OR gate 7 is connected to the clock input of the D flip-flop b8. The outputs of the reset button 9 are connected to the reset terminals of the frequency divider 1, the D flip-flop a3, the clear terminal of the binary counter 4, and the reset terminal of the D flip-flop b, respectively.

[0021] The oscillation frequency of the crystal oscillator 1 is 32.768 kHz.

[0022] The frequency divider 2 is a multi-stage frequency divider circuit that divides 32.768kHz to 1Hz.

[0023] The binary counter 4 is a 13-bit counter with a counting range of 0-8191 seconds, meeting the timing requirements of 1 hour and 2 hours.

[0024] The multi-input AND gate 5 includes at least two four-input AND gates, which are used to decode the 3600-second count value and the 7200-second count value, respectively, corresponding to a timing length of 1 hour and 2 hours. The four input terminals of each AND gate are connected to different combinations of output bits of the binary counter 4 to form several timing decoding channels, which are used to generate decoding pulses when the corresponding count is reached, so as to realize the accurate decoding of a specific count value.

[0025] The three-position selector switch 6 selects 1 hour, 2 hours or normally open mode. When it is in the normally open position, the corresponding input is grounded and suppressed, and the OR gate 7 does not generate a timed trigger.

[0026] The data terminal of the D flip-flop b8 is fixed at a high level so that the timing end signal is set and held at its Q terminal when triggered. The output timing control signal is used to drive the external level conversion circuit 12 to control the high-side switch to realize the small timing switch function.

[0027] The reset button 9 is used to clear the count and release the latch to restart the timing.

[0028] It also includes an LED running indicator 10, whose input is connected to the 1Hz second pulse output of the D flip-flop a3, for periodically flashing during timing.

[0029] It also includes an LED status indicator 11, whose input is connected to the Q terminal of the D flip-flop b8, and is used to keep it constantly lit when the timing ends.

[0030] The two channels mentioned above use dual-color LEDs to achieve differentiated display.

[0031] Working principle: (1) Clock generation and frequency division logic: The clock generation of this utility model consists of a 32.768kHz crystal oscillator and a multi-stage frequency divider. The crystal oscillator adopts a standard quartz crystal resonator and outputs a stable 32.768kHz reference frequency signal. This signal is connected to the oscillation input terminal of the frequency divider. The frequency divider adopts a multi-stage binary frequency divider circuit design to divide the 32.768kHz signal by two stage by stage. The high-order frequency division output of the frequency divider is 2Hz and connected to the clock terminal of D flip-flop a. D flip-flop a divides the frequency by two again to generate a precise 1Hz second pulse signal.

[0032] This 1Hz second pulse serves as the reference clock for the entire discrete logic circuit, ensuring high precision and long-term stability in timing control. Compared to traditional RC oscillator circuits, crystal oscillators offer advantages such as better temperature stability and higher frequency accuracy, maintaining a stable clock output over a wider ambient temperature range.

[0033] (2) Counting and decoding logic: A 1Hz second pulse is connected to the clock input of a 13-bit binary counter. The counter accumulates counts by second, covering a range of 0-8191 seconds, which fully meets the timing requirements of 1 hour (3600 seconds) and 2 hours (7200 seconds). Each output bit Q0-Q12 of the 13-bit binary counter represents a different binary weight. By selecting the combination of these output bits, any second value can be accurately decoded.

[0034] Specifically, the four inputs of the first four-input AND gate are connected to the output bits Q11, Q10, Q9, and Q4 of the counter. When the logic state of these bits is high simultaneously, it indicates that the counter value is exactly 3600, and the AND gate outputs a high-level pulse, corresponding to the arrival of the 1-hour timer. Similarly, the second four-input AND gate is connected to the output bits Q12, Q11, Q10, and Q5. When the count value is 7200, it outputs a pulse, corresponding to the arrival of the 2-hour timer.

[0035] This binary decoding-based method features high precision and stability, avoids the drift problem of analog circuits, and achieves truly precise timing control.

[0036] (3) Mode selection and logic control: The three fixed contacts of the three-position selector switch are connected to: the first position is connected to the 1-hour decoding output, the second position is connected to the 2-hour decoding output, and the third position is connected to the circuit ground. When the user switches to the first position, the 1-hour decoding signal can be transmitted to the subsequent circuit through the selector switch; when switched to the second position, the 2-hour decoding signal is selected; when switched to the third position (normally open mode), the selection path is grounded, all timing signals are suppressed, the discrete logic circuit does not generate timing triggers, and the normally open control logic is realized.

[0037] (4) Latch and Reset Logic: The timing trigger signal output by the OR gate is connected to the clock input of the D flip-flop b, and the data input of the D flip-flop b is fixedly connected to the power supply voltage (logic high level). Under normal operating conditions, the clock input of the D flip-flop b remains at a low level, and the output remains at a low level. When the timing arrives, the timing trigger signal generates a positive transition. Triggered by the rising edge of the clock signal, the D flip-flop b latches the high level of the data input to the output. Thereafter, the output continues to output a high level, forming a stable timing end indication signal.

[0038] Due to the latching characteristic of the D flip-flop b, even if the timing trigger signal is only a momentary pulse, the output state will remain unchanged, ensuring the stability and reliability of the timing end signal. This latching logic design avoids the impact of signal jitter on the control logic and improves the reliability of discrete logic circuits.

[0039] The reset button provides a manual clearing function. After the button output is processed by the RC debouncing circuit, when the reset button is pressed, the reset signal acts on all logic devices simultaneously: the frequency divider is reset to the initial state and starts frequency division again; the binary counter is cleared and starts counting again; the D flip-flop b is reset, causing the Q output to return to a low level, and the entire discrete logic circuit returns to the initial working state and starts a new round of timing control cycle.

[0040] (5) Indication and Output Logic: The discrete logic circuit is equipped with LED indicator logic for intuitive display of the working status: The anode of the operation indicator LED is connected to a 1Hz second pulse signal via a current-limiting resistor, while the cathode is grounded. During timed operation, the 1Hz pulse drives the LED to blink at a 1-second cycle, providing a clear indication of the timed operation.

[0041] The anode of the status indicator LED is connected to the output of the D flip-flop b through a current-limiting resistor, and the cathode is grounded. During normal timing, the Q terminal is at a low level and the status LED is off. When the timing ends, the Q terminal outputs a high level and the status LED stays on, clearly indicating that the timing control has been completed.

[0042] Using dual-color LEDs or two LEDs of different colors can achieve a more intuitive display of status differentiation. Users can accurately understand the working status of discrete logic circuits by observing the blinking or constant-on state of the LEDs.

[0043] The following application example in a small timer switch will further illustrate this utility model.

[0044] The specific application of this utility model's discrete logic circuit in a small Type-C timer power switch is as follows: Figure 2 As shown in the image, this application example demonstrates how discrete logic circuits can work with external circuits to form a complete small-scale timing switch control system.

[0045] System Composition and Connection: The entire small timing switch system includes: a Type-C input interface, an input protection circuit, the discrete logic circuit of this invention, a level conversion unit, a high-side switch, an output protection circuit, and a Type-C output interface. This invention serves as the core control unit of the system, with its D flip-flop b output connected to the input of the level conversion unit. The level conversion unit uses an NMOSFET switch, whose gate receives the timing control signal from the discrete logic circuit, its drain is connected to the turn-off control terminal of the high-side switch, and its source is grounded. The turn-off control terminal of the high-side switch is connected to the logic power supply through a pull-up resistor, ensuring that the high-side switch remains on when the discrete logic circuit outputs a low level.

[0046] Workflow: Initial state: After the system is powered on, the discrete logic circuit automatically resets to the initial state, the 32.768kHz crystal oscillator starts oscillating, and a stable 1Hz second pulse is generated by the frequency divider and D flip-flop a. The 13-bit binary counter starts counting from zero. At this time, the output of D flip-flop b outputs a low level, which turns off the NMOSFET in the external level conversion unit and turns on the high-side switch, so that the Type-C output interface is powered normally. Timing control process: The user selects the desired timing mode via a three-position selector switch: 1 hour, 2 hours, or normally open; in timing mode, the binary counter continuously accumulates counts, and the operation indicator LED flashes periodically driven by a 1Hz pulse to indicate to the user that the device is in timing control; when the count reaches the preset 3600 seconds (1 hour) or 7200 seconds (2 hours), the corresponding four-input AND gate outputs a decoded pulse, which is then selected by the three-position selector switch and OR gate to trigger the D flip-flop b; Timed arrival processing: After the D flip-flop b is triggered, the output terminal outputs a high level and maintains it. This high-level signal drives the NMOSFET in the level conversion unit to conduct, pulling down the high-side switch's turn-off control terminal to ground potential, thus turning off the high-side switch and cutting off the Type-C output power supply. At the same time, the status indicator LED remains lit, clearly indicating to the user that the timer has been reached and the device has stopped receiving power. Reset and Restart: When the user needs to restart the timing or restore the power supply, pressing the reset button will synchronously clear all logic states of the discrete logic circuits: the frequency divider and binary counter will reset and start working again, the output of the D flip-flop b will return to a low level, the high-side switch will be turned on again, and the system will return to its initial working state.

[0047] Specific application scenarios for the miniature timer switch: Smartphone charging control: When charging your phone before bed, set a 1-2 hour timer to avoid the impact of charging overnight on battery life.

[0048] Power supply for small electronic products: timed power supply control for devices such as Bluetooth speakers, LED desk lamps, and desktop fans.

[0049] Laboratory equipment protection: Provide timed power to testing instruments, charging equipment, etc., to avoid equipment damage that may be caused by prolonged operation.

[0050] The above application examples and scenarios fully demonstrate the practical value and technical advantages of this utility model in small-scale timer switch control, and provide an effective technical solution for the design and development of related products.

Claims

1. A discrete logic circuit for a small timer switch, characterized in that: The system includes a crystal oscillator, a frequency divider, a D flip-flop a, a binary counter, a multi-input AND gate, a three-position selector switch, an OR gate, a D flip-flop b, and a reset button. The output of the crystal oscillator is connected to the oscillation input of the frequency divider. The high-order division output of the frequency divider is connected to the clock input of the D flip-flop a. The 1Hz second pulse output of the D flip-flop a is connected to the clock input of the binary counter. The multiple outputs of the binary counter are connected to the inputs of the multi-input AND gate, respectively. The three positions of the three-position selector switch are connected to the outputs of different timing decoding channels of the multi-input AND gate and the ground terminal, respectively. The common terminal is connected to one input of the OR gate. The output of the OR gate is connected to the clock input of the D flip-flop b, respectively. The outputs of the reset button are connected to the reset terminals of the frequency divider, the D flip-flop a, the clear terminal of the binary counter, and the reset terminal of the D flip-flop b, respectively.

2. The discrete logic circuit for a small timer switch according to claim 1, characterized in that: The oscillation frequency of the crystal oscillator is 32.768 kHz.

3. A discrete logic circuit for a small timer switch according to claim 1, characterized in that: The frequency divider is a multi-stage frequency divider circuit that divides 32.768kHz to 1Hz.

4. A discrete logic circuit for a small timer switch according to claim 1, characterized in that: The binary counter is a 13-bit counter with a counting range of 0-8191 seconds, meeting the timing requirements of 1 hour and 2 hours.

5. A discrete logic circuit for a small timer switch according to claim 1, characterized in that: The multi-input AND gate includes at least two four-input AND gates, which are used to decode 3600-second and 7200-second count values, respectively, corresponding to 1-hour and 2-hour timing lengths. The four input terminals of each AND gate are connected to different combinations of output bits of the binary counter to form several timing decoding channels, which are used to generate decoding pulses when the corresponding count is reached, so as to achieve accurate decoding of specific count values.

6. A discrete logic circuit for a small timer switch according to claim 1, characterized in that: The three-position selector switch can be set to 1 hour, 2 hours, or normally open mode. When it is in the normally open position, the corresponding input is grounded and suppressed, or the door does not generate a timed trigger.

7. A discrete logic circuit for a small timer switch according to claim 1, characterized in that: The data terminal of the D flip-flop b is fixed at a high level so that the timing end signal is set and held at its Q terminal when triggered. The output timing control signal is used to drive an external level conversion circuit to control the high-side switch to realize the function of a small timing switch.

8. A discrete logic circuit for a small timer switch according to claim 1, characterized in that: The reset button is used to clear the count and release the latch to restart the timing.

9. A discrete logic circuit for a small timer switch according to claim 1, characterized in that: It also includes an LED running indicator, whose input is connected to the 1Hz second pulse output of the D flip-flop a, for periodically flashing during timing.

10. A discrete logic circuit for a small timer switch according to claim 1, characterized in that: It also includes an LED status indicator, whose input is connected to the Q terminal of the D flip-flop b, and is used to keep it constantly lit when the timing ends.

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