A PLC signal hierarchical dynamic noise reduction system and a PLC signal transmission device

Abstract

This utility model discloses a hierarchical dynamic noise reduction system and a PLC signal transmission device. The system includes a main control module, a signal input module, a first-level preprocessing unit, a second-level isolation unit, a noise feature extraction unit, a noise reduction strategy inference unit, a third-level fine processing unit, and a signal output module. The first-level preprocessing unit includes a pre-filter circuit and a signal type recognition circuit, with the pre-filter circuit incorporating a first-level RC low-pass filter. The noise feature extraction unit includes a sampling circuit and a noise feature analysis chip. The noise reduction strategy inference unit incorporates a flash memory chip storing a noise reduction strategy inference neural network model. The third-level fine processing unit includes an adaptive FIR filter. This utility model improves the noise reduction capability of PLC signal transmission and optimizes the transmission effect and accuracy of PLC signals by setting a hierarchical processing mechanism combined with a dynamic identification noise reduction mechanism.

Description

Technical Field

[0001] This utility model relates to the field of power line communication technology, and in particular to a PLC signal hierarchical dynamic noise reduction system and a PLC signal transmission device. Background Technology

[0002] Power line communication (PLC) is a communication technology that uses existing power lines as the physical transmission medium to transmit information such as data, voice, and images. Its core idea is to "reuse power infrastructure," upgrading power lines from a single carrier of electrical energy to a comprehensive transmission platform of "electrical energy + information." The birth and development of this technology profoundly reflects the surge in demand for "ubiquitous connectivity" in the information age, as well as the trend of deep integration between traditional infrastructure and emerging information technologies.

[0003] As power line communication (PLC) technology becomes more widespread in low-voltage power line communication scenarios such as smart grids and smart homes, its shortcomings are gradually becoming apparent. Traditional PLC transmission devices suffer from severely insufficient noise immunity, poor adaptability to dynamic noise, and an inability to dynamically identify and adjust noise reduction strategies. This results in significant consumption of communication resources while maintaining poor communication performance. Furthermore, the noise reduction process employs only a single-level processing method, which is insufficient to cover the noise suppression requirements of PLC signals from input acquisition to output drive, leading to poor noise reduction effects. Utility Model Content

[0004] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a PLC signal hierarchical dynamic noise reduction system and a PLC signal transmission device. By setting up a hierarchical processing mechanism and combining it with a dynamic identification noise reduction mechanism, the noise reduction capability of PLC signal transmission is improved, and the transmission effect and accuracy of PLC signals are optimized.

[0005] This utility model provides a PLC signal hierarchical dynamic noise reduction system. The system includes a main control module, a signal input module, a first-level preprocessing unit, a second-level isolation unit, a noise feature extraction unit, a noise reduction strategy inference unit, a third-level fine processing unit, and a signal output module. The main control module is connected to the signal input module, the first-level preprocessing unit, the second-level isolation unit, the noise feature extraction unit, the noise reduction strategy inference unit, the third-level fine processing unit, and the signal output module respectively. The signal input module, the first-level preprocessing unit, the second-level isolation unit, the noise feature extraction unit, the noise reduction strategy inference unit, the third-level fine processing unit, and the signal output module are connected sequentially. The first-level preprocessing unit includes a pre-filtering circuit and a signal type recognition circuit. The pre-filtering circuit has a built-in first-level RC low-pass filter, and the signal type recognition circuit has a built-in voltage comparator. The noise feature extraction unit includes a sampling circuit and a noise feature analysis chip, and the sampling circuit has a built-in sampling ADC. The noise reduction strategy inference unit has a built-in flash memory chip, which stores a noise reduction strategy inference neural network model. The three-stage fine processing unit includes an adaptive FIR filter.

[0006] Furthermore, the main control module has a built-in main control chip, the model of which is STM32H747DIH6.

[0007] Furthermore, the noise feature analysis chip is model ADI ADSP-BF533.

[0008] Furthermore, the secondary isolation unit incorporates a magnetic coupling isolation chip, an optocoupler isolation chip, and a DC-DC isolated power supply.

[0009] Furthermore, the magnetic coupling isolation chip is model ADI ADuM5402, and the optical coupling separation chip is model HCPL-0630.

[0010] Furthermore, the system also includes a feedback adjustment unit, which is located at the output of the third-level fine processing unit and is fed back into the noise reduction strategy inference unit.

[0011] Furthermore, the signal input module includes a differential input circuit.

[0012] Furthermore, the signal output module includes a level conversion circuit, which incorporates an LM358 operational amplifier.

[0013] Furthermore, the signal output module also includes a drive enhancement circuit, which incorporates a ULN2003 Darlington transistor.

[0014] This utility model also provides a PLC signal transmission device, which has the above-mentioned PLC signal hierarchical dynamic noise reduction system built in.

[0015] This invention provides a PLC signal hierarchical dynamic noise reduction system and a PLC signal transmission device. By setting up a hierarchical processing mechanism based on a first-level preprocessing unit, a second-level isolation unit, and a third-level fine processing unit, combined with a dynamic identification and noise reduction mechanism based on a noise feature extraction unit and a noise reduction strategy inference unit, the noise reduction capability of PLC signal transmission is improved, the transmission effect and accuracy of PLC signals are optimized, and the efficiency of power line communication is further improved. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a diagram of the PLC signal hierarchical dynamic noise reduction system architecture in Embodiment 1 of this utility model; Figure 2 This is a diagram of the architecture of the first-level preprocessing unit in Embodiment 1 of this utility model; Figure 3 This is a schematic diagram of the first-stage preprocessing unit circuit in Embodiment 1 of this utility model; Figure 4 This is a diagram of the noise feature extraction unit architecture in Embodiment 1 of this utility model; Figure 5 This is a diagram of the noise reduction strategy inference unit architecture in Embodiment 1 of this utility model; Figure 6 This is a diagram of the three-level fine processing unit architecture in Embodiment 1 of this utility model; Figure 7 This is a diagram of the secondary isolation unit architecture in Embodiment 1 of this utility model. Detailed Implementation

[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0019] In this invention, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, actions, components, portions or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the presence or addition of one or more other features, figures, steps, actions, components, portions or combinations thereof.

[0020] It should also be noted that, where there is no conflict, the embodiments and features in the embodiments of this utility model can be combined with each other. The present utility model will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] Example 1 This utility model provides a PLC signal hierarchical dynamic noise reduction system, which includes a main control module, a signal input module, a first-level preprocessing unit, a second-level isolation unit, a noise feature extraction unit, a noise reduction strategy inference unit, a third-level fine processing unit, and a signal output module. The main control module is connected to the signal input module, the first-level preprocessing unit, the second-level isolation unit, the noise feature extraction unit, the noise reduction strategy inference unit, the third-level fine processing unit, and the signal output module, which are connected sequentially. The first-level preprocessing unit includes a pre-filter circuit and a signal type recognition circuit. The pre-filter circuit has a built-in first-level RC low-pass filter, and the signal type recognition circuit has a built-in voltage comparator. The noise feature extraction unit includes a sampling circuit and a noise feature analysis chip. The sampling circuit has a built-in sampling ADC. The noise reduction strategy inference unit has a built-in flash memory chip, which stores a noise reduction strategy inference neural network model. The third-level fine processing unit includes an adaptive FIR filter.

[0022] In one optional implementation of this embodiment, such as Figure 1 As shown, Figure 1 The diagram illustrates the architecture of a PLC signal hierarchical dynamic noise reduction system according to Embodiment 1 of this utility model. The system includes a main control module, a signal input module, a first-level preprocessing unit, a second-level isolation unit, a noise feature extraction unit, a noise reduction strategy inference unit, a third-level fine processing unit, and a signal output module. The main control module is connected to the signal input module, the first-level preprocessing unit, the second-level isolation unit, the noise feature extraction unit, the noise reduction strategy inference unit, the third-level fine processing unit, and the signal output module, respectively. The signal input module, the first-level preprocessing unit, the second-level isolation unit, the noise feature extraction unit, the noise reduction strategy inference unit, the third-level fine processing unit, and the signal output module are connected sequentially.

[0023] Specifically, the PLC signal hierarchical dynamic noise reduction system mainly includes three main functional mechanisms: a hierarchical processing mechanism consisting of a first-level preprocessing unit, a second-level isolation unit, and a third-level fine processing unit; a dynamic identification and noise reduction mechanism consisting of a noise feature extraction unit and a noise reduction strategy inference unit; and a signal input and output mechanism consisting of a signal input module and a signal output module. The hierarchical dynamic noise reduction of PLC signals is achieved through the cooperation of these three mechanisms.

[0024] Furthermore, the input terminal of the signal input module is connected to the PLC input signal, and the output terminal of the signal output module outputs the PLC output signal.

[0025] In an optional implementation of this embodiment, the main control module has a built-in main control chip, the model of which is STM32H747DIH6.

[0026] In one optional implementation of this embodiment, such as Figure 2 and Figure 3 As shown, Figure 2 This diagram illustrates the architecture of the primary preprocessing unit in Embodiment 1 of the present invention. Figure 3 The schematic diagram of the first-stage preprocessing unit circuit in Embodiment 1 of this utility model is shown. The first-stage preprocessing unit includes a pre-filter circuit and a signal type recognition circuit. The pre-filter circuit has a built-in first-stage RC low-pass filter, and the signal type recognition circuit has a built-in voltage comparator.

[0027] Specifically, the pre-filter circuit includes an amplifier U1, resistors R1 and R2, a gain resistor Rg, diodes D1 and D2, a resistor R3, and a capacitor C1. The first end of resistor R1 is connected to the positive component of the PLC input signal, the first end of resistor R2 is connected to the negative component of the PLC input signal, the second end of resistor R1 is connected to the positive input terminal of amplifier U1, the second end of resistor R2 is connected to the negative input terminal of amplifier U1, the first end of gain resistor Rg is connected to the first end of resistor R1, and the second end of gain resistor Rg is connected to the output terminal of amplifier U1. The cathode of diode D1 is connected to the first end of resistor R1, the cathode of diode D2 is connected to the first end of resistor R2, and the anodes of diodes D1 and D2 are both grounded. The first end of resistor R3 is connected to the output terminal of amplifier U1, the second end of resistor R3 is connected to the first end of capacitor C1, and the second end of capacitor C1 is grounded.

[0028] Furthermore, the amplifier U1 provides differential input, suppresses common-mode noise, and amplifies the signal. The gain resistor Rg serves as the gain setting resistor, determining the gain of the amplifier U1. The diodes D1 and D2 act as input protection diodes to prevent overvoltage of the input signal. The resistor R3 and capacitor C1 form a first-stage RC low-pass filter to suppress high-frequency noise.

[0029] Furthermore, the amplifier U1 is an AD620 instrumentation amplifier, the gain resistor Rg has a resistance of 1kΩ, the diodes D1 and D2 are Schottky diodes, the resistor R3 has a resistance of 1kΩ, the capacitor C1 has a capacitance of 100pF, and the cutoff frequency is 1.59MHz.

[0030] Furthermore, the signal type identification circuit includes a voltage comparator U2, a resistor R4, and a resistor R5. The positive input terminal of the voltage comparator U2 is connected to the second terminal of the resistor R3 and the first terminal of the capacitor C1. The first terminal of the resistor R4 is connected to the reference voltage terminal Vref. The second terminal of the resistor R4 and the first terminal of the resistor R5 are connected to the negative input terminal of the voltage comparator U2. The second terminal of the resistor R5 is grounded. The output terminal of the voltage comparator U2 is connected to the secondary isolation unit.

[0031] Furthermore, the voltage comparator U2 detects the amplitude and edge of the PLC signal after it has been processed by the pre-filter circuit. Based on the reference voltage signal, it automatically identifies the digital and analog quantities in the PLC signal and outputs a high-level or low-level signal to the secondary isolation unit.

[0032] Furthermore, the voltage comparator U2 is an LM339 comparator, and the resistance values ​​of resistors R4 and R5 are both 10kΩ.

[0033] In one optional implementation of this embodiment, such as Figure 4 As shown, Figure 4 The diagram shows the architecture of a noise feature extraction unit in Embodiment 1 of this utility model. The noise feature extraction unit includes a sampling circuit and a noise feature analysis chip. The sampling circuit has a built-in sampling ADC.

[0034] Specifically, the sampling ADC is model ADI AD7606.

[0035] Furthermore, the noise feature analysis chip is model ADI ADSP-BF533.

[0036] Furthermore, the noise feature extraction unit samples the PLC signal processed by the first-level preprocessing unit based on the sampling circuit, and combines it with the noise feature analysis chip to analyze the noise spectrum characteristics of the sampled signal based on the FFT analysis method, including frequency, amplitude, and time-domain waveform, and transmits the data to the noise reduction strategy inference unit.

[0037] In one optional implementation of this embodiment, such as Figure 5 As shown, Figure 5 The diagram shows the architecture of the noise reduction strategy inference unit in Embodiment 1 of this utility model. The noise reduction strategy inference unit has a built-in flash memory chip, which stores the noise reduction strategy inference neural network model.

[0038] Specifically, the flash memory chip is model W25Q128, which has a pre-trained noise reduction strategy inference neural network model (using LSTM or 1D-CNN framework). When the noise feature extraction unit sends the noise spectrum features of the PLC signal, it processes and outputs the optimal filtering strategy, including FIR coefficients and isolation level.

[0039] In one optional implementation of this embodiment, such as Figure 6 As shown, Figure 6 The diagram shows the architecture of a three-level fine processing unit in Embodiment 1 of this utility model. The three-level fine processing unit includes an adaptive FIR filter, which performs FIR adaptive filtering based on the FIR coefficients generated by the noise reduction strategy inference unit.

[0040] In one optional implementation of this embodiment, such as Figure 7 As shown, Figure 7 The diagram shows the architecture of a secondary isolation unit in Embodiment 1 of this utility model. The secondary isolation unit incorporates a magnetic coupling isolation chip, an optocoupler isolation chip, and a DC-DC isolation power supply.

[0041] Specifically, the magnetic coupling isolation chip is model ADI ADuM5402, and the optical coupling separation chip is model HCPL-0630.

[0042] Furthermore, the secondary isolation unit is equipped with a dual isolation mechanism to block the conduction path of common-mode interference, avoid power supply noise coupling, and adaptively adjust the isolation level based on the noise reduction strategy inference unit.

[0043] In one optional implementation of this embodiment, such as Figure 1 As shown, the system also includes a feedback adjustment unit, which is located at the output of the third-level fine processing unit and is fed back into the noise reduction strategy inference unit.

[0044] Specifically, the feedback adjustment unit collects the PLC signal processed by the three-level fine processing unit, generates an error signal based on the internal error calculation chip, and sends it back to the noise reduction strategy inference unit to achieve closed-loop optimization.

[0045] In an optional implementation of this embodiment, the signal input module includes a differential input circuit.

[0046] Specifically, the differential input circuit is used to amplify or reduce the input circuit of the PLC.

[0047] In an optional implementation of this embodiment, the signal output module includes a level conversion circuit, which incorporates an LM358 operational amplifier.

[0048] Specifically, the level conversion circuit is used to adjust the output level according to the PLC input requirements (such as 24V digital quantity, ±10V analog quantity).

[0049] In an optional implementation of this embodiment, the signal output module further includes a drive enhancement circuit, which incorporates a ULN2003 Darlington transistor.

[0050] Specifically, the drive enhancement circuit uses a ULN2003 Darlington transistor with a push-pull output structure to improve the driving capability of the PLC output signal and avoid attenuation caused by long-distance transmission.

[0051] In summary, Embodiment 1 of this utility model provides a hierarchical dynamic noise reduction system for PLC signals. By setting up a hierarchical processing mechanism based on a first-level preprocessing unit, a second-level isolation unit, and a third-level fine processing unit, combined with a dynamic identification and noise reduction mechanism based on a noise feature extraction unit and a noise reduction strategy inference unit, the noise reduction capability of PLC signal transmission is improved, the transmission effect and accuracy of PLC signals are optimized, and the efficiency of power line communication is further improved.

[0052] Example 2 This utility model provides a PLC signal transmission device in embodiment two, wherein the PLC signal transmission device has a built-in PLC signal hierarchical dynamic noise reduction system as described in embodiment one.

[0053] In summary, Embodiment 2 of this utility model provides a PLC signal transmission device that incorporates the PLC signal hierarchical dynamic noise reduction system described in Embodiment 1. By setting up a hierarchical processing mechanism based on a first-level preprocessing unit, a second-level isolation unit, and a third-level fine processing unit, combined with a dynamic identification and noise reduction mechanism based on a noise feature extraction unit and a noise reduction strategy inference unit, the noise reduction capability of PLC signal transmission is improved, the transmission effect and accuracy of PLC signals are optimized, and the efficiency of power line communication is further improved.

[0054] The above provides a detailed description of a PLC signal hierarchical dynamic noise reduction system and a PLC signal transmission device provided by the embodiments of this utility model. Specific examples have been used to illustrate the principle and implementation of this utility model. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A PLC signal hierarchical dynamic noise reduction system, characterized in that, The system includes a main control module, a signal input module, a first-level preprocessing unit, a second-level isolation unit, a noise feature extraction unit, a noise reduction strategy inference unit, a third-level fine processing unit, and a signal output module. The main control module is connected to the signal input module, the first-level preprocessing unit, the second-level isolation unit, the noise feature extraction unit, the noise reduction strategy inference unit, the third-level fine processing unit, and the signal output module, respectively. The signal input module, the first-level preprocessing unit, the second-level isolation unit, the noise feature extraction unit, the noise reduction strategy inference unit, the third-level fine processing unit, and the signal output module are connected in sequence. The first-level preprocessing unit includes a pre-filtering circuit and a signal type recognition circuit. The pre-filtering circuit has a built-in first-level RC low-pass filter, and the signal type recognition circuit has a built-in voltage comparator. The noise feature extraction unit includes a sampling circuit and a noise feature analysis chip, and the sampling circuit has a built-in sampling ADC. The noise reduction strategy inference unit has a built-in flash memory chip, which stores a noise reduction strategy inference neural network model. The three-stage fine processing unit includes an adaptive FIR filter.

2. The PLC signal hierarchical dynamic noise reduction system as described in claim 1, characterized in that, The main control module has a built-in main control chip, which is an STM32H747DIH6.

3. The PLC signal hierarchical dynamic noise reduction system as described in claim 1, characterized in that, The noise feature analysis chip is model ADI ADSP-BF533.

4. The PLC signal hierarchical dynamic noise reduction system as described in claim 1, characterized in that, The secondary isolation unit incorporates a magnetic coupling isolation chip, an optocoupler isolation chip, and a DC-DC isolated power supply.

5. The PLC signal hierarchical dynamic noise reduction system as described in claim 4, characterized in that, The magnetic isolation chip is model ADI ADuM5402, and the opto-isolation chip is model HCPL-0630.

6. The PLC signal hierarchical dynamic noise reduction system as described in claim 1, characterized in that, The system also includes a feedback adjustment unit, which is located at the output of the third-level fine processing unit and is connected to the noise reduction strategy inference unit.

7. The PLC signal hierarchical dynamic noise reduction system as described in claim 1, characterized in that, The signal input module includes a differential input circuit.

8. The PLC signal hierarchical dynamic noise reduction system as described in claim 1, characterized in that, The signal output module includes a level conversion circuit, which incorporates an LM358 operational amplifier.

9. The PLC signal hierarchical dynamic noise reduction system as described in claim 1, characterized in that, The signal output module also includes a drive enhancement circuit, which incorporates a ULN2003 Darlington transistor.

10. A PLC signal transmission device, characterized in that, The PLC signal transmission device has a built-in PLC signal hierarchical dynamic noise reduction system as described in any one of claims 1-9.

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