An edge computing gateway system with data cleaning function

Abstract

This utility model relates to the field of edge computing technology, and in particular to an edge computing gateway system with data cleaning function. It includes an aluminum metal casing, a main circuit board disposed inside the aluminum metal casing, an expansion function board connected to the main circuit board, and a multi-protocol interface module mounted on the side wall of the aluminum metal casing. The main circuit board integrates a main controller chip, a power management chip, and a storage chipset. The expansion function board integrates an FPGA chip and a communication module. The main circuit board and the expansion function board are connected via two 90-degree angled board-to-board connectors, symmetrically arranged at both ends of one side of the expansion function board. The multi-protocol interface module is connected to the main circuit board via a flexible circuit board. This utility model can ensure the synchronization and integrity of high-speed data streams during data cleaning through physical structure, thereby improving the overall processing efficiency and reliability of the system.

Description

Technical Field

[0001] This utility model relates to the field of edge computing technology, and in particular to an edge computing gateway system with data cleaning function. Background Technology

[0002] In industrial IoT and edge computing scenarios, gateways serve as core nodes for data aggregation and processing. Their data cleaning capabilities are crucial for improving cloud efficiency. This function typically relies on the collaborative work of the main controller and dedicated processing units such as FPGAs to achieve real-time processing of high-speed data streams.

[0003] However, existing edge gateways with data cleaning capabilities have significant limitations in their hardware architecture, which restricts the efficiency and reliability of data cleaning and processing.

[0004] First, the internal circuit board layout mostly adopts single-board integration or flexible cable connection, resulting in excessively long and unequal high-speed signal transmission paths between the main controller and the FPGA. This leads to prominent signal delay and asynchrony issues, which severely restrict the real-time performance and reliability of data cleaning.

[0005] Secondly, in pursuit of device miniaturization, high-power chips are often clustered together, resulting in poor heat dissipation efficiency and making it difficult for the system to maintain sustained high-performance operation. Furthermore, the dense component layout and improper interface arrangement create a complex electromagnetic environment inside the gateway, making it susceptible to interference in harsh industrial environments and leading to decreased data transmission stability.

[0006] Therefore, it is necessary to further improve an edge computing gateway system with data cleaning capabilities. Utility Model Content

[0007] The technical problem to be solved by this utility model is to overcome the existing defects and provide an edge computing gateway system with data cleaning function. The physical structure ensures the synchronization and integrity of high-speed data streams during the data cleaning process, thereby improving the overall processing efficiency and reliability of the system and effectively solving the problems in the background technology.

[0008] To achieve the above objectives, this utility model provides the following technical solution: an edge computing gateway system with data cleaning function, comprising an aluminum metal shell, a main circuit board disposed inside the aluminum metal shell, an expansion function board connected to the main circuit board, and a multi-protocol interface module installed on the side wall of the aluminum metal shell;

[0009] The main circuit board integrates a main controller chip, a power management chip, and a memory chipset.

[0010] The expansion board integrates an FPGA chip and a communication module;

[0011] The main circuit board and the expansion function board are connected by two board-to-board connectors with a 90-degree bend, and are symmetrically arranged at both ends of one side of the expansion function board. The FPGA chip is located in the central area between the two board-to-board connectors.

[0012] The multi-protocol interface module is connected to the main circuit board via a flexible circuit board.

[0013] Preferably, the main circuit board is an eight-layer PCB board, with the top and bottom layers being the main component layers, and the second and sixth layers being complete ground plane layers; a high-speed signal line group is connected between the main controller chip and the memory chip group, and the high-speed signal line group is arranged on the top layer.

[0014] Preferably, each high-speed signal line in the high-speed signal line group is provided with grounding copper foil connected to the second ground plane layer through blind holes on both sides and directly below, so that the high-speed signal line is surrounded by the grounding copper foil on both sides in the horizontal direction and shielded by the second ground plane directly below in the vertical direction.

[0015] Preferably, the main controller chip abuts against the inner top wall of the aluminum metal casing via a first thermally conductive silicone pad, and the top outer surface of the aluminum metal casing is provided with a first heat dissipation fin.

[0016] The FPGA chip of the expansion board is in close contact with the inner surface of the side wall of the aluminum metal shell through the second thermal conductive silicone pad; the outer surfaces of the left and right side walls of the aluminum metal shell are symmetrically provided with second heat dissipation fins perpendicular to their bottoms.

[0017] Preferably, it also includes a built-in antenna; the top of the aluminum metal casing is provided with an antenna window, and the built-in antenna is attached to the inside of the antenna window;

[0018] The communication module is a 5G module; the antenna interface of the 5G module is electrically connected to the built-in antenna via a coaxial cable.

[0019] Preferably, the multi-protocol interface module includes an RJ45 network port, an RS-485 interface, and a CAN bus interface; these interfaces are arranged from left to right on the side wall of the aluminum metal casing, wherein a first isolation gap is provided between the RJ45 network port and the adjacent RS-485 interface, and a second isolation gap is provided between the RS-485 interface and the CAN bus interface, and the first isolation gap is greater than the second isolation gap.

[0020] Compared with the prior art, the beneficial effects of this utility model are:

[0021] By arranging the FPGA chip and the main controller chip face-to-face on a vertical expansion board and using symmetrically arranged board-to-board connectors, the high-speed data signal transmission path is minimized and of equal length, effectively reducing latency and signal differences, and ensuring the synchronization and integrity of the high-speed data stream during the data cleaning process.

[0022] The system employs a combination structure of a horizontal main circuit board and a vertical expansion function board, which directs the heat from the two main heat sources, the main controller and the FPGA, to independent heat dissipation surfaces on the top and side walls of the casing, achieving efficient heat dissipation while maintaining the miniaturization and modularity of the device.

[0023] Through the specific stack-up design of the eight-layer PCB, the grounding shielding structure of the high-speed signal lines, and the differentiated spacing layout between interfaces, signal crosstalk and electromagnetic interference are effectively suppressed, improving the stability and connection reliability of multi-protocol interfaces in industrial environments. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the overall structure of this utility model;

[0025] Figure 2 This is a schematic diagram of the high-speed signal line shielding structure of this utility model;

[0026] Figure 3 This is a schematic diagram of the multi-protocol interface module of this utility model;

[0027] Figure 4 This is a schematic diagram (b) of the multi-protocol interface module of this utility model.

[0028] Explanation of reference numerals in the attached diagram: 1. First heat sink fin; 2. First thermally conductive silicone pad; 3. High-speed signal line; 4. Memory chipset; 5. Antenna window; 6. Built-in antenna; 7. Coaxial cable; 8. Main circuit board; 9. Power management chip; 10. Expansion function board; 11. FPGA chip; 12. Communication module; 13. Second heat sink fin; 14. Second thermally conductive silicone pad; 15. Board-to-board connector; 16. Main controller chip; 17. Blind via; 18. Grounding copper strip; 19. RJ45 network port; 20. RS-485 interface; 21. CAN bus interface; 22. Multi-protocol interface module; 23. Flexible circuit board. Detailed Implementation

[0029] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0030] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of a descriptive feature, integral, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or sets.

[0031] To keep the drawings concise, only the parts relevant to this invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of the components with the same structure or function is schematically depicted, or only one is labeled. In this document, "one" not only means "only one," but can also mean "more than one."

[0032] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0033] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0034] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the specific implementation methods of this utility model will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of this utility model. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0035] Currently, although the above problems can be partially alleviated by adding external shielding or complex circuits, this inevitably leads to new problems such as complex system structure and reduced reliability.

[0036] Please see Figure 1-4 This utility model provides a technical solution: an edge computing gateway system with data cleaning function, including an aluminum metal shell, a main circuit board 8 disposed inside the aluminum metal shell, an expansion function board 10 connected to the main circuit board 8, and a multi-protocol interface module 22 installed on the side wall of the aluminum metal shell.

[0037] The main circuit board 8 is fixed to the middle of the aluminum metal casing by fasteners; the main circuit board 8 integrates the main controller chip 16, the power management chip 9 and the memory chipset 4.

[0038] The expansion board 10 integrates an FPGA chip 11 and a communication module 12; the mounting position of the FPGA chip 11 on the expansion board 10 is spatially opposite to the mounting position of the main controller chip 16 on the main circuit board 8.

[0039] The main circuit board 8 and the expansion function board 10 are connected by two board-to-board connectors 15 with a 90-degree bend, and are symmetrically arranged at both ends of one side of the expansion function board 10. The expansion function board 10 is vertically connected to the main circuit board 8 through the two board-to-board connectors 15. The FPGA chip 11 is located in the central area between the two board-to-board connectors 15. This layout means that the transmission path length of the high-speed signal lines used to transmit data to be cleaned and cleaned between the FPGA chip 11 and the main controller is the shortest and is basically the same length. This effectively reduces signal transmission delay and difference, and ensures the synchronization and integrity of the high-speed data stream in the data cleaning task.

[0040] The multi-protocol interface module 22 is fixedly installed on the pre-fabricated opening on the side wall of the aluminum metal shell and is electrically connected to the internal main circuit board 8 through a flexible circuit board 23 that can withstand slight deformation and vibration.

[0041] Furthermore, the eight-layer PCB adopts a stacked design that includes two complete ground plane layers. In a preferred embodiment, the first top layer is the main component layer and the high-speed signal routing layer; the second layer is the complete ground plane layer; the third and fourth layers are internal signal routing layers; the fifth layer is the power plane layer; the sixth layer is the complete ground plane layer; the seventh layer is the internal signal routing layer; and the eighth bottom layer is the secondary component layer and the routing layer.

[0042] The stack-up order can be adjusted appropriately according to actual impedance control, power distribution and wiring density requirements, such as swapping the positions of the power plane and the ground plane, but the core is to ensure that high-speed signal line groups are routed adjacent to a complete ground plane layer.

[0043] A high-speed signal line group is connected between the main controller chip 16 and the memory chip group 4, and the high-speed signal line group is arranged on the top layer.

[0044] Furthermore, each high-speed signal line 3 in the high-speed signal line group has a grounding copper strip 18 on both sides and directly below it, which is connected to the second ground plane layer through blind vias 17. These two grounding copper strips 18 extend parallel to the high-speed signal line 3 and always maintain a fixed spacing. Directly below the high-speed signal line 3 and the grounding copper strips 18 on both sides is the second ground plane layer, which serves as a complete reference plane. The grounding copper strips 18 on both sides are electrically connected and physically fixed to the second ground plane layer directly below through the arranged blind vias 17. The blind vias 17 are drilled from the top layer to... The second layer, but does not penetrate other layers of the PCB; thus, the high-speed signal line 3 is surrounded laterally by ground copper foils 18 on both sides and shielded vertically by the second ground plane directly below it. This structure can extremely effectively suppress near-end crosstalk and far-end crosstalk between high-speed signal lines, provide the optimal return path, and reduce electromagnetic radiation. In addition, the use of blind vias 17 that only connect the top and second layers, instead of through-holes, avoids the generation of useless pads and via anti-pads on the third layer and below signal or power layers, thereby protecting the integrity of the underlying critical routing layers and power planes.

[0045] Furthermore, the main controller chip 16 abuts against the inner top wall of the aluminum metal shell through the first thermally conductive silicone pad 2. The top outer surface of the aluminum metal shell is pre-pressed with the first heat dissipation fin 1, which increases the surface area of ​​the aluminum metal shell. The heat generated by the main controller chip 16 during operation is conducted to the aluminum metal shell through the first thermally conductive silicone pad 2 and effectively dissipated through the first heat dissipation fin 1.

[0046] The expansion board 10 is mounted vertically, and the FPGA chip 11 is in close contact with the aluminum metal casing through the second thermal conductive silicone pad 14. The outer surfaces of the left and right side walls of the aluminum metal casing are symmetrically provided with second heat dissipation fins 13 perpendicular to their bottoms. The second heat dissipation fins 13 can increase the heat dissipation efficiency of the FPGA chip 11, thereby reducing the operating temperature of the FPGA chip 11.

[0047] The main controller chip 16 located on the horizontal main circuit board 8 and the FPGA chip 11 located on the vertical expansion function board 10 are the two largest heat sources; through physical layout, this structure guides their heat to the top of the housing and the side wall of the housing, which are almost orthogonal heat dissipation surfaces.

[0048] Furthermore, the top of the aluminum metal casing is provided with an antenna window 5 made of a non-metallic material, such as polycarbonate (PC). The built-in antenna 6 is attached to the inside of the antenna window 5, making it an integrally mounted module with the window.

[0049] As a good conductor, the aluminum metal casing reflects and absorbs electromagnetic waves, severely hindering the signal transmission and reception of the built-in antenna 6. This structure physically creates a channel for electromagnetic waves to pass through freely by opening a non-metallic window on the top of the metal casing.

[0050] The communication module 12 is a 5G module. This choice ensures that a large amount of effective data, after being efficiently cleaned and preprocessed at the edge, can be uploaded to the cloud in real time and without obstruction through the 5G module.

[0051] The system also includes a built-in antenna 6, and the antenna interface of the 5G module is electrically connected to the feed point of the built-in antenna 6 via a coaxial cable 7.

[0052] Furthermore, the multi-protocol interface module 22 includes an RJ45 network port 19, an RS-485 interface 20, and a CAN bus interface 21; these interfaces are arranged from left to right on the side wall of the aluminum metal casing, wherein the RJ45 network port 19 and the adjacent RS-485 interface 20 are provided with a first isolation gap, the RS-485 interface 20 and the CAN bus interface 21 are provided with a second isolation gap, and the first isolation gap is greater than the second isolation gap.

[0053] Specifically, a larger initial isolation gap D1 is set between the RJ45 network port 19 and the RS-485 interface 20, physically increasing the spatial distance and creepage distance between them. This effectively attenuates the intensity of the high-frequency electromagnetic energy generated by the RJ45 network port 19 that is conducted to the RS-485 interface 20 through spatial coupling or along the circuit board, preventing high-speed network noise from impacting sensitive industrial bus circuits and improving stability in harsh electrical environments. Furthermore, the RS-485 interface 20 and the CAN bus both belong to the balanced differential serial bus category, and their operating mechanisms and spectral characteristics are relatively similar. The potential interference intensity between them is lower than the potential interference between them and the RJ45 network port 19.

[0054] In this embodiment, the first isolation gap can be no less than 25mm. The high harmonic frequency of the gigabit Ethernet signal can exceed 100MHz, and the spatial radiation it generates is the main interference. The 25mm gap provides sufficient distance for the attenuation of high-frequency electromagnetic fields. This value can usually meet the test requirements of most EMC standards for inter-port coupling.

[0055] In this embodiment, the second isolation gap can be approximately 15mm. Both the RS-485 interface 20 and the CAN bus are low-to-medium speed differential signals, with operating fundamental frequencies and harmonic components far lower than Ethernet. Potential interference between them originates more from ground noise or lower-frequency coupling. A 15mm gap effectively prevents low-frequency field coupling caused by their physical proximity. Setting the second isolation gap to 15mm, instead of the same width as the first isolation gap, significantly saves lateral space on the sidewalls, making the overall device structure more compact. This is an optimized design while ensuring basic isolation performance.

[0056] This utility model relates to an edge computing gateway system with data cleaning function. Its working principle is based on an optimized physical structure design to ensure the efficiency and reliability of data acquisition, processing and transmission.

[0057] The working principle of this utility model is as follows:

[0058] The system collects industrial field data through the multi-protocol interface module 22. The main controller chip 16 on the main circuit board 8 is responsible for system scheduling and data coordination, while the FPGA chip 11 on the vertical expansion function board 10 is dedicated to performing efficient data cleaning tasks. The two achieve high-speed data interaction through symmetrically arranged board-to-board connectors 15, ensuring the synchronization and low latency of the data stream during the cleaning process. The cleaned and effective data is uploaded to the cloud in real time via the 5G communication module 12.

[0059] The working principle of this utility model is as follows:

[0060] The system collects data from various industrial equipment through the multi-protocol interface module 22 on the side wall and transmits it to the main circuit board 8 via the flexible circuit board 23. The main controller chip 16 is responsible for system scheduling and task allocation, transmitting the data to be cleaned to the FPGA chip 11 through the vertically connected expansion function board 10. The FPGA and the main controller are spatially aligned and achieve high-speed data exchange via symmetrically distributed board-to-board connectors 15 to complete the data cleaning process. The cleaned and valid data is uploaded to the cloud platform in real time through the isolated 5G module and dedicated antenna window 5. Throughout the process, the various functional modules work together through optimized physical structure and layout to ensure the stability and efficiency of the data acquisition, cleaning, and transmission links.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An edge computing gateway system with data cleaning function, characterized in that: It includes an aluminum metal casing, a main circuit board (8) disposed inside the aluminum metal casing, an expansion function board (10) connected to the main circuit board (8), and a multi-protocol interface module (22) mounted on the side wall of the aluminum metal casing. The main circuit board (8) integrates a main controller chip (16), a power management chip (9), and a memory chipset (4). The expansion board (10) integrates an FPGA chip (11) and a communication module (12). The main circuit board (8) and the expansion function board (10) are connected by two board-to-board connectors (15) with a 90-degree bend, and are symmetrically arranged at both ends of one side of the expansion function board (10). The FPGA chip (11) is located in the central area between the two board-to-board connectors (15). The multi-protocol interface module (22) is connected to the main circuit board (8) via a flexible circuit board (23). 2.The edge computing gateway system with data cleaning function according to claim 1, wherein: The main circuit board (8) is an eight-layer PCB board, with the top and bottom layers being the main component layers, and the second and sixth layers being complete ground plane layers; a high-speed signal line group is connected between the main controller chip (16) and the memory chip group (4), and the high-speed signal line group is arranged on the top layer. 3.The edge computing gateway system with data cleaning function of claim 2, wherein: Each high-speed signal line (3) in the high-speed signal line group is provided with grounding copper foil (18) connected to the second ground plane layer through blind holes (17) on both sides and directly below, so that the high-speed signal line (3) is surrounded by the grounding copper foil (18) on both sides in the horizontal direction and shielded by the second ground plane directly below it in the vertical direction. 4.The edge computing gateway system with data cleaning function of claim 1, wherein: The main controller chip (16) abuts against the inner top wall of the aluminum metal shell through the first thermally conductive silicone pad (2), and the top outer surface of the aluminum metal shell is provided with the first heat dissipation fin (1). The FPGA chip (11) of the expansion board (10) is in close contact with the inner surface of the side wall of the aluminum metal shell through the second thermal conductive silicone pad (14); the outer surfaces of the left and right side walls of the aluminum metal shell are symmetrically provided with second heat dissipation fins (13) perpendicular to their bottom.

5. The edge computing gateway system with data cleaning function according to claim 1, characterized in that: It also includes a built-in antenna (6); the top of the aluminum metal casing is provided with an antenna window (5), and the built-in antenna (6) is attached to the inside of the antenna window (5); The communication module (12) is a 5G module; the antenna interface of the 5G module is electrically connected to the built-in antenna (6) via a coaxial cable (7).

6. The edge computing gateway system with data cleaning function according to claim 1, characterized in that: The multi-protocol interface module (22) includes an RJ45 network port (19), an RS-485 interface (20), and a CAN bus interface (21). These interfaces are arranged from left to right on the side wall of the aluminum metal casing. A first isolation gap is provided between the RJ45 network port (19) and the adjacent RS-485 interface (20), and a second isolation gap is provided between the RS-485 interface (20) and the CAN bus interface (21). The first isolation gap is greater than the second isolation gap.

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