A more stable iridescent chip

Abstract

This utility model discloses a more stable color chip, including an input port, a return-to-zero (RZ) code protocol circuit, and an output port. The input port and the RZ code protocol circuit are electrically connected through a deployed digital logic processing circuit. The RZ code protocol circuit includes a serial interface for the RZ code protocol. The input terminal of the digital logic processing circuit is connected to the input port, and the output terminal of the digital logic processing circuit is connected to the RZ code protocol circuit through the serial interface. Its advantages are: by using digital logic circuits for functional implementation and design, the use of multiple frequency dividers ensures that the system is operating under a unified timing sequence. Compared with the original delay circuit design, the use of digital logic circuits can significantly improve the stability and temperature characteristics during operation. Furthermore, the frequency dividers and comparators in the digital logic circuits can effectively reduce the chip area through high integration, further reducing chip production costs.

Description

Technical Field

[0001] This utility model relates to the field of LED RGB light strip chip technology, specifically to a more stable RGB chip. Background Technology

[0002] Currently, color-coded chips have been widely used, and existing color-coded chips already have the function of continuous breakpoint resume transmission, such as the previously applied adjustable current color-coded chip for continuous breakpoint resume transmission, CN221509823U.

[0003] However, the original circuit design within the chip relied on multiple delay circuits to control the timing of internal data bits. This method is highly dependent on the accuracy and stability of the internal clock. Since the clock circuit can also experience varying degrees of temperature drift under different environments, the clock frequency changes, affecting the timing control of the delay circuit. Utility Model Content

[0004] In view of the shortcomings of the prior art, the purpose of this utility model is to provide a more stable color chip, which aims to solve the defects of the prior art that relies on multiple delay circuits for timing control.

[0005] This utility model provides a more stable color chip, including an input port, a return-to-zero code protocol circuit, and an output port. The input port and the return-to-zero code protocol circuit are electrically connected through a deployed digital logic processing circuit. The return-to-zero code protocol circuit includes a serial interface for the return-to-zero code protocol.

[0006] The input terminal of the digital logic processing circuit is connected to the input port, and the output terminal of the digital logic processing circuit is connected to the return-to-zero code protocol circuit through the serial interface.

[0007] Furthermore, the input ports include at least a DIN port, a DIN1 port, and a DIN2 port, and are respectively connected to the digital logic processing circuit.

[0008] Furthermore, the digital logic processing circuit includes a judgment circuit U1, a judgment circuit U2, and two frequency dividers;

[0009] The DIN2 port is connected to one end of one of the frequency dividers, the other end of one of the frequency dividers is connected to one input of the judgment circuit U1, the other input of the judgment circuit U1 is connected to the DIN1 port, the output of the judgment circuit U1 is connected to one input of the judgment circuit U2 after being connected to another frequency divider, the other input of the judgment circuit U2 is connected to the DIN port, and the output of the judgment circuit U1 is connected to the serial interface of the return-to-zero code protocol.

[0010] Furthermore, both the judgment circuit U1 and the judgment circuit U2 employ comparator circuits.

[0011] Furthermore, the zero-return code protocol circuit also includes a counter, an adder, an RGB display memory, and a command decoder. The adder is connected to the counter, the RGB display memory, and the command decoder, respectively. The RGB display memory and the command decoder are also connected to the output port, respectively.

[0012] Furthermore, the counter is a 24-bit counter.

[0013] Furthermore, the data received by the DIN of the preceding chip will be simultaneously transmitted to the DIN1 of the next level chip and the DIN2 of the next-next chip. The output of the preceding chip is transmitted to the DIN of the next level chip as an input signal, and is also connected to the DIN1 of the next-next chip as a backup signal, and is also connected to the DIN2 of the third-next chip as a secondary backup signal. That is, the output DOUT of one chip can provide different levels of input to the subsequent three chips.

[0014] The more stable iridescent chip provided by this utility model has the following beneficial effects:

[0015] By using digital logic circuits for functional implementation and design, the use of multiple frequency dividers can ensure that the system composed of them operates under a unified timing sequence. Compared with the original delay circuit design, the use of digital logic circuits can significantly improve the stability and temperature characteristics during operation.

[0016] Furthermore, the high integration of frequency dividers and comparators in digital logic circuits can effectively reduce chip area, thereby further reducing chip production costs. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0018] Figure 1 A schematic diagram of a more stable iridescent chip provided by an embodiment of the present invention is shown.

[0019] Figure 2 A schematic diagram of the structure of a more stable iridescent chip provided by an embodiment of the present invention is shown;

[0020] Figure 3 A schematic diagram of a multi-chip transmission structure provided by an embodiment of the present invention is shown. Detailed Implementation

[0021] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0022] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0023] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. Furthermore, it should be understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items, and all possible combinations thereof.

[0024] It should be noted that this solution is based on a continuously interrupted transmission adjustable current color chip [Patent No.: ZL2024 2 0081022.4], with more specific optimization of the circuit. It also has the functions of continuously interrupted transmission and adjustable current. The implementation method is the same as the aforementioned application, and will not be repeated here; this embodiment only describes the improved part in detail.

[0025] Unless otherwise stated, the technical or scientific terms used in this application shall have the ordinary meaning as understood by one of ordinary skill in the art to which this utility model pertains.

[0026] like Figures 1 to 2 As shown in the figure, the present invention provides a more stable color chip, including an input port, a return-to-zero code protocol circuit and an output port. The input port and the return-to-zero code protocol circuit are electrically connected through a deployed digital logic processing circuit. The return-to-zero code protocol circuit includes a serial interface for the return-to-zero code protocol.

[0027] The input terminal of the digital logic processing circuit is connected to the input port, and the output terminal of the digital logic processing circuit is connected to the return-to-zero code protocol circuit through the serial interface.

[0028] In this embodiment, the input ports include at least a DIN port, a DIN1 port, and a DIN2 port, and are respectively connected to the digital logic processing circuit;

[0029] The digital logic processing circuit includes a judgment circuit U1, a judgment circuit U2, and two frequency dividers;

[0030] The DIN2 port is connected to one end of one of the frequency dividers, the other end of one of the frequency dividers is connected to one input of the judgment circuit U1, the other input of the judgment circuit U1 is connected to the DIN1 port, the output of the judgment circuit U1 is connected to one input of the judgment circuit U2 after being connected to another frequency divider, the other input of the judgment circuit U2 is connected to the DIN port, and the output of the judgment circuit U1 is connected to the serial interface of the return-to-zero code protocol.

[0031] Specifically, both the judgment circuit U1 and the judgment circuit U2 use comparator circuits; both frequency dividers use 24-bit frequency dividers; wherein, the judgment circuit U1 is used to determine whether it is DIN1 or DIN2; the judgment circuit U2 is used to determine whether it is DIN or something else.

[0032] For ease of understanding, its working process is as follows:

[0033] The data is generally input in the following order: DIN2 is input first, with a timing 48 bits faster than DIN; then DIN1 is input, with a timing 24 bits faster than DIN; and finally DIN is input. The data here can be understood as external control signals, which include, but are not limited to, data signals containing RESET or current codes.

[0034] After DIN2 is input, it first enters a 24-bit frequency divider for frequency division and recording. After the 24-bit timing is achieved, it enters the judgment circuit U1 [which is a comparator circuit that can compare the priority of the input circuit. The signal of the later input is set to have a higher priority. When the later input signal is detected, the previous input signal will be covered by the higher priority signal] to determine whether there is an input to DIN1. If there is an input to DIN1, the judgment circuit U1 outputs the DIN1 data. If there is no input to DIN1, it outputs the DIN2 data.

[0035] The data will enter a new 24-bit frequency divider for frequency division and recording again. After waiting for 24-bit timing again, it will enter the judgment circuit U2 to determine whether there is an input to DIN. If there is an input to DIN, the judgment circuit U2 will output the DIN data. If there is no input to DIN, it will output the data of DIN2 / DIN1. This completes the input and judgment of the digital logic processing circuit. The input data is then entered into the next step of the return-to-zero code protocol circuit, which will pass the signals to the subsequent DOUT output conditioning and RGB PWM constant current output drive, thereby completing the main digital logic processing operation inside the chip.

[0036] Furthermore, the return-to-zero code protocol circuit also includes a counter, an adder, an RGB display memory, and a command decoder. The adder is connected to the counter, the RGB display memory, and the command decoder, respectively. The RGB display memory and the command decoder are also connected to the output port, respectively. The counter is a 24-bit counter. The output port includes DOUT and OUT corresponding to RGB. In the accompanying drawings, RGB display memory and display memory have the same meaning.

[0037] Reference Figure 3 In a LED strip composed of multiple chips, the data received by the DIN pin of the preceding chip is simultaneously transmitted to the DIN1 pin of the next-level chip and the DIN2 pin of the next-next-level chip. The output of the preceding chip is transmitted to the DIN pin of the next-level chip as an input signal, and simultaneously connected to the DIN1 pin of the next-next-level chip as a backup signal, and also connected to the DIN2 pin of the third-next-level chip as a secondary backup signal. That is, the output DOUT of one chip can provide different levels of input to the subsequent three chips; the term "third-next-level" is used to describe the DIN2 pin of the third chip as a secondary backup, thus enabling the output of one chip to be transmitted to the next chip (i.e., the next level), the next two chips (i.e., the next-next-level), and the next three chips (i.e., the third-next-level).

[0038] During implementation, Figure 3 In this diagram, DIN1 / FDIN1 / FDIN2 represent the signal output terminals of the preceding stage controller. These are connected to the three input segments DIN / FDIN1 / FDIN2 of the first color chip d1. Simultaneously, DIN1 is also connected to FDIN1 of the second color chip d2 as a backup signal and FDIN2 of the third color chip d3 as a secondary backup signal; similarly, FDIN1 is connected to FDIN2 of the second color chip d2 as a secondary backup signal. The output of the first color chip d1 is connected to DIN of d2 as an input signal, and to FDIN1 of d3 as a backup signal, then to FDIN2 of the fourth color chip as a secondary backup signal, and so on. This enables continuous interruption and resume functionality.

[0039] The above solution uses digital logic circuits for functional implementation and design. The use of multiple frequency dividers ensures that the system is operating under a unified timing sequence. Compared with the original delay circuit design, the use of digital logic circuits can significantly improve the stability and temperature characteristics during operation.

[0040] Furthermore, the high integration of frequency dividers and comparators in digital logic circuits can effectively reduce chip area, thereby further reducing chip production costs.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model, and they should all be covered within the scope of the claims and specification of this utility model.

Claims

1. A more stable color-coded chip, comprising an input port, a return-to-zero code protocol circuit, and an output port, characterized in that, The input port is electrically connected to the return-to-zero code protocol circuit through a deployed digital logic processing circuit; wherein, the return-to-zero code protocol circuit includes a serial interface for the return-to-zero code protocol; The input terminal of the digital logic processing circuit is connected to the input port, and the output terminal of the digital logic processing circuit is connected to the return-to-zero code protocol circuit through the serial interface. The input ports include at least a DIN port, a DIN1 port, and a DIN2 port, and are respectively connected to the digital logic processing circuit; The digital logic processing circuit includes a judgment circuit U1, a judgment circuit U2, and two frequency dividers; The DIN2 port is connected to one end of one of the frequency dividers, the other end of one of the frequency dividers is connected to one input of the judgment circuit U1, the other input of the judgment circuit U1 is connected to the DIN1 port, the output of the judgment circuit U1 is connected to one input of the judgment circuit U2 after being connected to another frequency divider, the other input of the judgment circuit U2 is connected to the DIN port, and the output of the judgment circuit U1 is connected to the serial interface of the return-to-zero code protocol.

2. The more stable iridescent chip according to claim 1, characterized in that, Both the judgment circuit U1 and the judgment circuit U2 use comparator circuits.

3. A more stable iridescent chip according to any one of claims 1 to 2, characterized in that, The zero-return code protocol circuit also includes a counter, an adder, an RGB display memory, and a command decoder. The adder is connected to the counter, the RGB display memory, and the command decoder, respectively. The RGB display memory and the command decoder are also connected to the output port, respectively.

4. A more stable iridescent chip as described in claim 3, characterized in that, The counter is a 24-bit counter.

5. A more stable iridescent chip as described in claim 4, characterized in that, When multiple chips are used, the data received by the DIN of the previous chip will be transmitted to the DIN1 of the next level chip and the DIN2 of the next-next chip at the same time. The output of the previous chip is transmitted to the DIN of the next level chip as an input signal, and is also connected to the DIN1 of the next-next chip at the next-next chip as a backup signal, and is also connected to the DIN2 of the third level down as a secondary backup signal.

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