Polycrystalline wafer image sensor integrated circuit device with frontside isolation structure

Abstract

Some embodiments relate to an integrated circuit device having an integrated circuit layer including a plurality of pixel cell groups. Each pixel cell group includes a plurality of pixel cells arranged in a 2-by-2 configuration. Each pixel cell includes a photosensor in a substrate, and a transfer transistor electrically coupled to the photosensor and configured to transfer charge collected by the photosensor across a first surface of the substrate. The integrated circuit layer further includes at least one dielectric structure extending from the first surface to a second surface of the substrate and separating each pixel cell from an adjacent pixel cell. The dielectric structure includes a first gap located at a common corner of the pixel cells. A conductive structure is electrically connected to at least one of the photosensor or the transfer transistor of each pixel cell and is configured in the first gap above the first surface.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and more particularly to a multi-chip CMOS image sensor integrated circuit apparatus having a front-side isolation structure. Background Technology

[0002] The use of complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) in electronic devices typically involves utilizing various additional circuit resources to make the signals generated by the CIS useful. For example, in addition to the pixel array for receiving light, the CIS may also include one or more timing circuits for measuring the amount of light received, image processing circuitry for generating the resulting image data, and memory for storing the image data. These circuits may be integrated into a single CIS integrated circuit (IC) device to reduce the area occupied by the device on the printed circuit board (PCB).

[0003] Furthermore, separation or isolation structures can be placed between adjacent pixels in the pixel array to limit the amount of light that is properly received from the pixel from escaping and / or the amount of unwanted light (e.g., light from neighboring pixels) entering the pixel. These structures can also serve as electrical isolation structures, thereby potentially reducing optical and electrical crosstalk between pixels and limiting overall electrical noise in the resulting image signal. Utility Model Content

[0004] This disclosure discloses an image sensor integrated circuit (IC) device comprising: an integrated circuit layer including a plurality of pixel cell groups, each of the plurality of pixel cell groups including: a plurality of pixel cells arranged in a 2x2 configuration in a planar view, each of the plurality of pixel cells including: a photosensitive sensor in a substrate of the integrated circuit layer; and a transmission transistor electrically coupled to the photosensitive sensor and configured to transfer charge collected by the photosensitive sensor across a first surface of the substrate; and at least one dielectric structure extending from the first surface of the substrate to a second surface of the substrate and separating each of the plurality of pixel cells from adjacent pixel cells, wherein the at least one dielectric structure includes a first gap disposed at a common corner of the plurality of pixel cells, wherein a first conductive structure is electrically connected to at least one of the photosensitive sensor or the transmission transistor of each of the plurality of pixel cells and disposed in the first gap above the first surface of the substrate.

[0005] This disclosure discloses an image sensor integrated circuit (IC) device comprising: an integrated circuit layer including a plurality of pixel cell groups, each of the plurality of pixel cell groups including: a plurality of pixel cells arranged in a 2x2 configuration in a plan view, each of the plurality of pixel cells including: a photosensitive sensor located in a substrate of the integrated circuit layer; and a transmission transistor electrically coupled to the photosensitive sensor and configured to transfer charge collected by the photosensitive sensor across a first surface of the substrate; and at least one dielectric structure extending from the first surface of the substrate to a second surface of the substrate and separating each of the plurality of pixel cells from adjacent pixel cells in the plan view, wherein the at least one dielectric structure includes a plurality of first segments, each of the plurality of first segments having a first end and a second end, the first end being located at the periphery of the 2x2 configuration, and the second end being located outside a central region of the 2x2 configuration, wherein the first conductive structure is electrically connected to at least one of the photosensitive sensor or the transmission transistor of each of the plurality of pixel cells and is disposed above the first surface of the substrate in the central region. Attached Figure Description

[0006] The various aspects revealed are most readily understood when read in conjunction with the accompanying drawings in the following detailed description. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1 This illustration shows an exploded isometric view of some embodiments of a CIS multi-chip (e.g., multilayer) IC device according to this disclosure;

[0008] Figure 2A This illustration shows block diagrams of some embodiments of pixel cells that can be used in CIS multilayer IC devices according to this disclosure;

[0009] Figure 2B This illustration shows some embodiments of pixel cells that can be used in a CIS multilayer IC device according to this disclosure;

[0010] Figure 3 This illustration shows schematic / block diagrams of some embodiments of pixel cells, per-pixel circuits, in-pixel circuits, and application-specific integrated circuits (ASICs) that can be used in multilayer CISIC devices according to this disclosure.

[0011] Figure 4 Block diagrams illustrating some embodiments of the multilayer CISIC device according to this disclosure;

[0012] Figure 5A and Figure 5B Cross-sectional and plan views are shown respectively for some embodiments of a multilayer CISIC device employing a front-side isolation structure according to this disclosure;

[0013] Figure 6A and Figure 6B Cross-sectional and plan views are shown respectively of some embodiments of another multilayer CISIC device employing a frontal isolation structure according to this disclosure;

[0014] Figure 7A and Figure 7B Cross-sectional and plan views are shown respectively of some embodiments of another multilayer CISIC device employing a frontal isolation structure according to this disclosure;

[0015] Figure 8A and Figure 8B Cross-sectional and plan views are shown respectively of some embodiments of another multilayer CISIC device employing a frontal isolation structure according to this disclosure;

[0016] Figure 9A and Figure 9B This illustration shows plan views of some embodiments of a multilayer CISIC device employing a front-side isolation structure according to this disclosure;

[0017] Figures 10A to 10L This illustration shows cross-sectional side views of some embodiments of a CIS multi-chip IC device employing a front-side isolation structure at various stages of manufacturing, according to this disclosure.

[0018] Figure 11 This describes a method for forming a CIS multi-chip IC device with a front-side isolation structure according to some embodiments. Detailed Implementation

[0019] This disclosure provides many different embodiments or instances to implement the various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, embodiments in which a first feature is formed on or over a second feature may include direct contact between the first and second features, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, to facilitate the description of the relationship between one element or feature and another shown in the figures, this document may use spatial relative terms such as "below," "lower," "lower," "above," and "higher." These spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly.

[0021] In complementary metal-oxide-semiconductor (CMOS) image sensors (CIS), associating isolation structures (e.g., for optical and / or electrical isolation purposes) and associated circuitry (e.g., for image signal generation, storage, and processing) with each pixel in the pixel array and integrating them into a single integrated circuit (IC) device can become more challenging due to the increasing demand for higher image resolution and smaller pixel sizes. More specifically, the smaller the overall pixel size, the fewer areas (e.g., in a planar view) are available for the detection and measurement of light, and the fewer associated optical and electrical isolation structures are available.

[0022] To address these issues, this disclosure provides several embodiments of multi-wafer CIS IC devices with front-side isolation structures. In some embodiments, the layers or wafers of the IC device may include multiple cell groups, wherein each cell group includes multiple (e.g., four) pixel cells (e.g., arranged in a 2x2 (e.g., two rows and two columns) configuration in a planar view). Each pixel cell may include a photosensor in the IC layer substrate and a transfer transistor electrically coupled to the photosensor. In some embodiments, the transfer transistor may be configured to transfer charge collected by the photosensor across a first surface (e.g., the front surface) of the substrate.

[0023] The IC layer may also include at least one dielectric structure (e.g., a front-side deep trench isolation (DTI) structure) extending from a first surface of the substrate to a second surface and separating each pixel cell from its neighboring pixel cells. Furthermore, in some embodiments, at least one dielectric structure may include a gap at a common corner of multiple pixel cells (e.g., in or near the central region of a 2x2 configuration). A conductive structure may be electrically connected to at least one of a photosensitive or transmission transistor in each pixel cell and may be configured within the gap above the first surface of the substrate.

[0024] Therefore, some embodiments can provide CISIC devices where isolation between pixel cells is achieved through a single-layer dielectric structure created from one side of the substrate (e.g., the front side), opposite the side receiving image light. As a result, better overlay (e.g., lateral) alignment may occur between the dielectric structure and various features in the IC layer near the front side (e.g., floating diffusion (FD) nodes associated with transmission transistors). This improved alignment can facilitate an increase in device layout area and a corresponding reduction in the overall pixel cell area, potentially leading to improved image resolution.

[0025] Furthermore, the formation of at least one dielectric structure may occur relatively early in the overall CISIC manufacturing process. In some cases, forming such a trans-substrate-depth isolation structure may disrupt molecular (e.g., silicon-silicon) bonds, potentially leading to structural defects around the sidewalls of one or more trenches containing the dielectric structure. These defects can cause current leakage, adversely affecting key performance indicators (KPIs) for dark pixels. However, since the dielectric structure may form early in the manufacturing process, the heating generated by subsequent process steps may help compensate for these defects.

[0026] Figure 1 The illustration shows a schematic exploded isometric view of some embodiments of the CIS multi-chip IC device 100 disclosed herein. The CIS multi-chip IC device 100 (hereinafter also referred to as CISIC device 100) includes an upper IC wafer or layer 102A and one or more lower IC layers 102B and 102C bonded together. In some embodiments, the upper IC layer 102A and the lower IC layers 102B and 102C (e.g., a first lower IC layer 102B, a second lower IC layer, etc.) are bonded at the wafer level (e.g., before being diced into individual ICs). In other embodiments, one or more of the upper IC layer 102A and the lower IC layers 102B and 102C are bonded to each other according to a wafer-to-wafer or flip-wafer bonding method.

[0027] In some embodiments, the upper IC layer 102A includes a pixel array 103 comprising a plurality of pixel cells 104 organized into a plurality of pixel cell groups 105. Each pixel cell 104 is sensitive to light 101 impacting the upper surface (e.g., the back surface) of the upper IC layer 102A. Furthermore, in some embodiments, as described in more detail below, the upper IC layer 102A may include additional circuitry that can be integrated with the pixel cells 104. Additionally, one or more lower IC layers 102B and 102C may include processing circuitry (not included in...) Figure 1(As shown in the figure), these processing circuits can be collectively employed (e.g., to generate image data representing the light 101 received in pixel cell 104). In some embodiments, pixel cell 104 and other circuits are organized between different IC layers 102A-102C as described below, each such IC layer being constructed using a manufacturing process or technology node suitable for the associated circuitry.

[0028] Figure 2A This illustration shows block diagrams of some embodiments of a pixel cell 104 that can be used in a CIS multichip IC device 100 according to this disclosure. In these embodiments, the pixel cell 104 may include a light sensor 202 that provides a light sensor value 206 (e.g., charge quantity), and a transmission transistor 204 that forwards the value as a transmission output 210 under the control of a transmission input 208. In some embodiments, as described below, the light sensor 202 may include a photodiode 302, such as a PIN diode or a pinned photodiode (PPD). However, in other embodiments, the light sensor 202 may be a phototransistor or other type of light sensor. In some embodiments, the pixel cell 104 may be assigned to detect different wavelength ranges (e.g., grouped into red, blue, and green pixels) by associating it with pixels positioned in... Figure 1 The corresponding filter is associated with the upper IC layer 102A. Furthermore, while the light sensor 202 may be sensitive to a specific visible light band or range or a set of ranges, in other embodiments, the light sensor 202 may be sensitive to non-visible light (e.g., infrared light).

[0029] Figure 2B This illustration shows some embodiments of pixel cells 104 that can be used in a CIS multichip IC device 100 according to this disclosure. Figure 2B As depicted, pixel cell 104 may include a photodiode 302 with its anode grounded (e.g., connected to a power supply voltage VSS), whose cathode provides the light sensor value 206 to the first source / drain connection of the transmission transistor 204. Furthermore, the transmission transistor 204 may respond to a transmission input 208 (in the transmission transistor 204 gate input) Figure 2B Also labeled "TX"), the optical sensor value 206 is transmitted to the transmission output 210 of the second source / drain region. However, in other embodiments, it may be used... Figure 2A Other configurations of the light sensor 202 and the transmission transistor 204.

[0030] Figure 3 This describes embodiments in which pixel cell 104 and associated processing circuitry can be organized or distributed across the three IC layers of a CISIC device (e.g., to facilitate improved device performance and / or cost). More specifically, Figure 3This illustration depicts schematic / block diagrams of some embodiments of a pixel cell 104, per-pixel circuitry 308, in-pixel circuitry 310, and application-specific integrated circuit (ASIC) 320, which can be used in a three-layer CIS multi-chip IC device according to this disclosure. As shown, the pixel cell 104, including a light sensor (e.g., photodiode 302) and a transmission transistor 204, is contained in the upper IC layer 102A as described above. Furthermore, the per-pixel circuitry 308 and the in-pixel circuitry 310 are located on a first lower IC layer 102B, while the ASIC circuitry 320 is located on a second lower IC layer 102C.

[0031] Although Figure 3 The document depicts a single pixel cell 104 and a single per-pixel circuit 308, but at least some embodiments described herein include multiple pixel cells 104 (e.g., organized into pixel cell groups 105, which may include, for example...). Figure 1 The depicted pixel cells 104 (rows and columns) and a plurality of per-pixel circuits 308, wherein each per-pixel circuit 308 is electrically coupled to a corresponding pixel cell 104. Figure 3 The diagram also shows that each per-pixel circuit 308 can be coupled to the in-pixel circuit 310.

[0032] In some embodiments, per-pixel circuitry 308 is configured to provide a timing indication of charge (e.g., transfer output 210) transferred from photodiode 302 of the corresponding pixel cell 104 via transfer transistor 204. For example, in some embodiments, per-pixel circuitry 308 may include source follower transistor 304, row select transistor 306, and / or reset transistor 307. Source follower transistor 304 may be electrically coupled to transfer transistor 204 (e.g., at the gate connection of source follower transistor 304) and configured to buffer transfer transistor 204 (e.g., transfer output 210) from another circuit (e.g., within in-pixel circuitry 310, such as a column bus). In some embodiments, source follower transistor 304 may be configured as an amplifier of transfer output 210. In some instances, the gate connection of source follower transistor 304 may be considered as floating diffusion (in... Figure 3 The charge is marked "FD" and then transferred to the in-pixel circuitry 310.

[0033] The reset transistor 307 may also be coupled to the source follower transistor 304 (e.g., at the gate connection of the source follower transistor 304) to reset the charge transferred from the photodiode 302 by the transfer transistor 204 under the control of the reset ("RST") signal (e.g., by raising the gate connection of the source follower transistor to the drain (supply) voltage VDD).

[0034] In some embodiments, the row select transistor 306 may be configured to forward the charge of the pixel cell 104 to the in-pixel circuitry 310 in a timing manner via the source follower transistor 304 based on a row select ("RS") signal (e.g., driving the gate connection of the row select transistor 306). Furthermore, in some embodiments, the row select transistor 306 may couple the source follower transistor 304 to the column bus of the in-pixel circuitry 310 via a drain / source connection.

[0035] In some embodiments, the in-pixel circuitry 310 may process multiple timing charge indications received by the source follower transistor 304 (e.g., row-by-row processing of multiple columns of pixel cells 104) to at least partially generate analog image data represented by charges stored in the pixel cells 104. In some embodiments, the in-pixel circuitry 310 may generate signals (e.g., TX, RST, and RS signals) that control the pixel cells 104 and per-pixel circuitry 308 as described above. More broadly, in some embodiments, the in-pixel circuitry 310 may include one or more column-level circuits, column bus signal lines (e.g., one signal line per column), one or more bias transistors (e.g., for biasing voltage levels of one or more column bus signal lines), a row controller, and a column controller.

[0036] In some embodiments, the ASIC circuit 320 may include any additional circuitry (e.g., one or more analog-to-digital converters (ADCs), memory, image signal processors (ISPs), communication circuitry, power supply circuitry, and / or similar circuitry) that may be used as part of or connected to the CMOS image sensor integrated circuit device 100.

[0037] Figure 4 This illustration shows multilayer block diagrams of some embodiments of the CIS multichip IC device 100A according to this disclosure. For example, in Figure 4 In the CISIC device 100A, there is an upper integrated circuit layer 102A, which includes pixel cells 104, and further includes a first lower integrated circuit layer 102B, which includes per-pixel circuitry 308 and in-pixel circuitry 310 (e.g., as described above in conjunction with...). Figure 3 (As discussed). Furthermore, in some embodiments, the CISIC device 100A also includes a second lower integrated circuit layer 102C, which may include power supply circuitry 402 (e.g., for providing, filtering, and / or distributing power to the CISIC device 100A), one or more memories 404 (e.g., for storing digital image data represented in pixel cells 104), and / or column ADCs 406 (for converting charge timing indications of pixel cells 104 into digital image data per column of pixel cells 104). In some embodiments, the CISIC device 100A may include additional lower integrated circuit layers (not discussed in...). Figure 4As explicitly shown in the document, these layers contain additional circuitry such as phase-locked loops (PLLs) (e.g., for generating timing signals for the in-pixel circuitry 310 and other parts of the CISIC device 100A), internal integration circuitry (I2C) (e.g., for providing communication between the CISIC device 100A and other circuits or systems), and ISPs (e.g., for processing digital image data generated from charges in pixel cells 104).

[0038] In some embodiments, the partitioning of the above-described functions between the upper integrated circuit layer 102A and the lower integrated circuit layers 102B, 102C, etc., may simplify the manufacturing of each individual integrated circuit layer 102A-102C because this reduces the number of different process technologies required to generate each individual integrated circuit layer. For example, in Figure 4 In this configuration, the upper integrated circuit layer 102A can be fabricated using at least one specialized process designed to create pixel cells 104 (e.g., to minimize the footprint of each pixel cell 104). Furthermore, in some embodiments, the first lower integrated circuit layer 102B can be fabricated using at least one low-power technology node (e.g., to implement per-pixel circuitry 308 and in-pixel circuitry 310). In some embodiments, the second lower integrated circuit layer 102C can be implemented using at least one high-voltage (e.g., thick oxide) technology (e.g., to accommodate the relatively high voltage levels of power supply circuitry 402 and / or column ADC 406). In some embodiments, more than one technology node can be employed on one or more integrated circuit layers 102A-102C. However, employing more than one integrated circuit layer may help prevent the use of three or more process technology nodes on any single integrated circuit layer.

[0039] Figure 5A and 5B , Figure 6A and 6B , Figure 7A and 7B as well as Figure 8A and 8B Each pair illustrates cross-sectional and plan views of some embodiments of a multilayer CISIC device employing a front-side isolation structure according to this disclosure. More specifically, Figure 5A and 5B Depicting pixel cell group 105A, Figure 6A and 6B Depicting pixel cell group 105B, Figure 7A and 7B Depicting pixel cell group 105C, Figure 8A and 8B Pixel cell group 105D is depicted. Furthermore, each pair of figures above depicts a single pixel cell group 105 comprising a 2x2 configuration of four pixel cells 104 within the upper integrated circuit layer 102A. Figure 5A ,6A Parts of the first lower integrated circuit layer 102B and the second lower integrated circuit layer 102C are also shown in 7A and 8A.

[0040] Figure 5A , 6A References 7A and 8A further illustrate a lens (e.g., a microlens) 520 and a filter 518, wherein a lens 520 and an associated filter 518 may be configured over a corresponding pixel cell 104 to focus and subsequently filter light supplied to the pixel cell 104. In some embodiments, each pixel cell group 105 may include filters of different colors (e.g., red, green, and blue). Furthermore, in some embodiments, one or more pixel cell groups 105 may include one red, two green, and one blue filter. However, in other embodiments, the filter 518 may be associated with combinations of other colors or wavelength bands.

[0041] exist Figure 5A , 6A In models 7A and 8A, the upper integrated circuit layer 102A may include a substrate 502 and a dielectric layer 504. In some embodiments, the substrate 502 of the upper integrated circuit layer 102A, and the substrate 502 of the first lower integrated circuit layer 102B and / or the second lower integrated circuit layer 102C, may be a semiconductor substrate including silicon (Si) and / or other semiconductor materials. Furthermore, in some embodiments, the dielectric layer 504 of the upper integrated circuit layer 102A, and the dielectric layer 504 of the first lower integrated circuit layer 102B and / or the second lower integrated circuit layer 102C, may include one or more dielectric materials, including but not limited to silicon oxide (SiO2). x (e.g., silicon dioxide (SiO2)), silicon nitride (SiN), silicon carbide (SiC), carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials or the like.

[0042] Regarding these identical diagrams, the substrate 502 of the upper integrated circuit layer 102A may include a photosensitive region 506 for each pixel cell 104. Each photosensitive region 506 may form a corresponding light sensor with the area surrounding the substrate 502 (e.g., Figure 3(Photodiode 302). In some embodiments, photosensitive regions 506 are formed on the substrate 502 near the lower surface (e.g., the front surface), and the dielectric layer 504 of the upper integrated circuit layer 102A is disposed near this surface. Furthermore, in some embodiments, in the dielectric layer 504 near the lower surface of the substrate 502, a transmission transistor 508 (e.g., including at least one source / drain connection, a gate oxide material with connecting metal contacts, and possible spacing structures) may be coupled to each photosensitive region 506 to form a corresponding pixel cell 104.

[0043] In some embodiments, the dielectric layer 504 of the upper integrated circuit layer 102A may include a plurality of conductive structures on the lower surface of the dielectric layer 504 opposite to the substrate 502. Furthermore, the dielectric layer 504 of the upper integrated circuit layer 102A may include conductive structures that electrically connect the pixel cells 104 to the conductive structures of the upper integrated circuit layer 102A. In some embodiments, the conductive structures may include conductive (e.g., metal) layers interconnected by conductive (e.g., metal) vias. Meanwhile, in some embodiments, the conductive pads may include metals (e.g., copper, aluminum, or the like) or other conductive materials.

[0044] Furthermore, in some embodiments, as described in more detail below, at least one dielectric structure 501 is configured in the upper integrated circuit layer 102A to at least partially isolate each pixel cell 104 from other pixel cells 104, and possibly from other portions of the upper integrated circuit layer 102A.

[0045] The first lower integrated circuit layer 102B may include its own substrate 502 (e.g., a silicon substrate) and two dielectric layers 504. In the first lower integrated circuit layer 102B, the substrate 502 may include at least a portion of a first processing circuit (e.g., Figure 3 Multiple per-pixel circuits 308, such as source follower transistors 304 and / or row select transistors 306. Multiple conductive structures may be present on the upper surface of the first dielectric layer 504 of the first lower integrated circuit layer 102B near the lower surface of the dielectric layer 504 of the upper integrated circuit layer 102A, wherein each conductive structure of the first dielectric layer 504 of the first lower integrated circuit layer 102B is in direct contact with a corresponding conductive structure of the dielectric layer 504 of the upper integrated circuit layer 102A. Simultaneously, conductive structures (e.g., vias) may be disposed in the first dielectric layer 504 of the first lower integrated circuit layer 102B to electrically couple the conductive structures of the first dielectric layer 504 with… Figure 3 The per-pixel circuitry 308 (e.g., source follower transistor 304 and / or row select transistor 306).

[0046] The second dielectric layer 504 of the first lower integrated circuit layer 102B is disposed on the lower surface of the substrate 502. A plurality of conductive structures 516 are disposed on the lower surface of the second dielectric layer 504. In some embodiments, one or more through-substrate vias (TSVs) 514 may be disposed in the substrate 502 of the first lower integrated circuit layer 102B and extend into the first dielectric layer 504 to electrically couple the conductive structures 516 of the first dielectric layer 504 with the conductive structures 516 of the second dielectric layer 504 of the first lower integrated circuit layer 102B.

[0047] like Figure 5A , 6A As shown in Figures 7A and 8A, the second lower integrated circuit layer 102C may include a substrate 502 and a dielectric layer 504. The second lower integrated circuit layer 102C may include... Figure 3 The ASIC circuit 320 shown is in... Figure 5A , 6A These figures are not explicitly depicted in 7A and 8A to simplify them.

[0048] In some embodiments, some circuits in the substrate 502 of the upper integrated circuit layer 102A, the first lower integrated circuit layer 102B, and / or the second lower integrated circuit layer 102C may be formed using multiple well regions and multiple doped isolation regions, which may be separated by shallow trench isolation (STI) structures. In some embodiments, one or more such well regions may include doped source regions and / or drain regions separated by channel regions. For simplicity... Figure 5A , 6A 7A and 8A are not typically shown in these diagrams.

[0049] Figure 5B , 6B 7B and 8B respectively depict Figure 5A , 6A Plan views of the cross-sectional views of 7A and 8A. In addition, Figure 5B , 6B Each of 7B and 8B illustrates a corresponding combination of dielectric and conductive structure configurations to provide a reference voltage (e.g., ground) connection for a photodetector (e.g., photosensitive region 506) and / or to provide a floating diffusion (FD) connection for a transmission transistor 508.

[0050] exist Figure 5A and 5B Pixel cell group 105A, Figure 6A and 6B Pixel cell group 105B, Figure 7A and 7B pixel cell group 105C and Figure 8A and 8BIn the pixel cell group 105D, the dielectric structure 501 may extend from the lower (e.g., first or front) surface to the opposite upper (e.g., second or back) surface, such as... Figure 5A , 6A Cross-sectional views of 7A and 8A are shown. Figure 5B , 6B In the plan views of 7B and 8B, the dielectric structure 501 is at least partially laterally surrounding each pixel cell 104, including the lateral periphery surrounding pixel cell groups 105A, 105B, 105C, and 105D. Furthermore, the dielectric structure 501 may include a plurality of first segments 530 (or "finger-like structures"), each first segment extending from a portion of the dielectric structure 501 surrounding pixel cell groups 105A, 105B, 105C, and 105D toward but not into the central region of the pixel cell group (e.g., at a common corner of each pixel cell 104), thereby leaving a first "gap" 540 in the dielectric structure 501.

[0051] In addition, although Figure 5A , 5B In pixel cell groups 105A and 105B of 6A and 6B, the dielectric structure 501 is continuous around these pixel cell groups, but... Figure 7A , 7B The dielectric structure 501 of pixel cell groups 105C and 105D in 8A and 8B may incorporate a second gap 542 at the corner of each pixel cell 104 opposite the central region or common corner of pixel cell groups 105C and 105D. For example, as Figure 7B and 8B As shown, the dielectric structure 501 may include a plurality of second segments 532 extending along the periphery (e.g., along one side) of the pixel cell groups 105C and 105D, and having a first end located outside the corner regions of the pixel cell groups 105C and 105D, and a second end located outside the adjacent corner regions of the pixel cell groups 105C and 105D. Therefore, in some embodiments, the second segments 532 may define second gaps 542, wherein each second gap 542 is located in a corresponding corner region of the pixel cell groups 105C and 105D.

[0052] In some embodiments, the first gap 540 and the second gap 542 described above can serve as access points where conductive structures can be placed, providing additional space for the photosensitive area 506 in each pixel cell 104 to capture light. For example, as Figure 5BAs shown, the floating diffusion (FD) connection may be located at a first gap 540 in the central region of the pixel cell group 105A (e.g., in the dielectric layer 504 on the substrate 502 of the upper integrated circuit layer 102A). Furthermore, the transfer transistor 508 of each pixel cell 104 may be located near the central region of the pixel cell group 105A or at a shared corner, close to the FD connection. Additionally, in some embodiments, the transfer transistor 508 (e.g., the gate structure of the transfer transistor 508) may be triangular in a plan view (e.g., to increase the usable area of ​​the photosensitive region 506 of the pixel cell group 105A), although the gate structure may also have other shapes. In these embodiments, the FD connection may be shared among the transfer transistors 508 (e.g., in a time-division manner).

[0053] Furthermore, in some embodiments, such as Figure 5B As shown, the ground (GND) connection for each photosensitive area 506, and therefore each photosensor of the pixel cell group 105A, can be located near a corner opposite the common corner of the central region of each pixel cell 104 and the pixel cell group 105A (e.g., to maximize the usable area of ​​the photosensitive area 106). Similar to the FD connection, the GND connection can be located in the dielectric layer 504 on the substrate 502 of the upper integrated circuit layer 102A.

[0054] exist Figure 6A and 6B In the middle, dielectric structure 501 is depicted as being related to Figure 5A and 5B Similar (e.g., having a first gap 540, but without a second gap 542). However, as Figure 6B As shown, a shared GND connection between pixel cells 104 can be provided in the central region of pixel cell group 105A (e.g., in the dielectric layer 504 on the substrate 502 of the upper integrated circuit layer 102A, shared by the light sensor of each pixel cell 104). Furthermore, the FD connection of each corresponding transmission transistor 508 can be located near a corner opposite the common corner of the central region of each pixel cell 104 and pixel cell group 105A (e.g., in the dielectric layer 504 on the substrate 502 of the upper integrated circuit layer 102A). Therefore, each transmission transistor 508 can be located at a corner opposite the central region of its corresponding pixel cell 104 and pixel cell group 105B. Additionally, in some embodiments, in the plan view, each transmission transistor 508 may have a [missing information - likely a typo, should be "from"]. Figure 5B The shape of the triangle is modified to leave space for FD connections in the relevant pixel cell 104.

[0055] Although Figure 5A , 5B Embodiments 6A and 6B do not include the second gap 542, but Figure 7A , 7BImages 8A and 8B depict the presence of a second gap 542, as described above, in addition to the first gap 540 in the central regions of pixel cell groups 105C and 105D. For example, Figure 7A and 7B pixel cell group 105C and Figure 8A and 8B The pixel cell group 105D includes a second gap 542 at each corner of the pixel cell group (e.g., at the corner opposite the common corner of the central region of each pixel cell 104 and the pixel cell group 105C). Therefore, the second gap 542 can accommodate conductive structures, thereby potentially creating more area for the associated photosensitive area 506 in each pixel cell 104.

[0056] For example, such as Figure 7B As shown, each pixel cell 104 of the pixel cell group 105 may include a GND connection for each corresponding photosensor in a corresponding second gap 542 of the dielectric structure 501 (e.g., in the dielectric layer 504 on the substrate 502 of the upper integrated circuit layer 102A). A shared FD connection may also be located in a first gap 540 of the dielectric structure 501 in the central region of the pixel cell group 105C, in a manner similar to... Figure 5B The pixel cell group 105A.

[0057] In other embodiments, such as Figure 8B As shown, a shared GND connection may be located in the first gap 540 of the dielectric structure 501 in the central region of the pixel cell group 105D, similar to... Figure 6B The configuration is shown. Furthermore, the dielectric structure 501 of the pixel cell group 105D may include a second gap 542 at each of its corners (e.g., the corner opposite the shared corner to each pixel cell 104), in a manner similar to... Figure 7B As shown. Therefore, the FD connection of the transmission transistor 508 of each pixel cell 104 can be located in each of such second gaps 542 of the dielectric structure 501. As a result, as Figure 6B Similarly, each transmission transistor 508 may be located at a corner opposite the center region of its corresponding pixel cell 104 and pixel cell group 105B. However, due to the presence of the second gap 542 where the FD connection is located, in some embodiments, each transmission transistor 508 may remain... Figure 7B The triangle shape shown.

[0058] Figure 9A and 9B Plan views illustrating some embodiments of a multilayer CISIC device employing a front-side isolation structure are provided in this disclosure. For example, Figure 9A Four pixel cell groups 105E, 105F, 105G, and 105H are depicted, each with a similar dielectric structure 501, and FD and GND connections, as shown. Figure 7A and 7B The pixel cell group 105C is shown. In some embodiments, the peripheral portions of the dielectric structure 501 of the pixel cell groups 105E, 105F, 105G, and 105H, as well as their various second gaps 542 and associated GND connections, may be combined or shared among the pixel cell groups, as described above. Similarly, Figure 9B Four pixel cell groups 105I, 105J, 105K, and 105L are depicted, each with a similar dielectric structure 501, and FD and GND connections, as shown. Figure 8A and 8B The pixel cell group 105D is shown. In some embodiments, the peripheral portions of the dielectric structure 501 of the pixel cell groups 105I, 105J, 105K and 105L, as well as their various second gaps 542 and corresponding FD connections, may be combined or shared among the pixel cell groups as described above.

[0059] In other embodiments, Figure 5A and 5B The pixel cell group 105A, and Figure 6A and 6B The pixel cell group 105B can also provide a similar arrangement of multiple pixel cell groups, wherein the peripheral portion of the dielectric structure 501 can be shared between the pixel cell groups, but there is no second gap 542 or [other gap]. Figure 9A and 9B The co-located conductive connection is discussed together.

[0060] Figures 10A to 10L Cross-sectional side views illustrating various embodiments of a CIS multi-wafer IC device employing a front-side isolation structure at different stages of manufacturing, according to this disclosure. Although Figures 10A to 10L Special and Figure 5A and 5B The pixel cell group 105A is related to other pixel cell group embodiments, which may employ the same or similar manufacturing stages as described below.

[0061] Although Figures 10A to 10L Described as a series of actions, but it should be understood that these actions are not limited, as the order of the actions may be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions described and / or illustrated may be omitted in whole or in part.

[0062] Figure 10AThe diagram describes the formation (e.g., implantation or doping) of multiple photosensitive regions 506 on a first surface of substrate 502. Substrate 502 may be a semiconductor substrate (e.g., a silicon (Si) substrate) and will serve as the basis for the upper IC layer 102A of the pixel cell group 105A of the CISIC device 100. Each photosensitive region 506 may include a light-absorbing region that, combined with substrate 502, forms a light sensor (e.g., a photodiode) sensitive to a specific wavelength band. In some embodiments, semiconductor substrate 502 may be p-type doped silicon, and photosensitive region 506 may be a portion of substrate 502 that has been ion-implanted or doped to create an n-type doped region. In some embodiments, the photodiode generated by forming the photosensitive region 506 may be a PN photodiode sensitive to visible light photons (e.g., a "clamped" photodiode). Furthermore, other doped regions, such as the n-type doped region of each transmission transistor 508 associated with each light sensor, may also be formed in substrate 502, but not on the substrate. Figure 10A It is clearly shown in the text.

[0063] Figure 10B This describes the formation (e.g., etching or other removal) of at least one trench 1002 around the pixel cell group 105A and the associated photosensitive region 506. In some embodiments, the location of the at least one trench 1002 determines the location of at least one dielectric structure 501, as described above. Figure 5A and 5B As described above. In some embodiments, the trench 1002 is formed on the same side (e.g., the front) or surface as the photosensitive area 506 (e.g., opposite the side (e.g., the back) or surface where the CISIC device 100 ultimately receives light). Furthermore, in some embodiments, the trench 1002 may partially extend into the substrate 502, such as... Figure 10B As shown. In other embodiments, the trench 1002 may pass completely through the substrate 502 (e.g., in cases where a carrier or other structure is attached to the opposite side of the substrate 502). Also, in some embodiments, the trench 1002 may be wider on the front side of the substrate 502 and narrower on the back side of the substrate 502.

[0064] Figure 10C This describes the formation (e.g., deposition filling) of a dielectric material (e.g., silicon oxide (SiO2)). x Materials such as silicon dioxide (SiO2) or other dielectric materials are used to form dielectric structure 501, as described above. Figure 5A , 5B As described in 6A, 6B, 7A, 7B, 8A, and 8B. In some embodiments, the dielectric structure 501 may have the structure or characteristics of a deep trench isolation (DTI) structure. Furthermore, in some embodiments, after forming the dielectric structure 501, it may... Figure 10CA planarization process is performed on the front surface (e.g., using chemical mechanical planarization (CMP)).

[0065] Figure 10D This describes the gate structure of the transmission transistor 508 coupled to the associated photosensor in each pixel cell 104, formed (e.g., by deposition, photolithography, etching, and / or similar methods) in a dielectric layer 504 on substrate 502 (e.g., on its front surface). As shown, additional conductive elements (source-drain connections, conductive layers, interconnect vias, etc.) associated with the transmission transistor 508 may also be formed together with the dielectric layer 504. Like other dielectric layers discussed herein, the dielectric layer 504 may comprise silicon oxide (SiO2). x ), such as silicon dioxide (SiO2), and / or one or more other dielectric materials.

[0066] Figure 10E This describes the reorientation (e.g., flipping) of the substrate 502, dielectric layer 504, and the aforementioned related components to provide contact with the back side of the substrate 502.

[0067] Figure 10F This describes the removal (e.g., full-sided etching) of a portion of the back side of substrate 502 to facilitate the extension of dielectric structure 501 through substrate 502. In some embodiments where trench 1002 is initially formed through substrate 502 (e.g., in the case described above where a carrier or similar structure is used to stabilize substrate 502), Figure 10F The removal operation may not be necessary.

[0068] Figure 10G The description provides a second substrate 502 (e.g., a silicon substrate) and various electrical components (e.g., source follower transistors 304 and / or row select transistors 306) deposited in the substrate 502 and in a first dielectric layer 504 formed on the second substrate 502. Figure 3 Each pixel circuit (308) includes various conductive components, doped regions, etc.

[0069] Figure 10H The second dielectric layer 504 is formed (e.g., deposited) on the surface of the second substrate 502 opposite to the first dielectric layer 504 to form the first lower integrated circuit layer 102B. In some embodiments, one or more through-substrate vias (TSVs) 514 may be formed through the substrate 502 of the first lower integrated circuit layer 102B and partially extend into one or both of the first and second dielectric layers 504. Furthermore, a conductive structure 516 may be formed on the surface of the second dielectric layer 504 to facilitate connections from the first dielectric layer 504 through the second substrate 502 to the conductive structure 516.

[0070] Figure 10IThe diagram illustrates how a first lower integrated circuit layer 102B is connected (e.g., bonded) to the front side of an upper integrated circuit layer 102A via a dielectric layer 504 and corresponding conductive structures. In some embodiments, the bonding may include direct bond interconnect (DBI) or other methods or operations that bond dielectric layers and associated conductive structures together. For example, such bonding may be achieved by dielectric-to-dielectric bonding (e.g., at room temperature) to dielectrically bond the first and second dielectric layers 504. Subsequently, in some embodiments, heat may be applied to compress the material. Figure 10I The first and second plurality of aligned conductive structures shown are configured to create a direct connection between them. In some embodiments, this internal compression is possible because the coefficient of thermal expansion (CTE) of the first and second plurality of conductive structures is greater than the CTE of the first and second dielectric layers 504.

[0071] Figure 10J This describes the fabrication of the second lower integrated circuit layer 102C, which may include ASIC circuitry 320 (e.g., such as...). Figure 3 (as shown) and / or other circuits. The second lower integrated circuit layer 402C may include a third substrate 502 and a fourth (upper) dielectric layer 504. In some embodiments, the dielectric layer 504 may include a conductive structure 516 that is aligned with a corresponding conductive structure 516 of the first lower integrated circuit layer 102B.

[0072] Figure 10K The first lower integrated circuit layer 102B and the second lower integrated circuit layer 102C are connected (e.g., bonded) via the third and fourth dielectric layers 504 and the corresponding conductive structure 516 (e.g., to facilitate the creation of one or more electrical connections between the first lower integrated circuit layer 102B and the second lower integrated circuit layer 102C). In some embodiments, the bonding may include DBI or other bonding methods as described above.

[0073] Figure 10L The description describes the formation (e.g., deposition and / or bonding) of a filter 518 (e.g., a color filter) and a lens 520 (e.g., a microlens) on the upper surface (e.g., the back side) of the substrate 502 of the upper integrated circuit layer 102A for each associated pixel cell 104. As described above, the filter 518 can filter out or allow light of a specific wavelength band to pass through, while the lens 520 can focus or otherwise guide the received light to its corresponding pixel cell 104.

[0074] Although Figures 10A to 10LThis indicates a specific order in which the CISIC device 100 may be manufactured, but other operational sequences may exist in other embodiments. For example, in some embodiments, the bonding order of integrated circuit layers 102A-102C may be performed in a different order, such as bonding the first lower integrated circuit layer 102B and the second lower integrated circuit layer 102C together first, and then bonding them to the upper integrated circuit layer 102A.

[0075] Figure 11 This document describes a method 1100 for forming a CIS multi-chip IC device (e.g., CIS IC device 100, including pixel cell groups 105A, 105B, 105C, and 105D) according to some embodiments. While this method and other methods described and / or illustrated herein are described as a series of actions or events, it should be understood that this disclosure is not limited to the illustrated order or actions. Therefore, in some embodiments, actions may be performed in a different order than described, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, while other undescribed actions or events may be included.

[0076] For example, in action 1102, on the substrate (e.g., Figure 10A Four photosensitive areas are formed in a 2x2 configuration in the substrate 502 (e.g., ...). Figure 10A The photosensitive area 506) is used to create four light sensors (e.g., Figure 2A Optical sensor 202 or Figure 2B and 3 The four photodiodes 302 are located adjacent to the first surface (e.g., the front) of the substrate. Figure 10A The illustration shows cross-sectional views corresponding to some embodiments of action 1102.

[0077] In action 1104, at least one extending to the first surface of the substrate is formed (e.g., Figure 10B The groove 1002), and in the plan view, a groove is formed to separate each of the four photosensitive areas from the adjacent photosensitive areas of the four photosensitive areas, to create four pixel cells (e.g., Figure 5A , 6A Pixel cells 104 of 7A and 8A, wherein at least one trench includes a gap located at a common corner of the four pixel cells (e.g., a first gap 540, with a floating diffusion connection located in the central region). Figure 10B The illustration shows cross-sectional views corresponding to some embodiments of action 1104.

[0078] In action 1106, at least one dielectric structure is formed in at least one trench (e.g., Figure 5A , 5B Dielectric structures 501 for 6A, 6B, 7A, 7B, 8A, and 8B. Figure 10C The illustration shows cross-sectional views corresponding to some embodiments of action 1106.

[0079] In action 1108, a gate structure is formed on the first surface of the substrate in each of the four pixel cells to create a transmission transistor coupled to the four light sensors (e.g., Figure 2A , 2B and 3 transmission transistors 204; and Figure 5A , 5B Transmission transistors 508 of types 6A, 6B, 7A, 7B, 8A, and 8B. In operation 1110, a conductive structure is formed at the gap on the first surface of the substrate (e.g., ...). Figure 5B and 7B Floating diffusion connections; and Figure 6B and 8B (grounding connection), the conductive structure is electrically connected to at least one of the photosensitive or transmission transistors in each of the four pixel cells. Figure 10D Cross-sectional views are shown corresponding to some embodiments of actions 1108 and 1110.

[0080] Some embodiments relate to an integrated circuit device. The integrated circuit device includes an integrated circuit layer containing a plurality of pixel cell groups, each of the plurality of pixel cell groups including: a plurality of pixel cells arranged in a 2x2 configuration in a planar view; each of the plurality of pixel cells including: a photosensor in an integrated circuit layer substrate; and a transfer transistor electrically coupled to the photosensor, configured to transfer charge collected by the photosensor from a first surface of the substrate; and at least one dielectric structure extending from the first surface of the substrate to a second surface of the substrate and separating each of the plurality of pixel cells from adjacent pixel cells, wherein the at least one dielectric structure includes a first gap located at a common corner of the plurality of pixel cells, wherein a first conductive structure is electrically connected to at least one of the photosensor or transfer transistor of each of the plurality of pixel cells and is disposed in the first gap on the first surface of the substrate.

[0081] In the above embodiment, the transmission transistor of each of the plurality of pixel cells is configured near the common corner of the plurality of pixel cells.

[0082] In the above embodiments, the gate structure of the transmission transistor of each of the plurality of pixel cells includes a triangular shape in the plan view.

[0083] In the above embodiments, wherein: the first conductive structure provides a ground connection for the light sensor of each of the plurality of pixel cells; and each of the plurality of pixel cells includes a second conductive structure located above the first surface of the substrate, the second conductive structure providing a floating diffusion connection for the transmission transistor of the pixel cell, the second conductive structure being disposed near an opposite corner of the pixel cell opposite to the common corner.

[0084] In the above embodiments, wherein: the first conductive structure provides a floating diffusion connection for the transmission transistor of each of the plurality of pixel cells; and each of the plurality of pixel cells includes a second conductive structure located above the first surface of the substrate, the second conductive structure providing a ground connection for the photosensor of the pixel cell, the second conductive structure being disposed near an opposite corner of the pixel cell opposite the common corner.

[0085] In the above embodiments, the at least one dielectric structure further includes a plurality of second gaps, each of the plurality of second gaps being disposed at an opposite corner corresponding to one of the plurality of pixel cells opposite to the common corner.

[0086] In the above embodiments, wherein: the first conductive structure provides a ground connection for the light sensor of each of the plurality of pixel cells; and each of the plurality of pixel cells includes a second conductive structure located above the first surface of the substrate, the second conductive structure providing a floating diffusion connection for the transmission transistor of the pixel cell, the second conductive structure being disposed in a second gap associated with the pixel cell.

[0087] In the above embodiments, wherein: the first conductive structure provides a floating diffusion connection for the transmission transistor of each of the plurality of pixel cells; and each of the plurality of pixel cells includes a second conductive structure located above the first surface of the substrate, the second conductive structure providing a ground connection for the photosensor of the pixel cell, the second conductive structure being disposed in a second gap associated with the pixel cell.

[0088] In the above embodiments, wherein: one of the plurality of pixel cell groups is adjacent to another of the plurality of pixel cell groups; and one of the plurality of pixel cell groups shares at least one of the second gaps of the at least one dielectric structure with another of the plurality of pixel cell groups.

[0089] Some embodiments relate to another integrated circuit device. This integrated circuit device includes an integrated circuit layer containing a plurality of pixel cell groups, each of the plurality of pixel cell groups including: a plurality of pixel cells arranged in a 2x2 configuration in a plan view; each of the plurality of pixel cells including: a photosensitive sensor in a substrate of the integrated circuit layer; and a transfer transistor electrically coupled to the photosensitive sensor, configured to transfer charge collected by the photosensitive sensor from a first surface of the substrate; and at least one dielectric structure extending from the first surface of the substrate to a second surface of the substrate and separating each of the plurality of pixel cells from adjacent pixel cells in a plan view, wherein the at least one dielectric structure includes a plurality of first segments, each of the plurality of first segments having a first end and a second end, the first end being located at the periphery of the 2x2 configuration and the second end being located outside a central region of the 2x2 configuration, wherein a first conductive structure is electrically connected to at least one of the photosensitive sensor or transfer transistor of each of the plurality of pixel cells and is configured in a central region on the first surface of the substrate.

[0090] In the above embodiments, wherein: the first conductive structure provides a ground connection for the light sensor of each of the plurality of pixel cells; and each of the plurality of pixel cells includes a second conductive structure located above the first surface of the substrate and provides a floating diffusion connection for the transmission transistor of the pixel cell, the second conductive structure being disposed near the opposite corner of the pixel cell opposite the central region.

[0091] In the above embodiments, wherein: the first conductive structure provides a floating diffusion connection for the transmission transistor of each of the plurality of pixel cells; and each of the plurality of pixel cells includes a second conductive structure located above the first surface of the substrate and provides a ground connection for the photosensor of the pixel cell, the second conductive structure being disposed near the opposite corner of the pixel cell opposite the central region.

[0092] In the above embodiments, the at least one dielectric structure further includes a plurality of second segments, each of the plurality of second segments extending along the periphery of the 2x2 configuration, each of the plurality of second segments having a first end located outside one of the plurality of corner regions of the 2x2 configuration, and a second end located outside another of the plurality of corner regions of the 2x2 configuration.

[0093] In the above embodiments, wherein: the first conductive structure provides a ground connection for the light sensor of each of the plurality of pixel cells; and each of the plurality of pixel cells includes a second conductive structure located above the first surface of the substrate and provides a floating diffusion connection for the transmission transistor of the pixel cell, the second conductive structure being configured in one of the corresponding corner regions of the 2x2 configuration.

[0094] In the above embodiments, wherein: the first conductive structure provides a floating diffusion connection for the transmission transistor of each of the plurality of pixel cells; and each of the plurality of pixel cells includes a second conductive structure located above the first surface of the substrate and provides a ground connection for the photosensor of the pixel cell, the second conductive structure being configured in one of the corresponding corner regions of the 2x2 configuration.

[0095] Some embodiments relate to a method. The method includes: forming four photosensitive regions in a 2x2 configuration in a plan view in a substrate to create four photosensors, the four photosensitive regions adjacent to a first surface of the substrate; forming at least one trench extending into the first surface of the substrate and separating each of the four photosensitive regions from its adjacent photosensitive regions in the plan view to create four pixel cells, wherein the at least one trench includes a first gap located at a common corner of the four pixel cells; forming at least one dielectric structure in the at least one trench; forming a gate structure on the first surface of the substrate, in each of the four pixel cells, to create a transmission transistor coupled to one of the four photosensors; and forming a first conductive structure on the first surface of the substrate, at the first gap, electrically connected to at least one of the photosensors or transmission transistors in each of the four pixel cells.

[0096] In the above embodiments, the manufacturing method further includes: forming a second conductive structure on the first surface of the substrate, near the opposite corner of each of the four pixel cells opposite to the common corner, wherein the first conductive structure provides a ground connection for the light sensor of each of the four pixel cells; and each of the second conductive structures provides a floating diffusion connection for the transmission transistor of the corresponding pixel cell.

[0097] In the above embodiments, the manufacturing method further includes: forming a second conductive structure on the first surface of the substrate, near the opposite corner of each of the four pixel cells opposite to the common corner, wherein the first conductive structure provides a floating diffusion connection for the transmission transistor of each of the four pixel cells; and each of the second conductive structures provides a ground connection for the light sensor of the corresponding pixel cell.

[0098] In the above embodiments, the at least one trench further includes four second gaps, each of the four second gaps being disposed at a corresponding opposite corner of one of the four pixel cells opposite the common corner, the method further including: forming a second conductive structure in each of the four second gaps on the first surface of the substrate, wherein the first conductive structure provides a ground connection for the photosensor of each of the four pixel cells; and each of the second conductive structures provides a floating diffusion connection for the transmission transistor of the corresponding pixel cell.

[0099] In the above embodiments, the at least one trench further includes four second gaps, each of the four second gaps being disposed at a corresponding opposite corner of one of the four pixel cells opposite the common corner, the method further including: forming a second conductive structure in each of the four second gaps on the first surface of the substrate, wherein the first conductive structure provides a floating diffusion connection for the transmission transistor of each of the four pixel cells; and each of the second conductive structures provides a ground connection for the photosensor of the corresponding pixel cell.

[0100] It should be understood that in this written description and the claims below, the terms "first," "second," "third," etc., are merely general identifiers used for ease of description to distinguish different elements in a figure or series of figures. These terms themselves do not imply any temporal order or structural proximity of these elements, nor are they intended to describe corresponding elements in different illustrative embodiments and / or unillustrative embodiments. For example, "first dielectric layer" described in relation to a first figure does not necessarily correspond to "first dielectric layer" described in relation to another figure, nor does it necessarily correspond to "first dielectric layer" in unillustrative embodiments.

[0101] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

Claims

1. An image sensor integrated circuit device, characterized in that, include: An integrated circuit layer includes multiple pixel cell groups, each of which includes: A plurality of pixel cells are arranged in a 2x2 configuration in a planar diagram, each of the plurality of pixel cells comprising: The optical sensor in the substrate of the integrated circuit layer; and A transmission transistor, electrically coupled to the optical sensor and configured to transfer the charge collected by the optical sensor across a first surface of the substrate; and At least one dielectric structure extends from the first surface of the substrate to the second surface of the substrate and separates each of the plurality of pixel cells from its neighboring pixel cells, wherein the at least one dielectric structure includes a first gap disposed at a common corner of the plurality of pixel cells, wherein a first conductive structure is electrically connected to at least one of the photosensor or the transmission transistor of each of the plurality of pixel cells and is disposed in the first gap above the first surface of the substrate.

2. The image sensor integrated circuit device of claim 1, wherein the transmission transistor of each of the plurality of pixel cells is disposed near the common corner of the plurality of pixel cells.

3. The image sensor integrated circuit device of claim 1, wherein the gate structure of the transmission transistor of each of the plurality of pixel cells comprises a triangular shape in the plan view.

4. The image sensor integrated circuit device of claim 1, wherein the at least one dielectric structure further comprises a plurality of second gaps, each of the plurality of second gaps being disposed at an opposite corner corresponding to one of the plurality of pixel cells opposite to the common corner.

5. The image sensor integrated circuit device according to claim 4, wherein: The first conductive structure provides a ground connection for the light sensor in each of the plurality of pixel cells; and Each of the plurality of pixel cells includes a second conductive structure located above the first surface of the substrate, the second conductive structure providing a floating diffusion connection for the transmission transistor of the pixel cell, the second conductive structure being disposed in a second gap associated with the pixel cell.

6. The image sensor integrated circuit device according to claim 4, wherein: One of the plurality of pixel cell groups is adjacent to another of the plurality of pixel cell groups; and One of the plurality of pixel cell groups shares at least one of the second gaps of the at least one dielectric structure with another of the plurality of pixel cell groups.

7. An image sensor integrated circuit device, comprising: include: An integrated circuit layer includes multiple pixel cell groups, each of which includes: A plurality of pixel cells are arranged in a 2x2 configuration in a planar diagram, each of the plurality of pixel cells comprising: A photosensitive sensor located in the substrate of the integrated circuit layer; and A transmission transistor, electrically coupled to the optical sensor and configured to transfer the charge collected by the optical sensor across a first surface of the substrate; and At least one dielectric structure extends from a first surface of the substrate to a second surface of the substrate and separates each of the plurality of pixel cells from its neighboring pixel cells in the plan view, wherein the at least one dielectric structure includes a plurality of first segments, each of the plurality of first segments having a first end and a second end, the first end being located at the periphery of the 2x2 configuration and the second end being located outside the central region of the 2x2 configuration, wherein a first conductive structure is electrically connected to at least one of the photosensor or the transmission transistor of each of the plurality of pixel cells and is disposed above the first surface of the substrate in the central region.

8. The image sensor integrated circuit device of claim 7, wherein the at least one dielectric structure further comprises a plurality of second segments, each of the plurality of second segments extending along the periphery of the 2x2 configuration, each of the plurality of second segments having a first end located outside one of the plurality of corner regions of the 2x2 configuration, and a second end located outside another of the plurality of corner regions of the 2x2 configuration.

9. The image sensor integrated circuit device according to claim 8, wherein: The first conductive structure provides a ground connection for the light sensor in each of the plurality of pixel cells; and Each of the plurality of pixel cells includes a second conductive structure located above the first surface of the substrate and providing a floating diffusion connection for the transmission transistor of the pixel cell, the second conductive structure being configured in one of the corresponding corner regions of the 2x2 configuration.

10. The image sensor integrated circuit device according to claim 8, wherein: The first conductive structure provides a floating diffusion connection for the transmission transistor of each of the plurality of pixel cells; and Each of the plurality of pixel cells includes a second conductive structure located above the first surface of the substrate and providing a ground connection for the light sensor of the pixel cell, the second conductive structure being configured in one of the corresponding corner regions of the 2x2 configuration.

Images