Packaging structure

Abstract

This utility model relates to the field of semiconductor technology and provides a packaging structure, including: a chip, a carrier board, and a packaging layer. The chip includes a substrate and a functional layer disposed on the substrate. The functional layer has multiple pads, each of which has a bump. The carrier board is soldered to the bumps. The packaging layer is disposed on the carrier board and is used to encapsulate the chip and the carrier board into a whole. The substrate extends beyond the packaging layer. This packaging structure, by flip-chip bonding, connects the chip to the carrier board. During packaging, the chip's substrate is encapsulated outside the packaging layer, allowing the substrate to directly contact the heat sink, improving the thermal conductivity of the packaging structure. Both the substrate and the carrier board can dissipate heat, reducing thermal resistance and enhancing the heat dissipation effect of the packaging structure, thus improving its performance.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a packaging structure. Background Technology

[0002] Flip-chip technology, an advanced technology in semiconductor packaging, is characterized by flipping the active side of the chip directly downwards, achieving electrical and mechanical connections with the carrier substrate via bumps. Specifically, after the chip and carrier substrate are connected, a packaging process is required to integrate the chip and substrate into a functional unit. At this stage, a heat sink is typically placed outside the package to aid in heat dissipation. However, existing packaging structures suffer from significant thermal management bottlenecks—the overall thermal resistance after packaging is relatively high, making it difficult to effectively dissipate heat, thus affecting the performance stability and reliability of the product. Utility Model Content

[0003] This invention provides a packaging structure to solve the problem of poor overall heat dissipation after flip chip packaging in the prior art.

[0004] This utility model provides a packaging structure, including: a chip, the chip including a substrate and a functional layer disposed on the substrate, the functional layer having a plurality of pads, each of the pads having a bump; a carrier board, soldered to the bumps; and a packaging layer disposed on the carrier board, the packaging layer being used to package the chip and the carrier board into a whole; wherein, the substrate extends beyond the packaging layer.

[0005] According to the encapsulation structure provided by this utility model, a filling layer is further included, and there is a gap between the carrier plate and the functional layer, and the filling layer fills the gap between the carrier plate and the functional layer.

[0006] According to the packaging structure provided by this utility model, the filling layer extends beyond the end of the chip, and the packaging layer is disposed on the filling layer.

[0007] According to the packaging structure provided by this utility model, the thickness of the substrate extending outside the packaging layer is 10±5 micrometers.

[0008] According to the packaging structure provided by this utility model, a metallization layer under the bump is further provided between the pad and the bump.

[0009] According to the packaging structure provided by this utility model, the under-bump metallization layer includes: an adhesive / barrier layer disposed on one side of the pad; a wetting layer disposed on one side of the adhesive / barrier layer, and the bump is disposed on one side of the wetting layer.

[0010] According to the packaging structure provided by this utility model, the number of chips is multiple, and the substrate of at least one chip extends outside the packaging layer.

[0011] According to the packaging structure provided by this utility model, the plurality of pads are divided into a first type of pad, a second type of pad, and a third type of pad. The areas of the first type of pad, the second type of pad, and the third type of pad are not equal. The first type of pad, the second type of pad, and the third type of pad are used to connect different electrodes.

[0012] According to the packaging structure provided by this utility model, solder paste is provided at multiple positions on the carrier board, and the positions of the solder paste correspond one-to-one with the positions of the multiple bumps.

[0013] According to the packaging structure provided by this utility model, the carrier board is a rewiring structure.

[0014] The packaging structure provided by this utility model connects the chip to the carrier board by flipping the chip. During packaging, the chip substrate is encapsulated outside the packaging layer, allowing the substrate to directly contact the heat sink, which improves the thermal conductivity of the packaging structure. Both the substrate and the carrier board can dissipate heat, reducing thermal resistance, enhancing the heat dissipation effect of the packaging structure, and improving the performance of the packaging structure. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is one of the structural diagrams of the packaging structure provided by this utility model.

[0017] Figure 2 This is the second schematic diagram of the packaging structure provided by this utility model.

[0018] Figure 3 This is a schematic diagram of the structure of the metallization layer under the bump.

[0019] Figure label: 10. Carrier board; 11. First solder mask layer; 12. First conductive layer; 13. Insulating layer; 14. Conductive pillar; 15. Second conductive layer; 16. Second solder mask layer; 17. Lead; 20. Chip; 21. Substrate; 22. Functional layer; 23. Bump; 24. Pad; 25. Under-bump metallization layer; 30. Encapsulation layer; 40. Filler layer; 251. Adhesive / barrier layer; 252. Wetting layer. Detailed Implementation

[0020] The embodiments of this utility model will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of this utility model.

[0021] In the description of the embodiments of this utility model, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this utility model. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0022] In the description of the embodiments of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this utility model based on the specific circumstances.

[0023] In this embodiment of the utility model, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0024] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0025] The following is combined with Figures 1-3 Describe the packaging structure of this utility model.

[0026] like Figure 1 As shown, in an embodiment of this utility model, the packaging structure includes a carrier board 10, a chip 20, and a packaging layer 30. The chip 20 includes a substrate 21 and a functional layer 22 disposed on the substrate 21. The functional layer 22 has a plurality of pads 24, each pad 24 having a bump 23, and the bump 23 is soldered to the carrier board 10. The packaging layer 30 is disposed on the carrier board 10 and is used to package the chip 20 and the carrier board 10 into a whole, wherein the substrate 21 extends beyond the packaging layer 30.

[0027] Specifically, in this embodiment, the carrier board 10 is a redistribution structure, configured to reroute the pads 24 to pins 17 on the redistribution structure away from the chip 20; the redistribution structure may include one or more structured conductive layers, with structured insulating layers 13 deployed between the structured conductive layers. Figure 1 For example, the carrier board 10 includes: a first solder resist layer 11, a first conductive layer 12, an insulating layer 13, a second conductive layer 15, and a second barrier layer 16, arranged sequentially. Through-holes are formed in the insulating layer 13, and conductive metal is deposited in the through-holes to form conductive pillars 14. The two ends of the conductive pillars 14 are connected to the first conductive layer 12 and the second conductive layer 15, respectively, to achieve interconnection between multiple conductive layers. Through-grooves are formed in the first solder resist layer 11 and the second solder resist layer 16, and nickel, gold, etc., are deposited in the through-grooves to form leads 17.

[0028] When flipping the chip 20, the bump 23 is inserted into the through slot on the second solder mask layer 16. Through reflow soldering, the bump 23 is soldered to the pin 17 to connect the chip 20 to the carrier board 10. Then, the chip 20 and the carrier board 10 are packaged together to form a package structure. During packaging, the surface of the substrate 21 is exposed outside the package layer 30. When using the package structure, a heat sink can be placed on the substrate 21. Compared to encapsulating the substrate 21 inside the package layer 30, the substrate 21 is in direct contact with the heat sink, improving the thermal conductivity of the package structure. Simultaneously, the side of the carrier board 10 away from the chip 20 is also located outside the package layer 30, allowing heat dissipation from both sides of the package structure, reducing the thermal resistance of the package structure and enhancing its heat dissipation effect.

[0029] In this embodiment, chip 20 can be a power chip such as a gallium nitride chip, a silicon chip, or a silicon carbide chip. The specific structure of the functional layer 22 varies depending on the type of chip 20, and those skilled in the art can design it flexibly based on existing technology. Taking a gallium nitride chip as an example, the functional layer 22 includes: a nucleation layer, a buffer layer, a high-resistivity layer, a channel layer, a barrier layer, a source, a gate, and a drain. The substrate 21, nucleation layer, buffer layer, high-resistivity layer, channel layer, and barrier layer are stacked sequentially. The source, gate, and drain are disposed on the barrier layer. Pads 24 are disposed on the source, drain, and gate.

[0030] Optionally, the thickness of the substrate 21 extending beyond the encapsulation layer 30 can be 10 ± 5 micrometers.

[0031] The packaging structure provided in this embodiment of the utility model connects the chip to the carrier board by flipping the chip. During packaging, the chip substrate is encapsulated outside the packaging layer, which allows the substrate to directly contact the heat sink, improving the thermal conductivity of the packaging structure. Both the substrate and the carrier board can dissipate heat, reducing thermal resistance, enhancing the heat dissipation effect of the packaging structure, and improving the performance of the packaging structure.

[0032] like Figure 2 As shown, in embodiments of this utility model, the number of chips 20 can be multiple. When multiple chips 20 are flip-chip packaged with the carrier board 10, the substrate 21 of each chip 20 can be exposed outside the packaging layer 30, or the substrate 21 of some chips 20 can be exposed outside the packaging layer 30. Figure 2 In the illustrated embodiment, there are two chips 20. When the two chips 20 are flip-chip packaged with the carrier 10, the substrate 21 of one chip 20 is exposed outside the packaging layer 30, while the substrate 21 of the other chip 20 is located inside the packaging layer 30. In this embodiment, even if the substrate 21 of one chip 20 is located outside the packaging layer 30, it can still improve thermal conductivity, reduce thermal resistance, and enhance heat dissipation, thereby ensuring the performance of the packaging structure.

[0033] Furthermore, in practical applications, each package structure may contain one chip 20 or multiple chips. When there is only one chip 20 in the package structure, the substrate 21 of the chip 20 extends outside the package layer 30; when there are multiple chips 20 in the package structure, it must be ensured that the substrate 21 of at least one chip 20 extends outside the package layer 30.

[0034] Furthermore, during the manufacturing of the packaging structure, multiple chips 20 can be simultaneously packaged on a carrier board 10, with the substrate 21 of each chip 20 extending beyond the packaging layer 30. Then, the packaging structure is cut into multiple packages, each package containing one chip 20.

[0035] like Figure 1 As shown, in an embodiment of this utility model, an under-bump metallization layer 25 is further provided between the pad 24 and the bump 23. The under-bump metallization layer 25 is used to improve the adhesion between the bump 23 and the pad 24, and to prevent the bump 23 and the pad 24 from undergoing chemical reactions or interdiffusion in order to maintain their respective chemical stability.

[0036] Specifically, such as Figure 3 As shown, the under-bump metallization layer 25 includes an adhesive / barrier layer 251 and a wetting layer 252. The adhesive / barrier layer 251 is disposed on one side of the pad 24, the wetting layer 252 is disposed on one side of the adhesive / barrier layer 251, and the bump 23 is disposed on one side of the wetting layer 252.

[0037] Specifically, in manufacturing bump 23, a Ti layer or TiW layer is sputtered onto functional layer 22, followed by a copper layer to form an adhesive / barrier layer 251. Photoresist is coated onto the adhesive / barrier layer 251, and then ultraviolet light exposure is performed using a solder bump mask to define the position and shape of bump 23. A copper layer is electroplated at the location of bump 23 as a wetting layer 252. To ensure that the thickness of bump 23 reaches the target value, the electroplating height of bump 23 is controlled to exceed the coated photoresist layer during the electroplating process, allowing bump 23 to form a mushroom shape. The photoresist is then stripped, and excess metallization layer 25 under the bump is removed from other locations to form bump 23.

[0038] Furthermore, in a further embodiment of this utility model, solder paste is provided at multiple locations on the carrier plate 10, and the positions of the solder paste correspond one-to-one with the positions of multiple bumps 23. After the bumps 23 are aligned with the solder paste, reflow soldering is used, that is, the solder paste is melted and connected to the bumps 23. After cooling and solidification, the bumps 23 are welded together with the carrier plate 10, thus achieving a reliable electrical and mechanical connection.

[0039] The packaging structure provided in this embodiment of the utility model achieves a high number of pins and free arrangement of multiple pins by setting bumps on the pads; the chip is connected to the carrier board through the bumps, and the internal chip does not need to be connected by wire bonding, thus realizing multi-layer interconnection.

[0040] like Figure 1 As shown in the embodiment of this utility model, the encapsulation structure further includes a filling layer 40. After the bump 23 is welded to the carrier plate 10, there is a gap between the carrier plate 10 and the functional layer 22, and the filling layer 40 fills the gap between the carrier plate 10 and the functional layer 22.

[0041] Specifically, filling the gap between the carrier 10 and the functional layer 22 with a filler layer 40 can better protect the bumps 23, enhance the mechanical connection between the chip 20 and the carrier 10, alleviate thermal stress, protect the chip 20 from environmental influences, and improve the reliability of the packaging structure.

[0042] like Figure 1 As shown, in this embodiment of the present invention, the fill layer 40 extends beyond the end of the chip 20, and the encapsulation layer 30 is disposed on the fill layer 40 to encapsulate the chip 20 and the carrier board 10 into a whole. In this embodiment, since the encapsulation layer 30 is located on the fill layer 40, the carrier board 10 is exposed outside the encapsulation layer 30, thereby allowing heat dissipation to occur on the side of the carrier board 10 away from the chip 20, achieving double-sided heat dissipation of the encapsulation structure and enhancing the heat dissipation effect.

[0043] In embodiments of this invention, the multiple pads 24 are divided into a first type of pad, a second type of pad, and a third type of pad. The areas of the first, second, and third type of pads are not equal, allowing the pads 24 to be soldered to different electrodes. For example, the largest pad 24 can be soldered to the drain electrode, the medium-sized pad 24 can be soldered to the source electrode, and the smallest pad 24 can be soldered to the gate electrode. The larger pads 24 are more conducive to heat dissipation in the package structure.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A packaging structure, characterized in that, include: A chip, the chip including a substrate and a functional layer disposed on the substrate, the functional layer having a plurality of pads, each of the pads having a bump; The carrier plate is welded to the protrusions; An encapsulation layer is disposed on the carrier board, and the encapsulation layer is used to encapsulate the chip and the carrier board into a whole; The substrate extends beyond the encapsulation layer.

2. The packaging structure according to claim 1, characterized in that, It also includes a filler layer, with a gap between the carrier plate and the functional layer, and the filler layer fills the gap between the carrier plate and the functional layer.

3. The packaging structure according to claim 2, characterized in that, The filling layer extends beyond the end of the chip, and the encapsulation layer is disposed on the filling layer.

4. The packaging structure according to claim 1, characterized in that, The thickness of the substrate extending beyond the encapsulation layer is 10 ± 5 micrometers.

5. The packaging structure according to claim 1, characterized in that, A metallization layer under the bump is also provided between the pad and the bump.

6. The packaging structure according to claim 5, characterized in that, The under-bump metallization layer includes: An adhesive / barrier layer is provided on one side of the pad; A wetting layer is provided on one side of the adhesive / barrier layer, and the protrusions are provided on one side of the wetting layer.

7. The packaging structure according to claim 1, characterized in that, The number of chips is multiple, and the substrate of at least one chip extends beyond the encapsulation layer.

8. The packaging structure according to claim 1, characterized in that, The multiple pads are divided into a first type of pad, a second type of pad, and a third type of pad. The areas of the first type of pad, the second type of pad, and the third type of pad are not equal. The first type of pad, the second type of pad, and the third type of pad are used to connect different electrodes.

9. The packaging structure according to claim 1, characterized in that, Solder paste is provided at multiple locations on the carrier plate, and the positions of the solder paste correspond one-to-one with the positions of the multiple bumps.

10. The packaging structure according to claim 1, characterized in that, The carrier board has a rewiring structure.

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