High precision programmable temperature sensing circuit for dc-dc power supply controller

Abstract

The utility model relates to a kind of high-precision programmable temperature detection circuit for DC-DC power supply controller, including common-source common-gate current mirror and bias voltage generation circuit, temperature sensing circuit, temperature sensing voltage Vtd differential amplifier circuit and programmable quantization comparison circuit of voltage Vtd, finally obtain the temperature detection quantization code dt1~dtM of M bit.The utility model has the advantages that: every reference voltage size in the M reference voltage Vrt1~VrtM in the programmable quantization comparison circuit can be fine-tuned by adjusting code, set it to the size value matched with temperature sensing voltage Vtd nonlinearity, the error amount of temperature sensing voltage voltage Vtd nonlinearity can be compensated, so that the temperature detection quantization code dt1~dtM output by quantization comparison circuit and actual temperature size keep consistent, realize high-precision temperature detection.

Description

Technical Field

[0001] This utility model relates to a high-precision programmable temperature detection circuit for DC-DC power controllers, belonging to the field of integrated circuit technology. Background Technology

[0002] As power modules evolve towards miniaturization, lightweight design, and portability, battery life has become one of the most crucial technical indicators. To launch more competitive switching converter products, power management controller chips need higher conversion efficiency, lower noise and output ripple, and faster transient response characteristics to achieve higher power density. However, high power density power supplies generate more heat in a smaller volume, leading to increased temperatures. Poor heat dissipation can degrade component performance and even cause malfunctions. Therefore, precise monitoring of the on-chip temperature of the power management chip is essential.

[0003] High-precision on-chip temperature monitoring is crucial for ensuring the stability and reliability of power chips and equipment. Temperature directly affects the chip's conversion efficiency, output stability, and lifespan. High temperatures can lead to increased leakage current and timing deviations, while low temperatures can cause startup difficulties or performance degradation. By monitoring the on-chip temperature in real time, abnormal temperature rises can be detected promptly, and protective measures can be taken to prevent thermal runaway or equipment damage.

[0004] In addition, temperature data helps engineers identify thermal design flaws, such as inadequate heat dissipation structures or insufficient temperature resistance of key components. In fields such as new energy vehicles and industrial equipment, power chips need to operate stably within a wide temperature range of -40℃ to 125℃. On-chip temperature detection can verify its reliability over this wide temperature range, ensuring normal operation even under extreme temperatures. For example, power battery packs require real-time temperature monitoring to avoid the risk of thermal runaway. To improve the monitoring accuracy of temperature characteristics by DC-DC power controller ICs, a high-precision programmable temperature detection circuit with flexibly configurable temperature detection range and accuracy is of significant practical importance for the realization of high-performance lithium battery DC-DC power controllers. Summary of the Invention

[0005] Based on existing technology, this invention provides a high-precision programmable temperature detection circuit for DC-DC power controllers, which improves the overall efficiency and accuracy of DC-DC controllers.

[0006] This utility model provides a high-precision programmable temperature detection circuit for a DC-DC power controller, comprising an operational amplifier A1, a capacitor C11, resistors R11, R12, and R13, PMOS transistors M100, M101, M102, M103, M104, M105, M106, M107, M108, and M109, PNP transistors Q101 and Q102, NMOS transistors M110, M111, M112, M113, M114, M115, M116, and M117, a resistor R140, M detection resistors, M programmable current source arrays, and M voltage comparators; where M is greater than 1. x = [2, ..., M]; Specifically, the upper end of capacitor C11, the sources of PMOS transistors M100, M101, M103, M106, M112, M114, and M116 are all connected to the power supply voltage VCC; the drain of PMOS transistor M101 is connected to the source of PMOS transistor M102, and the gate of PMOS transistor M101 is connected to the drain of PMOS transistor M102 and PMOS transistor M106. The drain of S-channel transistor M100, the upper end of resistor R11, and the gate of PMOS transistor M103 generate a bias voltage Vbp1; the gate of PMOS transistor M102 is connected to the lower end of resistor R11, the gate of PMOS transistor M104, the drain of NMOS transistor M109, and the lower end of capacitor C11, generating a bias voltage Vbp2; the positive input terminal of operational amplifier A1 is connected to the reference voltage Vr, and the negative input terminal of operational amplifier A1 is connected to the source of NMOS transistor M109 and the upper end of resistor R12; The source of PMOS transistor M105 is connected to the drain of PMOS transistor M104, the source of PMOS transistor M104 is connected to the drain of PMOS transistor M103, the source of PMOS transistor M108 is connected to the drain of PMOS transistor M107, the source of PMOS transistor M107 is connected to the drain of PMOS transistor M106, the gate of PMOS transistor M106 is connected to the bias voltage Vbp1, and the gate of PMOS transistor M107 is connected to the bias voltage Vbp2. The drain of PMOS transistor M105 is connected to the collector of PNP transistor Q101, generating a temperature sensing voltage Vt1 that is connected to the gate of NMOS transistor M110. The drain of PMOS transistor M108 is connected to the collector of PNP transistor Q102, generating a temperature sensing voltage Vt2 that is connected to the gate of NMOS transistor M111. The drain of PMOS transistor M112 is connected to the source of PMOS transistor M113. The gate of PMOS transistor M112 is connected to the drain of PMOS transistor M113, the drain of PMOS transistor M116, the upper end of resistor R13, and the gate of PMOS transistor M114. The gate of PMOS transistor M113 is connected to the lower end of resistor R13, the gate of PMOS transistor M115, and the drain of NMOS transistor M110. The source of PMOS transistor M115 is connected to the drain of PMOS transistor M114, and the drain of PMOS transistor M115 is connected to the drain of NMOS transistor M111. The generated signal Vtd is connected to the positive input terminals of the comparison signals of M voltage comparators. The input of the first programmable current source array is connected to bias voltages Vbp1 and Vbp2 and adjustment code Daj1, and outputs a current of magnitude Iaj1. Its output terminal Vrt1 is connected to the upper end of resistor R140, the source of PMOS transistor M117, and the negative input terminal of the comparison signal of voltage comparator CP1. The lower end of resistor R140 is connected to the drain of PMOS transistor M117 and the upper end of detection resistor R141. The gate of PMOS transistor M117 is connected to the comparison result output terminal of voltage comparator CP1. No. x The input terminals of the programmable current source array are connected to bias voltages Vbp1 and Vbp2 and adjustment code Daj. x The output size is Iaj x The current, its output terminal Vrt x Connect the sensing resistor R14 x Upper end and voltage comparator CP x The negative input terminal of the comparison signal; the output terminals of the comparison results of the M voltage comparators output dt1~dtM respectively; The lower end of resistor R12, the emitter of PNP transistor Q101, the base of PNP transistor Q101, the emitter of PNP transistor Q102, the base of PNP transistor Q102, the source of NMOS transistor M110, the source of NMOS transistor M111, and the lower ends of M sensing resistors R141~R14M are all connected to ground potential GND. The gates of PMOS transistors M100 and M116 are connected to the reset signal EN, and the gates of PMOS transistors M105 and M108 are connected to the reset negative signal ENN. ENN and EN are control signals with opposite high and low levels.

[0007] When EN is 0 and ENN is 1, the circuit is in a reset state; when EN is 1 and ENN is 0, the circuit is in a normal operating state.

[0008] The operational amplifier A1, capacitor C11, resistor R11, NMOS transistor M109, resistor R12, PMOS transistor M100, PMOS transistor M101, and PMOS transistor M102 constitute a common-source cascode current mirror and bias voltage generation circuit to generate bias voltages Vbp1 and Vbp2. PMOS transistors M103, M104, and M105 form a common-source, common-gate current source, with current It1 outputting from the drain of PMOS transistor M105; PMOS transistors M106, M107, and M108 form a common-source, common-gate current source, with current It2 outputting from the drain of PMOS transistor M108; the magnitudes of currents It1 and It2 are controlled by bias voltages Vbp1 and Vbp2. PMOS transistors M103, M104, M105, M106, M107, and M108, along with PNP transistors Q101 and Q102, form a differential temperature sensing circuit that outputs temperature sensing voltages Vt1 and Vt2. The device area of ​​PNP transistor Q101 is twice the device area of ​​PNP transistor Q102. K The two must be matched symmetrically on the map, and K is an integer greater than 2; NMOS transistors M110, M111, M112, M113, M114, M115, and M116 form a differential amplifier circuit for temperature sensing voltages Vt1 and Vt2. Its output voltage Vtd is simultaneously connected to the positive input terminals of the comparison signals of M voltage comparators. The PMOS transistor M117, resistor R140, M detection resistors R141~R14M, M programmable current source arrays, and M voltage comparators CP1~CPM constitute the quantization comparison circuit for voltage Vtd, obtaining M-bit temperature detection quantization codes dt1~dtM.

[0009] Specifically, each of the M programmable current source array circuits contains N sets of common-source cascode current sources, which generate output current under the control of bias voltages Vbp1, Vbp2 and N-bit adjustment codes; the external control input N-bit adjustment codes are connected to the gates of N switch-select PMOS transistors in the N sets of common-source cascode current sources to realize the adjustment of the output current magnitude.

[0010] Specifically, the magnitudes of the reference voltages Vrt1 to VrtM output from the output terminals of the M programmable current source arrays can also be fine-tuned through adjustment codes. The M reference voltages Vrt1 to VrtM are set to values ​​that match the nonlinearity of voltage Vtd, compensating for the error of the nonlinearity of voltage Vtd, so that the data of the temperature detection quantization codes dt1 to dtM are consistent with the actual temperature.

[0011] When the voltage Vtd is greater than the maximum reference voltage Vrt1, dt1 will reach a high level 1. At this time, the over-temperature protection clamp will occur, the circuit will turn off the PMOS transistor M117, and further lock the high level 1 of dt1, locking the over-temperature protection signal.

[0012] The advantages of this invention are: to reduce the nonlinearity of the temperature detection circuit, this invention designs a high-precision programmable temperature quantization comparison circuit. The magnitude of each of the M reference voltages Vrt1 to VrtM in the circuit can be finely adjusted by adjustment codes to match the nonlinearity of the temperature sensing voltage Vtd. This can compensate for the error of the nonlinearity of the temperature sensing voltage Vtd, so that the temperature detection quantization codes dt1 to dtM output by the quantization comparison circuit are consistent with the actual temperature, thus achieving high-precision temperature detection. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the high-precision programmable temperature detection circuit of this utility model.

[0014] Figure 2 This is a schematic diagram of the temperature detection voltage versus temperature change curve of this utility model.

[0015] Figure 3 This is the circuit schematic diagram of the programmable current source array of this utility model. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0017] like Figure 1The diagram shows the high-precision programmable temperature detection circuit structure of this utility model for a DC-DC power controller. The circuit includes: the upper end of capacitor C11, the source of PMOS transistors M100, M101, M103, M106, M112, M114, and M116, all connected to the power supply voltage VCC; the drain of PMOS transistor M101 is connected to the source of PMOS transistor M102, and the gate of PMOS transistor M101 is connected to... The drain of PMOS transistor M102, the drain of PMOS transistor M100, the upper end of resistor R11, and the gate of PMOS transistor M103 generate a bias voltage Vbp1. The gate of PMOS transistor M102 is connected to the lower end of resistor R11, the gate of PMOS transistor M104, the lower end of resistor R11, and also to the drain of NMOS transistor M109 and the lower end of capacitor C11, generating a bias voltage Vbp2. The positive input terminal of operational amplifier A1 is connected to the reference voltage Vr, and the negative input terminal of operational amplifier A1 is connected to the source of NMOS transistor M109 and the upper end of resistor R12.

[0018] The source of PMOS transistor M105 is connected to the drain of PMOS transistor M104, the source of PMOS transistor M104 is connected to the drain of PMOS transistor M103, the source of PMOS transistor M108 is connected to the drain of PMOS transistor M107, the source of PMOS transistor M107 is connected to the drain of PMOS transistor M106, the gate of PMOS transistor M106 is connected to the bias voltage Vbp1, and the gate of PMOS transistor M107 is connected to the bias voltage Vbp2. The drain of PMOS transistor M105 is connected to the collector of PNP transistor Q101, generating a temperature sensing voltage Vt1 that is connected to the gate of NMOS transistor M110. The drain of PMOS transistor M108 is connected to the collector of PNP transistor Q102, generating a temperature sensing voltage Vt2 that is connected to the gate of NMOS transistor M111.

[0019] The drain of PMOS transistor M112 is connected to the source of PMOS transistor M113. The gate of PMOS transistor M112 is connected to the drain of PMOS transistor M113, the drain of PMOS transistor M116, the upper end of resistor R13, and the gate of PMOS transistor M114. The gate of PMOS transistor M113 is connected to the lower end of resistor R13 and the gate of PMOS transistor M115, and is also connected to the drain of NMOS transistor M110. The source of PMOS transistor M115 is connected to the drain of PMOS transistor M114, and the drain of PMOS transistor M115 is connected to the drain of NMOS transistor M111, generating a signal Vtd. The Vtd voltage is connected to the positive input terminals of the comparison signals of M voltage comparators CP1~CPM.

[0020] The first programmable current source array generates a current of magnitude Iaj1 under the control of bias voltages Vbp1 and Vbp2 and adjustment code Daj1. Its output terminal Vrt1 is connected to the upper end of resistor R140 and the source of PMOS transistor M117, and also to the negative input terminal of comparator CP1. The lower end of resistor R140 and the drain of PMOS transistor M117 are connected to the upper end of detection resistor R141, and the gate of PMOS transistor M117 is connected to the comparison result output terminal of comparator CP1.

[0021] No. x The programmable current source array has bias voltages Vbp1, Vbp2 and adjustment code Daj. x Generate size Iaj under control x The current, its output terminal Vrt x Connected to sense resistor R14 x The upper end and comparator CP x The negative input terminal of the comparison signal; x = [2, ..., M].

[0022] The lower end of resistor R12, the emitter and base of PNP transistor Q101, the emitter and base of PNP transistor Q102, the source of NMOS transistor M110, the source of NMOS transistor M111, and the lower ends of M sensing resistors R141~R14M are all connected to ground potential GND; the gates of PMOS transistors M105 and M108 are both connected to the reset negative signal ENN, and the gates of PMOS transistors M100 and M116 are connected to the reset signal EN. The reset negative signal ENN and the reset signal EN are control signals with opposite high and low levels; the comparison results output terminals of M voltage comparators CP1~CPM are dt1~dtM.

[0023] Figure 1In the high-precision programmable temperature detection circuit of this utility model described herein, when EN is 0 and ENN is 1, the circuit is in a reset state; when EN is 1 and ENN is 0, the circuit is in a normal operating state. The operational amplifier A1, capacitor C11, resistor R11, NMOS transistor M109, resistor R12, PMOS transistors M100, M101, and M102 form a common-source cascode current mirror and bias voltage generation circuit, generating bias voltages Vbp1 and Vbp2. PMOS transistors M103, M104, and M105 form a common-source cascode current source, outputting current It1 at the drain of PMOS transistor M105. The magnitude of current It1 is controlled by bias voltages Vbp1 and Vbp2. PMOS transistors M106, M107, and M108 form a common-source cascode current source, outputting current It2 at the drain of PMOS transistor M108. The magnitude of current It2 is controlled by bias voltages Vbp1 and Vbp2.

[0024] PMOS transistors M103, M104, M105, M106, M107, and M108, along with PNP transistors Q101 and Q102, form a differential temperature sensing circuit that outputs temperature sensing voltages Vt1 and Vt2. The device area of ​​PNP transistor Q101 is twice the device area of ​​PNP transistor Q102. K The two must be matched symmetrically on the map, and K is an integer greater than 2.

[0025] The NMOS transistors M110, M111, M112, M113, M114, M115, and M116 form a differential amplifier circuit for temperature sensing voltages Vt1 and Vt2. Its output voltage Vtd also serves as the positive input of the comparison signals for M voltage comparators CP1 to CPM. The PMOS transistor M117, resistor R140, M sensing resistors R141 to R14M, the first programmable current source array to the Mth programmable current source array, and the M voltage comparators CP1 to CPM form a quantization comparison circuit for voltage Vtd, obtaining M-bit temperature detection quantization codes dt1 to dtM.

[0026] Figure 1The circuit shown starts working when EN is 1 and ENN is 0. The reference voltage Vr will output current It1 at the drain of PMOS transistor M105 and current It2 at the drain of PMOS transistor M107. In this embodiment, PMOS transistors M103 and M106 are of equal size, PMOS transistors M104 and M107 are of equal size, and PMOS transistors M105 and M108 are of equal size, so It1 = It2. The device area of ​​PNP transistor Q101 is twice the device area of ​​PNP transistor Q102. K If the temperature increases by a factor of 1, then the collector voltage Vt1 of PNP transistor Q101 and the collector voltage Vt2 of PNP transistor Q102 will exhibit different slopes as temperature changes. These differences are amplified by a differential amplifier circuit and output as a voltage Vtd that changes proportionally with temperature. This voltage Vtd is then compared with M reference voltages Vrt1 to VrtM by M voltage comparators CP1~CPM, resulting in M-bit temperature detection quantization codes dt1~dtM. Generally, the higher the temperature, the higher the voltage Vtd, and the larger the data of the M-bit temperature detection quantization codes dt1~dtM. When the voltage Vtd exceeds the maximum reference voltage Vrt1, dt1 will reach a high level (1). At this point, the high-precision programmable temperature detection circuit of this invention will issue an over-temperature protection clamp, turning off PMOS transistor M117 and further locking the high level (1) of dt1, thus locking the over-temperature protection signal.

[0027] In actual circuit implementation, various nonlinear factors are encountered. The most typical errors are component mismatch errors and the nonlinearity of PNP transistor voltage changes with temperature, resulting in nonlinearity in voltage Vtd. Figure 2 As shown, the ideal temperature curve is a straight line, while the actual temperature curve exhibits significant nonlinearity. Figure 2In this context, Vtd0 represents the ideal temperature change curve, a linear curve with a fixed slope. Taking M=10, the 10 reference voltages Vrt10~Vrt100 can be set to equally spaced values. The quantized temperature detection codes dt1~dt10 will then exhibit linear changes. However, due to various non-ideal characteristics, the actual voltage Vtd1 will become non-linear, showing a significant deviation from Vtd0. Therefore, if the 10 reference voltages Vrt10~Vrt100 are kept at equally spaced intervals, the quantized temperature detection codes dt1~dt10 will deviate significantly from the actual temperature, resulting in temperature detection errors. In this embodiment of the invention, the magnitude of each of the M reference voltages Vrt1 to VrtM can be finely adjusted using adjustment codes. Therefore, it can be matched and adjusted according to the actual temperature test conditions and the data magnitude of the temperature detection quantization codes dt1 to dt10. By setting the 10 reference voltages Vrt11 to Vrt101 to values ​​that match the nonlinearity of voltage Vtd1, the error of the nonlinearity of voltage Vtd1 can be compensated, so that the data of the temperature detection quantization codes dt1 to dt10 are consistent with the actual temperature magnitude, thereby achieving high-precision temperature detection.

[0028] Figure 3 for Figure 1 The circuit schematic of an embodiment of a single programmable current source array is shown. Each programmable current source array circuit contains N groups (N columns in the figure) of common-source cascode current sources, where N is greater than 1. A current of magnitude Iaj is generated under the control of bias voltages Vbp1 and Vbp2 and N-bit adjustment codes daj1~dajN. The magnitude of Iaj can be adjusted by adjusting the gates of N switching PMOS transistors M213~M2N3 in the N groups of common-source cascode current sources using the external control input N-bit adjustment codes.

[0029] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A high-precision programmable temperature detection circuit for DC-DC power controllers, characterized in that, This includes operational amplifier A1, capacitor C11, resistors R11, R12, R13, PMOS transistors M100, M101, M102, M103, M104, M105, M106, M107, M108, NMOS transistor M109, PNP transistors Q101, Q102, NMOS transistors M110, M111, M112, M113, M114, M115, M116, M117, resistor R140, M sense resistors, M programmable current source arrays, and M voltage comparators; M is greater than 1. x = [2, ..., M]; Specifically, the upper end of capacitor C11, the sources of PMOS transistors M100, M101, M103, M106, M112, M114, and M116 are all connected to the power supply voltage VCC; the drain of PMOS transistor M101 is connected to the source of PMOS transistor M102, and the gate of PMOS transistor M101 is connected to the drain of PMOS transistor M102 and PMOS transistor M106. The drain of S-channel transistor M100, the upper end of resistor R11, and the gate of PMOS transistor M103 generate a bias voltage Vbp1; the gate of PMOS transistor M102 is connected to the lower end of resistor R11, the gate of PMOS transistor M104, the drain of NMOS transistor M109, and the lower end of capacitor C11, generating a bias voltage Vbp2; the positive input terminal of operational amplifier A1 is connected to the reference voltage Vr, and the negative input terminal of operational amplifier A1 is connected to the source of NMOS transistor M109 and the upper end of resistor R12; The source of PMOS transistor M105 is connected to the drain of PMOS transistor M104, the source of PMOS transistor M104 is connected to the drain of PMOS transistor M103, the source of PMOS transistor M108 is connected to the drain of PMOS transistor M107, the source of PMOS transistor M107 is connected to the drain of PMOS transistor M106, the gate of PMOS transistor M106 is connected to the bias voltage Vbp1, and the gate of PMOS transistor M107 is connected to the bias voltage Vbp2. The drain of PMOS transistor M105 is connected to the collector of PNP transistor Q101, generating a temperature sensing voltage Vt1 that is connected to the gate of NMOS transistor M110. The drain of PMOS transistor M108 is connected to the collector of PNP transistor Q102, generating a temperature sensing voltage Vt2 that is connected to the gate of NMOS transistor M111. The drain of PMOS transistor M112 is connected to the source of PMOS transistor M113. The gate of PMOS transistor M112 is connected to the drain of PMOS transistor M113, the drain of PMOS transistor M116, the upper end of resistor R13, and the gate of PMOS transistor M114. The gate of PMOS transistor M113 is connected to the lower end of resistor R13, the gate of PMOS transistor M115, and the drain of NMOS transistor M110. The source of PMOS transistor M115 is connected to the drain of PMOS transistor M114, and the drain of PMOS transistor M115 is connected to the drain of NMOS transistor M111. The generated signal Vtd is connected to the positive input terminals of the comparison signals of M voltage comparators. The input of the first programmable current source array is connected to bias voltages Vbp1 and Vbp2 and adjustment code Daj1, and outputs a current of magnitude Iaj1. Its output terminal Vrt1 is connected to the upper end of resistor R140, the source of PMOS transistor M117, and the negative input terminal of the comparison signal of voltage comparator CP1. The lower end of resistor R140 is connected to the drain of PMOS transistor M117 and the upper end of detection resistor R141. The gate of PMOS transistor M117 is connected to the comparison result output terminal of voltage comparator CP1. No. x The input terminals of the programmable current source array are connected to bias voltages Vbp1 and Vbp2 and adjustment code Daj. x The output size is Iaj x The current, its output terminal Vrt x Connect the sensing resistor R14 x Upper end and voltage comparator CP x The negative input terminal of the comparison signal; the output terminals of the comparison results of the M voltage comparators output dt1~dtM respectively; The lower end of resistor R12, the emitter of PNP transistor Q101, the base of PNP transistor Q101, the emitter of PNP transistor Q102, the base of PNP transistor Q102, the source of NMOS transistor M110, the source of NMOS transistor M111, and the lower ends of M sensing resistors R141~R14M are all connected to ground potential GND. The gates of PMOS transistors M100 and M116 are connected to the reset signal EN, and the gates of PMOS transistors M105 and M108 are connected to the reset negative signal ENN. ENN and EN are control signals with opposite high and low levels.

2. The high-precision programmable temperature detection circuit for a DC-DC power controller according to claim 1, characterized in that, When EN is 0 and ENN is 1, the circuit is in a reset state; when EN is 1 and ENN is 0, the circuit is in a normal operating state.

3. The high-precision programmable temperature detection circuit for a DC-DC power controller according to claim 2, characterized in that, The operational amplifier A1, capacitor C11, resistor R11, NMOS transistor M109, resistor R12, PMOS transistor M100, PMOS transistor M101, and PMOS transistor M102 constitute a common-source cascode current mirror and bias voltage generation circuit, generating bias voltages Vbp1 and Vbp2. PMOS transistors M103, M104, and M105 form a common-source, common-gate current source, with current It1 outputting from the drain of PMOS transistor M105; PMOS transistors M106, M107, and M108 form a common-source, common-gate current source, with current It2 outputting from the drain of PMOS transistor M108; the magnitudes of currents It1 and It2 are controlled by bias voltages Vbp1 and Vbp2. PMOS transistors M103, M104, M105, M106, M107, and M108, along with PNP transistors Q101 and Q102, form a differential temperature sensing circuit that outputs temperature sensing voltages Vt1 and Vt2. The device area of ​​PNP transistor Q101 is twice the device area of ​​PNP transistor Q102. K The two must be matched symmetrically on the map, and K is an integer greater than 2; NMOS transistors M110, M111, M112, M113, M114, M115, and M116 form a differential amplifier circuit for temperature sensing voltages Vt1 and Vt2. Its output voltage Vtd is simultaneously connected to the positive input terminals of the comparison signals of M voltage comparators. The PMOS transistor M117, resistor R140, M detection resistors R141~R14M, M programmable current source arrays, and M voltage comparators CP1~CPM constitute the quantization comparison circuit for voltage Vtd, obtaining M-bit temperature detection quantization codes dt1~dtM.

4. The high-precision programmable temperature detection circuit for a DC-DC power controller according to claim 3, characterized in that, Each of the M programmable current source arrays contains N sets of common-source cascode current sources, which generate output current under the control of bias voltages Vbp1, Vbp2 and N-bit adjustment codes. The external control input N-bit adjustment codes are connected to the gates of N switch-select PMOS transistors in the N sets of common-source cascode current sources to realize the adjustment of the output current magnitude.

5. The high-precision programmable temperature detection circuit for a DC-DC power controller according to claim 4, characterized in that, The magnitudes of the reference voltages Vrt1 to VrtM output from the output terminals of the M programmable current source arrays can also be fine-tuned through adjustment codes. The M reference voltages Vrt1 to VrtM are set to values ​​that match the nonlinearity of voltage Vtd, compensating for the error of the nonlinearity of voltage Vtd, so that the data of the temperature detection quantization codes dt1 to dtM are consistent with the actual temperature.

6. The high-precision programmable temperature detection circuit for a DC-DC power controller according to claim 5, characterized in that, When the voltage Vtd is greater than the maximum reference voltage Vrt1, dt1 will reach a high level 1. At this time, the over-temperature protection clamp will occur, the circuit will turn off the PMOS transistor M117, and further lock the high level 1 of dt1, locking the over-temperature protection signal.

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