Analog-digital hybrid complex self-balancing bridge device

Abstract

The utility model aims at providing a kind of analog device defect processing implementation high-precision measurement's mixed complex self-balancing bridge device. The utility model includes analog circuit unit and FPGA digital unit, FPGA digital unit includes excitation signal source, balance signal source and processor, excitation signal source applies voltage to the resistance under test, balance signal source applies balance voltage to the resistance under test by variable resistance module, analog circuit unit includes first ADC acquisition module and second ADC acquisition module, first ADC acquisition module is connected with the resistance under test, second ADC acquisition module is connected with variable resistance module, first ADC acquisition module is connected with processor by first zero detector, second ADC acquisition module is connected with processor, processor is connected with excitation signal source control end, balance signal source control end and variable resistance module control end. The utility model is applied to the technical field of measuring device.

Description

Technical Field

[0001] This invention relates to the technical field of measuring devices, and in particular to a modular-digital hybrid complex self-balancing bridge device. Background Technology

[0002] With the development of electronic testing technology, industrial production lines have placed higher demands on the accuracy, speed, and cost of LCR measurement equipment. LCR measurement equipment is used to measure the characteristics of electronic components. Traditional LCR measurement methods mainly include the bridge method, resonance method, network analysis method, and automatic balancing bridge method. Among them, the automatic balancing bridge method dominates in industrial applications due to its wider testing range and higher accuracy.

[0003] Currently, there are two schemes for the automatic balancing bridge method: 1. Pure analog solution: relies on high-precision analog devices or automatic bridge balance adjustment. Device characteristics are easily not met, the anti-interference ability is weak, and it is easily affected by the ambient temperature. 2. Pure digital scheme: This scheme uses a microprocessor or DSP to control digital devices for balance adjustment. However, it is limited by serial processing capabilities, involves a large amount of mathematical calculation, has a slow response speed, and a large quantization error.

[0004] Although mixed-signal solutions (such as ARM-based complex bridges) that have emerged in recent years combine the advantages of analog and digital, they still have the following problems: inherent defects of analog devices: analog components (resistors, capacitors, operational amplifiers) have tolerances, temperature drift and time drift, and analog circuits may have nonlinearity, which affects the accuracy of signal processing.

[0005] If a hybrid analog-digital complex self-balancing bridge device that can handle the defects of analog devices and achieve high-precision measurement can be provided, the above-mentioned technical problems can be solved well. Utility Model Content

[0006] The technical problem to be solved by this utility model is to overcome the shortcomings of the prior art and provide a hybrid analog-digital complex self-balancing bridge device that can handle the defects of analog devices and achieve high-precision measurement.

[0007] The technical solution adopted by this utility model is as follows: This utility model includes an analog circuit unit and an FPGA digital unit. The FPGA digital unit includes an excitation signal source, a balancing signal source, and a processor. The excitation signal source applies a voltage to the resistor under test. The balancing signal source applies a balancing voltage to the resistor under test through a variable resistor module. The analog circuit unit includes a first ADC acquisition module and a second ADC acquisition module. The first ADC acquisition module is connected to the resistor under test, and the second ADC acquisition module is connected to the variable resistor module. The first ADC acquisition module is connected to the processor through a first zero detector, and the second ADC acquisition module is connected to the processor. The processor is connected to the control terminal of the excitation signal source and the control terminal of the balancing signal source.

[0008] As can be seen from the above scheme, the processor, in conjunction with the excitation signal source, generates a high-precision, adjustable frequency / phase / amplitude sinusoidal signal, which then applies a sinusoidal voltage to the resistor under test and generates a corresponding current containing real and imaginary components. The balancing signal source outputs signals from two sources with opposite phases and adjustable amplitudes to the excitation signal, with a digital-to-analog converter (DAC) simultaneously handling the in-phase and quadrature components. The unbalanced current is then acquired by the first and second ADC acquisition modules and converted into a digital signal, outputting a complex error signal of the unbalanced current. The processor of the FPGA digital unit then processes the signal to control the variable resistor module and the balancing signal source to adjust the output to bridge balance. Once the system is balanced, the digital code value output by the DAC of the balancing signal source directly represents the real part (resistance R) and imaginary part (reactance X) of the impedance Zx under test. A mixed-signal architecture based on FPGA is implemented, employing a direct digital automatic balancing bridge combined with complex signal processing. This effectively reduces measurement errors and improves measurement accuracy, achieving a high level of relative accuracy. Simultaneously, the parallel processing capabilities of the FPGA and direct digital balancing shorten the time for a single measurement, enhancing measurement efficiency. Furthermore, the overall structure of the mixed-signal complex self-balancing bridge device exhibits strong anti-interference and adaptability, meeting diverse testing requirements while facilitating cost reduction and better aligning with the practical application requirements of industrial production lines.

[0009] In a preferred embodiment, the zero detector includes two phase processing channels and an amplifier. Each phase processing channel includes a phase detector, an integrator, and a modulator connected in sequence. The input terminals of the two phase processing channels are connected to the output terminals of the ADC acquisition module, and the output terminals of the two phase processing channels are connected to the amplifier. The phase difference between the two phase processing channels is 90 degrees.

[0010] In a preferred embodiment, the modulators of both phase processing channels are connected to the output of the excitation signal source, and a phase shifter is also provided between the modulator of the phase processing channel with a phase of 90 degrees and the output of the excitation signal source.

[0011] In a preferred embodiment, the phase shifter outputs a signal with a negative 90-degree phase to the modulator of the phase processing channel.

[0012] In a preferred embodiment, a first filtering unit is provided between the excitation signal source and the resistor under test, and a second filtering unit is provided between the balanced signal source and the variable resistor module.

[0013] In a preferred embodiment, the variable resistor module includes an analog switch and several sets of reference resistors, one end of each of the reference resistors is connected to several switching ports of the analog switch, the fixed port of the analog switch is connected to the resistor under test, and the other end of each of the reference resistors is connected to the balanced signal source.

[0014] In a preferred embodiment, the second ADC acquisition module is connected to the processor via a signal processing module, which is a second zero detector or synchronizer. Attached Figure Description

[0015] Figure 1 This is a system block diagram of this utility model; Figure 2 This is a block diagram of the principle of the first zero detector. Detailed Implementation

[0016] like Figure 1As shown, in this embodiment, the present invention includes an analog circuit unit and an FPGA digital unit. The FPGA digital unit includes an excitation signal source 1, a balancing signal source 2, and a processor 3. The excitation signal source 1 applies a voltage to the resistor under test Zx. The balancing signal source 2 applies a balancing voltage to the resistor under test Zx through a variable resistor module 4. The analog circuit unit includes a first ADC acquisition module 5 and a second ADC acquisition module 6. The first ADC acquisition module 5 is connected to the resistor under test Zx, and the second ADC acquisition module 6 is connected to the variable resistor module 4. The first ADC acquisition module 5 is connected to the processor 3 through a first zero detector 7, and the second ADC acquisition module 6 is connected to the processor 3. The processor 3 is connected to the control terminals of the excitation signal source 1, the balancing signal source 2, and the variable resistor module 4. Both the excitation signal source 1 and the balancing signal source 2 are controlled by the processor 3, implemented through a direct digital frequency synthesis unit in conjunction with a digital-to-analog converter. The excitation signal source 1 generates a high-precision, adjustable frequency / phase / amplitude sinusoidal signal, applies a sinusoidal voltage U to the product under test, and generates a current i containing real and imaginary components. The balancing signal source 2, through the direct digital frequency synthesis unit and the digital-to-analog converter, constructs a "back electromotive force" equal in magnitude and opposite in phase to the voltage drop across the impedance Zx under test. Specifically, the direct digital frequency synthesis unit outputs two adjustable sinusoidal digital signals, which are then synthesized into a final balanced signal via an analog mixer circuit and output as an electromotive force in conjunction with the digital-to-analog converter. The first ADC acquisition module 5 and the second ADC acquisition module 6 of the analog circuit unit then acquire the microampere-level unbalanced current and convert it into a digital signal, outputting a complex error signal of the unbalanced current.

[0017] In this embodiment, the first zero detector 7 includes two phase processing channels and an amplifier. Each phase processing channel includes a phase detector 8, an integrator 9, and a modulator 10 connected in sequence. The input terminals of both phase processing channels are connected to the output terminal of the ADC acquisition module, and the output terminals of both phase processing channels are connected to the amplifier. The phase difference between the two phase processing channels is 90 degrees. The modulators 10 of both phase processing channels are connected to the output terminal of the excitation signal source 1. A phase shifter 11 is also provided between the modulator 10 of the phase processing channel with the 90-degree phase difference and the output terminal of the excitation signal source 1. The phase shifter 11 outputs a signal with a negative 90-degree phase to the modulator 10 of that phase processing channel.

[0018] In this embodiment, a first filtering unit 12 is provided between the excitation signal source 1 and the resistor under test Zx, and a second filtering unit 13 is provided between the balanced signal source 2 and the variable resistor module 4. Both the first filtering unit 12 and the second filtering unit 13 are low-pass filters, thereby filtering out high-frequency interference.

[0019] In this embodiment, the variable resistor module 4 includes an analog switch 14 and several sets of reference resistors Rr. One end of each reference resistor Rr is connected to a number of switching ports of the analog switch 14, and a fixed port of the analog switch 14 is connected to the resistor under test Zx. The other end of each reference resistor Rr is connected to the balanced signal source 2. The processor 3 of the FPGA digital unit switches the gain and reference resistor Rr levels according to the impedance value of the resistor under test Zx. The processor 3 controls the analog switch 14 via I / O, enabling the system to maintain high measurement accuracy across different measurement ranges and adapt to various testing requirements.

[0020] In this embodiment, the processor 3 of the FPGA digital unit also communicates with an external display through a communication port to perform human-computer interaction.

[0021] In this embodiment, the second ADC acquisition module 6 is connected to the processor 3 via a signal processing module 15, which is either a second zero detector or a synchronizer. The signal processing module 15 is used as a zero detector or for data processing and synchronization. The structure of the second zero detector is the same as that of the first zero detector 7.

[0022] The working principle of this utility model: The processor 3 of the FPGA digital unit controls the direct digital frequency synthesis unit to generate three synchronous adjustable sinusoidal digital signals. These signals are converted into analog signals by two sets of digital-to-analog converters. One of these signals is applied to the resistor under test (Zx) as the excitation signal source 1. The other two signals are synthesized by an analog mixer circuit to form a final balanced signal, which is then converted into analog signals and also applied to the resistor under test (Zx). The current flowing through the reference resistor Rr, which is turned on by the analog switch 14, is converted into a voltage signal. The unbalanced current is detected by the first zero detector 7 and sent back to the processor 3 of the FPGA digital unit. The processor 3 of the FPGA digital unit processes the signal, dynamically adjusts the amplitude and phase of the balanced signal source 2, and controls the analog switch 14 to switch ranges via I / O until the bridge is balanced. Once the system is balanced, the digital code value output by the digital-to-analog converter of the balanced signal source 2 directly represents the real part (resistance R) and the imaginary part (reactance X) of the impedance under test (Zx). Finally, the processor 3 of the FPGA digital unit interacts with the host computer through a communication interface and outputs the impedance measurement result.

[0023] The processor 3 of the FPGA digital unit performs parallel processing, calculating the real and imaginary parts of the complex impedance in real time and dynamically adjusting the output of the balanced signal source. The processor 3 of the FPGA digital unit uniformly controls the sampling, signal output, and execution of the ADC acquisition module, ensuring timing consistency and reducing phase errors. This avoids measurement deviations caused by timing asynchrony between analog and digital circuits, improving overall measurement accuracy.

[0024] Although the embodiments of this utility model are described with reference to actual solutions, they do not constitute a limitation on the meaning of this utility model. For those skilled in the art, modifications to the implementation schemes and combinations with other schemes based on this specification are obvious.

Claims

1. A mixed-signal complex self-balancing bridge device, comprising an analog circuit unit and an FPGA digital unit, characterized in that: The FPGA digital unit includes an excitation signal source (1), a balance signal source (2), and a processor (3). The excitation signal source (1) applies a voltage to the resistor under test (Zx). The balance signal source (2) applies a balance voltage to the resistor under test (Zx) through a variable resistor module (4). The analog circuit unit includes a first ADC acquisition module (5) and a second ADC acquisition module (6). The first ADC acquisition module (5) is connected to the resistor under test (Zx). The second ADC acquisition module (6) is connected to the variable resistor module (4). The first ADC acquisition module (5) is connected to the processor (3) through a first zero detector (7). The second ADC acquisition module (6) is connected to the processor (3). The processor (3) is connected to the control terminal of the excitation signal source (1), the control terminal of the balance signal source (2), and the control terminal of the variable resistor module (4).

2. The hybrid analog-digital complex self-balancing bridge device according to claim 1, characterized in that: The first zero detector (7) includes two phase processing channels and an amplifier. The phase processing channels include a phase detector (8), an integrator (9), and a modulator (10) connected in sequence. The input terminals of the two phase processing channels are connected to the output terminals of the ADC acquisition module, and the output terminals of the two phase processing channels are connected to the amplifier. The phase difference between the two phase processing channels is 90 degrees.

3. The hybrid analog-digital complex self-balancing bridge device according to claim 2, characterized in that: The modulators (10) of both phase processing channels are connected to the output of the excitation signal source (1). A phase shifter (11) is also provided between the modulator (10) of the phase processing channel with a phase of 90 degrees and the output of the excitation signal source (1).

4. The hybrid analog-digital complex self-balancing bridge device according to claim 3, characterized in that: The phase shifter (11) outputs a signal with a negative 90-degree phase to the modulator (10) of the phase processing channel.

5. The hybrid analog-digital complex self-balancing bridge device according to claim 1, characterized in that: A first filter unit (12) is provided between the excitation signal source (1) and the resistor to be measured (Zx), and a second filter unit (13) is provided between the balance signal source (2) and the variable resistor module (4).

6. The hybrid analog-digital complex self-balancing bridge device according to claim 1, characterized in that: The variable resistor module (4) includes an analog switch (14) and several sets of reference resistors (Rr). One end of each of the reference resistors (Rr) is connected to several switching ports of the analog switch (14). The fixed port of the analog switch (14) is connected to the resistor under test (Zx). The other end of each of the reference resistors (Rr) is connected to the balanced signal source (2).

7. The hybrid analog-digital complex self-balancing bridge device according to claim 1, characterized in that: The second ADC acquisition module (6) is connected to the processor (3) through the signal processing module (15), which is a second zero detector or synchronizer.

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