A zero-crossing detection and gate detection multiplexing circuit
Patent Information
- Application Number
- CN202521675763.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-07
- Publication Date
- 2026-09-15
- Estimated Expiration
- 2035-08-07
AI Technical Summary
[0004]现有的控制电路中，对于门控信号的检测和对于过零信号的检测存在以下问题：对门控信号和过零信号的检测一般都是各接一个IO口，也就是控制器上共需要通过2个IO口分别检测这两种信号，这对于IO口资源紧张的应用场景的引脚功能分配会带来问题，并且通过个IO口检测不同的信号也会造成控制器更多运算资源的消耗
[0011] Compared with the prior art, the beneficial effects of this utility model are as follows: The circuit for multiplexing zero-crossing detection and gate control detection includes a common signal detection terminal, a ground terminal, a switching power supply terminal, a detection signal output terminal, an AC power supply terminal, and a gate control branch circuit. The common signal detection terminal is electrically connected to the ground terminal through a first electronic switch and a second electronic switch. The common signal detection terminal is electrically connected to the switching power supply terminal through a first current-limiting resistor and to the detection signal output terminal through a second current-limiting resistor. The control terminal of the first electronic switch is electrically connected to the AC power supply terminal through the current-limiting branch circuit. The gate control branch circuit includes a gate control power supply terminal, a gate control switch, and a third current-limiting resistor. One end of the gate control switch is electrically connected to the gate control power supply terminal through the third current-limiting resistor, and the other end is electrically connected to the ground terminal. The control terminal of the second electronic switch is electrically connected between the gate control switch and the third current-limiting resistor. This circuit for multiplexing zero-crossing detection and gate control detection can realize the detection of zero-crossing signals and gate control signals by a single IO port, providing a feasible option for application scenarios with limited IO port resources. Furthermore, since the controller only needs one IO port to detect different signals, the consumption of the controller's computing resources is reduced.
Smart Images
Figure CN224758614U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the field of signal detection circuit technology, specifically relating to a circuit that multiplexes zero-crossing detection and gating detection. Background Technology
[0002] In control circuits, a gating signal is a signal used to control the operation of a specific system or device. That is, one signal controls the passage or blockage of another signal. For example, in the control of a speed-regulating motor, a gating signal is sent to the motor controller, and the motor controller controls the motor to start upon receiving the gating signal.
[0003] In control circuits, zero-point voltage detection is also a common functional requirement. Zero-point detection outputs a detection signal when the AC voltage is "zero". This detection signal is used to further realize other control functions. For example, in motor speed regulation, the motor controller can control the AC conduction angle from zero point through the zero-point voltage detection signal to realize the adjustment of motor speed.
[0004] In existing control circuits, the detection of gating signals and zero-crossing signals has the following problems: the detection of gating signals and zero-crossing signals is generally connected to one I / O port each, that is, the controller needs to use two I / O ports to detect these two signals respectively. This will cause problems for pin function allocation in application scenarios with limited I / O port resources, and detecting different signals through one I / O port will also cause the controller to consume more computing resources. Utility Model Content
[0005] The present invention aims to provide a circuit that multiplexes zero-crossing detection and gating detection, so as to realize the detection of zero-crossing signals and gating signals by an IO port through the circuit that multiplexes zero-crossing detection and gating detection.
[0006] To achieve the above objectives, the present invention adopts the following technical solution: A circuit that multiplexes zero-crossing detection and gating detection is provided, comprising: A common signal detection terminal and a grounding terminal are provided, wherein the common signal detection terminal is electrically connected to the grounding terminal via a first electronic switch and a second electronic switch, respectively. The common signal detection terminal is electrically connected to the switching power supply terminal through a first current-limiting resistor; A detection signal output terminal is provided, wherein the common signal detection terminal is electrically connected to the detection signal output terminal via a second current-limiting resistor. An AC power supply terminal is provided, and the control terminal of the first electronic switch is electrically connected to the AC power supply terminal via a current-limiting branch circuit. A gate control branch circuit includes a gate control power terminal, a gate control switch, and a third current-limiting resistor. One end of the gate control switch is electrically connected to the gate control power terminal through the third current-limiting resistor, and the other end is electrically connected to the ground terminal. The control terminal of the second electronic switch is electrically connected between the gate control switch and the third current-limiting resistor.
[0007] Preferably, the current-limiting branch circuit includes a diode and a fourth current-limiting resistor connected in series, with the positive terminal of the diode electrically connected to the AC power supply terminal.
[0008] Preferably, the fourth resistor is composed of two equal resistors connected in series.
[0009] Preferably, both the first electronic switch and the second electronic switch are NPN transistors.
[0010] Preferably, a bias resistor and a filter capacitor are connected in parallel between the base and emitter of the first electronic switch.
[0011] Compared with the prior art, the beneficial effects of this utility model are as follows: The circuit for multiplexing zero-crossing detection and gate control detection includes a common signal detection terminal, a ground terminal, a switching power supply terminal, a detection signal output terminal, an AC power supply terminal, and a gate control branch circuit. The common signal detection terminal is electrically connected to the ground terminal through a first electronic switch and a second electronic switch. The common signal detection terminal is electrically connected to the switching power supply terminal through a first current-limiting resistor and to the detection signal output terminal through a second current-limiting resistor. The control terminal of the first electronic switch is electrically connected to the AC power supply terminal through the current-limiting branch circuit. The gate control branch circuit includes a gate control power supply terminal, a gate control switch, and a third current-limiting resistor. One end of the gate control switch is electrically connected to the gate control power supply terminal through the third current-limiting resistor, and the other end is electrically connected to the ground terminal. The control terminal of the second electronic switch is electrically connected between the gate control switch and the third current-limiting resistor. This circuit for multiplexing zero-crossing detection and gate control detection can realize the detection of zero-crossing signals and gate control signals by a single IO port, providing a feasible option for application scenarios with limited IO port resources. Furthermore, since the controller only needs one IO port to detect different signals, the consumption of the controller's computing resources is reduced. Attached Figure Description
[0012] The accompanying drawings are provided to further illustrate the present invention and form part of the specification. They are used together with the embodiments of the present invention to explain the present invention, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a circuit schematic diagram of one embodiment of the circuit for multiplexing zero-crossing detection and gating detection of this utility model. Detailed Implementation
[0013] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0014] In one embodiment, a circuit that multiplexes zero-crossing detection and gating detection is provided, such as... Figure 1 As shown, the circuit for multiplexing zero-crossing detection and gating detection includes a common signal detection terminal A, a ground terminal GND, a switching power supply terminal (+5V DC power supply terminal), a detection signal output terminal IO1, an AC power supply terminal AC, and a gating branch circuit. Here, the common signal detection terminal A, the ground terminal GND, the switching power supply terminal, the detection signal output terminal IO1, and the AC power supply terminal AC refer to the physical terminals specifically provided in the circuit for connecting the corresponding electrical components or circuit terminals.
[0015] like Figure 1 As shown, the common signal detection terminal A is electrically connected to the ground terminal GND through the first electronic switch Q1 and the second electronic switch Q2. Both the first electronic switch Q1 and the second electronic switch Q2 are NPN transistors. The control terminal (base B) of the first electronic switch Q1 is electrically connected to the AC power supply terminal AC through a current limiting branch circuit. The current limiting branch circuit is used to protect the first electronic switch Q1. This current limiting branch circuit includes a diode D1 connected in series and a fourth current limiting resistor. The positive terminal of the diode D1 is electrically connected to the AC power supply terminal AC. The fourth resistor is composed of two equal resistors R1 and R2 connected in series, which reduces the cost of resistor usage.
[0016] A bias resistor R3 and a filter capacitor C1 are connected in parallel between the base (B) and emitter (E) of the first electronic switch Q1. The bias resistor R3 and the filter capacitor C1 are used to ensure the stability of the operation of the first electronic switch Q1.
[0017] The common signal detection terminal A is electrically connected to the switching power supply terminal (+5V DC power supply terminal) through the first current-limiting resistor R4, and is also electrically connected to the detection signal output terminal IO1 through the second current-limiting resistor R5. The switching power supply terminal provides the operating voltage source for the first electronic switch Q1 and the second electronic switch Q2. The detection signal output terminal IO1 is used to send the detected gating signal or zero-crossing signal to a microcontroller or other controller that needs to acquire the gating signal or zero-crossing signal.
[0018] The gate control branch circuit includes a gate control power supply terminal (+5V DC power supply terminal), a gate control switch SW1, and a third current-limiting resistor R6. The gate control power supply terminal can share a single terminal with the preceding switching power supply terminal, both serving to provide a +5V DC voltage source. The gate control switch SW1 can be a push-button switch. One end of SW1 is electrically connected to the gate control power supply terminal (+5V DC power supply terminal) through the third current-limiting resistor R6, and the other end is electrically connected to the ground terminal GND. The control terminal (base) of the second electronic switch Q2 is electrically connected between the gate control switch SW1 and the third current-limiting resistor R6. This gate control branch circuit provides a gate control signal; that is, when the gate control switch SW1 is closed, a gate control signal is output through the detection signal output terminal IO1, instructing the controller to perform the corresponding action.
[0019] The working principle of this circuit that multiplexes zero-crossing detection and gating detection is as follows: (1) Combination Figure 1 As shown, when the gate switch SW1 is closed, and the AC voltage source output from the AC power supply terminal is in the positive half-cycle, power is supplied to the control terminal (B-side) of transistor Q1 through diode D1, resistors R1 and R2, causing transistor Q1 to conduct. Since the gate switch SW1 is closed, the voltage at the control terminal (B-side) of transistor Q2 is pulled down to 0V, and transistor Q2 does not conduct. Therefore, the voltage at point A of the common signal detection terminal is low at this time. When the gate switch SW1 is closed, and the AC voltage source output from the AC power supply terminal is in the negative half-cycle, transistor Q1 does not conduct. Similarly, since the gate switch SW1 is closed, transistor Q2 does not conduct. Because the first current-limiting resistor R4 is connected to the +5V switching power supply terminal, the voltage at point A of the common signal detection terminal is high at this time.
[0020] In this way, the detection signal output terminal IO1 can detect the complete zero-crossing signal.
[0021] (2) For example Figure 1 As shown, when the gate switch SW1 is open, the voltage at the control terminal (B terminal) of transistor Q2 is provided with a high level by the third current limiting resistor R6, transistor Q2 is turned on, and the voltage at point A of the common signal detection terminal is pulled down to 0V. At this time, regardless of whether transistor Q1 is turned on or off, the voltage at point A of the common signal detection terminal is 0V, so the signal detected by the detection signal output terminal IO1 is always low.
[0022] In summary, when the door switch SW1 is closed, the detection signal output terminal IO port can detect a zero-crossing pulse signal; when the door switch SW1 is open, the detection signal output terminal IO port can only detect a low level. Therefore, it is possible to determine whether the door switch SW1 is open or closed.
[0023] Based on the above principles, it can be seen that the circuit that multiplexes zero-crossing detection and gating detection can detect zero-crossing signals and gating signals through a single IO port. On the one hand, this circuit provides a feasible option for application scenarios with limited IO port resources. On the other hand, since the controller only needs one IO port to detect different signals, it reduces the consumption of the controller's computing resources.
[0024] It should be noted that, unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, and terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art. It should also be understood that the above is a description of this disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of this disclosure have been described, those skilled in the art will readily understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of this invention. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims, and will not be detailed here.
Claims
1. A circuit that multiplexes zero-crossing detection and gating detection, characterized in that, include: A common signal detection terminal and a grounding terminal are provided, wherein the common signal detection terminal is electrically connected to the grounding terminal via a first electronic switch and a second electronic switch, respectively. The common signal detection terminal is electrically connected to the switching power supply terminal through a first current-limiting resistor; A detection signal output terminal is provided, wherein the common signal detection terminal is electrically connected to the detection signal output terminal via a second current-limiting resistor. An AC power supply terminal is provided, and the control terminal of the first electronic switch is electrically connected to the AC power supply terminal via a current-limiting branch circuit. A gate control branch circuit includes a gate control power terminal, a gate control switch, and a third current-limiting resistor. One end of the gate control switch is electrically connected to the gate control power terminal through the third current-limiting resistor, and the other end is electrically connected to the ground terminal. The control terminal of the second electronic switch is electrically connected between the gate control switch and the third current-limiting resistor.
2. The circuit for multiplexing zero-crossing detection and gating detection according to claim 1, characterized in that: The current-limiting branch circuit includes a diode and a fourth current-limiting resistor connected in series, with the positive terminal of the diode electrically connected to the AC power supply terminal.
3. The circuit for multiplexing zero-crossing detection and gating detection according to claim 2, characterized in that: The fourth current-limiting resistor consists of two resistors of equal value connected in series.
4. The circuit for multiplexing zero-crossing detection and gating detection according to claim 1, characterized in that: Both the first electronic switch and the second electronic switch are NPN transistors.
5. The circuit for multiplexing zero-crossing detection and gating detection according to claim 4, characterized in that: A bias resistor and a filter capacitor are connected in parallel between the base and emitter of the first electronic switch.