Packaged device

Abstract

The embodiment of the present application relates to a kind of packaging devices.The device includes: packaging substrate, packaging substrate includes waveguide structure, waveguide structure has first preset position and second preset position at upper surface interval arrangement;Waveguide structure is used to transmit optical signal between first preset position and second preset position;Optical transmission module is located in the side of packaging substrate provided with waveguide structure, and close to first preset position, and optical signal is transmitted between optical transmission module and first preset position;Optoelectronic module is located in the side of packaging substrate provided with waveguide structure, and is spaced apart from optical transmission module, and close to second preset position;Optical signal is transmitted between optoelectronic module and second preset position.Simplify the design of optoelectronic module, reduce the processing difficulty of optoelectronic module.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a packaging device. Background Technology

[0002] Typically, the network interface of a server computing system is an optoelectronic module. To connect the optical path to the optoelectronic module, waveguides need to be fabricated in the silicon substrate of the optoelectronic module, which is costly and complex. As data transmission rates increase, the requirements for optical path alignment become more stringent. The optical path alignment method of first mechanical alignment and then using adhesive curing is becoming increasingly difficult to meet the requirements. Utility Model Content

[0003] Therefore, it is necessary to provide a packaging device that can simplify the design and processing of optoelectronic modules, reduce optical noise and optical loss, reduce the difficulty of optical path alignment, and improve the accuracy of optical path alignment.

[0004] A packaged device, comprising:

[0005] A packaging substrate, the packaging substrate including a waveguide structure having a first preset position and a second preset position spaced apart on its upper surface; the waveguide structure is used to transmit optical signals between the first preset position and the second preset position;

[0006] An optical transmission module is located on the side of the packaging substrate where the waveguide structure is provided, and is close to the first preset position, and the optical signal is transmitted between the optical transmission module and the first preset position;

[0007] The optoelectronic module is located on the side of the packaging substrate where the waveguide structure is provided, and is spaced apart from the optical transmission module and close to the second preset position; the optical signal is transmitted between the optoelectronic module and the second preset position.

[0008] In one embodiment, the optical transmission module includes: a first optical transmission port, wherein the optical signal is transmitted between the first optical transmission port and a first preset position; the optoelectronic module includes a second optical transmission port, wherein the optical signal is transmitted between the second optical transmission port and a second preset position.

[0009] In one embodiment, the waveguide structure includes: a first reflecting surface and a second reflecting surface spaced apart, the first reflecting surface corresponding to a first preset position, and the second reflecting surface corresponding to a second preset position; the first reflecting surface and the second reflecting surface are used to reflect the optical signal to change the transmission direction of the optical signal in the waveguide structure.

[0010] In one embodiment, along the line connecting the optical transmission module and the optoelectronic module, and in a direction perpendicular to the packaging substrate, the cross-section of the waveguide structure is an inverted trapezoidal structure.

[0011] The first reflective surface and the second reflective surface are the waist of the inverted trapezoidal structure.

[0012] In one embodiment, the angle between the first reflective surface and the upper surface is equal to the angle between the second reflective surface and the upper surface;

[0013] Wherein, the included angle is greater than 0 degrees and less than 90 degrees.

[0014] In one embodiment, the packaging substrate further includes:

[0015] The fixing pad is located on the surface of the packaging substrate near the optical transmission module, and is used to fix the packaging substrate and the optical transmission module, and also to fix the packaging substrate and the optoelectronic module.

[0016] In one embodiment, in a plane parallel to the packaging substrate, the fixed pad corresponding to the optical transmission module surrounds the first preset position; and / or the fixed pad corresponding to the optoelectronic module surrounds the second preset position.

[0017] In one embodiment, the photoelectric module includes:

[0018] A photosensitive chip is used to receive a first optical signal output by the waveguide structure through the second preset position, and to generate a first electrical signal based on the first optical signal; and / or

[0019] A photonic device is used to generate a second optical signal based on a second electrical signal and output the second optical signal to the waveguide structure through a second preset position.

[0020] In one embodiment, the optical transmission module includes:

[0021] An optical fiber connector, connected to an optical fiber, is used to transmit the optical signal between the optical fiber and the waveguide structure.

[0022] In one embodiment, the packaging substrate further includes:

[0023] The first signal line layer is located on the surface of the packaging substrate near the optical transmission module;

[0024] The first pad is located on the side of the first signal line layer away from the waveguide structure and is electrically connected to the first signal line layer;

[0025] Packaged devices also include:

[0026] Multiple first functional devices are located on the side of the first pad away from the packaging substrate and are soldered onto the packaging substrate via corresponding first pads.

[0027] In one embodiment, the packaging substrate further includes:

[0028] A first conductive plug is located in the packaging substrate and is electrically connected to the first signal line layer, for connecting the first signal line layer to the side of the packaging substrate away from the first signal line layer.

[0029] In one embodiment, the packaging substrate further includes:

[0030] The layered structure is located on the side of the first conductive plug away from the first signal line layer; the layered structure includes conductive layers and dielectric layers alternately stacked in a direction away from the waveguide structure, and adjacent conductive layers are connected by a second conductive plug penetrating the dielectric layer; the conductive layers are electrically connected to the first conductive plug; the conductive layers are used to fan out and electrically connect to the controllable collapse chip connection bump pad in the first pad.

[0031] In one embodiment, the packaging substrate further includes:

[0032] The second pad is located on the side of the added-layer structure away from the first conductive plug; and is electrically connected to the conductor layer;

[0033] Packaged devices also include:

[0034] Multiple second functional devices are located on the side of the second pad away from the added-layer structure; they are soldered onto the packaging substrate via corresponding second pads.

[0035] In one embodiment, the packaging device further includes:

[0036] A heat dissipation module is located on the side of the optoelectronic module away from the packaging substrate;

[0037] The orthographic projection of the optoelectronic module on the packaging substrate is located within the orthographic projection of the heat dissipation module on the packaging substrate.

[0038] In one embodiment, the packaging substrate includes a glass substrate; the waveguide structure includes silver-doped glass.

[0039] A method for fabricating a packaged device, comprising:

[0040] A packaging substrate including a waveguide structure is provided; the waveguide structure has a first preset position and a second preset position spaced apart on its upper surface; the waveguide structure is used to transmit optical signals between the first preset position and the second preset position;

[0041] An optical transmission module and an optoelectronic module are formed at intervals on one side of the packaging substrate where the waveguide structure is provided; the optical transmission module is close to the first preset position, and the optical signal is transmitted between the optical transmission module and the first preset position; the optoelectronic module is close to the second preset position, and the optical signal is transmitted between the optoelectronic module and the second preset position.

[0042] In one embodiment, a packaging substrate including a waveguide structure is provided, comprising:

[0043] A mask layer is formed on a substrate, and the mask layer has an opening that exposes the substrate;

[0044] Based on the opening, the waveguide structure is formed in the substrate at the bottom of the opening to obtain the packaging substrate.

[0045] In one embodiment, the waveguide structure is formed in the substrate at the bottom of the opening, based on the opening, including:

[0046] Based on the opening, doped ions are implanted into the substrate at the bottom of the opening to form the waveguide structure.

[0047] In one embodiment, implanting doped ions into the substrate at the bottom of the opening includes:

[0048] The substrate is placed in a mixed solution containing doped ions;

[0049] A preset electric field is applied to the substrate at the bottom of the opening, causing the doped ions to enter the substrate at the bottom of the opening.

[0050] In one embodiment, along the line connecting the optical transmission module and the photoelectric module, the bottom of the opening includes a central region and edge regions located on opposite sides of the central region. A preset electric field is applied to the substrate at the bottom of the opening to allow the doped ions to enter the substrate at the bottom of the opening, including:

[0051] A preset electric field is applied to the substrate at the bottom of the opening to control the morphology of the waveguide structure formed by the doped ions on the substrate at the bottom of the opening; the depth of the first doped region formed by the doped ions in the substrate at the edge region decreases linearly from the middle region to the direction away from the middle region, and the depth of the second doped region formed by the doped ions in the substrate at the middle region is the same.

[0052] The waveguide structure includes the first doped region and the second doped region.

[0053] In one embodiment, the mask layer is made of a conductive material, and the package substrate, which includes a waveguide structure, is further comprising:

[0054] After the waveguide structure is formed, the mask layer is patterned to form the first signal line layer;

[0055] A first pad is formed on the side of the first signal line layer away from the waveguide structure; the first pad is electrically connected to the first signal line layer.

[0056] The methods for fabricating packaged devices also include:

[0057] A plurality of first functional devices are formed on the side of the first pad away from the packaging substrate; the plurality of first functional devices are soldered onto the packaging substrate through corresponding first pads;

[0058] The packaging substrate further includes the first signal line layer and the first pad.

[0059] In one embodiment, a mask layer is formed on the substrate, including:

[0060] A first through-hole is formed in the substrate;

[0061] Conductive materials are formed in the first through-hole and on the surface of the substrate, respectively. The conductive material in the first through-hole forms a first conductive plug. The first conductive plug is electrically connected to the first signal line layer.

[0062] The conductive material on the surface of the substrate is patterned to form the mask layer;

[0063] The packaging substrate further includes the first conductive plug.

[0064] In one embodiment, a packaging substrate including a waveguide structure is provided, comprising:

[0065] A first pre-defined substrate including the waveguide structure is provided;

[0066] A fixing pad is formed on the surface of the first preset substrate where the waveguide structure is provided, to obtain the packaging substrate;

[0067] An optical transmission module and an optoelectronic module are formed at intervals on one side of the packaging substrate where the waveguide structure is provided, including:

[0068] The optical transmission module and the optoelectronic module are fixedly connected to the packaging substrate by fixing pads.

[0069] In one embodiment, the optical transmission module and the optoelectronic module are fixedly connected to the packaging substrate via fixed pads, including:

[0070] The optical transmission module and the optoelectronic module are fixedly soldered onto the packaging substrate using a reflow soldering method and fixed pads.

[0071] In one embodiment, a packaging substrate including a waveguide structure is provided, comprising:

[0072] A second preset substrate is provided, including the waveguide structure, a controllable collapse chip connection bump pad, and a first conductive plug; the controllable collapse chip connection bump pad is located on the side of the second preset substrate where the waveguide structure is provided; the first conductive plug and the controllable collapse chip connection bump pad are electrically connected.

[0073] An add-in structure is formed on the side of the second preset substrate away from the waveguide structure to obtain the packaging substrate; the add-in structure includes conductive layers and dielectric layers that are alternately stacked in a direction away from the second preset substrate, and adjacent conductive layers are electrically connected through a second conductive plug that penetrates the dielectric layer; the conductive layers fan out and connect to the controllable collapse chip connection bump pad through a first conductive plug in the second preset substrate.

[0074] In one embodiment, a packaging substrate including a waveguide structure is provided, further comprising:

[0075] A second pad is formed on the side of the added layer structure away from the first conductive plug, and the second pad is electrically connected to the conductor layer;

[0076] The methods for fabricating packaged devices also include:

[0077] A plurality of second functional devices are formed on the side of the second pad away from the layered structure, and the plurality of second functional devices are soldered onto the packaging substrate through corresponding second pads.

[0078] In one embodiment, an add-on structure is formed on the side of the second preset substrate away from the waveguide structure to obtain the packaging substrate, comprising:

[0079] The top surfaces of two second preset substrates having the waveguide structure are bonded together to form a bonding substrate, wherein the top surface is the surface of the second preset substrate on the side where the waveguide structure is provided;

[0080] An additive layer process is used to form additive layer structures on opposite surfaces of the bonding substrate, wherein the additive layer structures on opposite surfaces are axially symmetrical about the bonding substrate.

[0081] The bonding substrates forming the added-layer structure are debonded to obtain two packaging substrates forming the added-layer structure.

[0082] In one embodiment, an add-on structure is formed on the side of the second preset substrate away from the waveguide structure to obtain the packaging substrate, comprising:

[0083] After each conductor layer is formed, the conductors in the conductor layer are automatically detected by optical means, and electrical tests are performed on the target area by an electrical fixture. The target area is the chip interconnect area where the conductor density is greater than a density threshold.

[0084] In one embodiment, the method for fabricating the packaged device further includes:

[0085] A heat dissipation module is formed on the side of the optoelectronic module away from the packaging substrate;

[0086] The orthographic projection of the optoelectronic module on the packaging substrate is located within the orthographic projection of the heat dissipation module on the packaging substrate.

[0087] In the above-mentioned method for fabricating the packaged device, a packaged substrate including a waveguide structure is provided. Then, an optical transmission module and an optoelectronic module are formed and spaced apart on one side of the packaged substrate where the waveguide structure is provided. The optical signal is transmitted between the optical transmission module and the optoelectronic module through the waveguide structure in the packaged substrate. It is not necessary to form a waveguide structure in the optoelectronic module, which simplifies the design of the optoelectronic module, reduces the processing difficulty of the optoelectronic module, reduces thermal noise and optical loss, and makes optical path alignment simple and easy to operate.

[0088] In the above-mentioned packaging device, the packaging substrate includes a waveguide structure. On one side of the packaging substrate with the waveguide structure, there are spaced-apart optical transmission modules and optoelectronic modules. The optical signal is transmitted between the optical transmission modules and optoelectronic modules through the waveguide structure in the packaging substrate. It is not necessary to form a waveguide structure in the optoelectronic module, which simplifies the design of the optoelectronic module, reduces the processing difficulty of the optoelectronic module, reduces thermal noise and optical loss, and makes optical path alignment simple and easy to operate. Attached Figure Description

[0089] Figure 1 This is one of the flowcharts illustrating the fabrication method of the packaged device in this disclosure.

[0090] Figure 2 This is one of the process diagrams for providing a packaging substrate including a waveguide structure in an embodiment of this disclosure;

[0091] Figure 3 This is one of the schematic cross-sectional views of the encapsulation substrate along a first direction perpendicular to the encapsulation substrate after the first conductive plug has been formed in an embodiment of this disclosure;

[0092] Figure 4This is one of the schematic cross-sectional views of the packaging substrate along a first direction perpendicular to the packaging substrate after the waveguide structure is formed in an embodiment of this disclosure;

[0093] Figure 5 This is one of the top views of the packaging substrate after the waveguide structure has been formed in an embodiment of this disclosure;

[0094] Figure 6 This is one of the process diagrams for forming a mask layer on a substrate in an embodiment of this disclosure;

[0095] Figure 7 Selected for the embodiments of this disclosure Figure 3 One of the enlarged schematic diagrams of the area within the dashed box;

[0096] Figure 8 This is one of the schematic diagrams of optical signal transmission in the waveguide structure in the embodiments of this disclosure;

[0097] Figure 9 This is the second schematic diagram of optical signal transmission in the waveguide structure in this embodiment of the present disclosure;

[0098] Figure 10 This is one of the schematic cross-sectional views of the encapsulation substrate along a first direction perpendicular to the encapsulation substrate after the formation of the first pad in this embodiment of the present disclosure;

[0099] Figure 11 As described in this embodiment of the disclosure Figure 10 One of the top views of the corresponding packaging substrate;

[0100] Figure 12 This is one of the top views of the packaged device after the first functional device is formed in an embodiment of this disclosure;

[0101] Figure 13 This is a second schematic diagram of the process of providing a packaging substrate including a waveguide structure in an embodiment of this disclosure;

[0102] Figure 14 This is the third schematic diagram of the process of providing a packaging substrate including a waveguide structure in the embodiments of this disclosure;

[0103] Figure 15 This is one of the schematic cross-sectional views of the encapsulation substrate along the first direction in a direction perpendicular to the encapsulation substrate after the second pad is formed in an embodiment of this disclosure;

[0104] Figure 16 This is one of the top views of the packaged device after the second functional device is formed in an embodiment of this disclosure;

[0105] Figure 17 This is one of the schematic cross-sectional views of the packaged device along the first direction in a direction perpendicular to the packaged substrate after the second functional device is formed in the embodiments of this disclosure;

[0106] Figure 18 This is one of the schematic cross-sectional views of the bonding substrate along a first direction in a direction perpendicular to the packaging substrate in the embodiments of this disclosure;

[0107] Figure 19 This is one of the schematic cross-sectional views of the bonding substrate along the first direction in a direction perpendicular to the packaging substrate after the layered structure is formed in an embodiment of this disclosure;

[0108] Figure 20 This is one of the process diagrams for forming an add-on structure on the side of the second preset substrate away from the waveguide structure to obtain a packaging substrate in an embodiment of this disclosure;

[0109] Figure 21 This is one of the cross-sectional views of the bonding substrate along a first direction perpendicular to the packaging substrate after the heat dissipation module has been formed in an embodiment of this disclosure.

[0110] Explanation of reference numerals in the attached figures:

[0111] Packaging substrate 100; substrate 102; mask layer 104; first conductive plug 106; waveguide structure 108; first signal line layer 110; first pad 112; fixed pad 114; second signal line layer 115; build-up structure 116; micro solder ball 117; temporary bonding adhesive 119; heat dissipation module 120; support structure 122; backplate 123; heat sink mechanical via 124; first reflective surface 1081; second reflective surface 1082; first preset position 1083; second preset position 1084; opening 202; middle region 2021; edge region 2022; first doped region 2023; second doped region 2024; conductive material 204; wire layer 206; dielectric layer 208. Detailed Implementation

[0112] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0113] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0114] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0115] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0116] It should be understood that although the terms "first," "second," etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of this application, a first pad may be referred to as a second pad, and similarly, a second pad may be referred to as a first pad.

[0117] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0118] Furthermore, in the instruction manual, the phrase "top view" refers to the diagram when viewing the target portion from above, and the phrase "sectional view" refers to the diagram when viewing a cross-section of the target portion taken by vertically cutting it from the side.

[0119] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0120] To facilitate understanding, the technical terms involved in this application will be explained first: CPU refers to Central Processing Unit, DCU refers to Deep Computing Processor, HBM refers to High Bandwidth Memory, IVR refers to Integrated Power Module, RAM refers to Random Access Memory, NAND SSD refers to Non-Volatile Hard Disk Drive, CPO refers to Co-packaged Optoelectronics, BGA refers to Ball Grid Array, MCM refers to Multi-Module Integration, Chiplet refers to Chip Packaging, PHY refers to High Speed ​​Interconnect Interface, DDR refers to Parallel Data, SerDes refers to Serial Data, CoW is an abbreviation for Chipon Wafer, referring to a module, c4 bump refers to Controlled Collapse Chip Connector Bump, PIC refers to Optical Chip, EIC refers to Electrical Chip, and TGV refers to Through-Glass Via.

[0121] Server computing systems comprise various components, including a CPU (Central Processing Unit), DCU (Depth Computing Unit), RAM (Random Access Memory), HBM (High Bandwidth Memory), NAND SSD (Non-Volatile Hard Disk Drive), IVR (Integrated Power Module), and network interfaces. These components must interconnect to form a complete system for proper operation. The network interfaces of server computing systems typically utilize optoelectronic modules. To connect the optical path to devices such as optocouplers, lasers, and modulators, which function as optoelectronic modules, waveguide structures need to be fabricated in the silicon substrate of these devices. This process is costly and complex in terms of both manufacturing and design. Furthermore, with the increasing data transmission rates, the requirements for optical path alignment are becoming increasingly stringent, and traditional mechanical alignment and adhesive-cured optical alignment methods are finding it increasingly difficult to meet these demands.

[0122] To address the aforementioned problems, this disclosure provides a method for fabricating a packaged device. Figure 1 This is one of the flowcharts illustrating the fabrication method of the packaged device in this disclosure. See also: Figure 1 In this embodiment, a method for fabricating a packaged device is provided, comprising:

[0123] S102 provides a packaging substrate including a waveguide structure.

[0124] Specifically, a packaging substrate is provided, the packaging substrate includes a waveguide structure, the waveguide structure has a first preset position and a second preset position, the first preset position and the second preset position are spaced apart on the upper surface of the waveguide structure, and the waveguide structure is used to transmit optical signals between the first preset position and the second preset position.

[0125] The packaging substrate is the carrier board in the packaged device; the size of the packaging substrate is determined based on the machine capability. For example, the size of the packaging substrate can be less than or equal to 512 mm × 512 mm. In other embodiments, the size of the packaging substrate can be determined to be other ranges based on the machine capability, and no specific limitation is made here.

[0126] The first preset position includes a first light incident position and a first light exit position, and the second preset position includes a second light incident position and a second light exit position. After the optical signal enters the waveguide structure from the first light incident position, it is transmitted in the waveguide structure and exits the waveguide structure from the second light exit position; or after the optical signal enters the waveguide structure from the second light incident position, it is transmitted in the waveguide structure and exits the waveguide structure from the first light exit position; that is, the optical signal enters the waveguide structure from one of the first preset position and the second preset position and exits the waveguide structure from the other.

[0127] A microlens is provided at at least one of the first and second preset positions. By using microlenses, the performance of the optical path for optical signal transmission can be improved, and the loss of optical signal can be reduced.

[0128] It is understood that when the optical signal enters or exits the waveguide structure from the same position within the first preset position, the first light incident position and the first light exit position are the same; when the optical signal enters or exits the waveguide structure from different positions within the first preset position, the first light incident position and the first light exit position are different. Similarly, when the optical signal enters or exits the waveguide structure from the same position within the second preset position, the second light incident position and the second light exit position are the same; when the optical signal enters or exits the waveguide structure from different positions within the second preset position, the second light incident position and the second light exit position are different. This disclosure does not limit this aspect.

[0129] S104, an optical transmission module and an optoelectronic module are formed at intervals on one side of the packaging substrate where a waveguide structure is provided.

[0130] Specifically, an optical transmission module and an optoelectronic module are formed on the side of the packaging substrate where the waveguide structure is provided, respectively. The optical transmission module and the optoelectronic module are arranged at intervals in a plane parallel to the upper surface of the waveguide structure. The optical transmission module is close to a first preset position, and the optical signal is transmitted between the optical transmission module and the first preset position. The optoelectronic module is close to a second preset position, and the optical signal is transmitted between the optoelectronic module and the second preset position.

[0131] It can be understood that after the optical signal enters the waveguide structure from the optical transmission module through the first preset position, it is transmitted to the second preset position in the waveguide structure, and then enters the optoelectronic module from the second preset position; or after the optical signal enters the waveguide structure from the optoelectronic module through the second preset position, it is transmitted to the first preset position in the waveguide structure, and then enters the optical transmission module from the first preset position; the optical transmission module and the optoelectronic module are optically interconnected through the waveguide structure in the packaging substrate.

[0132] In the above-mentioned method for fabricating the packaged device, a packaged substrate including a waveguide structure is provided. Then, an optical transmission module and an optoelectronic module are formed and spaced apart on one side of the packaged substrate where the waveguide structure is provided. The optical signal is transmitted between the optical transmission module and the optoelectronic module through the waveguide structure in the packaged substrate. It is not necessary to form a waveguide structure in the optoelectronic module, which simplifies the design of the optoelectronic module, reduces the processing difficulty of the optoelectronic module, reduces thermal noise and optical loss, and makes optical path alignment simple and easy to operate.

[0133] Figure 2 This is one of the process diagrams illustrating a packaging substrate including a waveguide structure in an embodiment of this disclosure. Figure 3 This is one of the schematic cross-sectional views of the packaging substrate along a first direction perpendicular to the packaging substrate after the first conductive plug has been formed in an embodiment of this disclosure. Figure 4 This is one of the schematic cross-sectional views of the packaging substrate along a first direction perpendicular to the packaging substrate after the waveguide structure has been formed in an embodiment of this disclosure. Figure 5 This is one of the top views of the packaging substrate after the waveguide structure has been formed in an embodiment of this disclosure. Figure 3 The X direction shown is a first direction parallel to the packaging substrate, the Y direction is a second direction perpendicular to the packaging substrate, and the Z direction is a third direction parallel to the packaging substrate. The second direction Y and the third direction Z intersect, and further, the second direction Y is perpendicular to the third direction Z.

[0134] See Figures 2-5 In some embodiments, a packaging substrate 100 including a waveguide structure 108 is provided, comprising:

[0135] S202, a mask layer is formed on the substrate, and an opening is formed in the mask layer to expose the substrate.

[0136] Specifically, a substrate 102, such as a glass substrate, is provided; a mask layer 104 is formed on the substrate 102, and an opening 202 is provided in the mask layer 104 to expose the substrate 102. The shape and position of the waveguide structure 108 in the plane (the plane containing the first direction X and the third direction Z) of the parallel packaging substrate 100 are defined by the mask layer 104.

[0137] In some embodiments, forming a mask layer 104 on a substrate 102 includes: forming a mask material on the substrate 102; performing patterning processing on the mask material to remove the mask material in a preset region 1, forming an opening 202 exposing the substrate 102, and obtaining a mask layer 104 formed by the remaining mask material, wherein the preset region 1 is the region where the waveguide structure 108 is located on the substrate 102.

[0138] Figure 6 This is one of the schematic diagrams illustrating the process of forming a mask layer on a substrate in an embodiment of this disclosure. Figure 7 Selected for the embodiments of this disclosure Figure 3One of the enlarged illustrations of the area within the dashed box, see [link / reference]. Figures 3-7 In some embodiments, a mask layer is formed on the substrate, including:

[0139] S302, a first through hole is formed in the substrate.

[0140] Specifically, a modified region is formed in the substrate 102 using a picosecond laser; the laser-treated substrate 102 is placed in a hydrofluoric acid solution and the modified region is etched away to form a first through hole penetrating the substrate 102 in the second direction Y; the modified region is the portion of the substrate 102 treated by the picosecond laser.

[0141] S304, conductive materials are formed in the first through hole and on the surface of the substrate, respectively, and the conductive material in the first through hole forms a first conductive plug.

[0142] Specifically, an electroplating process is used to form conductive material 204 in the first through-hole and on the surface of the substrate 102. The conductive material 204 fills the first through-hole, forming a first conductive plug 106 located in the first through-hole. The packaging substrate 100 also includes the first conductive plug 106, through which signal and power connections can be achieved between opposite sides of the substrate 102. By forming the first conductive plug 106 and the conductive material 204 (which subsequently serves as a mask layer) in the packaging substrate 100 simultaneously in a single electroplating process, the manufacturing process of the packaging device is simplified, and costs are reduced. As an example, the conductive material includes metallic copper.

[0143] Furthermore, prior to step S304, the method for fabricating the packaged device further includes: surface treatment of the substrate 102; wherein, the surface treatment includes flatness treatment and smoothness treatment. Surface treatment can improve the performance of the packaged device. Flatness treatment can increase the uniformity of the subsequently formed conductive material and the alignment of the optical path for optical signal transmission, avoiding interference with the connection between the optoelectronic module and the optical transmission module and the packaged substrate 100, and preventing light loss. Smoothness treatment can increase the adhesion between the subsequently formed conductive material 204 and the substrate 102, avoiding subsequent delamination. After patterning the conductive material 204 to form signal line layers (first signal line layer and second signal line layer), defects such as detachment, breakage, and uneven thickness of the wires in the signal line layers may occur.

[0144] See Figure 3 In some embodiments, a conductive material 204 is formed on the surface of the substrate 102, including forming the conductive material 204 on the opposite surface of the substrate 102. By forming the conductive material 204 on the opposite surface of the substrate 102, it is easier to subsequently form a signal line layer on the opposite surface of the substrate 102, thus simplifying the process of packaging the device.

[0145] S306, patterning the conductive material on the substrate surface to form a mask layer.

[0146] Specifically, an exposure and development process is used to form a photoresist pattern layer on the surface of the conductive material 204, the photoresist pattern layer defining the position and shape of the opening 202; the conductive material 204 exposed by the photoresist pattern layer is etched away to form a mask layer 104 composed of the remaining conductive material 204.

[0147] S204, based on the opening, a waveguide structure is formed in the substrate at the bottom of the opening to obtain the packaging substrate.

[0148] Specifically, based on the opening 202 in the mask layer 104, a waveguide structure 108 is formed in the substrate 102 at the bottom of the opening 202 to obtain the packaging substrate 100; wherein, the bottom of the waveguide structure 108 is located in the substrate 102 and is in contact with the substrate 102. Furthermore, the upper surface of the waveguide structure 108 is flush with the surface of the substrate 102 near the waveguide structure 108.

[0149] See Figure 7 It can be understood that the waveguide structure 108 includes a first reflecting surface 1081 and a second reflecting surface 1082 spaced apart; the first reflecting surface 1081 corresponds to a first preset position, and the second reflecting surface 1082 corresponds to a second preset position; the first reflecting surface 1081 and the second reflecting surface 1082 are used to reflect optical signals to change the transmission direction of the optical signals in the waveguide structure 108.

[0150] In some embodiments, a waveguide structure 108 is formed in a substrate 102 at the bottom of the opening 202, based on the opening 202. This includes implanting dopant ions into the substrate 102 at the bottom of the opening 202 to form the waveguide structure 108, thereby obtaining a packaging substrate 100. As an example, the dopant ions include silver ions. By implanting dopant ions into the substrate 102, a doped region serving as the waveguide structure 108 is formed at the bottom of the opening 202. During the transmission of the optical signal in the waveguide structure 108, the portion entering the substrate 102 can be ignored.

[0151] See Figure 7 In some embodiments, implanting doped ions into the substrate 102 at the bottom of the opening 202 includes: placing the substrate 102 in a mixed solution containing doped ions; applying a preset electric field to the substrate 102 at the bottom of the opening 202 to allow the doped ions to enter the substrate 102 at the bottom of the opening 202, thereby forming a waveguide structure 108 located in the substrate 102.

[0152] A substrate 102 with a mask layer 104 is placed in a mixed solution containing doped ions. For example, the mixed solution includes silver and sodium doped ions. A preset electric field E is applied to the substrate 102 at the bottom of the opening 202. At a preset temperature, the preset electric field E causes ion exchange between the substrate 102 at the bottom of the opening 202 and the mixed solution. Doped ions enter the substrate 102 at the bottom of the opening 202, forming a doped region that serves as a waveguide structure 108. During the ion exchange process to form the doped region, the mask layer 104 acts as a barrier layer, preventing ion diffusion from the mixed solution into the substrate 102 covered by the mask layer 104. For example, the preset temperature includes 302°C to 410°C, such as 302°C, 310°C, 350°C, 370°C, 390°C, 400°C, and 310°C.

[0153] By adjusting the preset electric field E, the morphology and doping concentration of the doped region in the substrate 102 can be adjusted, thereby achieving precise adjustment of the position and morphology of the waveguide structure 108 and reducing the light loss of the optical signal during the transmission process of the waveguide structure 108.

[0154] See Figure 7 In some embodiments, the bottom of the opening 202 includes a central region 2021 and edge regions 2022 located on opposite sides of the central region 2021. In a first direction X, the edge regions 2022 and the central region 2021 are adjacent. A preset electric field E is applied to the substrate 102 at the bottom of the opening 202 to allow doped ions to enter the substrate 102 at the bottom of the opening 202. This includes: applying the preset electric field to the substrate 102 at the bottom of the opening 202 to control the morphology of the waveguide structure 108 formed by the doped ions on the substrate 102 at the bottom of the opening 202; the depth of the first doped region 2023 formed by the doped ions in the substrate 102 of the edge region 2022 decreases linearly from the central region 2021 in a direction away from the central region 2021, and the depth of the second doped region 2024 formed by the doped ions in the substrate of the central region 2021 is the same; wherein, the waveguide structure 108 includes the first doped region 2023 and the second doped region 2024.

[0155] Specifically, a preset electric field is applied to the substrate 102 at the bottom of the opening 202. The voltage corresponding to the preset electric field applied to the middle region 2121 is the same as the preset voltage. Doped ions enter the substrate 102 in the middle region 2121 to form a second doped region 2024. The depth of the second doped region 2024 in the second direction Y is the same. The voltage corresponding to the preset electric field applied to the edge region 2022 increases sequentially from the end of the edge region 2022 away from the middle region 2021 toward the middle region 2021 to the preset voltage. Doped ions enter the substrate 102 in the edge region 2022 to form a first doped region 2023. The depth of the first doped region 2023 in the second direction Y decreases linearly from the middle region 2021 toward the direction away from the middle region 2021.

[0156] It can be understood that along the first direction X, in the second direction Y perpendicular to the packaging substrate 100, the cross-section of the waveguide structure 108 is an inverted trapezoidal structure, and the first reflecting surface 1081 and the second reflecting surface 1082 are the waist of the inverted trapezoidal structure.

[0157] Figure 8 This is one of the schematic diagrams illustrating the transmission of optical signals in a waveguide structure according to an embodiment of this disclosure. Figure 9 This is the second schematic diagram of optical signal transmission in the waveguide structure according to an embodiment of this disclosure. See also... Figure 8 and Figure 9 In some embodiments, the angle A1 between the first reflective surface 1081 and the upper surface is equal to the angle A2 between the second reflective surface 1082 and the upper surface; wherein both angle A1 and angle A2 are greater than 0 degrees and less than 90 degrees.

[0158] As an example, both angles A1 and A2 are 45 degrees. It can be understood that the first reflecting surface 1081 corresponds to the first preset position 1083, and the second reflecting surface 1082 corresponds to the second preset position 1084. The 45-degree angles A1 and A2 ensure that after the light signal is incident on the first preset position 1083 or the second preset position 1084, it is transmitted to the first reflecting surface 1081 or the second reflecting surface 1082 and then undergoes mirror reflection, thereby changing the transmission direction (light path direction) of the light signal and enabling it to transmit within the waveguide structure 108.

[0159] In some embodiments, the optoelectronic module includes a photosensitive chip; the photosensitive chip is used to receive a first optical signal output by the waveguide structure 108 through a second preset position 1084, and to generate a first electrical signal based on the first optical signal. As an example, the photosensitive chip includes a photodiode and a receiving optocoupler.

[0160] In some embodiments, the optoelectronic module includes a photonic device; the photonic device is used to generate a second optical signal according to a second electrical signal, and output the second optical signal to the waveguide structure 108 through a second preset position 1084. As an example, the photonic device includes a laser, a modulator, and a detector.

[0161] In some embodiments, the optoelectronic module includes: a photosensitive chip and a photonic device; the photosensitive chip is used to receive a first optical signal output by the waveguide structure 108 through a second preset position 1084, and generate a first electrical signal based on the first optical signal; the photonic device is used to generate a second optical signal based on the second electrical signal, and output the second optical signal to the waveguide structure 108 through the second preset position 1084; the optoelectronic module can realize the conversion between optical signals and electrical signals.

[0162] In some embodiments, the optical transmission module includes: a fiber optic connector; the fiber optic connector connects to an external optical fiber for transmitting optical signals between the optical fiber and the waveguide structure 108. The fiber optic connector can decouple the optical fiber, significantly improving flexibility.

[0163] Furthermore, both the optoelectronic module and the optical transmission module include photosensitive chips and photonic devices. A waveguide structure enables the transmission of electrical signals between the optoelectronic module and the optical transmission module within the packaged device.

[0164] As an example, see Figure 8 The optical signal from the optical transmission module is transmitted from the first preset position 1083 to the first reflective surface 1081 in the second direction Y of the vertical packaging substrate 100; after specular reflection on the first reflective surface 1081, it is transmitted along the first direction X in the waveguide structure 108 to the second reflective surface 1082; after specular reflection on the second reflective surface 1082, it is transmitted along the second direction Y in the waveguide structure 108 to the second preset position 1084, and then enters the optoelectronic module from the second preset position 1084; the optical signal from the optoelectronic module is transmitted from the second preset position 1084 to the second reflective surface 1082 in the second direction Y of the vertical packaging substrate 100; after specular reflection on the second reflective surface 1082, it is transmitted along the first direction X in the waveguide structure 108 to the first reflective surface 1081; after specular reflection on the first reflective surface 1081, it is transmitted along the second direction Y in the waveguide structure 108 to the first preset position 1083, and then enters the optical transmission module from the first preset position 1083. Figure 8 The example illustrates that the optical signal is transmitted through the waveguide structure 108 between the optical transmission module and the optoelectronic module via the same optical path. The double arrows in the diagram indicate that the optical signal can be transmitted in two opposite directions.

[0165] Specifically, the external optical signal is guided through an optical fiber into a fiber optic connector, then transmitted through the connector to a first preset position 1083, and transmitted from the first preset position 1083 to a first reflective surface 1081 at a 45-degree angle corresponding to the first preset position 1083. The optical signal is then reflected by the first reflective surface 1081 and transmitted along the first direction X to a second reflective surface 1082 at a 45-degree angle corresponding to a second preset position 1084. The optical signal is then reflected by the second reflective surface 1082 and transmitted to the second preset position 1084, from where it enters the receiving optical coupler of the optical chip. It can be understood that the laser emitted by the laser in the optical chip as an optical signal has the opposite transmission direction, which will not be elaborated upon here.

[0166] As an example, see Figure 9The optical signal from the optical transmission module is transmitted from the first preset position 1083 to the first reflecting surface 1081 in a direction with an angle B1 less than 90 degrees to the second direction Y. After specular reflection at the first reflecting surface 1081, the optical signal is transmitted through reflection between the lower and upper surfaces of the waveguide structure 108 until it reaches the second reflecting surface 1082. The lower and upper surfaces of the waveguide structure 108 are arranged opposite to each other. After specular reflection at the second reflecting surface 1082, the optical signal is transmitted from the waveguide structure 108 to the second preset position 1084 in a direction with an angle B2 less than 90 degrees to the second direction Y. The optical signal from the photoelectric module is transmitted from the second preset position 1084 to the second reflective surface 1082 in a direction with an angle B2 of less than 90 degrees to the second direction Y. After specular reflection on the second reflective surface 1082, the optical signal is transmitted through reflection between the lower and upper surfaces of the waveguide structure 108 until it reaches the first reflective surface 1081. After specular reflection on the first reflective surface 1081, the optical signal is transmitted from the waveguide structure 108 to the first preset position 1083 in a direction with an angle B1 of less than 90 degrees to the second direction Y, and then enters the optical transmission module from the first preset position 1083. Figure 9 The example illustrates that the optical signal is transmitted through the waveguide structure 108 between the optical transmission module and the optoelectronic module via the same optical path. The double arrows in the diagram indicate that the optical signal can be transmitted in two opposite directions.

[0167] Figure 10 This is one of the schematic cross-sectional views of the encapsulation substrate along a first direction perpendicular to the encapsulation substrate after the formation of the first pad in an embodiment of this disclosure. Figure 11 As described in this embodiment of the disclosure Figure 10 One of the top views of the corresponding packaging substrate. Figure 12 This is one of the top views of the packaged device after the first functional device is formed in an embodiment of this disclosure. See also: Figures 10-12In some embodiments, the mask layer 104 is made of a conductive material. Providing a packaging substrate 100 including a waveguide structure 108 further includes: after forming the waveguide structure 108, patterning the mask layer 104 to form a first signal line layer 110; wherein the first signal line layer 110 and the first conductive plug 106 are electrically connected; forming a first pad 112 on the side of the first signal line layer 110 away from the waveguide structure 108, the first pad 112 being electrically connected to the first signal line layer 110; wherein the packaging substrate 100 further includes the first signal line layer 110 and the first pad 112. The method for fabricating the packaged device further includes: forming a plurality of first functional devices on the side of the first pad 112 away from the packaging substrate 100; the plurality of first functional devices are soldered onto the packaging substrate 100 through corresponding first pads 112. As an implementation, the orthographic projection of the first pad 112 onto the substrate 102 includes a circle and / or a square.

[0168] The first functional device and the first signal line layer 110 are electrically connected through the first pad 112 in the packaging substrate 100, and the first signal line layer 110 can be connected to the side of the packaging substrate 100 away from the optoelectronic module through the first conductive plug 106.

[0169] After the waveguide structure 108 is formed, the mask layer 104 of the conductive material is patterned to form a first signal line layer 110. The first signal line layer 110 includes multiple first signal lines, including signal traces for transmitting data signals, power traces for connecting power supplies, and ground traces for connecting ground. The signal traces are electrically connected to the signal pads in the first pads 112, the power traces are electrically connected to the power pads in the first pads 112, and the ground traces are connected to the ground pads in the first pads 112. The first pads 112 include controllable collapse chip connection bump pads and ordinary pads. The multiple first pads 112 and the multiple first signal lines in the first signal line layer 110 are respectively connected.

[0170] It is understood that when the material of the mask layer 104 is not a conductive material, after the waveguide structure 108 is formed, the first signal line layer 110 is formed, including: forming a conductive material on one side of the substrate 102 where the waveguide structure 108 is formed; and patterning the conductive material to form the first signal line layer 110.

[0171] The first functional device includes the device in the target system corresponding to the packaged device, such as memory device, electronic component and chip. As an example, the first functional device includes CPU, DCU (typically the DCU chip and HBM are packaged together in 2.5D package to form CoW), EIC (Electronic Chip), 3D RAM, 3D NAND SSD, IVR, power connector; Figure 12 In this context, PIC stands for optoelectronic module, and fiber optic connector stands for optical transmission module.

[0172] The target system can be a server computing system, which includes a CPU (Central Processing Unit), DCU (Depth Computing Unit), RAM (Random Access Memory), HBM (High Bandwidth Memory), NAND SSD (Non-Volatile Hard Disk Drive), IVR (Integrated Power Module), opto-co-packaged CPO, and connectors, among other components.

[0173] In traditional technologies, key components of the target system, such as the CPU, DCU, RAM, and NAND SSD, are first packaged and then integrated onto a large motherboard. Interconnection between these components is then completed at the motherboard level to form a complete system. However, as the target signal rate and power consumption increase, this approach presents at least the following problems:

[0174] First, key components such as CPUs and DCUs require a large amount of data transmission, placing extremely high demands on data bandwidth and speed. However, high-speed signals are very sensitive to impedance discontinuities in the link. Traditional solutions require packaging for high-speed signals from CPUs, DCUs, RAM, NAND, etc. This inevitably involves a large number of vias on the packaging substrate and solder balls in the BGA (Ball Grid Array). These are impedance discontinuities in the signal link, causing a large number of reflections and resulting in high-speed signal integrity issues. At the same time, due to the high requirements for the link, the area and power consumption of the chip's high-speed interconnect interface PHY are also relatively large.

[0175] Secondly, the clock speed and computational load of key components such as CPUs and DCUs have increased significantly, and the power consumption required has increased to hundreds or even thousands of watts. The corresponding supply current has also increased significantly to hundreds or even thousands of amperes. Due to the additional packaging, the length of the power supply link has increased, which in turn has increased the DC loss on the link. According to the power formula, the power loss of the link is equal to the DC resistance multiplied by the square of the current. Therefore, the DC power loss brought by the link is proportional to the square of the current. Even if the link is only tens of milliohms or even a few milliohms, the DC loss on the link will reach tens of watts. At the same time, because the power supply module is far away from the power-consuming device, the power ripple is also large, which leads to power integrity issues.

[0176] Third, the traditional method involves packaging the chip first and then integrating it onto the motherboard. This process requires a high-temperature soldering step during packaging, and another high-temperature soldering step during integration onto the motherboard. As the integration density of CPUs and DCUs increases, their area also increases. Each high-temperature soldering step causes greater warping of the chip and package, leading to a significant increase in reliability risks and a decrease in yield.

[0177] By treating the devices in the target system as first functional devices and soldering them onto the packaging substrate 100 via the first pad 112, the packaging substrate 100 already provides interconnections for signals, power, and ground, ensuring signal and power integrity, improving the integration of the target system, increasing the data transmission speed of the target system, and reducing the power consumption of the target system. This eliminates the need for reflow soldering of chips on the motherboard, reducing the number of reflow soldering cycles, and eliminates concerns about warpage and copper core balls during chip BGA soldering, thus improving yield and reliability.

[0178] Figure 12 The example only includes two CPUs (each CPU has one IO die and one core die) and one DCU (each DCU has one DCU die and four HBMs). This is for illustrative purposes only. This application can include any number of CPUs, with no limit on the number of IO dies and core dies in each CPU, and no limit on whether they are packaged in 2D, 2.5D, or 3D, as long as the final C4 bump is provided for this application. It can also include multiple DCUs, each DCU with any number of DCU dies and any number of HBMs, and no limit on whether they are packaged in 2D, 2.5D, or 3D, as long as the final C4 bump is provided for this application. It can also add any number of conversion chips, regardless of whether they are packaged in 2D, 2.5D, or 3D, as long as the final C4 bump is provided for this application. Thus, the substrate design can be realized based on these pads.

[0179] Figure 13 This is a second schematic diagram illustrating the process of providing a packaging substrate including a waveguide structure in an embodiment of this disclosure. See also... Figure 11 , Figure 12 and Figure 13 In some embodiments, the packaging substrate including the waveguide structure includes:

[0180] S402 provides a first pre-defined substrate including a waveguide structure.

[0181] S404, a fixing pad is formed on the surface of the first preset substrate where a waveguide structure is provided, to obtain a packaging substrate.

[0182] A mask layer 104 is formed on a substrate 102, and an opening 202 is formed in the mask layer 104 to expose the substrate 102. Based on the opening 202, a waveguide structure 108 is formed in the substrate 102 at the bottom of the opening 202, and the substrate 102 with the waveguide structure 108 is used as the first preset substrate. The scheme for forming the mask layer and the waveguide structure is described in steps S202 and S204 above, and will not be repeated here. A fixing pad 114 is formed on the surface of the first preset substrate where the waveguide structure 108 is provided, to obtain a packaged substrate 100. The fixing pad 114 corresponds to the optical transmission module and the optoelectronic module respectively. The fixing pad 114 is a fixedly connected pad, and the first pad is an electrically connected pad. Figure 11 As shown, the location of the fixed pad 114 shows the micro solder ball on the fixed pad 114.

[0183] An optical transmission module and an optoelectronic module are formed at intervals on one side of the packaging substrate 100 where the waveguide structure 108 is provided. The process includes fixing the optical transmission module and the optoelectronic module to the packaging substrate 100 via fixing pads 114. Fixing the optical transmission module and the optoelectronic module to the packaging substrate 100 via the fixing pads 114 stabilizes the optical path of the optical signal transmission between the optical transmission module, the optoelectronic module, and the waveguide structure 108 in the packaging substrate 100, preventing optical path deviation.

[0184] In some embodiments, the optical transmission module and the optoelectronic module are fixedly connected to the packaging substrate 100 via the fixing pads 114, respectively. This includes using a reflow soldering method to fix the optical transmission module and the optoelectronic module onto the packaging substrate 100 via the fixing pads 114. The self-alignment function of the reflow soldering method aligns the optical path for optical signal transmission while soldering the optical transmission module and the optoelectronic module, simplifying the optical path alignment steps and improving the alignment accuracy of the optical path.

[0185] In some embodiments, the optical transmission module and the optoelectronic module are fixedly connected to the packaging substrate 100 via the fixing pads 114, respectively. This includes using thermocompression welding to fix the optical transmission module and the optoelectronic module to the packaging substrate 100 via the fixing pads 114. Welding the optical transmission module and the optoelectronic module via thermocompression welding can reduce warping of the packaging substrate 100, avoid affecting the transmission of optical signals, and improve the alignment accuracy of the optical path for optical signal transmission.

[0186] See Figure 11 In some embodiments, in a plane parallel to the packaging substrate 100, the fixing pad 114 corresponding to the optical transmission module surrounds the first preset position 1083. This fixes the optical transmission module on the packaging substrate 100 while avoiding the influence of the fixing pad 114 on the optical signal transmission.

[0187] In some embodiments, in a plane parallel to the packaging substrate 100, the fixing pad 114 corresponding to the optoelectronic module surrounds the second preset position 1084. This fixes the optoelectronic module on the packaging substrate 100 while avoiding the influence of the fixing pad 114 on the optical signal transmission.

[0188] Figure 14 This is the third schematic diagram of the process for providing a packaging substrate including a waveguide structure in this embodiment of the present disclosure. Figure 15 This is one of the schematic cross-sectional views of the encapsulation substrate along the first direction in a direction perpendicular to the encapsulation substrate after the formation of the second pad in this embodiment of the present disclosure. See also: Figure 14 and Figure 15 In some embodiments, the packaging substrate 100, which includes the waveguide structure 108, further includes:

[0189] S502 provides a second pre-defined substrate including a waveguide structure, a controllable collapse chip connection bump pad, and a first conductive plug.

[0190] Specifically, a first conductive plug 106 is formed in the substrate 102; a mask layer 104 is formed on the substrate 102, and an opening 202 is formed in the mask layer 104 to expose the substrate 102; based on the opening 202, a waveguide structure 108 is formed in the substrate 102 at the bottom of the opening 202; a controllable collapse chip connection bump pad is formed on one side of the substrate 102 where the waveguide structure 108 is formed, and the controllable collapse chip connection bump pad and the first conductive plug 106 are electrically connected; the substrate 102 with the waveguide structure 108, the controllable collapse chip connection bump pad, and the first conductive plug 106 is used as a second preset substrate; wherein, the scheme for forming the first conductive plug is described in steps S302 and S304 above, and the scheme for forming the mask layer and the waveguide structure is described in steps S202 and S204 above, and will not be repeated here. It can be understood that the controllable collapse chip connection bump pad here can be the first pad 112 in the above embodiment.

[0191] S504, an add-on structure is formed on the side of the second preset substrate away from the waveguide structure to obtain a packaging substrate.

[0192] Specifically, along the direction away from the waveguide structure 108, alternating layers of conductive wire layers 206 and dielectric layers 208 are formed on the side of the substrate 102 away from the waveguide structure 108, forming a build-up structure 116. The conductive wire layers 206 and dielectric layers 208 are alternately stacked along the second direction Y. Adjacent conductive wire layers 206 are electrically connected through second conductive plugs penetrating the dielectric layers 208. The conductive wire layers 206 fan out and are electrically connected to the controllable collapse chip connection bump pads through the first conductive plugs 106 in the substrate 102. Through the build-up structure 116, the controllable collapse chip connection bump pads are fanned out on the side of the substrate 102 away from the waveguide structure 108, facilitating the connection of functional devices on the side of the packaging substrate 100 away from the waveguide structure 108 and increasing the integration of the packaged devices.

[0193] It is understood that when a conductive material is formed on the surface of the substrate 102 away from the waveguide structure 108, step S504 includes: patterning the conductive material on the surface of the substrate 102 to form a second signal line layer 115, the second signal line layer 115 being electrically connected to the first conductive plug 106; forming an add-on structure 116 on the side of the second signal line layer 115 away from the substrate 102 to obtain a package substrate 100; wherein, the conductive layer 206 is electrically connected to the controllable collapse chip connection bump pad through the second signal line layer 115.

[0194] Figure 16 This is one of the top views of the packaged device after the second functional device is formed in an embodiment of this disclosure. Figure 17 This is one of the schematic cross-sectional views of the packaged device along the first direction in a direction perpendicular to the packaged substrate after the second functional device has been formed in the embodiments of this disclosure. See also Figures 15-17 In some embodiments, the packaging substrate 100 including the waveguide structure 108 further includes: forming a second pad on the side of the layered structure 116 away from the first conductive plug 106, the second pad being electrically connected to the conductive layer 206. The method of fabricating the packaged device further includes: forming a plurality of second functional devices on the side of the second pad away from the layered structure 116, the plurality of second functional devices being soldered onto the packaging substrate 100 via corresponding second pads. As an example, the second pad is located at... Figure 15 Between the micro solder ball 117 and the conductor layer 206, not shown in the figure.

[0195] Secondary functional devices include packaged devices corresponding to components in the target system, such as memory devices, electronic components, and chips. For example, secondary functional devices include CPUs, DCUs (typically packaged in 2.5D with HBM to form a CoW), EICs (electrical integrated circuits), 3D RAM, 3D NAND SSDs, IVRs, and capacitors.

[0196] The devices in the target system are used as second functional devices and are soldered onto the packaging substrate 100 through the second pad. The signal, power and ground interconnections have been completed in the packaging substrate 100 to ensure the integrity of the signal and power, further improve the integration of the target system, increase the data transmission speed of the target system, and reduce the power consumption of the target system.

[0197] Figure 18 This is one of the schematic cross-sectional views of the bonding substrate along a first direction in a direction perpendicular to the packaging substrate, as shown in the embodiments of this disclosure. Figure 19 This is one of the schematic cross-sectional views of the bonding substrate along a first direction perpendicular to the packaging substrate after the addition structure is formed in an embodiment of this disclosure. Figure 20 This is one of the schematic diagrams illustrating the process of forming a build-up structure on the side of the second preset substrate away from the waveguide structure to obtain a packaging substrate in this embodiment of the present disclosure. See also... Figures 18-20 In some embodiments, an add-on structure is formed on the side of the second preset substrate away from the waveguide structure to obtain a packaging substrate, including:

[0198] S602, bonding the top surfaces of two second preset substrates having waveguide structures to form a bonding substrate.

[0199] See Figure 18 Specifically, temporary bonding adhesive 119 is used to bond the top surfaces of two second preset substrates with waveguide structures 108 together to form a bonding substrate; wherein, the top surface of the second preset substrate is the surface of substrate 102 with waveguide structures 108, that is, the surfaces of two second preset substrates with waveguide structures 108 that have the same structure are bonded together, and the structure of the bonding substrate is symmetrical about the bonding surface.

[0200] S604 employs an additive layering process to form additive layer structures on the opposite surfaces of the bonding substrate, wherein the additive layer structures on the opposite surfaces are axially symmetrical about the bonding substrate.

[0201] See Figure 19 The process employs a layer-addition process, simultaneously forming alternating layers of conductive wire layer 206 and dielectric layer 208 on the top and bottom surfaces of the bonding substrate. The top and bottom surfaces of the bonding substrate are arranged opposite to each other, and the conductive wire layer 206 and dielectric layer 208 at the same positions on the top and bottom surfaces of the bonding substrate are symmetrical about the bonding surfaces.

[0202] Specifically, a semi-cured resin film is vacuum thermo-cured on the top and bottom surfaces of the bonding substrate to form a dielectric layer M11 on the top surface and a dielectric layer M21 on the bottom surface, respectively. Then, laser drilling is used to form through-holes in dielectric layers M11 and M21. The through-holes have the same shape and position in both dielectric layers M11 and M21. Finally, exposure development and electroplating processes are used to form a second conductive plug N11 located within the through-hole and a conductive layer W11 on the surface of dielectric layer M11. Simultaneously, a second conductive plug N21 located in a through-hole and a conductive layer W21 located on the surface of the dielectric layer M21 are formed in the dielectric layer M21; wherein, the second conductive plug N11 and the conductive layer W11 are integrally connected, the second conductive plug N21 and the conductive layer W21 are integrally connected, and the shapes of the conductive layers W11 and W21 are symmetrical about the bonding surface; the surfaces of the conductive layers W11 and W21 are roughened to increase the adhesion of the dielectric layer and the conductive layer; the steps of forming the dielectric layer and the conductive layer are repeated until the required number of layers are completed.

[0203] In some embodiments, a build-up structure is formed on the side of the second preset substrate away from the waveguide structure 108 to obtain a packaging substrate 100. This includes: after forming each conductive layer 206, optically automatically detecting the conductive lines in the conductive layers, and performing electrical testing on a target area using an electrical fixture. The target area is a chip interconnect region where the conductive line density is greater than a density threshold. Each conductive layer is detected during the formation of the build-up structure 116 to ensure normal open and short circuit operation, thereby ensuring yield for each layer.

[0204] S606, debond the bonding substrate that forms the add-on structure to obtain two packaging substrates that form the add-on structure.

[0205] A debonding process is used to separate two second preset substrates in the bonding substrate at the bonding surface, resulting in two packaging substrates 100 forming a build-up structure 116. A solder resist layer (typically around 10µm) is added to the surface of the packaging substrates 100 through exposure and development. Then, micro-solder balls 117 (typically around 40µm-70µm) are placed at the corresponding first and second pad positions, and the micro-solder balls 117 are soldered to the corresponding pad positions by hot pressing, maintaining a certain coplanarity (typically around 15-30µm) in different areas to facilitate the subsequent soldering of functional devices. By using temporary bonding and debonding processes, a build-up structure 116 is simultaneously formed on the back side of the two second preset substrates, improving the production efficiency of the packaging substrates 100 and reducing costs.

[0206] Figure 21 This is one of the schematic cross-sectional views of the bonding substrate along the first direction perpendicular to the packaging substrate after the heat dissipation module has been formed in the embodiments of this disclosure. See also Figure 21In some embodiments, the method for fabricating the packaged device further includes forming a heat dissipation module 120 on the side of the optoelectronic module away from the packaged substrate 100; wherein the orthographic projection of the optoelectronic module on the packaged substrate 100 lies within the orthographic projection of the heat dissipation module 120 on the packaged substrate 100. Forming the heat dissipation module 120 on the side of the optoelectronic module away from the packaged substrate 100 increases the integration of the packaged device. The optoelectronic module generates a relatively large amount of heat, which can improve the heat dissipation efficiency of the packaged device. As an example, the heat dissipation module 120 includes a heat sink. Furthermore, the side of the heat dissipation module 120 close to the optoelectronic module is in contact with the optoelectronic module, increasing the heat dissipation efficiency.

[0207] Furthermore, the heat dissipation module 120 is located on the side of the second functional device away from the packaging substrate 100, which further improves the heat dissipation efficiency of the heat dissipation module.

[0208] See Figure 21 The packaging device also includes a support structure 122 and a back plate 123; the support structure 122 is located on the periphery of the optoelectronic module, and a number of heat sink mechanical through holes 124 are provided on the support structure 122; the back plate 123 is located on the other side of the packaging substrate 100; the heat sink module 120 is fixed to the support structure 122 by fasteners, the back plate 123 and the number of heat sink mechanical through holes 124.

[0209] The support structure can be a support ring, and optionally, the material of the support structure 122 can be metal. In order to improve the integration density and reduce the area occupied by the mechanism, several heat sink mechanical through holes are opened in the support structure, so that it can simultaneously support the heat sink, lock the heat sink, and prevent warping.

[0210] In the above embodiments, the integration density is improved, the interconnection distance is shortened, the interconnection speed is increased, the interconnection power consumption is reduced, the interconnection PHY is smaller and the chip area is reduced, which is beneficial to PPA (performance power area); moreover, it realizes the innovation of semiconductor device manufacturing mode, that is, in the future, motherboard manufacturers will not need to produce motherboards, but only need to put forward configuration requirements, chip manufacturers will provide chips and substrates, and packaging plants will complete the integration.

[0211] In one alternative embodiment, the material, size, and shape of the backplate 123 may be the same as or different from the material, size, and shape of the support structure.

[0212] Among them, the mechanical via 124 of the heat sink must be kept at a certain distance from the subsequent high-speed signal traces to avoid affecting the high-speed signals.

[0213] In order to increase integration density and reduce the area occupied by the mechanism, several heat sink mechanical through holes are opened in the support structure, so that it can simultaneously support the heat sink, lock the heat sink and prevent warping; the back plate on the back of the packaging substrate can be made of metal or other materials, and its size and shape do not need to be consistent with the support structure on the front of the packaging substrate. Its main function is to lock the heat sink and prevent warping, and it does not need to provide support.

[0214] As an example, the various modules and functional devices in a packaged device can be integrated into a single package using large-scale integration technology.

[0215] For example, the large-scale integration technology involves placing a first functional device and a second functional device on opposite sides of a packaging substrate 100, including a CPU, a DCU (typically using 2.5D packaging to encapsulate the DCU chip and HBM into a CoW), an EIC (Electronic Chip), a 3D RAM, a 3D NAND SSD, an IVR, a capacitor, and a power connector. The packaging substrate 100 includes a first pad 112, a fixed pad 114, a first signal line, a first conductive plug 106, a conductor layer 206, a second signal line, and a second pad. The first pad 112 is electrically connected to the first signal line, the first conductive plug 106 is electrically connected to the conductor layer 206, and the second pad is electrically connected to the second signal line. The first signal line and the second signal line are sequentially electrically connected through the first conductive plug 106 and the conductor layer 206. The first functional device is soldered to the packaging substrate 100 through the first pad 112 or the fixed pad 114, and the second functional device is soldered to the packaging substrate 100 through the second pad.

[0216] The first functional device is electrically connected to the first pad 112 in the packaging substrate 100. Two first functional devices are interconnected via the first pad 112 and a first signal line, enabling high-speed signal transmission between them. The second functional device is electrically connected to the first pad in the packaging substrate 100. Two second functional devices are interconnected via a second pad and a second signal line, enabling high-speed signal transmission between them. The first and second functional devices are interconnected via the first pad 112, a first signal line, a first conductive plug 106, a conductor layer 206, a second signal line, and a second pad, enabling high-speed signal transmission between them.

[0217] It should be understood that, although Figure 1 , Figure 2 , Figure 6 , Figure 13 , Figure 14 and Figure 20The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 , Figure 2 , Figure 6 , Figure 13 , Figure 14 and Figure 20 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0218] Based on the same inventive concept, this application also provides a packaging device. The solution to the problem provided by the packaging device is similar to the solution described in the above-described packaging device preparation method. The parts that are the same as or corresponding to the embodiments in the above-described packaging device preparation method will not be described in detail below.

[0219] See Figure 17 In this embodiment, a packaging device is provided, including: a packaging substrate 100, an optical transmission module, and an optoelectronic module.

[0220] The packaging substrate 100 includes a waveguide structure 108, which has a first preset position 1083 and a second preset position 1084 spaced apart on its upper surface; the waveguide structure 108 is used to transmit optical signals between the first preset position 1083 and the second preset position 1084.

[0221] The optical transmission module is located on the side of the packaging substrate 100 where the waveguide structure 108 is provided, and is close to the first preset position 1083. The optical signal is transmitted between the optical transmission module and the first preset position 1083.

[0222] The optoelectronic module is located on the side of the packaging substrate 100 where the waveguide structure 108 is provided, and is spaced apart from the optical transmission module and close to the second preset position 1084; the optical signal is transmitted between the optoelectronic module and the second preset position 1084.

[0223] In the above-mentioned packaging device, the packaging substrate includes a waveguide structure. On one side of the packaging substrate with the waveguide structure, there are spaced-apart optical transmission modules and optoelectronic modules. The optical signal is transmitted between the optical transmission modules and optoelectronic modules through the waveguide structure in the packaging substrate. It is not necessary to form a waveguide structure in the optoelectronic module, which simplifies the design of the optoelectronic module, reduces the processing difficulty of the optoelectronic module, reduces thermal noise and optical loss, and makes optical path alignment simple and easy to operate.

[0224] In some embodiments, the optical transmission module includes: a first optical transmission port, wherein an optical signal is transmitted between the first optical transmission port and a first preset position 1083; the optoelectronic module includes a second optical transmission port, wherein an optical signal is transmitted between the second optical transmission port and a second preset position 1084.

[0225] Referring to 4, in some embodiments, the waveguide structure 108 includes: a first reflecting surface 1081 and a second reflecting surface 1082 spaced apart; the first reflecting surface 1081 corresponds to a first preset position 1083, and the second reflecting surface 1082 corresponds to a second preset position 1084; the first reflecting surface 1081 and the second reflecting surface 1082 are used to reflect optical signals to change the transmission direction of the optical signals in the waveguide structure 108.

[0226] See Figure 4 In some embodiments, the waveguide structure 108 has an inverted trapezoidal cross-section along the line connecting the optical transmission module and the optoelectronic module (first direction X) and in the direction perpendicular to the packaging substrate 100 (second direction Y); wherein the first reflecting surface 1081 and the second reflecting surface 1082 are the waist of the inverted trapezoidal structure.

[0227] In some embodiments, the angle A1 between the first reflective surface 1081 and the upper surface is equal to the angle A2 between the second reflective surface 1082 and the upper surface; wherein both angle A1 and angle A2 are greater than 0 degrees and less than 90 degrees.

[0228] As an example, both angles A1 and A2 are 45 degrees. It can be understood that the first reflecting surface 1081 corresponds to the first preset position 1083, and the second reflecting surface 1082 corresponds to the second preset position 1084. The 45-degree angles A1 and A2 ensure that after the light signal is incident on the first preset position 1083 or the second preset position 1084, it is transmitted to the first reflecting surface 1081 or the second reflecting surface 1082 and then undergoes mirror reflection, thereby changing the transmission direction (light path direction) of the light signal and allowing it to be transmitted within the waveguide structure 108.

[0229] In some embodiments, the optoelectronic module includes a photosensitive chip; the photosensitive chip is used to receive a first optical signal output by the waveguide structure 108 through a second preset position 1084, and to generate a first electrical signal based on the first optical signal. As an example, the photosensitive chip includes a photodiode and a receiving optocoupler.

[0230] In some embodiments, the optoelectronic module includes a photonic device; the photonic device is used to generate a second optical signal according to a second electrical signal, and output the second optical signal to the waveguide structure 108 through a second preset position 1084. As an example, the photonic device includes a laser, a modulator, and a detector.

[0231] In some embodiments, the optoelectronic module includes: an optical transmission module including: an optical fiber connector; the optical fiber connector is connected to an external optical fiber for transmitting optical signals between the optical fiber and the waveguide structure 108.

[0232] As an example, see Figure 8 The optical signal from the optical transmission module is transmitted from the first preset position 1083 to the first reflective surface 1081 in the second direction Y of the vertical packaging substrate 100; after specular reflection on the first reflective surface 1081, it is transmitted along the first direction X in the waveguide structure 108 to the second reflective surface 1082; after specular reflection on the second reflective surface 1082, it is transmitted along the second direction Y in the waveguide structure 108 to the second preset position 1084, and then enters the optoelectronic module from the second preset position 1084; the optical signal from the optoelectronic module is transmitted from the second preset position 1084 to the second reflective surface 1082 in the second direction Y of the vertical packaging substrate 100; after specular reflection on the second reflective surface 1082, it is transmitted along the first direction X in the waveguide structure 108 to the first reflective surface 1081; after specular reflection on the first reflective surface 1081, it is transmitted along the second direction Y in the waveguide structure 108 to the first preset position 1083, and then enters the optical transmission module from the first preset position 1083. Figure 8 The example illustrates that the optical signal is transmitted through the waveguide structure 108 between the optical transmission module and the optoelectronic module via the same optical path. The double arrows in the diagram indicate that the optical signal can be transmitted in two opposite directions.

[0233] Specifically, the external optical signal is guided through an optical fiber into a fiber optic connector, then transmitted through the connector to a first preset position 1083, and transmitted from the first preset position 1083 to a first reflective surface 1081 at a 45-degree angle corresponding to the first preset position 1083. The optical signal is then reflected by the first reflective surface 1081 and transmitted along the first direction X to a second reflective surface 1082 at a 45-degree angle corresponding to a second preset position 1084. The optical signal is then reflected by the second reflective surface 1082 and transmitted to the second preset position 1084, from where it enters the receiving optical coupler of the optical chip. It can be understood that the laser emitted by the laser in the optical chip as an optical signal has the opposite transmission direction, which will not be elaborated upon here.

[0234] As an example, see Figure 9The optical signal from the optical transmission module is transmitted from the first preset position 1083 to the first reflecting surface 1081 in a direction with an angle B1 less than 90 degrees to the second direction Y. After specular reflection at the first reflecting surface 1081, the optical signal is transmitted through reflection between the lower and upper surfaces of the waveguide structure 108 until it reaches the second reflecting surface 1082. The lower and upper surfaces of the waveguide structure 108 are arranged opposite to each other. After specular reflection at the second reflecting surface 1082, the optical signal is transmitted from the waveguide structure 108 to the second preset position 1084 in a direction with an angle B2 less than 90 degrees to the second direction Y. The optical signal from the photoelectric module is transmitted from the second preset position 1084 to the second reflective surface 1082 in a direction with an angle B2 of less than 90 degrees to the second direction Y. After specular reflection on the second reflective surface 1082, the optical signal is transmitted through reflection between the lower and upper surfaces of the waveguide structure 108 until it reaches the first reflective surface 1081. After specular reflection on the first reflective surface 1081, the optical signal is transmitted from the waveguide structure 108 to the first preset position 1083 in a direction with an angle B1 of less than 90 degrees to the second direction Y, and then enters the optical transmission module from the first preset position 1083. Figure 9 The example illustrates that the optical signal is transmitted through the waveguide structure 108 between the optical transmission module and the optoelectronic module via the same optical path. The double arrows in the diagram indicate that the optical signal can be transmitted in two opposite directions.

[0235] See Figure 11 In some embodiments, the packaging substrate further includes a fixing pad 114. The fixing pad 114 is located on the surface of the packaging substrate 100 near the optical transmission module, and is used to fix the packaging substrate 100 and the optical transmission module, and also to fix the packaging substrate 100 and the optoelectronic module. The fixing pad 114 is a fixing pad for fixed connection, and the fixed connection between the optoelectronic module, the optical transmission module and the packaging substrate 100 is realized through the fixing pad 114.

[0236] See Figure 11 In some embodiments, in a plane parallel to the packaging substrate 100, the fixing pad 114 corresponding to the optical transmission module surrounds the first preset position 1083. This fixes the optical transmission module on the packaging substrate 100 while avoiding the influence of the fixing pad 114 on the optical signal transmission.

[0237] In some embodiments, in a plane parallel to the packaging substrate 100, the fixing pad 114 corresponding to the optoelectronic module surrounds the second preset position 1084. This fixes the optoelectronic module on the packaging substrate 100 while avoiding the influence of the fixing pad 114 on the optical signal transmission.

[0238] See Figures 10-12In some embodiments, the packaging substrate 100 further includes a first signal line layer 110 and a first pad 112. The first signal line layer 110 is located on the surface of the packaging substrate 100 near the optical transmission module; the first pad 112 is located on the side of the first signal line layer 110 away from the waveguide structure 108 and is electrically connected to the first signal line layer 110; the packaged device further includes a plurality of first functional devices located on the side of the first pad 112 away from the packaging substrate 100, and soldered to the packaging substrate 100 through corresponding first pads 112. The first functional devices and the first signal line layer 110 are electrically connected through the first pads 112 in the packaging substrate 100.

[0239] The first functional device includes the packaged device corresponding to the device in the target system, such as memory device, electronic component and chip. As an example, the first functional device includes CPU, DCU (typically the DCU chip and HBM are packaged together in 2.5D package to form CoW), EIC (Electronic Chip), 3D RAM, 3D NAND SSD, IVR, and power connector.

[0240] The target system can be a server computing system, which includes a CPU (Central Processing Unit), DCU (Depth Computing Unit), RAM (Random Access Memory), HBM (High Bandwidth Memory), NAND SSD (Non-Volatile Hard Disk Drive), IVR (Integrated Power Module), opto-co-packaged CPO, and connectors, among other components.

[0241] In traditional technologies, key components of the target system, such as the CPU, DCU, RAM, and NAND SSD, are first packaged and then integrated onto a large motherboard. Interconnection between these components is then completed at the motherboard level to form a complete system. However, as the target signal rate and power consumption increase, this approach presents at least the following problems:

[0242] First, key components such as CPUs and DCUs require a large amount of data transmission, placing extremely high demands on data bandwidth and speed. However, high-speed signals are very sensitive to impedance discontinuities in the link. Traditional solutions require packaging for high-speed signals from CPUs, DCUs, RAM, NAND, etc. This inevitably involves a large number of vias on the packaging substrate and solder balls in the BGA (Ball Grid Array). These are impedance discontinuities in the signal link, causing a large number of reflections and resulting in high-speed signal integrity issues. At the same time, due to the high requirements for the link, the area and power consumption of the chip's high-speed interconnect interface PHY are also relatively large.

[0243] Secondly, the clock speed and computational load of key components such as CPUs and DCUs have increased significantly, and the power consumption required has increased to hundreds or even thousands of watts. The corresponding supply current has also increased significantly to hundreds or even thousands of amperes. Due to the additional packaging, the length of the power supply link has increased, which in turn has increased the DC loss on the link. According to the power formula, the power loss of the link is equal to the DC resistance multiplied by the square of the current. Therefore, the DC power loss brought by the link is proportional to the square of the current. Even if the link is only tens of milliohms or even a few milliohms, the DC loss on the link will reach tens of watts. At the same time, because the power supply module is far away from the power-consuming device, the power ripple is also large, which leads to power integrity issues.

[0244] Third, the traditional method involves packaging the chip first and then integrating it onto the motherboard. This process requires a high-temperature soldering step during packaging, and another high-temperature soldering step during integration onto the motherboard. As the integration density of CPUs and DCUs increases, their area also increases. Each high-temperature soldering step causes greater warping of the chip and package, leading to a significant increase in reliability risks and a decrease in yield.

[0245] By treating the devices in the target system as first functional devices and soldering them onto the packaging substrate 100 via the first pad 112, the packaging substrate 100 already provides interconnections for signals, power, and ground, ensuring signal and power integrity, improving the integration of the target system, increasing the data transmission speed of the target system, and reducing the power consumption of the target system. This eliminates the need for reflow soldering of chips on the motherboard, reducing the number of reflow soldering cycles, and eliminates concerns about warpage and copper core balls during chip BGA soldering, thus improving yield and reliability.

[0246] See Figures 10-12 In some embodiments, the packaging substrate 100 further includes a first conductive plug 106; the first conductive plug 106 is located in the packaging substrate 100 and is electrically connected to the first signal line layer 110, for connecting the first signal line layer 110 to the side of the packaging substrate 100 away from the first signal line layer 100.

[0247] See Figure 15In some embodiments, the packaging substrate further includes: a layer-addition structure 116; the layer-addition structure 116 is located on the side of the first conductive plug 106 away from the first signal line layer 110; the layer-addition structure 116 includes conductive layers 206 and dielectric layers 208 alternately stacked along a direction away from the waveguide structure 108, adjacent conductive layers 206 are connected by a second conductive plug penetrating the dielectric layer 208; the conductive layers 206 are electrically connected to the first conductive plug 106; the conductive layers 206 are used for fan-out and electrical connection of the controllable collapse chip connection bump pad in the first pad 112. Through the layer-addition structure 116, the controllable collapse chip connection bump pad is fanned out on the side of the substrate 102 away from the waveguide structure 108, facilitating the connection of functional devices on the side of the packaging substrate 100 away from the waveguide structure 108, and increasing the integration of the packaged devices.

[0248] See Figure 15 In some embodiments, the packaging substrate 100 further includes: a second pad; the second pad is located on the side of the build-up structure 116 away from the first conductive plug 106; and is electrically connected to the conductive layer 206. The packaged device further includes: a plurality of second functional devices located on the side of the second pad away from the build-up structure 116; the second functional devices are soldered onto the packaging substrate 100 via corresponding second pads.

[0249] Secondary functional devices include packaged devices corresponding to components in the target system, such as memory devices, electronic components, and chips. For example, secondary functional devices include CPUs, DCUs (typically packaged in 2.5D with HBM to form a CoW), EICs (electrical integrated circuits), 3D RAM, 3D NAND SSDs, IVRs, and capacitors.

[0250] The devices in the target system are used as second functional devices and are soldered onto the packaging substrate 100 through the second pad. The signal, power and ground interconnections have been completed in the packaging substrate 100 to ensure the integrity of the signal and power, further improve the integration of the target system, increase the data transmission speed of the target system, and reduce the power consumption of the target system.

[0251] See Figure 21 In some embodiments, the packaging device further includes a heat dissipation module 120; the heat dissipation module 120 is located on the side of the optoelectronic module away from the packaging substrate 100; wherein the orthographic projection of the optoelectronic module on the packaging substrate 100 lies within the orthographic projection of the heat dissipation module 120 on the packaging substrate 100. Forming the heat dissipation module 120 on the side of the optoelectronic module away from the packaging substrate 100 increases the integration of the packaging device. Since the optoelectronic module generates a relatively large amount of heat, this increases the heat dissipation efficiency of the packaging device. As an example, the heat dissipation module includes a heat sink. Furthermore, the side of the heat dissipation module 120 close to the optoelectronic module contacts the optoelectronic module, increasing heat dissipation efficiency and alleviating heat dissipation pressure.

[0252] In some embodiments, the packaging substrate 100 includes a glass substrate; the waveguide structure 108 includes silver-doped glass. The entire optical path for optical signal transmission is implemented on the glass substrate, avoiding light loss due to thermal expansion. Furthermore, glass has characteristics such as low warpage and high flatness, meeting the requirements for surface flatness and high uniformity in optical signal connections. Simultaneously, using a glass substrate, whose coefficient of thermal expansion is close to that of silicon, significantly reduces warpage. This greatly simplifies the assembly process.

[0253] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0254] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A packaged device, characterized in that, include: A packaging substrate, the packaging substrate including a waveguide structure, the waveguide structure having a first preset position and a second preset position spaced apart on its upper surface; The waveguide structure is used to transmit optical signals between the first preset position and the second preset position; An optical transmission module is located on the side of the packaging substrate where the waveguide structure is provided, and is close to the first preset position, and the optical signal is transmitted between the optical transmission module and the first preset position; The optoelectronic module is located on the side of the packaging substrate where the waveguide structure is provided, and is spaced apart from the optical transmission module and close to the second preset position; the optical signal is transmitted between the optoelectronic module and the second preset position.

2. The packaged device according to claim 1, characterized in that, The optical transmission module includes: a first optical transmission port, wherein the optical signal is transmitted between the first optical transmission port and the first preset position; the photoelectric module includes a second optical transmission port, wherein the optical signal is transmitted between the second optical transmission port and the second preset position.

3. The packaged device according to claim 1, characterized in that, The waveguide structure includes: a first reflecting surface and a second reflecting surface spaced apart, the first reflecting surface corresponding to a first preset position, and the second reflecting surface corresponding to a second preset position; the first reflecting surface and the second reflecting surface are used to reflect the optical signal to change the transmission direction of the optical signal in the waveguide structure.

4. The packaging device according to claim 3, characterized in that, Along the line connecting the optical transmission module and the optoelectronic module, and in a direction perpendicular to the packaging substrate, the cross-section of the waveguide structure is an inverted trapezoidal structure. The first reflective surface and the second reflective surface are the waist of the inverted trapezoidal structure.

5. The packaging device according to claim 4, characterized in that, The angle between the first reflective surface and the upper surface is equal to the angle between the second reflective surface and the upper surface; Wherein, the included angle is greater than 0 degrees and less than 90 degrees.

6. The packaged device according to claim 1, characterized in that, The packaging substrate further includes: The fixing pad is located on the surface of the packaging substrate near the optical transmission module, and is used to fix the packaging substrate and the optical transmission module, and also to fix the packaging substrate and the optoelectronic module.

7. The packaging device according to claim 6, characterized in that, In a plane parallel to the packaging substrate, the fixed pad corresponding to the optical transmission module surrounds the first preset position; and / or the fixed pad corresponding to the optoelectronic module surrounds the second preset position.

8. The packaged device according to claim 1, characterized in that, The photoelectric module includes: A photosensitive chip is used to receive a first optical signal output by the waveguide structure through the second preset position, and to generate a first electrical signal based on the first optical signal; and / or A photonic device is used to generate a second optical signal based on a second electrical signal and output the second optical signal to the waveguide structure through a second preset position.

9. The packaged device according to claim 1, characterized in that, The optical transmission module includes: An optical fiber connector, connected to an optical fiber, is used to transmit the optical signal between the optical fiber and the waveguide structure.

10. The packaged device according to claim 1, characterized in that, The packaging substrate further includes: The first signal line layer is located on the surface of the packaging substrate near the optical transmission module; The first pad is located on the side of the first signal line layer away from the waveguide structure and is electrically connected to the first signal line layer; The packaging device further includes: Multiple first functional devices are located on the side of the first pad away from the packaging substrate and are soldered onto the packaging substrate via corresponding first pads.

11. The packaged device according to claim 10, characterized in that, The packaging substrate further includes: A first conductive plug is located in the packaging substrate and is electrically connected to the first signal line layer, for connecting the first signal line layer to the side of the packaging substrate away from the first signal line layer.

12. The packaged device according to claim 11, characterized in that, The packaging substrate further includes: The layered structure is located on the side of the first conductive plug away from the first signal line layer; the layered structure includes conductive layers and dielectric layers alternately stacked in a direction away from the waveguide structure, and adjacent conductive layers are connected by a second conductive plug penetrating the dielectric layer; the conductive layers are electrically connected to the first conductive plug; the conductive layers are used to fan out and electrically connect to the controllable collapse chip connection bump pad in the first pad.

13. The packaged device according to claim 12, characterized in that, The packaging substrate further includes: The second pad is located on the side of the added-layer structure away from the first conductive plug; and is electrically connected to the conductor layer; The packaging device further includes: Multiple second functional devices are located on the side of the second pad away from the added-layer structure; they are soldered onto the packaging substrate via corresponding second pads.

14. The packaged device according to claim 1, characterized in that, The packaging device further includes: A heat dissipation module is located on the side of the optoelectronic module away from the packaging substrate; The orthographic projection of the optoelectronic module on the packaging substrate is located within the orthographic projection of the heat dissipation module on the packaging substrate.

15. The packaged device according to claim 1, characterized in that, The packaging substrate includes a glass substrate; the waveguide structure includes silver-doped glass.

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