A switch-on / off control circuit with adjustable time length

Abstract

The utility model discloses a switch control circuit of adjustable time length, including switch control module and PMOS switch circuit, and switch control module includes button circuit, RC charge -discharge circuit and D flip -flop circuit, and the input of button circuit is connected power supply input Vin, and the output of button circuit is connected RC charge -discharge circuit's input and D flip -flop circuit's first input, and the output of RC charge -discharge circuit is connected D flip -flop circuit's second input, and the output of D flip -flop circuit is connected PMOS switch circuit's first input, and the output of PMOS switch circuit is connected D flip -flop circuit's third input and the input of the system circuit of being controlled, and the second input of PMOS switch circuit is connected power supply input Vin. The utility model discloses through pure hardware realizes long press switch control circuit, need not software to participate, and long press time can be according to the design demand flexible configuration, and the shutdown power consumption is extremely low.

Description

Technical Field

[0001] This utility model relates to the field of power on / off circuit technology, and in particular to a power on / off control circuit with adjustable duration. Background Technology

[0002] Currently, commonly used long-press power on / off circuits mainly include two solutions: using dedicated long-press power on / off chips and controlling power on / off via an MCU. When using dedicated long-press power on / off chips, the fixed long-press duration prevents designers from flexibly configuring it according to product requirements; furthermore, the available chip models are limited, and incompatibility between different chip models introduces proprietary risks. In addition, controlling power on / off via an MCU requires at least two MCU I / O ports (one for real-time button status monitoring and one for power enable); power on / off also requires software monitoring and control; and when power is off, the relevant MCU functional modules need to remain operational, resulting in power consumption issues during shutdown.

[0003] Therefore, a new solution is needed. Utility Model Content

[0004] The purpose of this invention is to provide a power on / off control circuit with adjustable duration.

[0005] To achieve the above objectives, this utility model provides a time-adjustable power-on / off control circuit connected between the power supply input Vin and the controlled system circuit. It includes a power-on / off control module and a PMOS switch circuit. The input terminals of the power-on / off control module and the PMOS switch circuit are connected to the power supply input Vin. The output terminal of the power-on / off control module is connected to the control terminal of the PMOS switch circuit. The output terminal of the PMOS switch circuit is connected to the input terminal of the controlled system circuit and the control terminal of the power-on / off control module. The power-on / off control module includes a button circuit, an RC charging / discharging circuit, and a D flip-flop circuit. The input terminal of the button circuit is connected to the power supply input Vin. The output terminal of the button circuit is connected to the input terminal of the RC charging / discharging circuit and the first input terminal of the D flip-flop circuit. The output terminal of the RC charging / discharging circuit is connected to the second input terminal of the D flip-flop circuit. The output terminal of the D flip-flop circuit is connected to the first input terminal of the PMOS switch circuit. The output terminal of the PMOS switch circuit is connected to the third input terminal of the D flip-flop circuit and the input terminal of the controlled system circuit. The second input terminal of the PMOS switch circuit is connected to the power supply input Vin.

[0006] In the adjustable-duration power-on / off control circuit provided by this utility model, the button circuit includes a button switch K1, a first resistor R1, a second resistor R2, a first capacitor C1, and a first PMOS transistor Q1. The gate of the first PMOS transistor Q1 is connected to the first end of the first resistor R1, the first end of the second resistor R2, and the first end of the first capacitor C1. The source of the first PMOS transistor Q1 is connected to the second end of the second resistor R2 and the power supply input Vin. The drain of the first PMOS transistor Q1 is connected to the input terminal of the RC charging and discharging circuit and the first input terminal of the D flip-flop circuit. The second end of the first resistor R1 is connected to the first end of the button switch K1. The second end of the button switch K1 and the second end of the first capacitor C1 are grounded.

[0007] In the adjustable-duration power-on / off control circuit provided by this utility model, the RC charging and discharging circuit includes a third resistor R3, a fourth resistor R4, a second capacitor C2, a third capacitor C3, and a first diode D1. The cathode of the first diode D1 is connected to the first terminal of the third resistor R3, the first terminal of the fourth resistor R4, the first terminal of the second capacitor C2, and the drain of the first PMOS transistor Q1. The anode of the first diode D1 is connected to the second terminal of the third resistor R3, the first terminal of the third capacitor C3, and the second input terminal of the D flip-flop circuit. The second terminal of the fourth resistor R4, the second terminal of the second capacitor C2, and the second terminal of the third capacitor C3 are grounded.

[0008] In the adjustable-duration power-on / off control circuit provided by this utility model, the D flip-flop circuit includes an inverting D flip-flop chip U1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a fourth capacitor C4, and a common-cathode diode D2. The first pin of the inverting D flip-flop chip U1 is connected to the first end of the fifth resistor R5. The second end of the fifth resistor R5 is connected to the second anode of the common-cathode diode D2 and the output terminal of the PMOS switching circuit. The second pin of the inverting D flip-flop chip U1 is connected to the anode of the first diode D1 via the sixth resistor R6. The third pin of the inverting D flip-flop chip U1 is grounded. The fourth pin of the inverting D flip-flop chip U1 is connected to the first input terminal of the PMOS switching circuit via the seventh resistor R7. The fifth pin of the inverting D flip-flop chip U1 is grounded via the fourth capacitor C4. The first anode of the common-cathode diode D2 is connected to the drain of the first PMOS transistor Q1, and the cathode of the common-cathode diode D2 is connected to the fifth pin of the inverting D flip-flop chip U1.

[0009] In the time-adjustable power-on / off control circuit provided by this utility model, the PMOS switching circuit includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a fifth capacitor C5, a second NMOS transistor Q2, and a third PMOS transistor Q3. The gate of the second NMOS transistor Q2 is connected to the first terminal of the eighth resistor R8 and the output terminal of the D flip-flop circuit. The source of the second NMOS transistor Q2 and the second terminal of the eighth resistor R8 are grounded. The drain of the second NMOS transistor Q2 is connected to the gate of the third PMOS transistor Q3 via the ninth resistor R9. The source of the third PMOS transistor Q3 is connected to the power supply input Vin and the first terminal of the tenth resistor R10. The second terminal of the tenth resistor R10 is connected to the gate of the third PMOS transistor Q3. The drain of the third PMOS transistor Q3 is grounded via the fifth capacitor C5. The drain of the third PMOS transistor Q3 also serves as the output terminal of the PMOS switching circuit.

[0010] The adjustable power-on / off control circuit provided by this utility model has the following beneficial effects: In this utility model, the button circuit controls the power supply input Vin to supply power to the RC charging and discharging circuit and the D flip-flop circuit; the output of the RC charging and discharging circuit and the output Vout of the PMOS switch circuit serve as the input of the D flip-flop circuit, controlling the output state of the D flip-flop circuit; the output of the D flip-flop circuit controls the conduction and cutoff of the PMOS switch circuit, thereby switching the power-on and power-off states of Vout; thus, the long-press power-on / off function is realized through the hardware circuit including the RC charging and discharging circuit and the D flip-flop circuit. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0012] Figure 1 The diagram shown is a schematic of an adjustable-duration power-on / off control circuit according to an embodiment of the present invention.

[0013] Figure 2 The diagram shown is a circuit diagram of an adjustable-duration power-on / off control circuit according to an embodiment of the present invention. Detailed Implementation

[0014] To facilitate understanding of this utility model, a more complete description will be given below with reference to the accompanying drawings. Typical embodiments of this utility model are shown in the drawings. However, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this utility model will be more thorough and complete.

[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0016] Figure 1 The diagram shown is a schematic of an adjustable-duration power-on / off control circuit according to an embodiment of this utility model. Figure 1 As shown, the adjustable-duration power-on / off control circuit provided by this utility model is connected between the power supply input Vin and the controlled system circuit 300. It includes a power-on / off control module 100 and a PMOS switch circuit 200. The input terminals of the power-on / off control module 100 and the PMOS switch circuit 200 are connected to the power supply input Vin. The output terminal of the power-on / off control module 100 is connected to the control terminal of the PMOS switch circuit 200. The output terminal of the PMOS switch circuit 200 is connected to the input terminal of the controlled system circuit and the control terminal of the power-on / off control module 100. The power-on / off control module 100 includes a button circuit 110, an RC charging / discharging circuit 120, and a D flip-flop circuit 130. The input terminal of the button circuit 110 is connected to the power supply input Vin. The output terminal of the button circuit 110 is connected to the input terminal of the RC charging / discharging circuit 120 and the first input terminal of the D flip-flop circuit 130. The output terminal of the RC charging / discharging circuit 120 is connected to the second input terminal of the D flip-flop circuit 130. The output terminal of the D flip-flop circuit 130 is connected to the first input terminal of the PMOS switch circuit 200. The output terminal of the PMOS switch circuit 200 is connected to the third input terminal of the D flip-flop circuit 130 and the input terminal of the controlled system circuit. The second input terminal of the PMOS switch circuit 200 is connected to the power supply input Vin. In this circuit, the button circuit 110 controls the power input Vin to supply power to the RC charging / discharging circuit 120 and the D flip-flop circuit 130. The output of the RC charging / discharging circuit 120 and the output Vout of the PMOS switching circuit 200 serve as the inputs to the D flip-flop circuit 130, controlling its output state. The output of the D flip-flop circuit 130 controls the PMOS switching circuit 200 to turn on and off, thereby switching the power-on and power-off states of Vout. Thus, a long-press power-on / off function is achieved through hardware circuitry including the RC charging / discharging circuit and the D flip-flop circuit.

[0017] Figure 2 The diagram shown is a circuit diagram of an adjustable-duration power-on / off control circuit according to an embodiment of this utility model. Figure 2 As shown, the button circuit 110 includes a button switch K1, a first resistor R1, a second resistor R2, a first capacitor C1, and a first PMOS transistor Q1; the RC charging and discharging circuit 120 includes a third resistor R3, a fourth resistor R4, a second capacitor C2, a third capacitor C3, and a first diode D1; the D flip-flop circuit 130 includes an inverting D flip-flop chip U1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a fourth capacitor C4, and a common cathode diode D2; the PMOS switch circuit 200 includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a fifth capacitor C5, a second NMOS transistor Q2, and a third PMOS transistor Q3.

[0018] Furthermore, such as Figure 2As shown, the gate of the first PMOS transistor Q1 is connected to the first terminal of the first resistor R1, the first terminal of the second resistor R2, and the first terminal of the first capacitor C1. The source of the first PMOS transistor Q1 is connected to the second terminal of the second resistor R2 and the power supply input Vin. The drain of the first PMOS transistor Q1 is connected to the input terminal of the RC charging and discharging circuit 120 and the first input terminal of the D flip-flop circuit 130. The second terminal of the first resistor R1 is connected to the first terminal of the push-button switch K1. The second terminal of the push-button switch K1 and the second terminal of the first capacitor C1 are grounded. The cathode of the first diode D1 is connected to the first terminal of the third resistor R3, the first terminal of the fourth resistor R4, the first terminal of the second capacitor C2, and the drain of the first PMOS transistor Q1. The anode of the first diode D1 is connected to the second terminal of the third resistor R3, the first terminal of the third capacitor C3, and the second input terminal of the D flip-flop circuit 130. The second terminal of the fourth resistor R4, the second terminal of the second capacitor C2, and the second terminal of the third capacitor C3 are grounded. The first pin of the inverting D flip-flop chip U1 is connected to the first end of the fifth resistor R5. The second end of the fifth resistor R5 is connected to the second anode of the common cathode diode D2 and the output terminal of the PMOS switching circuit 200. The second pin of the inverting D flip-flop chip U1 is connected to the anode of the first diode D1 via the sixth resistor R6. The third pin of the inverting D flip-flop chip U1 is grounded. The fourth pin of the inverting D flip-flop chip U1 is connected to the first input terminal of the PMOS switching circuit 200 via the seventh resistor R7. The fifth pin of the inverting D flip-flop chip U1 is grounded via the fourth capacitor C4. The first anode of the common cathode diode D2 is connected to the drain of the first PMOS transistor Q1. The cathode of the common cathode diode D2 is connected to the fifth pin of the inverting D flip-flop chip U1. The gate of the second NMOS transistor Q2 is connected to the first terminal of the eighth resistor R8 and the output terminal of the D flip-flop circuit 130. The source of the second NMOS transistor Q2 and the second terminal of the eighth resistor R8 are grounded. The drain of the second NMOS transistor Q2 is connected to the gate of the third PMOS transistor Q3 via the ninth resistor R9. The source of the third PMOS transistor Q3 is connected to the power supply input Vin and the first terminal of the tenth resistor R10. The second terminal of the tenth resistor R10 is connected to the gate of the third PMOS transistor Q3. The drain of the third PMOS transistor Q3 is grounded via the fifth capacitor C5. The drain of the third PMOS transistor Q3 also serves as the output terminal of the PMOS switching circuit 200.

[0019] The following is combined Figure 2 The working principle of the adjustable-duration on / off control circuit provided by this utility model is explained as follows:

[0020] 1. Long press power-on procedure (i.e., the system is in a power-off state, the initial voltage of Vout is 0V, and the first pin of the inverting D flip-flop chip U1 is 0V):

[0021] Keep the first switch K1 pressed (hold), which turns on the first PMOS transistor Q1 of the button circuit. The power input Vin supplies power to the inverting D flip-flop chip U1 through the common cathode diode D2. At this time, in the RC charging and discharging circuit, the third capacitor C3 is charged through the third resistor R3. After the charging time Δt (the duration of Δt can be flexibly configured by the resistance value of the third resistor R3 and the capacitance value of the third capacitor C3), the rising edge threshold of the second pin (CP pin) of the inverting D flip-flop chip U1 is triggered. The fourth pin (Qn pin) of the inverting D flip-flop chip U1 outputs a high level, which turns on the second NMOS transistor Q2 of the PMOS switching circuit, and then turns on the third PMOS transistor Q3 of the PMOS switching circuit. Subsequently, Vout is powered on (≈Vin).

[0022] Then the first switch K1 is released, so the first PMOS transistor Q1 is turned off; the output Vout of the PMOS switching circuit powers the inverting D flip-flop chip U1 through the common cathode diode D2, and the charge of the third capacitor C3 is rapidly discharged through the first diode D1 and the fourth resistor R4; since no rising edge of the second pin (CP pin) of the inverting D flip-flop chip U1 is detected, the fourth pin (Qn pin) of the inverting D flip-flop chip U1 remains at a high level; the second NMOS transistor Q2 and the third PMOS transistor Q3 remain on, and Vout remains powered on.

[0023] 2. Long press to power off (i.e., the system is in working state, the initial voltage Vout ≈ Vin, and the first pin of the inverting D flip-flop chip U1 is at a high level):

[0024] Keep the first switch K1 in the pressed state, so that the first PMOS transistor Q1 is turned on; the power supply input Vin supplies power to the inverting D flip-flop chip U1 through the common cathode diode D2, and charges the third capacitor C3 through the third resistor R3; after the charging time Δt (the duration of Δt can be flexibly configured by the resistance value of the third resistor R3 and the capacitance value of the third capacitor C3), the rising edge threshold of the second pin (CP pin) of the inverting D flip-flop chip U1 is triggered, and a low level is output through the fourth pin (Qn pin) of the inverting D flip-flop chip U1, so that the second NMOS transistor Q2 and the third PMOS transistor Q3 are turned off, thereby turning off Vout.

[0025] Subsequently, releasing the first switch K1 turns off the first PMOS transistor Q1, de-energizes the inverting D flip-flop chip U1, and rapidly discharges the charge of the third capacitor C3 through the first diode D1 and the fourth resistor R4. As a result, the gate voltage of the second NMOS transistor Q2 is pulled down to ground by the resistor R8 and remains off, while the third PMOS transistor Q3 remains off, thus keeping Vout in a de-energized state.

[0026] 3. Briefly press button K1 (first switch):

[0027] When the first switch K1 is pressed briefly (i.e., the pressing time is less than Δt), since the charging time of the third capacitor C3 is less than Δt, the rising edge threshold of the second pin (CP pin) of the inverting D flip-flop chip U1 is not triggered. Therefore, the level of the fourth pin (Qn pin) of the inverting D flip-flop chip U1 remains unchanged, and the states of the second NMOS transistor Q2, the third PMOS transistor Q3, and Vout remain unchanged.

[0028] The formula for calculating charging time Δt is: Δt=R3*C3*ln[Vin / (Vin-Vth)];

[0029] Where Vth is the rising edge threshold voltage of the second pin (CP pin) of the U1 chip.

[0030] The adjustable power-on / off control circuit provided by this utility model is implemented purely in hardware, requiring no software intervention. The long-press time can be flexibly configured according to design requirements, and the power consumption during shutdown is extremely low (<1uA). The main components required for the circuit include resistors, capacitors, diodes, MOSFETs, and D flip-flops, all of which are extremely mature and common general-purpose components, with low cost and strong substitutability.

[0031] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0032] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, the inventive aspect lies in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0033] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of this invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0034] It should be noted that the above embodiments are illustrative of the present invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

Claims

1. A time-adjustable on / off control circuit, connected between the power supply input Vin and the controlled system circuit (300), characterized in that, The system includes a power-on / off control module (100) and a PMOS switching circuit (200). The input terminals of the power-on / off control module (100) and the PMOS switching circuit (200) are connected to the power supply input Vin. The output terminal of the power-on / off control module (100) is connected to the control terminal of the PMOS switching circuit (200). The output terminal of the PMOS switching circuit (200) is connected to the input terminal of the controlled system circuit and the control terminal of the power-on / off control module (100). The power-on / off control module (100) includes a button circuit (110), an RC charging / discharging circuit (120), and a D flip-flop circuit (130). The button circuit (110)... The input terminal of the button circuit (110) is connected to the power supply input Vin. The output terminal of the button circuit (110) is connected to the input terminal of the RC charging and discharging circuit (120) and the first input terminal of the D flip-flop circuit (130). The output terminal of the RC charging and discharging circuit (120) is connected to the second input terminal of the D flip-flop circuit (130). The output terminal of the D flip-flop circuit (130) is connected to the first input terminal of the PMOS switch circuit (200). The output terminal of the PMOS switch circuit (200) is connected to the third input terminal of the D flip-flop circuit (130) and the input terminal of the controlled system circuit. The second input terminal of the PMOS switch circuit (200) is connected to the power supply input Vin.

2. The time-adjustable power-on / off control circuit as described in claim 1, characterized in that, The button circuit (110) includes a button switch K1, a first resistor R1, a second resistor R2, a first capacitor C1, and a first PMOS transistor Q1. The gate of the first PMOS transistor Q1 is connected to the first end of the first resistor R1, the first end of the second resistor R2, and the first end of the first capacitor C1. The source of the first PMOS transistor Q1 is connected to the second end of the second resistor R2 and the power supply input Vin. The drain of the first PMOS transistor Q1 is connected to the input terminal of the RC charging and discharging circuit (120) and the first input terminal of the D flip-flop circuit (130). The second end of the first resistor R1 is connected to the first end of the button switch K1. The second end of the button switch K1 and the second end of the first capacitor C1 are grounded.

3. The adjustable-duration on / off control circuit as described in claim 2, characterized in that, The RC charging and discharging circuit (120) includes a third resistor R3, a fourth resistor R4, a second capacitor C2, a third capacitor C3, and a first diode D1. The cathode of the first diode D1 is connected to the first terminal of the third resistor R3, the first terminal of the fourth resistor R4, the first terminal of the second capacitor C2, and the drain of the first PMOS transistor Q1. The anode of the first diode D1 is connected to the second terminal of the third resistor R3, the first terminal of the third capacitor C3, and the second input terminal of the D flip-flop circuit (130). The second terminals of the fourth resistor R4, the second terminal of the second capacitor C2, and the second terminal of the third capacitor C3 are grounded.

4. The time-adjustable power-on / off control circuit as described in claim 3, characterized in that, The D flip-flop circuit (130) includes an inverting D flip-flop chip U1, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a fourth capacitor C4, and a common cathode diode D2. The first pin of the inverting D flip-flop chip U1 is connected to the first end of the fifth resistor R5. The second end of the fifth resistor R5 is connected to the second anode of the common cathode diode D2 and the output terminal of the PMOS switching circuit (200). The second pin of the inverting D flip-flop chip U1 is connected to the anode of the first diode D1 via the sixth resistor R6. The third pin of the inverting D flip-flop chip U1 is grounded. The fourth pin of the inverting D flip-flop chip U1 is connected to the first input terminal of the PMOS switching circuit (200) via the seventh resistor R7. The fifth pin of the inverting D flip-flop chip U1 is grounded via the fourth capacitor C4. The first anode of the common cathode diode D2 is connected to the drain of the first PMOS transistor Q1. The cathode of the common cathode diode D2 is connected to the fifth pin of the inverting D flip-flop chip U1.

5. The adjustable-duration on / off control circuit as described in claim 4, characterized in that, The PMOS switching circuit (200) includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a fifth capacitor C5, a second NMOS transistor Q2, and a third PMOS transistor Q3. The gate of the second NMOS transistor Q2 is connected to the first terminal of the eighth resistor R8 and the output terminal of the D flip-flop circuit (130). The source of the second NMOS transistor Q2 and the second terminal of the eighth resistor R8 are grounded. The drain of the second NMOS transistor Q2 is connected to the gate of the third PMOS transistor Q3 via the ninth resistor R9. The source of the third PMOS transistor Q3 is connected to the power supply input Vin and the first terminal of the tenth resistor R10. The second terminal of the tenth resistor R10 is connected to the gate of the third PMOS transistor Q3. The drain of the third PMOS transistor Q3 is grounded via the fifth capacitor C5. The drain of the third PMOS transistor Q3 also serves as the output terminal of the PMOS switching circuit (200).

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