A compensation circuit and voltage regulator

Abstract

The utility model discloses a kind of compensation circuit and voltage stabilizer, it is related to circuit field, control module is connected with the output end of voltage stabilizer, the output voltage of voltage stabilizer can be detected, the output end of control module is connected with the control end of first controllable switch and the control end of second controllable switch, the action of first controllable switch and second controllable switch can be controlled according to the output voltage of voltage stabilizer, to adjust the on-resistance of regulating tube in voltage stabilizer, to adjust the output current of regulating tube by the change of regulating tube on-resistance, and then directly adjust the output voltage of stabilivolt by the change of regulating tube output current. Not simply rely on the feedback control of voltage stabilizer itself, but further utilize compensation circuit to be directly adjusted by regulating tube to realize the rapid adjustment of output voltage, so that voltage stabilizer can quickly respond to the output voltage change caused by load current change, improve the stability of the output voltage of voltage stabilizer, reduce voltage recovery time.

Description

Technical Field

[0001] This utility model relates to the field of circuits, and in particular to a compensation circuit and a voltage regulator. Background Technology

[0002] LDO (Low Dropout Voltage Regulator) is primarily used to provide stable voltage to equipment or circuits. In its application, load transient response is a key performance indicator for LDO regulators. The load transient response refers to the LDO regulator's ability to quickly respond and adjust its output voltage to maintain stability when the load current changes suddenly. This characteristic is crucial for ensuring the stability and reliability of electronic systems. In modern electronic systems, load current changes are commonplace. For example, when a digital circuit switches from one operating mode to another, or when the signal amplitude changes in an analog circuit, rapid changes in load current can occur. If the LDO regulator's load transient response is poor, it may produce large output voltage fluctuations (i.e., overshoot or undershoot) when the load changes, thus affecting the performance and stability of the entire electronic system. Therefore, a good load transient response is one of the important performance indicators of LDO regulators, and ensuring a good load transient response is a technical problem that needs to be optimized. Utility Model Content

[0003] The purpose of this invention is to provide a compensation circuit and a voltage regulator, which aims to achieve good load transient response characteristics of voltage regulators such as LDOs.

[0004] To solve the above-mentioned technical problems, this utility model provides a compensation circuit, comprising:

[0005] The first controllable switch is used to output a first voltage when it is turned on in order to control the on-resistance of the regulating tube in the voltage regulator to decrease by a first preset value.

[0006] The second controllable switch is used to output a second voltage when it is turned on to control the on-resistance of the regulating tube to increase by a second preset value;

[0007] The first controllable switch and the second controllable switch are connected in series, and the first end of the series circuit is connected to the power supply, while the second end is grounded.

[0008] The control module has an input terminal connected to the output terminal of the voltage regulator, a first output terminal connected to the control terminal of the first controllable switch, and a second output terminal connected to the control terminal of the second controllable switch. It is used to control the operation of the first controllable switch and the second controllable switch based on the output voltage of the voltage regulator.

[0009] Optionally, the control module includes:

[0010] An input module, with its input terminal connected to the output terminal of the voltage regulator, is used to detect the output voltage of the voltage regulator.

[0011] The first control submodule has an input terminal connected to the output terminal of the input module and an output terminal connected to the control terminal of the first controllable switch, and is used to control the operation of the first controllable switch based on the output voltage of the voltage regulator;

[0012] The second control submodule has its input terminal connected to the output terminal of the input module and its output terminal connected to the control terminal of the second controllable switch. It is used to control the operation of the second controllable switch based on the output voltage of the voltage regulator.

[0013] Optionally, the regulating transistor of the voltage regulator is a PMOS transistor, the first controllable switch is a first NMOS transistor, and the second controllable switch is a first PMOS transistor;

[0014] The source of the first NMOS transistor is grounded, and its gate is connected to the output terminal of the first control submodule.

[0015] The source of the first PMOS transistor is connected to the power supply, the gate is connected to the output terminal of the second control submodule, and the drain is connected to the drain of the first NMOS transistor, serving as the output terminal of the compensation circuit.

[0016] Optionally, the input module includes:

[0017] The second PMOS transistor has its source connected to the power supply, and its gate serves as the output terminal of the input module.

[0018] The drain of the second NMOS transistor is connected to the gate and the source of the second PMOS transistor, respectively, and the gate is connected to a preset bias voltage.

[0019] The first current limiting module has its first terminal connected to the source of the second NMOS transistor and the output terminal of the voltage regulator, respectively, and its second terminal grounded.

[0020] The second NMOS transistor is turned off when the output voltage of the regulator is greater than the upper limit of the target range, and turned on when the output voltage of the regulator is less than or equal to the upper limit of the target range; and the on-resistance of the first NMOS transistor is positively correlated with the output voltage of the regulator.

[0021] Optional, also includes:

[0022] The bias voltage generation module has its output terminal connected to the gate of the second NMOS transistor and is used to output a preset bias voltage.

[0023] Optionally, the bias voltage generation module includes:

[0024] The third PMOS transistor has its source connected to the power supply and its gate connected to the bias power supply.

[0025] The drain of the third NMOS transistor is connected to the gate of the third NMOS transistor and the drain of the third PMOS transistor, respectively, and the gate serves as the output terminal of the bias voltage generation module.

[0026] The second current limiting module has its first terminal connected to the source of the third NMOS transistor and its second terminal grounded.

[0027] Both the third PMOS transistor and the third NMOS transistor remain in the on state.

[0028] Optional, also includes:

[0029] The third current limiting module has its first end connected to the output end of the voltage regulator, and its second end connected to the source of the second NMOS transistor and the first end of the first current limiting module, respectively.

[0030] Optionally, the first control submodule includes:

[0031] The fourth PMOS transistor has its source connected to the power supply and its gate connected to the output terminal of the input module. It is used to turn off the voltage regulator based on the control of the input module when the output voltage of the regulator is greater than the upper limit of the target range.

[0032] The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor and the gate of the first NMOS transistor, respectively, and the gate is connected to a preset bias voltage.

[0033] The fourth current limiting module has its first terminal connected to the source of the fourth NMOS transistor and its second terminal grounded.

[0034] The fourth NMOS transistor remains on, and when the output voltage of the regulator is within the target range, the on-resistance of the fourth NMOS transistor is less than that of the fourth PMOS transistor.

[0035] Optionally, the second control submodule includes:

[0036] The fifth PMOS transistor has its source connected to the power supply and its gate connected to the output terminal of the input module. It is used to turn off the voltage regulator based on the control of the input module when the output voltage of the regulator is greater than the upper limit of the target range.

[0037] The drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor and the gate of the first PMOS transistor, respectively, and the gate is connected to a preset bias voltage.

[0038] The fifth current limiting module has its first terminal connected to the source of the fifth NMOS transistor and its second terminal grounded.

[0039] The fifth NMOS transistor remains on, and when the output voltage of the regulator is in the target range, the on-resistance of the fifth NMOS transistor is greater than that of the fifth PMOS transistor.

[0040] To solve the above-mentioned technical problems, this utility model also provides a voltage regulator, including an adjustment tube, an error amplifier, and a compensation circuit as described above. The non-inverting input terminal of the error amplifier is connected to a reference voltage. The first terminal of the adjustment tube is connected to a preset power supply, and the second terminal serves as the output terminal of the voltage regulator. It is also connected to the inverting input terminal of the error amplifier and the input terminal of the compensation circuit, respectively. The control terminal is connected to the output terminal of the error amplifier and the output terminal of the compensation circuit, respectively.

[0041] This invention provides a compensation circuit, including a first controllable switch, a second controllable switch, and a control module. The control module is connected to the output terminal of a voltage regulator and can detect the output voltage of the voltage regulator. The output terminal of the control module is connected to the control terminals of the first and second controllable switches, and can control the operation of the first and second controllable switches according to the output voltage of the voltage regulator to adjust the on-resistance of the regulating transistor in the voltage regulator. This change in the on-resistance of the regulating transistor adjusts the output current of the regulating transistor, and ultimately, the change in the output current of the regulating transistor directly adjusts the output voltage of the voltage regulator. Instead of relying solely on the feedback control of the voltage regulator itself, this invention further utilizes an added compensation circuit to directly and rapidly adjust the output voltage through the regulating transistor. This allows the voltage regulator to quickly respond to changes in output voltage caused by changes in load current, improving the stability of the voltage regulator's output voltage and reducing voltage recovery time.

[0042] This invention also provides a voltage regulator that has the same beneficial effects as the compensation circuit described above. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A schematic diagram of the structure of a compensation circuit provided by this utility model;

[0045] Figure 2 A schematic diagram of another compensation circuit provided by this utility model;

[0046] Figure 3 This is a schematic diagram of the structure of a voltage regulator provided by this utility model;

[0047] Figure 4 A schematic diagram illustrating the working effect of a compensation circuit provided by this utility model. Detailed Implementation

[0048] The core of this invention is to provide a compensation circuit and a voltage regulator. By using the added compensation circuit, the output voltage can be quickly adjusted directly through the regulating tube, enabling the voltage regulator to respond quickly to changes in output voltage caused by changes in load current, thereby improving the stability of the voltage regulator's output voltage and reducing voltage recovery time.

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0050] See Figure 1 As shown, Figure 1 A schematic diagram of a compensation circuit provided by this utility model; see also Figure 2 As shown, Figure 2 A schematic diagram of another compensation circuit provided by this utility model; wherein, VOUT represents the output voltage of the voltage regulator, and VS represents the power supply; to solve the above technical problems, this utility model provides a compensation circuit, including:

[0051] The first controllable switch 1 is used to output a first voltage when it is turned on in order to control the on-resistance of the regulating tube Q0 in the voltage regulator to decrease by a first preset value;

[0052] The second controllable switch 2 is used to output a second voltage when it is turned on to control the on-resistance of the regulating tube Q0 to increase the second preset value;

[0053] The first controllable switch 1 and the second controllable switch 2 are connected in series, and the first end of the series circuit is connected to the power supply, while the second end is grounded.

[0054] The control module 3 has an input terminal connected to the output terminal of the voltage regulator, a first output terminal connected to the control terminal of the first controllable switch 1, and a second output terminal connected to the control terminal of the second controllable switch 2. It is used to control the operation of the first controllable switch 1 and the second controllable switch 2 based on the output voltage of the voltage regulator.

[0055] It's easy to understand that voltage regulators need to output a stable voltage during application. Generally, the output voltage of a voltage regulator will stabilize within the target range that allows for error, or even stabilize at the target voltage value. Therefore, a feedback loop based on an error amplifier is set up in the voltage regulator to control the output voltage. Considering that the response speed of the voltage regulator relying solely on the external feedback circuit of its internal error amplifier for output voltage feedback adjustment is relatively slow, this application adds a compensation circuit to the voltage regulator to specifically compensate for changes in the output voltage. The input terminal of the compensation circuit, i.e., the input terminal of the control module 3, is connected to the output terminal of the voltage regulator, which can detect changes in the output voltage of the voltage regulator in real time. Then, based on the changes in the output voltage, it controls the operation of the first controllable switch 1 and the second controllable switch 2. The operation of the first controllable switch 1 and the second controllable switch 2 will affect the change in the on-resistance of the regulating transistor Q0 in the voltage regulator. When the on-resistance of the regulating transistor Q0 increases, its conductivity decreases, the output current of the regulator flowing through the regulating transistor Q0 decreases, and thus the output voltage of the regulator decreases; when the on-resistance of the regulating transistor Q0 decreases, its conductivity increases, the output current of the regulator flowing through the regulating transistor Q0 increases, and thus the output voltage of the regulator increases.

[0056] It should be noted that, see Figure 3 As shown, Figure 3 This utility model provides a schematic diagram of a voltage regulator structure. The regulating transistor Q0 refers to the power device in the voltage regulator that dynamically adjusts the output voltage and / or output current by changing its own conduction state. By utilizing changes in its conduction degree, the voltage regulator's output is stabilized within the target range or at the target voltage value. Considering that the fluctuation of the voltage regulator's output voltage in practical applications is generally small due to the internal feedback loop, the compensation circuit needs to be able to detect and compensate for small changes in the voltage regulator's output voltage in a timely manner. Therefore, the compensation circuit includes a first controllable switch 1 to compensate for a decrease in the voltage regulator's output voltage, and a second controllable switch 2 to compensate for an increase in the voltage regulator's output voltage. The first controllable switch 1 and the second controllable switch 2 have three operating states: the first is that both the first controllable switch 1 and the second controllable switch 2 are off; the second is that the first controllable switch 1 is on and the second controllable switch 2 is off; and the third is that the first controllable switch 1 is off and the second controllable switch 2 is on. As a specific embodiment, the series connection point of the first controllable switch 1 and the second controllable switch 2 is connected to the control terminal of the regulating tube Q0. When the first controllable switch 1 or the second controllable switch 2 is turned on, the voltage of the control terminal of the regulating tube Q0 can be pulled up or down by the power supply or ground connected in series, thereby controlling the change of the on-resistance and the degree of conduction of the regulating tube Q0.

[0057] Specifically, when the voltage regulator's output voltage is within the target range (or target voltage value), both the first controllable switch 1 and the second controllable switch 2 are in the off state. At this time, the voltage regulator's output voltage is stable, and no compensation circuit is required. When the voltage regulator's output voltage is less than the lower limit of the target range (or target voltage value), the first controllable switch 1 is turned on. At this time, the voltage regulator's output voltage is too low, and the first controllable switch 1 in the compensation circuit needs to be turned on to reduce the on-resistance of the regulating transistor Q0, thereby increasing the conduction degree of the regulating transistor Q0 and controlling the voltage regulator's output voltage to rise to return to the target range (or target voltage value). When the voltage regulator's output voltage is greater than the upper limit of the target range (or target voltage value), the second controllable switch 2 is turned on. At this time, the voltage regulator's output voltage is too high, and the second controllable switch 2 in the compensation circuit needs to be turned on to increase the on-resistance of the regulating transistor Q0, thereby reducing the conduction degree of the regulating transistor Q0 and controlling the voltage regulator's output voltage to decrease to return to the target range (or target voltage value).

[0058] It should be noted that this application does not impose any special limitations on the specific types and implementation methods of the first controllable switch 1 and the second controllable switch 2. Various types of switching devices, such as MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), can be used. This application mainly uses MOSFETs as an example for explanation. Similarly, this application does not impose any special limitations on the specific types and implementation methods of the control module 3. Circuits built using power devices can be used. The specific types and implementation methods of the voltage regulator and its regulating transistor Q0 are not specifically limited here. The specific values ​​of the first and second preset values ​​are not specifically limited here and can be set and adjusted according to the type of regulating transistor Q0 and device parameters of the actual voltage regulator. The specific types and implementation methods of the power supply are not specifically limited here. The target range or target voltage value of the voltage regulator's output voltage depends on the voltage regulator's settings and the actual application scenario; this application does not impose any special limitations on these aspects.

[0059] This invention provides a compensation circuit whose input terminal is directly connected to the output terminal of a voltage regulator. Once the output voltage of the voltage regulator changes, the first controllable switch 1 and the second controllable switch 2 in the compensation circuit will respond in time and perform corresponding actions. When the output voltage of the voltage regulator is too low or too high, the first controllable switch 1 and the second controllable switch 2 are used to adjust the on-resistance of the regulating transistor Q0 to adjust the output voltage of the voltage regulator. Thus, the compensation circuit constructs an additional output voltage feedback control loop for the voltage regulator, avoiding the problem that the voltage regulator cannot capture load changes in time, resulting in transient spikes and voltage instability. It realizes transient response enhancement compensation for voltage regulators such as LDOs. When the load current changes instantaneously (for example, the load current changes instantaneously from 0mA to 100mA), the voltage regulator can maintain the stability of the output voltage with a faster response speed with the help of the compensation circuit, quickly stabilize the output voltage, and reduce the recovery time.

[0060] Based on the above embodiments:

[0061] As an optional embodiment, control module 3 includes:

[0062] The input module, whose input terminal is connected to the output terminal of the voltage regulator, is used to detect the output voltage of the voltage regulator;

[0063] The first control submodule has its input terminal connected to the output terminal of the input module and its output terminal connected to the control terminal of the first controllable switch 1. It is used to control the operation of the first controllable switch 1 based on the output voltage of the voltage regulator.

[0064] The second control submodule has its input terminal connected to the output terminal of the input module and its output terminal connected to the control terminal of the second controllable switch 2. It is used to control the operation of the second controllable switch 2 based on the output voltage of the voltage regulator.

[0065] Understandably, the control module 3 not only needs to detect the changes in the output voltage of the voltage regulator in real time, but also needs to control the actions of the first controllable switch 1 and the second controllable switch 2 respectively. Therefore, the control module 3 is specifically equipped with an input module, a first control submodule and a second control submodule. The input module is used to detect the output voltage of the voltage regulator and output different signals (voltage signals) to the first control submodule and the second control submodule according to the relationship between the output voltage and the target range (or target voltage value). When the output voltage is within the target range (or equal to the target voltage value), the input module outputs a first signal to the first control submodule and the second control submodule. At this time, the first control submodule controls the first controllable switch 1 to turn off, and the second control submodule controls the second controllable switch 2 to turn off. When the output voltage is greater than the upper limit of the target range (or the target voltage value), the input module outputs a second signal to the first control submodule and the second control submodule. At this time, the first control submodule controls the first controllable switch 1 to turn off, and the second control submodule controls the second controllable switch 2 to turn on. When the output voltage is less than the lower limit of the target range (or the target voltage value), the input module outputs a second signal to the first control submodule and the second control submodule. At this time, the first control submodule controls the first controllable switch 1 to turn on, and the second control submodule controls the second controllable switch 2 to turn off. This application does not specifically limit the specific types and implementation methods of the input module, the first control submodule, and the second control submodule; they can all be implemented using circuits built with MOSFETs.

[0066] Specifically, by setting up an input module, a first control submodule, and a second control submodule in the control module 3 respectively to realize different functions of the control module 3, the internal architecture of the control module 3 is further clarified.

[0067] As an optional embodiment, the regulator's regulating transistor Q0 is a PMOS transistor, the first controllable switch 1 is a first NMOS transistor NM1, and the second controllable switch 2 is a first PMOS transistor PM1;

[0068] The source of the first NMOS transistor NM1 is grounded, and its gate is connected to the output terminal of the first control submodule.

[0069] The source of the first PMOS transistor PM1 is connected to the power supply, the gate is connected to the output of the second control submodule, and the drain is connected to the drain of the first NMOS transistor NM1, serving as the output of the compensation circuit.

[0070] It is easy to understand that, taking the PMOS transistor as an example, the conduction level of the PMOS transistor is negatively correlated with its gate voltage. A higher gate voltage results in a higher on-resistance and a lower conduction level, while a lower gate voltage results in a lower on-resistance and a higher conduction level. In this case, the first controllable switch 1 is implemented using the first NMOS transistor NM1, and the second controllable switch 2 is implemented using the first PMOS transistor PM1. The source of the first NMOS transistor NM1 is grounded. When the first NMOS transistor NM1 is turned on, it pulls down the gate voltage of the adjustment transistor Q0, thereby reducing the on-resistance and increasing the conduction level of Q0. The source of the first PMOS transistor PM1 is connected to the power supply. When the first PMOS transistor PM1 is turned on, it pulls up the gate voltage of the adjustment transistor Q0, thereby increasing the on-resistance and decreasing the conduction level of Q0. This application does not specifically limit the specific types and device parameters of the first NMOS transistor NM1 and the first PMOS transistor PM1. This application uses a PMOS transistor as an example for illustration. In practical applications, the adjustment transistor Q0 can also be implemented using an NMOS transistor or other types of power devices. This application does not make any special restrictions here. When other types of power devices are used, the implementation methods of the first controllable switch 1, the second controllable switch 2, and the control module 3 can be adjusted according to the specific type of power device. The overall working principle is similar to that of the adjustment transistor Q0 using a PMOS transistor, and will not be described in detail here.

[0071] Specifically, taking the implementation of the regulating transistor Q0 using a PMOS transistor as an example, the first controllable switch 1 and the second controllable switch 2 can also be implemented using MOS transistors. The gate voltage of the regulating transistor Q0 can be effectively adjusted by using the conduction or cutoff of the MOS transistor. The circuit structure is simple and easy to implement. The components used are low in cost and have low power consumption, which is conducive to the simple implementation of the entire compensation circuit.

[0072] As an optional embodiment, the input module includes:

[0073] The second PMOS transistor PM2 has its source connected to the power supply, and its gate serves as the output terminal of the input module.

[0074] The drain of the second NMOS transistor NM2 is connected to the gate of the second PMOS transistor PM2 and the source of the second PMOS transistor PM2, respectively, and the gate is connected to a preset bias voltage.

[0075] The first current limiting module RX1 has its first terminal connected to the source of the second NMOS transistor NM2 and the output terminal of the voltage regulator, respectively, and its second terminal grounded.

[0076] The second NMOS transistor NM2 is used to turn off when the output voltage of the regulator is greater than the upper limit of the target range, and to turn on when the output voltage of the regulator is less than or equal to the upper limit of the target range; and the on-resistance of the first NMOS transistor NM1 is positively correlated with the output voltage of the regulator.

[0077] Understandably, the input module can also be implemented using a circuit built with MOSFETs. The second PMOS transistor PM2, the second NMOS transistor NM2, and the first current-limiting module RX1 are connected in series to form the input module. The first current-limiting module RX1 can limit the current in the input module, preventing overcurrent and other abnormal situations. The source of the second NMOS transistor NM2 is connected to the output terminal of the voltage regulator, and the drain of the second NMOS transistor NM2 is connected to the gate of the second PMOS transistor PM2. When the output voltage of the voltage regulator changes, the source voltage of the second NMOS transistor NM2 also changes, causing a change in the conduction level of the second NMOS transistor NM2, or even causing it to turn off. This, in turn, causes a change in the gate voltage of the second PMOS transistor PM2, affecting its conduction level, or even causing it to turn off. Therefore, the different voltages output by the second NMOS transistor NM2 in different operating states are used to detect whether the output voltage of the voltage regulator is normal.

[0078] It should be noted that when the regulator's output voltage is normally within the target range (or the target voltage value), both the second PMOS transistor PM2 and the second NMOS transistor NM2 remain in a conducting state under the action of a preset bias voltage. This allows the second PMOS transistor PM2 and the second NMOS transistor NM2, which are in operation, to quickly respond to changes in the output voltage when the regulator's output voltage changes. At this time, the gate of the second PMOS transistor PM2 is pulled down to a low level by the conducting second NMOS transistor NM2. When the regulator's output voltage is too high (greater than the upper limit of the target range or the target voltage value), the source voltage of the second NMOS transistor NM2 increases, and the second NMOS transistor NM2 turns off. The turned-off second NMOS transistor NM2 then controls the second PMOS transistor PM2 to turn off. When the regulator's output voltage is too low (less than the lower limit of the target range or the target voltage value), the source voltage of the second NMOS transistor NM2 decreases, and the conduction degree of the second NMOS transistor NM2 increases. This application does not impose specific limitations on the specific types and implementation methods of the second PMOS transistor PM2, the second NMOS transistor NM2, and the first current limiting module RX1, such as... Figure 2 As shown, the first current limiting module RX1 can be implemented using a resistor. This application does not impose any specific limitations on the specific value of the preset bias voltage or its implementation method.

[0079] Specifically, by utilizing the different operating states of the MOSFET under different operating conditions, the output voltage of the voltage regulator can be effectively detected. Therefore, the input module can also be implemented using a circuit built with MOSFETs. The circuit structure is simple, easy to implement, and the components used are low-cost and consume little power, which is conducive to the simple implementation of the entire compensation circuit.

[0080] As an optional embodiment, it also includes:

[0081] The bias voltage generation module has its output terminal connected to the gate of the second NMOS transistor NM2, and is used to output a preset bias voltage.

[0082] It is easy to understand that the conduction state of the second NMOS transistor NM2 when the regulator output voltage is normal requires a preset bias voltage to be applied to its gate. Therefore, a bias voltage generation module can be added to the compensation circuit to generate the preset bias voltage. While generating the preset bias voltage, the bias voltage generation module can also provide a stable bias current for the second PMOS transistor PM2 and the second NMOS transistor NM2 when the output voltage is normal, ensuring their conduction. This application does not specifically limit the specific type and implementation method of the bias voltage generation module.

[0083] Specifically, by adding a bias voltage generation module to generate a preset bias voltage, the second PMOS transistor PM2 and the second NMOS transistor NM2 are ensured to conduct stably when the output voltage of the regulator is normal, thus ensuring the input module responds quickly to changes in the output voltage of the regulator.

[0084] As an optional embodiment, the bias voltage generation module includes:

[0085] The third PMOS transistor PM3 has its source connected to the power supply and its gate connected to the bias power supply VBP.

[0086] The drain of the third NMOS transistor NM3 is connected to the gate of the third NMOS transistor NM3 and the drain of the third PMOS transistor PM3, respectively. The gate serves as the output terminal of the bias voltage generation module.

[0087] The second current limiting module RX2 has its first terminal connected to the source of the third NMOS transistor NM3, and its second terminal grounded.

[0088] Both the third PMOS transistor PM3 and the third NMOS transistor NM3 remain in the on state.

[0089] Understandably, the bias voltage generation module can also be implemented using a circuit built with MOSFETs. The third PMOS transistor PM3 maintains a stable conducting state under the influence of the power supply and bias power supply VBP. Simultaneously, the drain of the third PMOS transistor PM3 is connected to the gate of the third NMOS transistor NM3. The conducting third PMOS transistor PM3 utilizes the power supply to provide the third NMOS transistor NM3 with a supporting voltage for its conduction. At the same time, the gate voltage of the third NMOS transistor NM3 serves as the preset bias voltage output, connected to the second NMOS transistor NM2 to support its conduction, thereby generating the preset bias voltage. The second current limiting module RX2 can limit the current in the bias voltage generation module, preventing overcurrent and other abnormal conditions.

[0090] Furthermore, by directly connecting the gate of the second NMOS transistor NM2 to the gate of the third NMOS transistor NM3, a current mirror structure is formed. The third NMOS transistor NM3 can replicate the current in the bias voltage generation module to the input module, providing a stable bias current for the input module. This application does not specifically limit the specific types and implementation methods of the third PMOS transistor PM3, the third NMOS transistor NM3, and the second current limiting module RX2. Figure 2 As shown, the second current limiting module RX2 can be implemented using a resistor. This application does not impose any specific restrictions on the type and implementation method of the bias power supply; these need to be set according to the specific power supply voltage and the threshold voltage of the third PMOS transistor PM3.

[0091] Specifically, the circuit built using MOSFETs can effectively generate preset bias voltage and stable bias current. MOSFETs have a flexible operating voltage range and high flexibility, which can adapt to the bias voltage requirements of different application scenarios. The entire circuit structure is simple and easy to implement. The components used are low-cost, low-power, and easy to integrate, avoiding the power consumption of the bias voltage generation module, which is conducive to the simple implementation of the entire compensation circuit.

[0092] As an optional embodiment, it also includes:

[0093] The third current limiting module RX3 has its first end connected to the output end of the voltage regulator, and its second end connected to the source of the second NMOS transistor NM2 and the first end of the first current limiting module RX1.

[0094] It is easy to understand that, to avoid the direct impact of the regulator's output voltage on the source of the second NMOS transistor NM2, a third current-limiting module RX3 can be added between the regulator's output and the source of the second NMOS transistor NM2 to protect the second NMOS transistor NM2 and the compensation circuit. This application does not specifically limit the specific type and implementation of the third current-limiting module RX3. Figure 2 As shown, this can be achieved using a resistive element.

[0095] Specifically, the compensation circuit can be further protected by adding a third current limiting module RX3, avoiding the safety risks of the second NMOS transistor NM2 due to the large output voltage of the voltage regulator, and improving the safety and reliability of the second NMOS transistor NM2 and the compensation circuit.

[0096] As an optional embodiment, the first control submodule includes:

[0097] The fourth PMOS transistor, PM4, has its source connected to the power supply and its gate connected to the output of the input module. It is used to turn off the regulator based on the control of the input module when the output voltage of the regulator is greater than the upper limit of the target range.

[0098] The drain of the fourth NMOS transistor NM4 is connected to the drain of the fourth PMOS transistor PM4 and the gate of the first NMOS transistor NM1, respectively, and the gate is connected to a preset bias voltage.

[0099] The fourth current limiting module RX4 has its first terminal connected to the source of the fourth NMOS transistor NM4, and its second terminal grounded.

[0100] The fourth NMOS transistor NM4 remains on, and when the output voltage of the regulator is in the target range, the on-resistance of the fourth NMOS transistor NM4 is less than the on-resistance of the fourth PMOS transistor PM4.

[0101] Understandably, the first control submodule can specifically use a circuit built with MOS transistors to output different voltage signals, thereby controlling the conduction or cutoff of the first controllable switch 1. The gate of the fourth NMOS transistor NM4 is connected to a preset bias voltage, and its conduction state remains unchanged throughout the entire detection and compensation process. When the output voltage of the regulator is within the target range (or target voltage value), the on-resistance of the fourth NMOS transistor NM4 is less than that of the fourth PMOS transistor PM4, and the conduction degree of the fourth NMOS transistor NM4 is greater than that of the fourth PMOS transistor PM4. The output of the first control submodule is pulled low by the fourth NMOS transistor NM4, which has a greater conduction degree, to keep the first NMOS transistor NM1 off. When the output voltage of the regulator is too high, the fourth PMOS transistor PM4 is turned off, and the output of the first control submodule... The first control submodule's output terminal is pulled low by the fourth NMOS transistor NM4, which is turned on, to keep the first NMOS transistor NM1 off. When the regulator's output voltage is too low, the fourth PMOS transistor PM4's on-resistance decreases under the action of the input module. Its on-resistance will be less than that of the fourth NMOS transistor NM4, and its conduction degree will increase. Moreover, its conduction degree will be greater than that of the fourth NMOS transistor NM4. Therefore, the output terminal of the first control submodule will be pulled high by the fourth PMOS transistor with a greater conduction degree to turn on the first NMOS transistor NM1.

[0102] It should be noted that there are multiple ways to set the initial state where the on-resistance of the fourth NMOS transistor NM4 is less than that of the fourth PMOS transistor PM4. This application does not impose any particular limitation here. Specifically, the misalignment between the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4 can be achieved by reasonably setting the width-to-length ratio of the fourth NMOS transistor NM4 and / or the width-to-length ratio of the fourth PMOS transistor PM4. The larger the width-to-length ratio (W / L) of the MOS transistor, the smaller its on-resistance and the greater its conduction degree. At the same time, the fourth NMOS transistor NM4 and the second NMOS transistor NM2 in the input module form a current mirror structure, and the fourth PMOS transistor PM4 and the second PMOS transistor PM2 in the input module form a current mirror structure. The change in output voltage detected by the input module can be accurately transmitted to the first control submodule through the amplification of the current mirror. The drain current of the fourth NMOS transistor NM4 and / or the drain current of the fourth PMOS transistor PM4 can also be configured by configuring different replication ratios of these two sets of current mirrors, thereby realizing the setting of this initial state. Throughout the entire operation, the fourth NMOS transistor NM4 remains in a conducting state. Control of the first controllable switch 1 is achieved solely through the changes in the conduction level and operation of the fourth PMOS transistor PM4. This ensures a constant bias current in the first control submodule, enabling timely compensation for small voltage fluctuations. This application does not specifically limit the particular types and implementation methods of the fourth PMOS transistor PM4, the fourth NMOS transistor NM4, and the fourth current-limiting module RX4. The fourth current-limiting module RX4 limits the current in the first control submodule, preventing overcurrent and other abnormal situations. Figure 2 As shown, the fourth current limiting module RX4 can be implemented using a resistor.

[0103] As a specific embodiment, such as Figure 2As shown, when the load current of the voltage regulator increases, the output voltage VOUT of the voltage regulator decreases rapidly. After the current limiting effect of the third current limiting module RX3, the source voltage of the second NMOS transistor NM2 in the input module also decreases, resulting in a decrease in the on-resistance of the second NMOS transistor NM2 and an increase in its conduction degree. The increased conduction degree of the second NMOS transistor NM2 will further pull down the gate voltages of the second PMOS transistor PM2 and the fourth PMOS transistor PM4, controlling the conduction degree of the fourth PMOS transistor PM4 to increase. The drain of the fourth PMOS transistor PM4, that is, the gate voltage of the first NMOS transistor NM1, will be pulled up by the fourth PMOS transistor PM4 with a greater conduction degree, controlling the first NMOS transistor NM1 to conduct, thereby pulling down the gate voltage VG of the regulating transistor Q0, controlling the conduction degree of the regulating transistor Q0 to increase, and its output current increases rapidly, causing the output voltage of the voltage regulator to rise and return to a stable value. When the regulator's output voltage is within the target range (or target voltage value), the on-resistance of the fourth NMOS transistor NM4 is less than that of the fourth PMOS transistor PM4, and the conduction degree of the fourth NMOS transistor NM4 is greater than that of the fourth PMOS transistor PM4, pulling down the gate voltage of the first NMOS transistor NM1 and keeping the first NMOS transistor NM1 off. When the regulator's output voltage VOUT increases, the source voltage of the second NMOS transistor NM2 in the input module also increases, causing the on-resistance of the second NMOS transistor NM2 to increase, the conduction degree to decrease, or even to the point of being off, causing the second PMOS transistor PM2 to turn off. At the same time, the fourth PMOS transistor PM4 also turns off, and the gate voltage of the first NMOS transistor NM1 is pulled down by the conducting fourth NMOS transistor NM4, keeping the first NMOS transistor NM1 off.

[0104] Specifically, by configuring the on-resistance of the fourth NMOS transistor NM4 in the first control submodule to be less than that of the fourth PMOS transistor PM4 in the initial state, the first control submodule can control the first NMOS transistor NM1 to remain off when the output voltage of the regulator is in the target range or too high. Only when the output voltage of the regulator decreases will the first NMOS transistor NM1 be turned on, effectively realizing the function of controlling the output voltage to increase to restore the voltage when the output voltage decreases. The entire circuit structure is simple, easy to implement, and the components used are low in cost, small in size, and easy to integrate.

[0105] As an optional embodiment, the second control submodule includes:

[0106] The fifth PMOS transistor, PM5, has its source connected to the power supply and its gate connected to the output of the input module. It is used to turn off the regulator based on the control of the input module when the output voltage of the regulator is greater than the upper limit of the target range.

[0107] The drain of the fifth NMOS transistor NM5 is connected to the drain of the fifth PMOS transistor PM5 and the gate of the first PMOS transistor PM1, respectively, and the gate is connected to a preset bias voltage.

[0108] The fifth current limiting module RX5 has its first terminal connected to the source of the fifth NMOS transistor NM5, and its second terminal grounded.

[0109] The fifth NMOS transistor NM5 remains on, and when the output voltage of the regulator is in the target range, the on-resistance of the fifth NMOS transistor NM5 is greater than the on-resistance of the fifth PMOS transistor PM5.

[0110] It is understandable that the second control submodule can specifically use a circuit built with MOS transistors to output different voltage signals, thereby controlling the conduction or cutoff of the second controllable switch 2. The gate of the fifth NMOS transistor NM5 is connected to a preset bias voltage, and the conduction state of the fifth NMOS transistor NM5 remains unchanged throughout the entire detection and compensation process. When the regulator's output voltage is within the target range (or target voltage value), the on-resistance of the fifth NMOS transistor NM5 is greater than that of the fifth PMOS transistor PM5, and the conduction degree of the fifth NMOS transistor NM5 is less than that of the fifth PMOS transistor PM5. The output of the second control submodule is pulled high by the fifth PMOS transistor PM5, which has a greater conduction degree, to control the first PMOS transistor PM1 to remain off. When the regulator's output voltage is too high, the fifth PMOS transistor PM5 is turned off, and the output of the second control submodule is pulled low by the conducting fifth NMOS transistor NM5 to control the first PMOS transistor PM1 to conduct. When the regulator's output voltage is too low, the on-resistance of the fifth PMOS transistor PM5 decreases under the action of the input module, but it will still be less than the on-resistance of the fifth NMOS transistor NM5. The conduction degree increases, and it will be greater than that of the fifth NMOS transistor NM5. Therefore, the output of the second control submodule will be pulled high by the fifth PMOS transistor PM5, which has a greater conduction degree, to control the first PMOS transistor PM1 to turn off.

[0111] It should be noted that there are multiple ways to set the initial state where the on-resistance of the fifth NMOS transistor NM5 is greater than that of the fifth PMOS transistor PM5. This application does not impose any particular limitation here. Similar to the initial state settings of the fourth NMOS transistor NM4 and the fourth PMOS transistor PM4, it can be achieved by using a width-to-length ratio configuration or a current mirror replication ratio configuration, etc., which will not be elaborated further here. Specifically, the fifth NMOS transistor NM5 and the second NMOS transistor NM2 in the input module form a current mirror structure, and the fifth PMOS transistor PM5 and the second PMOS transistor PM2 in the input module also form a current mirror structure. Throughout the entire operation, the fifth NMOS transistor NM5 remains in a conducting state. The control of the second controllable switch 2 is achieved solely by the change in the conduction degree and action of the fifth PMOS transistor PM5, ensuring that a bias current always exists in the second control submodule, enabling timely response and compensation for small voltage fluctuations. This application does not specify the specific types and implementation methods of the fifth PMOS transistor PM5, the fifth NMOS transistor NM5, and the fifth current limiting module RX5. The fifth current limiting module RX5 can limit the current in the second control submodule to avoid abnormal situations such as overcurrent. Figure 2 As shown, the fifth current limiting module RX5 can be implemented using a resistor.

[0112] As a specific embodiment, such as Figure 2As shown, when the load current of the voltage regulator decreases, the output voltage VOUT of the voltage regulator increases. After the current limiting effect of the third current limiting module RX3, the source voltage of the second NMOS transistor NM2 in the input module also increases, causing the on-resistance of the second NMOS transistor NM2 to increase, the conduction degree to decrease, and even to the point of being turned off, causing the second PMOS transistor PM2 to turn off. At the same time, the fifth PMOS transistor PM5 also turns off. The gate voltage of the first PMOS transistor PM1 is pulled down by the conducting fifth NMOS transistor NM5, controlling the first PMOS transistor PM1 to conduct, thereby raising the gate voltage VG of the regulating transistor Q0, controlling the conduction degree of the regulating transistor Q0 to decrease, and its output current to decrease rapidly, so that the output voltage of the voltage regulator decreases to return to a stable value. When the regulator's output voltage is within the target range (or target voltage value), the on-resistance of the fifth NMOS transistor NM5 is greater than that of the fifth PMOS transistor PM5, and the conduction degree of the fifth NMOS transistor NM5 is less than that of the fifth PMOS transistor PM5. The gate voltage of the first PMOS transistor PM1 will be pulled up by the fifth PMOS transistor PM5, which has a greater conduction degree, thus keeping the first PMOS transistor PM1 off. When the regulator's output voltage VOUT decreases, the source voltage of the second NMOS transistor NM2 in the input module will also decrease, causing the on-resistance of the second NMOS transistor NM2 to decrease and its conduction degree to increase. The gate voltage of the second PMOS transistor PM2 will be quickly pulled down by the second NMOS transistor NM2, which has a greater conduction degree. The conduction degrees of the second PMOS transistor PM2 and the fifth PMOS transistor PM5 will increase, and the gate voltage of the first PMOS transistor PM1 will be pulled up by the fifth PMOS transistor PM5, which has a greater conduction degree, thus keeping the first PMOS transistor PM1 off.

[0113] Specifically, by configuring the on-resistance of the fifth NMOS transistor NM5 in the second control submodule to be greater than that of the fifth PMOS transistor PM5 in the initial state, the second control submodule can control the first PMOS transistor PM1 to remain off when the output voltage of the regulator is in the target range or too low. Only when the output voltage of the regulator increases will the first PMOS transistor PM1 be turned on, effectively realizing the function of controlling the output voltage to decrease to restore the voltage when the output voltage increases. The entire circuit structure is simple, easy to implement, and the components used are low in cost, small in size, and easy to integrate.

[0114] Further, see Figure 4 As shown, Figure 4 A schematic diagram illustrating the working effect of a compensation circuit provided by this utility model. The actual effect of the compensation circuit provided in this application when the voltage regulator is working is as follows: Figure 4As shown in the figure, the horizontal axis represents time and the vertical axis represents the output voltage of the voltage regulator. It can be seen from the figure that after adding a compensation circuit connected to the output terminal of the voltage regulator and the control terminal of the regulating tube therein, the compensation circuit can react quickly when the output voltage changes, and control the output voltage of the voltage regulator to recover to the target range (or target voltage value). By applying the compensation circuit provided in this application, the change time of the output voltage can be reduced, so as to achieve a fast response, quickly stabilize the output voltage, and reduce the recovery time.

[0115] To solve the above-mentioned technical problems, this utility model also provides a voltage regulator, including an adjustment tube, an error amplifier U0, and a compensation circuit as described above. The non-inverting input terminal of the error amplifier U0 is connected to a reference voltage Vref. The first terminal of the adjustment tube is connected to a preset power supply VDD, and the second terminal serves as the output terminal of the voltage regulator. It is also connected to the inverting input terminal of the error amplifier U0 and the input terminal of the compensation circuit, respectively. The control terminal is connected to the output terminal of the error amplifier U0 and the output terminal of the compensation circuit, respectively.

[0116] It should be noted that this application does not impose any particular limitations on the specific type and implementation method of the error amplifier U0 and its connected load in the voltage regulator. There are also multiple options for the specific implementation methods of the reference voltage Vref and the preset power supply VDD, which are not specifically limited here. Other circuit structures can also be set in the voltage regulator, such as... Figure 3 The voltage divider feedback structure shown, which consists of resistors R1 and R2 added to the output terminal, is not specifically limited in this application.

[0117] For a description of the voltage regulator provided by this utility model, please refer to the above-described embodiment of the compensation circuit; this utility model will not be described in detail here.

[0118] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should also be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0119] The above description of the disclosed embodiments enables those skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A compensation circuit, characterized in that, include: The first controllable switch is used to output a first voltage when it is turned on in order to control the on-resistance of the regulating tube in the voltage regulator to decrease by a first preset value. The second controllable switch is used to output a second voltage when it is turned on to control the on-resistance of the regulating tube to increase by a second preset value; The first controllable switch and the second controllable switch are connected in series, and the first end of the series circuit is connected to the power supply, while the second end is grounded. The control module has an input terminal connected to the output terminal of the voltage regulator, a first output terminal connected to the control terminal of the first controllable switch, and a second output terminal connected to the control terminal of the second controllable switch. It is used to control the operation of the first controllable switch and the second controllable switch based on the output voltage of the voltage regulator.

2. The compensation circuit according to claim 1, characterized in that, The control module includes: An input module, with its input terminal connected to the output terminal of the voltage regulator, is used to detect the output voltage of the voltage regulator. The first control submodule has an input terminal connected to the output terminal of the input module and an output terminal connected to the control terminal of the first controllable switch, and is used to control the operation of the first controllable switch based on the output voltage of the voltage regulator; The second control submodule has its input terminal connected to the output terminal of the input module and its output terminal connected to the control terminal of the second controllable switch. It is used to control the operation of the second controllable switch based on the output voltage of the voltage regulator.

3. The compensation circuit according to claim 2, characterized in that, The regulator's adjustment transistor is a PMOS transistor, the first controllable switch is a first NMOS transistor, and the second controllable switch is a first PMOS transistor; The source of the first NMOS transistor is grounded, and its gate is connected to the output terminal of the first control submodule. The source of the first PMOS transistor is connected to the power supply, the gate is connected to the output terminal of the second control submodule, and the drain is connected to the drain of the first NMOS transistor, serving as the output terminal of the compensation circuit.

4. The compensation circuit according to claim 3, characterized in that, The input module includes: The second PMOS transistor has its source connected to the power supply, and its gate serves as the output terminal of the input module. The drain of the second NMOS transistor is connected to the gate and the source of the second PMOS transistor, respectively, and the gate is connected to a preset bias voltage. The first current limiting module has its first terminal connected to the source of the second NMOS transistor and the output terminal of the voltage regulator, respectively, and its second terminal grounded. The second NMOS transistor is turned off when the output voltage of the regulator is greater than the upper limit of the target range, and turned on when the output voltage of the regulator is less than or equal to the upper limit of the target range; and the on-resistance of the first NMOS transistor is positively correlated with the output voltage of the regulator.

5. The compensation circuit according to claim 4, characterized in that, Also includes: The bias voltage generation module has its output terminal connected to the gate of the second NMOS transistor and is used to output a preset bias voltage.

6. The compensation circuit according to claim 5, characterized in that, The bias voltage generation module includes: The third PMOS transistor has its source connected to the power supply and its gate connected to the bias power supply. The drain of the third NMOS transistor is connected to the gate of the third NMOS transistor and the drain of the third PMOS transistor, respectively, and the gate serves as the output terminal of the bias voltage generation module. The second current limiting module has its first terminal connected to the source of the third NMOS transistor and its second terminal grounded. Both the third PMOS transistor and the third NMOS transistor remain in the on state.

7. The compensation circuit according to claim 6, characterized in that, Also includes: The third current limiting module has its first end connected to the output end of the voltage regulator, and its second end connected to the source of the second NMOS transistor and the first end of the first current limiting module, respectively.

8. The compensation circuit according to any one of claims 3 to 7, characterized in that, The first control submodule includes: The fourth PMOS transistor has its source connected to the power supply and its gate connected to the output terminal of the input module. It is used to turn off the voltage regulator based on the control of the input module when the output voltage of the regulator is greater than the upper limit of the target range. The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor and the gate of the first NMOS transistor, respectively, and the gate is connected to a preset bias voltage. The fourth current limiting module has its first terminal connected to the source of the fourth NMOS transistor and its second terminal grounded. The fourth NMOS transistor remains on, and when the output voltage of the regulator is within the target range, the on-resistance of the fourth NMOS transistor is less than that of the fourth PMOS transistor.

9. The compensation circuit according to claim 8, characterized in that, The second control submodule includes: The fifth PMOS transistor has its source connected to the power supply and its gate connected to the output terminal of the input module. It is used to turn off the voltage regulator based on the control of the input module when the output voltage of the regulator is greater than the upper limit of the target range. The drain of the fifth NMOS transistor is connected to the drain of the fifth PMOS transistor and the gate of the first PMOS transistor, respectively, and the gate is connected to a preset bias voltage. The fifth current limiting module has its first terminal connected to the source of the fifth NMOS transistor and its second terminal grounded. The fifth NMOS transistor remains on, and when the output voltage of the regulator is in the target range, the on-resistance of the fifth NMOS transistor is greater than that of the fifth PMOS transistor.

10. A voltage regulator, characterized in that, The device includes an adjustment transistor, an error amplifier, and a compensation circuit as described in any one of claims 1 to 9. The non-inverting input of the error amplifier is connected to a reference voltage. The first end of the adjustment transistor is connected to a preset power supply, and the second end serves as the output of a voltage regulator. The adjustment transistor is also connected to the inverting input of the error amplifier and the input of the compensation circuit. The control terminal is connected to the output of the error amplifier and the output of the compensation circuit.

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