Data storage device with electromagnetic interference protection

Abstract

The utility model discloses a data storage device of preventing electromagnetic interference belongs to data storage technical field, solved computer data memory in use, the electromagnetic field of high -speed data bus signal current generation and external strong electromagnetic field two -way coupling, destroy signal integrity, make digital signal timing jitter, superimposed noise, cause receiving end circuit misjudgment level, and the problem of data bit jump error of causing. Including address buffer module, control signal buffer module, data input buffer module, data write distribution module, three redundancy storage module. The utility model discloses through with data synchronous writing three independent storage array, and through majority decider real -time comparison three -way output data when reading, automatic output correct value, utilize error detection circuit positioning fault unit and trigger self -repair mechanism to rewrite correct data into error cell simultaneously, thereby realize to the real -time correction and self -repair of the transient error of electromagnetic interference.

Description

Technical Field

[0001] This utility model relates to the field of data storage technology, and in particular to a data storage device that is resistant to electromagnetic interference. Background Technology

[0002] Computer data storage devices are the core devices for storing and retrieving computer data. They are mainly divided into two categories: long-term storage and temporary storage. Long-term storage commonly uses mechanical hard drives and solid-state drives (SSDs) to save files, software, etc.; temporary storage relies on RAM, which allows programs to quickly access data during runtime and is cleared when power is off. It offers stable read and write operations, high data security, and is suitable for daily file storage and software operation needs, making it a key component for ensuring the normal operation of a computer.

[0003] During computer data storage, the signal current on the high-speed data bus generates an electromagnetic field, and strong external electromagnetic fields can also be induced on these lines. This bidirectional electromagnetic coupling effect is difficult to completely eliminate, leading to the destruction of signal integrity, jitter in the timing of digital signals during transmission, and the superposition of noise on the waveform. This causes the receiving circuit to incorrectly interpret a high level as a low level or vice versa, resulting in data bit transition errors. If this problem occurs during the writing process, it will cause erroneous data to be stored in the storage unit. If it occurs during the reading process, it will send erroneous data to the processor. The ultimate consequences are program errors, abnormal application process crashes, serious operating system errors leading to system crashes, and even damage or loss of stored files.

[0004] Therefore, a data storage device that is resistant to electromagnetic interference is proposed to solve or alleviate the above problems. Utility Model Content

[0005] The purpose of this invention is to address the shortcomings of existing technologies by proposing a data storage device that is resistant to electromagnetic interference.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] An electromagnetic interference-resistant data storage device includes an address buffer module, a control signal buffer module, a data input buffer module, a data write allocation module, a triple-redundant storage module, a majority voting module, an error detection and location module, a self-repair control module, and an output selection module.

[0008] The address signal input terminal of the address buffer module is used to connect to an external address pin. The first address output terminal of the address buffer module is connected to the first address input terminal of the triple redundant storage module. The second address output terminal of the address buffer module is connected to the second address input terminal of the triple redundant storage module. The third address output terminal of the address buffer module is connected to the third address input terminal of the triple redundant storage module.

[0009] The control signal input terminal of the control signal buffer module is used to connect to an external control pin. The first control signal output terminal of the control signal buffer module is connected to the first control signal input terminal of the triple redundant storage module. The second control signal output terminal of the control signal buffer module is connected to the second control signal input terminal of the triple redundant storage module. The third control signal output terminal of the control signal buffer module is connected to the third control signal input terminal of the triple redundant storage module.

[0010] The data input terminal of the data input buffer module is used to connect to an external bidirectional data pin, and the data output terminal of the data input buffer module is connected to the data input terminal of the data writing and allocation module.

[0011] The first data output terminal of the data write allocation module is connected to the first data write input terminal of the triple redundant storage module, the second data output terminal of the data write allocation module is connected to the second data write input terminal of the triple redundant storage module, and the third data output terminal of the data write allocation module is connected to the third data write input terminal of the triple redundant storage module.

[0012] The first data read output terminal of the triple redundant storage module is connected to the first data input terminal of the majority voting module and the first data input terminal of the error detection and location module. The second data read output terminal of the triple redundant storage module is simultaneously connected to the second data input terminal of the majority voting module and the second data input terminal of the error detection and location module. The third data read output terminal of the triple redundant storage module is connected to the third data input terminal of the majority voting module and the third data input terminal of the error detection and location module.

[0013] The data output terminal of the majority voting module is connected to the correct data input terminal of the error detection and location module and the first data input terminal of the output selection module;

[0014] The error flag output terminal of the error detection and location module is used to connect to an external error flag pin, the error array identifier output terminal of the error detection and location module is used to connect to an external error array identifier pin, the first error signal output terminal of the error detection and location module is connected to the first error signal input terminal of the self-repair control module, the second error signal output terminal of the error detection and location module is connected to the second error signal input terminal of the self-repair control module, and the third error signal output terminal of the error detection and location module is connected to the third error signal input terminal of the self-repair control module.

[0015] The first write control output terminal of the self-repair control module is connected to the first local write enable terminal of the triple redundant storage module, the second write control output terminal of the self-repair control module is connected to the second local write enable terminal of the triple redundant storage module, and the third write control output terminal of the self-repair control module is connected to the third local write enable terminal of the triple redundant storage module.

[0016] The data output terminal of the output selection module is connected to an external bidirectional data pin, and the channel selection terminal of the output selection module is connected to an external diagnostic enable pin.

[0017] Preferably, the address buffer module includes multiple address buffer units, each address buffer unit including a first input buffer 74LVC1 G125 and three input buffers 74LVC1 G34. The input terminal of the first input buffer 74LVC1 G125 is used to connect to the corresponding address pin in the external address pins. The output terminal of the first input buffer 74LVC1 G125 is connected to the input terminals of the first input buffer 74LVC1 G34, the second input buffer 74LVC1 G34, and the third input buffer 74LVC1 G34. The output terminal of the first input buffer 74LVC1 G34 is configured as the first address output terminal of the address buffer module and connected to the first address input terminal of the triple redundant storage module. The output terminal of the second input buffer 74LVC1 G34 is configured as the second address output terminal of the address buffer module and connected to the second address input terminal of the triple redundant storage module. The output terminal of the third input buffer 74LVC1 G34 is configured as the third address output terminal of the address buffer module and connected to the third address input terminal of the triple redundant storage module.

[0018] Preferably, the control signal buffer module includes multiple control signal buffer units. Each control signal buffer unit includes a second input buffer 74LVC1 G125, a fourth output buffer 74LVC1 G34, a fifth output buffer 74LVC1 G34, and a sixth output buffer 74LVC1 G34. The input terminal of the second input buffer 74LVC1 G125 is used to connect to the corresponding control pin in the external control pins. The output terminal of the second input buffer 74LVC1 G125 is simultaneously connected to the input terminals of the fourth output buffer 74LVC1 G34, the fifth output buffer 74LVC1 G34, and the sixth output buffer 74LVC1 G34. The output terminal of the fourth output buffer 74LVC1 G34 is configured as the first control signal output terminal of the control signal buffer module, connected to the first control signal input terminal of the triple redundant storage module. The output terminal of the fifth output buffer 74LVC1 G34 is configured as the second control signal output terminal of the control signal buffer module, connected to the second control signal input terminal of the triple redundant storage module. The sixth output buffer 74LVC1 G125... The output of G34 is configured as the third control signal output of the control signal buffer module, which is connected to the third control signal input of the triple redundant storage module.

[0019] Preferably, the data input buffer module includes an input buffer 74LVC245 and an output enable controller 74LVC1 G00. The input terminal of the input buffer 74LVC245 is used to connect to an external bidirectional data pin, and the output terminal of the input buffer 74LVC245 is connected to the data input terminal of the data writing and allocation module. The input terminal of the output enable controller 74LVC1 G00 is connected to an external output enable pin, and the output terminal of the output enable controller 74LVC1 G00 is connected to the enable terminal of the input buffer 74LVC245. When the output enable signal is valid, the input buffer 74LVC245 is in a high-impedance state and allows data to be output from the memory.

[0020] Preferably, the data write allocation module includes multiple data allocation units. Each data allocation unit includes a third input buffer 74LVC1 G125, a seventh output buffer 74LVC1 G34, an eighth output buffer 74LVC1 G34, and a ninth output buffer 74LVC1 G34. The input terminal of the third input buffer 74LVC1 G125 is connected to the corresponding data bit in the data output terminal of the data input buffer module. The output terminal of the third input buffer 74LVC1 G125 is simultaneously connected to the input terminals of the seventh output buffer 74LVC1 G34, the eighth output buffer 74LVC1 G34, and the ninth output buffer 74LVC1 G34. The output terminal of the seventh output buffer 74LVC1 G34 is configured as the first data output terminal of the data write allocation module and connected to the first data write input terminal of the triple redundant storage module. The output terminal of the eighth output buffer 74LVC1 G34 is configured as the second data output terminal of the data write allocation module and connected to the second data write input terminal of the triple redundant storage module. The ninth output buffer 74LVC1 G125... The output of G34 is configured as the third data output of the data write distribution module, connected to the third data write input of the triple redundant storage module.

[0021] Preferably, the triple-redundant storage module includes a first storage array, a second storage array, a third storage array, a first read latch 74LVC373, a second read latch 74LVC373, and a third read latch 74LVC373. The first, second, and third storage arrays all use IS61WV51216BLL-10TLI high-speed asynchronous SRAM chips. The address input terminal of the first storage array is connected to the first address output terminal of the address buffer module. The control signal input terminal of the first storage array is connected to the first control signal output terminal of the control signal buffer module. The data write input terminal of the first storage array is connected to the first data output terminal of the data write allocation module. The data read output terminal of the first storage array is connected to the data input terminal of the first read latch 74LVC373. The address input terminal of the second storage array is connected to the second address output terminal of the address buffer module. The control signal input terminal of the second storage array is connected to the second control signal output terminal of the control signal buffer module. The data write input terminal of the second storage array is connected to the first data output terminal of the data write allocation module. The second data output terminal of the write allocation module is connected to the data input terminal of the second read latch 74LVC373. The address input terminal of the third storage array is connected to the third address output terminal of the address buffer module. The control signal input terminal of the third storage array is connected to the third control signal output terminal of the control signal buffer module. The data write input terminal of the third storage array is connected to the third data output terminal of the write allocation module. The data read output terminal of the third storage array is connected to the data input terminal of the third read latch 74LVC373. The data output terminal of the first read latch 74LVC373 is connected to the first data input terminal of the majority voting module and the first data input terminal of the error detection and location module. The data output terminal of the second read latch 74LVC373 is connected to the second data input terminal of the majority voting module and the second data input terminal of the error detection and location module. The data output terminal of the third read latch 74LVC373 is connected to the third data input terminal of the majority voting module and the third data input terminal of the error detection and location module.

[0022] Preferably, the majority voting module includes multiple majority voting units. Each majority voting unit includes a first AND gate 74LVC08, a second AND gate 74LVC08, a third AND gate 74LVC08, and an OR gate 74LVC32. The first input of the first AND gate 74LVC08 is connected to the data output of the first read latch. The second input of the first AND gate 74LVC08 is connected to the data output of the second read latch 74LVC373 in the triple-redundant memory module. The first input of the second AND gate 74LVC08 is connected to the data output of the first read latch. The second input of the second AND gate 74LVC08 is connected to the data output of the third read latch 74LVC373 in the triple-redundant memory module. According to the output terminal, the first input terminal of the third AND gate circuit 74LVC08 is connected to the data output terminal of the second read latch, the second input terminal of the third AND gate circuit 74LVC08 is connected to the data output terminal of the third read latch 74LVC373 in the triple redundant storage module, the first input terminal of the OR gate circuit 74LVC32 is connected to the output terminal of the first AND gate circuit 74LVC08, the second input terminal of the OR gate circuit 74LVC32 is connected to the output terminal of the second AND gate circuit 74LVC08, the third input terminal of the OR gate circuit 74LVC32 is connected to the output terminal of the third AND gate circuit 74LVC08, and the output terminal of the OR gate circuit 74LVC32 is connected to the correct data input terminal of the error detection and location module and the first data input terminal of the output selection module.

[0023] Preferably, the error detection and localization module includes multiple error detection units and a priority encoder 74HC148. Each error detection unit includes a first XOR gate circuit 74LVC86, a second XOR gate circuit 74LVC86, and a third XOR gate circuit 74LVC86. The first input of the first XOR gate circuit 74LVC86 is connected to the data output of a first read latch, and the second input of the first XOR gate circuit 74LVC86 is connected to the data output of a majority voting module. The output of the first XOR gate circuit 74LVC86 generates a first error signal. The first input of the second XOR gate circuit 74LVC86 is connected to the data output of a second read latch, and the second input of the second XOR gate circuit 74LVC86 is connected to the data output of a majority voting module. The output of the second XOR gate circuit 74LVC86 generates a second error signal. The third XOR gate circuit 74LVC86 generates a second error signal. The first input of the XOR gate circuit 74LVC86 is connected to the data output of the third read latch. The second input of the third XOR gate circuit 74LVC86 is connected to the data output of the majority voting module. The output of the third XOR gate circuit 74LVC86 generates a third error signal. The first set of inputs of the priority encoder 74HC148 is connected to the output of the first XOR gate circuit 74LVC86. The second set of inputs of the priority encoder 74HC148 is connected to the outputs of all second XOR gate circuits 74LVC86. The third set of inputs of the priority encoder 74HC148 is connected to the outputs of all third XOR gate circuits 74LVC86. The error flag output of the priority encoder 74HC148 is used to connect to an external error flag pin. The error array identifier output of the priority encoder 74HC148 is used to connect to an external error array identifier pin.

[0024] Preferably, the self-repair control module includes a first write control unit, a second write control unit, and a third write control unit. All three units are 74LVC74 dual D-type flip-flops. The input of the first write control unit is connected to the first error signal output of the error detection and location module, and its output is connected to the local write enable of the first storage array in the triple redundant storage module. The input of the second write control unit is connected to the second error signal output of the error detection and location module, and its output is connected to the local write enable of the second storage array in the triple redundant storage module. The input of the third write control unit is connected to the third error signal output of the error detection and location module, and its output is connected to the local write enable of the third storage array in the triple redundant storage module.

[0025] Preferably, the output selection module includes a 74LVC257 data selector and a 74LVC245 output multiplexer. The first input of the 74LVC257 data selector is connected to the data output of a first read latch. The second input of the 74LVC257 data selector is connected to the data output of a second read latch. The third input of the 74LVC257 data selector is connected to the data output of a third read latch. The channel selection terminal of the 74LVC257 data selector is connected to an external array selection pin. The output of the 74LVC257 data selector is connected to the second input of the 74LVC245 output multiplexer. The first input of the 74LVC245 output multiplexer is connected to the data output of a majority voting module. The channel selection terminal of the 74LVC245 output multiplexer is used to connect to an external diagnostic enable pin. The output of the 74LVC245 output multiplexer is connected to an external bidirectional data pin through a data output driver.

[0026] This utility model has the following beneficial effects:

[0027] This invention synchronously writes data into three independent storage arrays and compares the three output data in real time through a majority voter during reading, automatically outputting the correct value. At the same time, it uses an error detection circuit to locate the faulty unit and triggers a self-repair mechanism to rewrite the correct data into the faulty unit, thereby achieving real-time correction and self-repair of transient errors caused by electromagnetic interference. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a structural block diagram of the present invention.

[0030] In the diagram: 1. Address buffer module; 2. Control signal buffer module; 3. Data input buffer module; 4. Data write allocation module; 5. Triple redundancy storage module; 6. Majority voting module; 7. Error detection and location module; 8. Self-repair control module; 9. Output selection module. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0033] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0034] In the description of this utility model, it should be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the utility model product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this utility model and to simplify the description, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.

[0035] Furthermore, the terms "first," "second," and "third" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0036] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0037] A data storage device resistant to electromagnetic interference, such as Figure 1As shown, it includes address buffer module 1, control signal buffer module 2, data input buffer module 3, data write allocation module 4, triple redundancy storage module 5, majority voting module 6, error detection and location module 7, self-repair control module 8, and output selection module 9.

[0038] The address signal input terminal of the address buffer module 1 is used to connect to an external address pin. The first address output terminal of the address buffer module 1 is connected to the first address input terminal of the triple redundant storage module 5. The second address output terminal of the address buffer module 1 is connected to the second address input terminal of the triple redundant storage module 5. The third address output terminal of the address buffer module 1 is connected to the third address input terminal of the triple redundant storage module 5.

[0039] The control signal input terminal of the control signal buffer module 2 is used to connect to an external control pin. The first control signal output terminal of the control signal buffer module 2 is connected to the first control signal input terminal of the triple redundant storage module 5. The second control signal output terminal of the control signal buffer module 2 is connected to the second control signal input terminal of the triple redundant storage module 5. The third control signal output terminal of the control signal buffer module 2 is connected to the third control signal input terminal of the triple redundant storage module 5.

[0040] The data input terminal of the data input buffer module 3 is used to connect to an external bidirectional data pin, and the data output terminal of the data input buffer module 3 is connected to the data input terminal of the data writing and distribution module 4.

[0041] The first data output terminal of the data write allocation module 4 is connected to the first data write input terminal of the triple redundant storage module 5, the second data output terminal of the data write allocation module 4 is connected to the second data write input terminal of the triple redundant storage module 5, and the third data output terminal of the data write allocation module 4 is connected to the third data write input terminal of the triple redundant storage module 5.

[0042] The first data read output terminal of the triple redundant storage module 5 is connected to the first data input terminal of the majority voting module 6 and the first data input terminal of the error detection and location module 7. The second data read output terminal of the triple redundant storage module 5 is simultaneously connected to the second data input terminal of the majority voting module 6 and the second data input terminal of the error detection and location module 7. The third data read output terminal of the triple redundant storage module 5 is connected to the third data input terminal of the majority voting module 6 and the third data input terminal of the error detection and location module 7.

[0043] The data output terminal of the majority voting module 6 is connected to the correct data input terminal of the error detection and location module 7 and the first data input terminal of the output selection module 9;

[0044] The error flag output terminal of the error detection and location module 7 is used to connect to an external error flag pin, the error array identifier output terminal of the error detection and location module 7 is used to connect to an external error array identifier pin, the first error signal output terminal of the error detection and location module 7 is connected to the first error signal input terminal of the self-repair control module 8, the second error signal output terminal of the error detection and location module 7 is connected to the second error signal input terminal of the self-repair control module 8, and the third error signal output terminal of the error detection and location module 7 is connected to the third error signal input terminal of the self-repair control module 8.

[0045] The first write control output terminal of the self-repair control module 8 is connected to the first local write enable terminal of the triple redundant storage module 5, the second write control output terminal of the self-repair control module 8 is connected to the second local write enable terminal of the triple redundant storage module 5, and the third write control output terminal of the self-repair control module 8 is connected to the third local write enable terminal of the triple redundant storage module 5.

[0046] The data output terminal of the output selection module 9 is connected to an external bidirectional data pin, and the channel selection terminal of the output selection module 9 is connected to an external diagnostic enable pin.

[0047] Address buffer module 1 includes multiple address buffer units. Each address buffer unit includes a first input buffer 74LVC1 G125 and three input buffers 74LVC1 G34. The input terminal of the first input buffer 74LVC1 G125 is used to connect to the corresponding address pin in the external address pin. The output terminal of the first input buffer 74LVC1 G125 is connected to the input terminal of the first input buffer 74LVC1 G34, the input terminal of the second input buffer 74LVC1 G34, and the input terminal of the third input buffer 74LVC1 G34. The output terminal of the first input buffer 74LVC1 G34 is configured as the first address output terminal of address buffer module 1 and connected to the first address input terminal of triple redundant storage module 5. The output terminal of the second input buffer 74LVC1 G34 is configured as the second address output terminal of address buffer module 1 and connected to the second address input terminal of triple redundant storage module 5. The output terminal of the third input buffer 74LVC1 G34 is configured as the third address output terminal of address buffer module 1 and connected to the third address input terminal of triple redundant storage module 5.

[0048] The control signal buffer module 2 includes multiple control signal buffer units. Each control signal buffer unit includes a second input buffer 74LVC1 G125, a fourth output buffer 74LVC1 G34, a fifth output buffer 74LVC1 G34, and a sixth output buffer 74LVC1 G34. The input terminal of the second input buffer 74LVC1 G125 is used to connect to the corresponding control pin in the external control pins. The output terminal of the second input buffer 74LVC1 G125 is simultaneously connected to the input terminals of the fourth, fifth, and sixth output buffers 74LVC1 G34. The output terminal of the fourth output buffer 74LVC1 G34 is configured as the first control signal output terminal of the control signal buffer module 2, connected to the first control signal input terminal of the triple redundant storage module 5. The output terminal of the fifth output buffer 74LVC1 G34 is configured as the second control signal output terminal of the control signal buffer module 2, connected to the second control signal input terminal of the triple redundant storage module 5. The sixth output buffer 74LVC1 G125... The output of G34 is configured as the third control signal output of the control signal buffer module 2, which is connected to the third control signal input of the triple redundant storage module 5.

[0049] The data input buffer module 3 includes an input buffer 74LVC245 and an output enable controller 74LVC1 G00. The input terminal of the input buffer 74LVC245 is used to connect to an external bidirectional data pin, and the output terminal of the input buffer 74LVC245 is connected to the data input terminal of the data writing and distribution module 4. The input terminal of the output enable controller 74LVC1 G00 is connected to an external output enable pin, and the output terminal of the output enable controller 74LVC1 G00 is connected to the enable terminal of the input buffer 74LVC245. When the output enable signal is valid, the input buffer 74LVC245 is in a high-impedance state and allows data to be output from the memory.

[0050] The data write allocation module 4 includes multiple data allocation units. Each data allocation unit includes a third input buffer 74LVC1 G125, a seventh output buffer 74LVC1 G34, an eighth output buffer 74LVC1 G34, and a ninth output buffer 74LVC1 G34. The input terminal of the third input buffer 74LVC1 G125 is connected to the corresponding data bit in the data output terminal of the data input buffer module 3. The output terminal of the third input buffer 74LVC1 G125 is simultaneously connected to the input terminals of the seventh, eighth, and ninth output buffers 74LVC1 G34. The output terminal of the seventh output buffer 74LVC1 G34 is configured as the first data output terminal of the data write allocation module 4 and connected to the first data write input terminal of the triple redundant storage module 5. The output terminal of the eighth output buffer 74LVC1 G34 is configured as the second data output terminal of the data write allocation module 4 and connected to the second data write input terminal of the triple redundant storage module 5. The ninth output buffer 74LVC1 G125 is configured as the second data output terminal of the data write allocation module 4 and connected to the second data write input terminal of the triple redundant storage module 5. The output of G34 is configured to connect the third data output of the data writing allocation module 4 to the third data writing input of the triple redundant storage module 5.

[0051] The triple-redundant storage module 5 includes a first storage array, a second storage array, a third storage array, a first read latch 74LVC373, a second read latch 74LVC373, and a third read latch 74LVC373. All three storage arrays utilize IS61WV51216BLL-10TLI high-speed asynchronous SRAM chips. The address input of the first storage array is connected to the first address output of the address buffer module 1. The control signal input of the first storage array is connected to the first control signal output of the control signal buffer module 2. The data write input of the first storage array is connected to the first data output of the data write allocation module 4. The data read output of the first storage array is connected to the data input of the first read latch 74LVC373. The address input of the second storage array is connected to the second address output of the address buffer module 1. The control signal input of the second storage array is connected to the second control signal output of the control signal buffer module 2. The data write input of the second storage array is connected to the data write allocation module 4. The second data output terminal of module 4 and the data read output terminal of the second storage array are connected to the data input terminal of the second read latch 74LVC373. The address input terminal of the third storage array is connected to the third address output terminal of the address buffer module 1. The control signal input terminal of the third storage array is connected to the third control signal output terminal of the control signal buffer module 2. The data write input terminal of the third storage array is connected to the third data output terminal of the data write allocation module 4. The data read output terminal of the third storage array is connected to the data input terminal of the third read latch 74LVC373. The data output terminal of the first read latch 74LVC373 is connected to the first data input terminal of the majority voting module 6 and the first data input terminal of the error detection and location module 7. The data output terminal of the second read latch 74LVC373 is connected to the second data input terminal of the majority voting module 6 and the second data input terminal of the error detection and location module 7. The data output terminal of the third read latch 74LVC373 is connected to the third data input terminal of the majority voting module 6 and the third data input terminal of the error detection and location module 7.

[0052] Majority voting module 6 includes multiple majority voting units. Each majority voting unit includes a first AND gate 74LVC08, a second AND gate 74LVC08, a third AND gate 74LVC08, and an OR gate 74LVC32. The first input of the first AND gate 74LVC08 is connected to the data output of the first read latch. The second input of the first AND gate 74LVC08 is connected to the data output of the second read latch 74LVC373 in the triple redundancy storage module 5. The first input of the second AND gate 74LVC08 is connected to the data output of the first read latch. The second input of the second AND gate 74LVC08 is connected to the data output of the third read latch 74LVC373 in the triple redundancy storage module 5. At the output terminals, the first input terminal of the third AND gate circuit 74LVC08 is connected to the data output terminal of the second read latch, the second input terminal of the third AND gate circuit 74LVC08 is connected to the data output terminal of the third read latch 74LVC373 in the triple redundant storage module 5, the first input terminal of the OR gate circuit 74LVC32 is connected to the output terminal of the first AND gate circuit 74LVC08, the second input terminal of the OR gate circuit 74LVC32 is connected to the output terminal of the second AND gate circuit 74LVC08, the third input terminal of the OR gate circuit 74LVC32 is connected to the output terminal of the third AND gate circuit 74LVC08, and the output terminal of the OR gate circuit 74LVC32 is connected to the correct data input terminal of the error detection and location module 7 and the first data input terminal of the output selection module 9.

[0053] Error detection and localization module 7 includes multiple error detection units and a priority encoder 74HC148. Each error detection unit includes a first XOR gate circuit 74LVC86, a second XOR gate circuit 74LVC86, and a third XOR gate circuit 74LVC86. The first input of the first XOR gate circuit 74LVC86 is connected to the data output of the first read latch, and the second input is connected to the data output of the majority voting module 6. The output of the first XOR gate circuit 74LVC86 generates a first error signal. The first input of the second XOR gate circuit 74LVC86 is connected to the data output of the second read latch, and the second input is connected to the data output of the majority voting module 6. The output of the second XOR gate circuit 74LVC86 generates a second error signal. The third XOR gate circuit 74LVC86 generates a second error signal. The first input of the gate circuit 74LVC86 is connected to the data output of the third read latch. The second input of the third XOR gate circuit 74LVC86 is connected to the data output of the majority voting module 6. The output of the third XOR gate circuit 74LVC86 generates the third error signal. The first set of inputs of the priority encoder 74HC148 is connected to the output of the first XOR gate circuit 74LVC86. The second set of inputs of the priority encoder 74HC148 is connected to the outputs of all the second XOR gate circuits 74LVC86. The third set of inputs of the priority encoder 74HC148 is connected to the outputs of all the third XOR gate circuits 74LVC86. The error flag output of the priority encoder 74HC148 is used to connect to the external error flag pin. The error array identifier output of the priority encoder 74HC148 is used to connect to the external error array identifier pin.

[0054] The self-repair control module 8 includes a first write control unit, a second write control unit, and a third write control unit. All three write control units are 74LVC74 dual D-type flip-flops. The input of the first write control unit is connected to the first error signal output of the error detection and location module 7, and the output of the first write control unit is connected to the local write enable of the first storage array in the triple redundant storage module 5. The input of the second write control unit is connected to the second error signal output of the error detection and location module 7, and the output of the second write control unit is connected to the local write enable of the second storage array in the triple redundant storage module 5. The input of the third write control unit is connected to the third error signal output of the error detection and location module 7, and the output of the third write control unit is connected to the local write enable of the third storage array in the triple redundant storage module 5.

[0055] Output selection module 9 includes a 74LVC257 data selector and a 74LVC245 output multiplexer. The first input of the 74LVC257 data selector is connected to the data output of the first read latch. The second input of the 74LVC257 data selector is connected to the data output of the second read latch. The third input of the 74LVC257 data selector is connected to the data output of the third read latch. The channel selection terminal of the 74LVC257 data selector is connected to an external array selection pin. The output of the 74LVC257 data selector is connected to the second input of the 74LVC245 output multiplexer. The first input of the 74LVC245 output multiplexer is connected to the data output of the majority voting module 6. The channel selection terminal of the 74LVC245 output multiplexer is used to connect to an external diagnostic enable pin. The output of the 74LVC245 output multiplexer is connected to an external bidirectional data pin through a data output driver.

[0056] When this data storage device is in operation, when an external processor needs to store data, the address signal is synchronously distributed to the address decoding terminals of the three independent storage arrays through the address buffer module 1, and the control signal is synchronously sent to the control terminals of each array through the control signal buffer module 2. After the data to be stored enters the data write distribution network through the data input buffer module 3, it is simultaneously copied into three identical copies and written to the same physical address unit of the first, second and third storage arrays respectively. This triple redundancy storage architecture lays a solid foundation for the subsequent error tolerance mechanism.

[0057] During the data reading phase, when the processor issues a read request, the three memory arrays synchronously start the read operation. The inductive amplifiers of each array convert the charge signal in the memory cell into a digital level signal. The data read by the three arrays are temporarily stored in the corresponding first, second and third read latches, and then these three data are sent in parallel to the three input terminals of the majority voting module 6.

[0058] The majority voting module 6 consists of multiple parallel logic gate units. Each unit contains three AND gates and one OR gate, which calculate the consistency of any two of the three data paths and output the majority voting result through the OR gate. This process can complete real-time error correction in nanoseconds, ensuring that the output result remains correct as long as no more than one memory unit is corrupted.

[0059] At the same time, the error detection and location module 7 synchronously receives three channels of read data and the majority voting result. Each bit unit inside it contains three XOR gates, which compare each array data with the correct data. When an array data is found to be inconsistent with the voting result, the corresponding XOR gate outputs a high-level error signal. The error signals of all bits are collected to the priority encoder. The encoder outputs the specific error array number and reports it to the outside through the error array identification pin. At the same time, the global error flag pin is set to the valid state.

[0060] The self-repair control module 8 continuously monitors error signals. When an error is detected in a certain array, it will automatically start the repair sequence after the current read cycle ends. The correct data generated by the majority voter will be rewritten to the corresponding address unit of the faulty memory array. This write-back operation is achieved by controlling the local write enable terminal of the corresponding array, making the error repair process completely transparent to the processor and not affecting the continuous operation of the system.

[0061] In addition, when the external diagnostic enable pin is active, the output selection module 9 switches to diagnostic mode, allowing raw data from any memory array to be read directly via the array selection pin, which facilitates maintenance and fault analysis.

[0062] Throughout the entire operation, the data output path is always protected. In normal mode, the output selection module 9 directly selects the majority voting result as the final output, ensuring that the processor always obtains the correct data. In special mode, the original data can be accessed through the diagnostic interface.

[0063] This architecture effectively overcomes signal integrity issues caused by electromagnetic interference. Through hardware-level real-time error correction and self-repair mechanisms, it achieves high reliability of data storage while maintaining interface timing compatible with traditional memory, providing stable data storage assurance for critical application areas.

[0064] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A data storage device resistant to electromagnetic interference, characterized in that, It includes an address buffer module (1), a control signal buffer module (2), a data input buffer module (3), a data write allocation module (4), a triple redundancy storage module (5), a majority voting module (6), an error detection and location module (7), a self-repair control module (8), and an output selection module (9); The address signal input terminal of the address buffer module (1) is used to connect to an external address pin. The first address output terminal of the address buffer module (1) is connected to the first address input terminal of the triple redundant storage module (5). The second address output terminal of the address buffer module (1) is connected to the second address input terminal of the triple redundant storage module (5). The third address output terminal of the address buffer module (1) is connected to the third address input terminal of the triple redundant storage module (5). The control signal input terminal of the control signal buffer module (2) is used to connect to an external control pin. The first control signal output terminal of the control signal buffer module (2) is connected to the first control signal input terminal of the triple redundant storage module (5). The second control signal output terminal of the control signal buffer module (2) is connected to the second control signal input terminal of the triple redundant storage module (5). The third control signal output terminal of the control signal buffer module (2) is connected to the third control signal input terminal of the triple redundant storage module (5). The data input terminal of the data input buffer module (3) is used to connect to an external bidirectional data pin, and the data output terminal of the data input buffer module (3) is connected to the data input terminal of the data writing and allocation module (4). The first data output terminal of the data writing allocation module (4) is connected to the first data writing input terminal of the triple redundant storage module (5), the second data output terminal of the data writing allocation module (4) is connected to the second data writing input terminal of the triple redundant storage module (5), and the third data output terminal of the data writing allocation module (4) is connected to the third data writing input terminal of the triple redundant storage module (5). The first data read output terminal of the triple redundant storage module (5) is connected to the first data input terminal of the majority voting module (6) and the first data input terminal of the error detection and location module (7). The second data read output terminal of the triple redundant storage module (5) is simultaneously connected to the second data input terminal of the majority voting module (6) and the second data input terminal of the error detection and location module (7). The third data read output terminal of the triple redundant storage module (5) is connected to the third data input terminal of the majority voting module (6) and the third data input terminal of the error detection and location module (7). The data output terminal of the majority voting module (6) is connected to the correct data input terminal of the error detection and location module (7) and the first data input terminal of the output selection module (9); The error flag output terminal of the error detection and positioning module (7) is used to connect to an external error flag pin. The error array identifier output terminal of the error detection and positioning module (7) is used to connect to an external error array identifier pin. The first error signal output terminal of the error detection and positioning module (7) is connected to the first error signal input terminal of the self-repair control module (8). The second error signal output terminal of the error detection and positioning module (7) is connected to the second error signal input terminal of the self-repair control module (8). The third error signal output terminal of the error detection and positioning module (7) is connected to the third error signal input terminal of the self-repair control module (8). The first write control output terminal of the self-repair control module (8) is connected to the first local write enable terminal of the triple redundant storage module (5), the second write control output terminal of the self-repair control module (8) is connected to the second local write enable terminal of the triple redundant storage module (5), and the third write control output terminal of the self-repair control module (8) is connected to the third local write enable terminal of the triple redundant storage module (5). The data output terminal of the output selection module (9) is connected to an external bidirectional data pin, and the channel selection terminal of the output selection module (9) is connected to an external diagnostic enable pin.

2. The data storage device for electromagnetic interference protection according to claim 1, characterized in that, The address buffer module (1) includes multiple address buffer units. Each address buffer unit includes a first input buffer 74LVC1G125 and three input buffers 74LVC1 G34. The input terminal of the first input buffer 74LVC1 G125 is used to connect to the corresponding address pin in the external address pin. The output terminal of the first input buffer 74LVC1 G125 is connected to the input terminal of the first input buffer 74LVC1 G34, the input terminal of the second input buffer 74LVC1 G34, and the input terminal of the third input buffer 74LVC1 G34. The output terminal of the first input buffer 74LVC1 G34 is configured as the first address output terminal of the address buffer module (1) and connected to the first address input terminal of the triple redundant storage module (5). The output terminal of the second input buffer 74LVC1 G34 is configured as the second address output terminal of the address buffer module (1) and connected to the second address input terminal of the triple redundant storage module (5). The output terminal of the third input buffer 74LVC1 G34 is configured as the third address output terminal of the address buffer module (1) and connected to the third address input terminal of the triple redundant storage module (5).

3. The data storage device for electromagnetic interference protection according to claim 1, characterized in that, The control signal buffer module (2) includes multiple control signal buffer units. Each control signal buffer unit includes a second input buffer 74LVC1 G125, a fourth output buffer 74LVC1 G34, a fifth output buffer 74LVC1 G34, and a sixth output buffer 74LVC1 G34. The input terminal of the second input buffer 74LVC1 G125 is used to connect to the corresponding control pin in the external control pin. The output terminal of the second input buffer 74LVC1 G125 is simultaneously connected to the input terminals of the fourth output buffer 74LVC1 G34, the fifth output buffer 74LVC1 G34, and the sixth output buffer 74LVC1 G34. The output terminal of the fourth output buffer 74LVC1 G34 is configured as the first control signal output terminal of the control signal buffer module (2) connected to the first control signal input terminal of the triple redundant storage module (5). The fifth output buffer 74LVC1 G125 is configured as the first control signal output terminal of the control signal buffer module (2) connected to the first control signal input terminal of the triple redundant storage module (5). The output terminal of G34 is configured as the second control signal output terminal of the control signal buffer module (2) and connected to the second control signal input terminal of the triple redundant storage module (5). The output terminal of the sixth output buffer 74LVC1 G34 is configured as the third control signal output terminal of the control signal buffer module (2) and connected to the third control signal input terminal of the triple redundant storage module (5).

4. The data storage device for electromagnetic interference protection according to claim 1, characterized in that, The data input buffer module (3) includes an input buffer 74LVC245 and an output enable controller 74LVC1 G00. The input terminal of the input buffer 74LVC245 is used to connect to an external bidirectional data pin. The output terminal of the input buffer 74LVC245 is connected to the data input terminal of the data writing and distribution module (4). The input terminal of the output enable controller 74LVC1 G00 is connected to an external output enable pin. The output terminal of the output enable controller 74LVC1 G00 is connected to the enable terminal of the input buffer 74LVC245. When the output enable signal is valid, the input buffer 74LVC245 is in a high-impedance state and allows data to be output from the memory.

5. The data storage device for electromagnetic interference protection according to claim 1, characterized in that, The data writing and allocation module (4) includes multiple data allocation units. Each data allocation unit includes a third input buffer 74LVC1G125, a seventh output buffer 74LVC1G34, an eighth output buffer 74LVC1G34, and a ninth output buffer 74LVC1G34. The input terminal of the third input buffer 74LVC1G125 is connected to the corresponding data bit in the data output terminal of the data input buffer module (3). The output terminal of the third input buffer 74LVC1G125 is simultaneously connected to the input terminals of the seventh output buffer 74LVC1G34, the eighth output buffer 74LVC1G34, and the ninth output buffer 74LVC1G34. The seventh output buffer 74LVC1G125 is connected to the corresponding data bit in the data output terminal of the data input buffer module (3). The output terminal of G34 is configured as the first data output terminal of the data write distribution module (4) and connected to the first data write input terminal of the triple redundant storage module (5). The output terminal of the eighth output buffer 74LVC1G34 is configured as the second data output terminal of the data write distribution module (4) and connected to the second data write input terminal of the triple redundant storage module (5). The output terminal of the ninth output buffer 74LVC1G34 is configured as the third data output terminal of the data write distribution module (4) and connected to the third data write input terminal of the triple redundant storage module (5).

6. The data storage device for electromagnetic interference protection according to claim 1, characterized in that, The triple redundant storage module (5) includes a first storage array, a second storage array, a third storage array, a first read latch 74LVC373, a second read latch 74LVC373, and a third read latch 74LVC373. The first, second, and third storage arrays all use IS61WV51216BLL-10TLI high-speed asynchronous SRAM chips. The address input terminal of the first storage array is connected to the first address output terminal of the address buffer module (1). The control signal input terminal of the first storage array is connected to the first control signal output terminal of the control signal buffer module (2). The data write input terminal of the first storage array is connected to the first data output terminal of the data write allocation module (4). The data read output terminal of the first storage array is connected to the data input terminal of the first read latch 74LVC373. The address input terminal of the second storage array is connected to the second address output terminal of the address buffer module (1). The control signal input terminal of the second storage array is connected to the second control signal output terminal of the control signal buffer module (2). The data write input terminal of the second storage array is connected to the data write allocation module (4). 4) The second data output terminal of the second storage array is connected to the data input terminal of the second read latch 74LVC373. The address input terminal of the third storage array is connected to the third address output terminal of the address buffer module (1). The control signal input terminal of the third storage array is connected to the third control signal output terminal of the control signal buffer module (2). The data write input terminal of the third storage array is connected to the third data output terminal of the data write allocation module (4). The data read output terminal of the third storage array is connected to the third read latch 74LVC373. The data input terminals of the first read latch 74LVC373 are connected to the first data input terminal of the majority voting module (6) and the first data input terminal of the error detection and location module (7). The data output terminal of the second read latch 74LVC373 is connected to the second data input terminal of the majority voting module (6) and the second data input terminal of the error detection and location module (7). The data output terminal of the third read latch 74LVC373 is connected to the third data input terminal of the majority voting module (6) and the third data input terminal of the error detection and location module (7).

7. The data storage device for electromagnetic interference protection according to claim 1, characterized in that, The majority voting module (6) includes multiple majority voting units. Each majority voting unit includes a first AND gate 74LVC08, a second AND gate 74LVC08, a third AND gate 74LVC08, and an OR gate 74LVC32. The first input of the first AND gate 74LVC08 is connected to the data output of the first read latch. The second input of the first AND gate 74LVC08 is connected to the data output of the second read latch 74LVC373 in the triple redundant storage module (5). The first input of the second AND gate 74LVC08 is connected to the data output of the first read latch. The second input of the second AND gate 74LVC08 is connected to the data output of the third read latch 74LVC373 in the triple redundant storage module (5). The first input terminal of the third AND gate circuit 74LVC08 is connected to the data output terminal of the second read latch, the second input terminal of the third AND gate circuit 74LVC08 is connected to the data output terminal of the third read latch 74LVC373 in the triple redundant storage module (5), the first input terminal of the OR gate circuit 74LVC32 is connected to the output terminal of the first AND gate circuit 74LVC08, the second input terminal of the OR gate circuit 74LVC32 is connected to the output terminal of the second AND gate circuit 74LVC08, the third input terminal of the OR gate circuit 74LVC32 is connected to the output terminal of the third AND gate circuit 74LVC08, and the output terminal of the OR gate circuit 74LVC32 is connected to the correct data input terminal of the error detection and location module (7) and the first data input terminal of the output selection module (9).

8. The data storage device for electromagnetic interference protection according to claim 1, characterized in that, The error detection and localization module (7) includes multiple error detection units and a priority encoder 74HC148. Each error detection unit includes a first XOR gate circuit 74LVC86, a second XOR gate circuit 74LVC86, and a third XOR gate circuit 74LVC86. The first input terminal of the first XOR gate circuit 74LVC86 is connected to the data output terminal of the first read latch, and the second input terminal of the first XOR gate circuit 74LVC86 is connected to the data output terminal of the majority voting module (6). The output terminal of the first XOR gate circuit 74LVC86 generates a first error signal. The first input terminal of the second XOR gate circuit 74LVC86 is connected to the data output terminal of the second read latch, and the second input terminal of the second XOR gate circuit 74LVC86 is connected to the data output terminal of the majority voting module (6). The output terminal of the second XOR gate circuit 74LVC86 generates a second error signal. The first input of the three XOR gate circuit 74LVC86 is connected to the data output of the third read latch. The second input of the third XOR gate circuit 74LVC86 is connected to the data output of the majority voting module (6). The output of the third XOR gate circuit 74LVC86 generates a third error signal. The first set of inputs of the priority encoder 74HC148 is connected to the output of the first XOR gate circuit 74LVC86. The second set of inputs of the priority encoder 74HC148 is connected to the outputs of all the second XOR gate circuits 74LVC86. The third set of inputs of the priority encoder 74HC148 is connected to the outputs of all the third XOR gate circuits 74LVC86. The error flag output of the priority encoder 74HC148 is used to connect to the external error flag pin. The error array identifier output of the priority encoder 74HC148 is used to connect to the external error array identifier pin.

9. A data storage device for electromagnetic interference protection according to claim 1, characterized in that, The self-repair control module (8) includes a first write control unit, a second write control unit, and a third write control unit. The first write control unit, the second write control unit, and the third write control unit are all 74LVC74 dual D-type flip-flops. The input terminal of the first write control unit is connected to the first error signal output terminal of the error detection and location module (7). The output terminal of the first write control unit is connected to the local write enable terminal of the first storage array in the triple redundant storage module (5). The input terminal of the second write control unit is connected to the second error signal output terminal of the error detection and location module (7). The output terminal of the second write control unit is connected to the local write enable terminal of the second storage array in the triple redundant storage module (5). The input terminal of the third write control unit is connected to the third error signal output terminal of the error detection and location module (7). The output terminal of the third write control unit is connected to the local write enable terminal of the third storage array in the triple redundant storage module (5).

10. A data storage device for electromagnetic interference protection according to claim 1, characterized in that, The output selection module (9) includes a 74LVC257 data selector and a 74LVC245 output multiplexer. The first input of the 74LVC257 data selector is connected to the data output of the first read latch. The second input of the 74LVC257 data selector is connected to the data output of the second read latch. The third input of the 74LVC257 data selector is connected to the data output of the third read latch. The channel selection of the 74LVC257 data selector is connected to an external array selection pin. The output of the 74LVC257 data selector is connected to the second input of the 74LVC245 output multiplexer. The first input of the 74LVC245 output multiplexer is connected to the data output of the majority voting module (6). The channel selection of the 74LVC245 output multiplexer is used to connect to an external diagnostic enable pin. The output of the 74LVC245 output multiplexer is connected to an external bidirectional data pin through a data output driver.

Images