A motorcycle brake system controller based on J1939 bus

Abstract

The utility model discloses a motorcycle brake system controller based on J1939 bus relates to motorcycle brake technical field, including power management circuit, main control chip, CAN bus transceiver, signal input circuit, drive control circuit, based on the hardware structure of improvement guarantee communication reliability, effectively reduced hardware cost, and this controller supports through CAN bus and carries out program flashing, need not special programming interface, and the production line and after -sales maintenance are convenient.

Description

Technical Field

[0001] This utility model relates to the field of motorcycle braking technology, and in particular to a motorcycle braking system controller based on the J1939 bus. Background Technology

[0002] Motorcycle electronic control systems typically have a smaller network scale than those in commercial vehicles, with fewer nodes, making them more sensitive to controller cost and configuration. Traditional motorcycle controllers usually use the UDS protocol based on the CAN bus or the KWP2000 protocol based on the K-line for communication and diagnostics. While these protocols are feature-rich, they place high demands on controller hardware resources, requiring significant storage space and strong processing power, thus increasing controller costs.

[0003] The SAE J1939 protocol is a high-level protocol based on CAN 2.0B, with significant advantages such as a clear and rigorous protocol structure and relatively low resource requirements. Existing motorcycle controllers have not fully considered efficient support and optimization of the J1939 protocol stack in their hardware design, and have not yet deeply integrated the J1939 protocol stack with the motorcycle controller hardware for systematic application in the vehicle communication network, thus failing to achieve an optimal balance between cost and performance. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, this invention optimizes the matching degree between the protocol stack and hardware resources, reduces the requirements for chip performance and storage space, and reduces the number of external components, thereby significantly reducing the hardware cost of the controller. The technical solution adopted in this invention is: a motorcycle braking system controller based on the J1939 bus, including a power management circuit, a main control chip, a CAN bus transceiver, a signal input circuit, and a drive control circuit; the main control chip is electrically connected to the power management circuit, signal input circuit, and drive control circuit respectively. The main control chip has a built-in CAN controller, Flash memory, and RAM. The CAN controller is configured based on the J1939 bus protocol, with a Flash memory of no less than 128KB and RAM of no less than 16KB. An external flashing device is connected to the CAN controller through the CAN bus transceiver interface to complete the program flashing and solidification based on the SAE J1939 protocol stack; the CAN bus transceiver uses a high-speed CAN transceiver chip, with one end connected to the CAN controller through a hardware interface, and the other end directly connected to the motorcycle CAN bus; J1939 bus data enters the CAN bus through the CAN bus transceiver. The controller; the signal input circuit is connected to the sensor; one end of the drive control circuit is connected to the main control chip, and the other end is connected to the actuator; the power management circuit has a built-in LDO linear regulator, which converts the input voltage of the power supply system into two stable outputs of 3.3V and 5V to power the main control chip, CAN bus transceiver, signal input circuit, and drive control circuit.

[0005] Furthermore, the main control chip is an Infineon XC2000 series chip.

[0006] Furthermore, the high-speed CAN transceiver chip model is TJA1043.

[0007] Furthermore, in the CAN bus transceiver and CAN controller circuit, the CAN_TX and CAN_RX pins of the main control chip are connected to the TXD and RXD pins of the high-speed CAN transceiver chip respectively through the first high-speed optocoupler and the second high-speed optocoupler; the CANH and CANL pins of the high-speed CAN transceiver chip are connected to the motorcycle CAN bus through a common-mode inductor; a terminating resistor is connected in parallel between the CANH and CANL pins of the high-speed CAN transceiver chip; and the CANH and CANL pins of the high-speed CAN transceiver chip are connected to ground by the second TVS diode and the first TVS diode respectively.

[0008] Furthermore, the main control chip is connected to an external crystal oscillator circuit and a reset circuit. The crystal oscillator circuit effectively ensures the running sequence of the J1939 protocol, and the reset circuit can reset the system and reinitialize the system state when the J1939 communication is abnormal.

[0009] Compared with the prior art, the beneficial effects of this utility model are: 1. Effectively reduce controller costs: The J1939 protocol stack, which has relatively low resource requirements, allows the use of lower-cost microprocessors while ensuring the integrity of communication functions.

[0010] 2. High reliability: The hardware circuit has been optimized and combined with the strict error handling mechanism of the J1939 protocol, which improves the reliability of the controller in the harsh working environment of motorcycles.

[0011] 3. Convenient flashing: Based on the J1939 standardized data transmission mechanism, it supports program flashing via CAN bus without the need for a dedicated programming interface, which is convenient for production line and after-sales maintenance.

[0012] 4. High integration: The communication protocol stack is tightly integrated with the hardware circuit, reducing the number of external components and improving the system's integration and stability. Attached Figure Description

[0013] Figure 1 This is a hardware architecture diagram of the system of this utility model; Figure 2 This is the circuit diagram of the CAN communication module of this utility model; Figure 3 This is a schematic diagram of the system architecture for a specific implementation of this utility model; Figure 4This is a flowchart of the system program flashing process for a specific implementation of this utility model; Wherein: U2 is the first high-speed optocoupler, U3 is the second high-speed optocoupler, L1 is the common-mode inductor, R1 is the terminating resistor, D1 is the first TVS diode, and D2 is the second TVS diode. Detailed Implementation

[0014] The present invention will be further described below with reference to the accompanying drawings.

[0015] like Figure 1 As shown, a motorcycle braking system controller based on the J1939 bus includes a power management circuit, a main control chip, a CAN bus transceiver, a signal input circuit, and a drive control circuit. The signal input circuit is connected to external sensors, and the drive control circuit is connected to external actuators. The main control chip is connected to the power management circuit, the CAN bus transceiver, the signal input circuit, and the drive control circuit. The power management circuit supplies power to the main control chip, the CAN bus transceiver, the signal input circuit, and the drive control circuit. The main control chip is connected to the vehicle's CAN bus network via the CAN bus transceiver circuit. The power management circuit, as the core of the hardware system's power supply, mainly uses a built-in LDO linear regulator to convert the external input voltage into two stable outputs: 3.3V and 5V. These outputs are connected to the main control chip, the CAN bus transceiver circuit, the drive control circuit, and the signal input circuit, respectively. The power management circuit provides reliable power to the core components, ensuring stable operation of each hardware unit under rated voltage.

[0016] The main control chip can be an Infineon XC2000 series microprocessor, with a built-in CAN controller, at least 128KB Flash memory and 16KB RAM. The Flash memory stores the firmware program based on the SAE J1939 protocol stack, while the RAM provides temporary storage space for protocol stack operation and data buffering. The CAN controller serves as the core interface for protocol communication, directly establishing a hardware connection with the CAN transceiver circuit. The main control chip also receives external sensor signals through the signal input circuit and drives the actuator through the power output drive circuit. Simultaneously, the main control chip is connected to an external crystal oscillator circuit and a reset circuit to provide a precise clock signal for chip operation and ensure rapid reset in case of system malfunction.

[0017] like Figure 2As shown, the high-speed CAN transceiver chip uses model TJA1043. In the circuit, the CAN_TX and CAN_RX pins of the main control chip are isolated by the first high-speed optocoupler U2 and the second high-speed optocoupler U3, and then connected to the TXD and RXD pins of the high-speed CAN transceiver chip U4, respectively. This achieves electrical isolation between the main control chip and the high-speed CAN transceiver chip, blocks ground loop interference, improves the circuit's anti-interference capability, and protects the main control chip from surges and voltage spikes on the bus side. The CANH and CANL pins of the high-speed CAN transceiver chip U4 are connected via common-mode inductor L1. Connected to the motorcycle CAN bus network, the common-mode inductor L1 effectively suppresses common-mode interference signals on the CAN bus, filtering out noise introduced by electromagnetic radiation or cable coupling, ensuring the transmission quality of differential signals. A 120-ohm terminating resistor R1 is connected in parallel between CANH and CANL to eliminate reflection interference during bus signal transmission, ensuring reliable data transmission on the bus. A second TVS diode D2 and a first TVS diode D1 are connected to ground on CANH and CANL respectively to achieve overvoltage protection for bus signals. Through optocoupler isolation, common-mode filtering, overvoltage protection, and termination matching, this circuit not only completes the physical layer connection between the main control chip and the motorcycle CAN bus network but also ensures the anti-interference and reliability of communication, ultimately supporting stable program flashing based on the J1939 protocol connection management and data transmission mechanism.

[0018] The signal input circuit filters the raw signals from external sensors to obtain the initial real-time vehicle information input signal. The drive control circuit is connected to the pins of the main control chip, receiving the drive control signal generated by the main control chip based on the vehicle state calculation. The other end is connected to the external actuators (motors, solenoid valves, etc.), and drives the external actuators based on the real-time operating conditions of the vehicle.

[0019] Based on the above hardware design, the following will detail the steps for flashing the program of the motorcycle braking system controller based on the J1939 bus, specifically including the following steps: S1. Disable active broadcasting from all devices.

[0020] In this step, after the device is powered on, the motorcycle braking system controller receives a command message sent by the diagnostic device on the motorcycle CAN bus network, which prohibits global device active broadcasting based on the J1939 bus protocol. The controller receives and confirms that the command is valid, and will shut down all actively sent messages on the CAN bus. This step is to prevent the device from interfering with the upgrade process due to active broadcasting data during the flashing process, and to ensure that the bus communication resources are dedicated to the transmission of flashing commands and data, thus creating conditions for the stable entry of the subsequent upgrade mode.

[0021] S2. Restart the device to enter upgrade mode.

[0022] In this step, the motorcycle braking system controller receives and parses the message command sent by the diagnostic device to enter upgrade mode. The controller restarts via hardware reset, and the bootloader program inside the main control chip runs first after power-on, guiding the device into upgrade mode that only supports flashing. At this time, the controller's regular application functions are temporarily disabled, and hardware resources such as the CAN controller and Flash memory are configured to adapt to flashing operations.

[0023] S3. Send online upgrade command.

[0024] In this step, the diagnostic equipment sends an online upgrade command based on the J1939 bus protocol to the motorcycle brake system controller via the motorcycle CAN bus network. After the CAN bus transceiver of the motorcycle brake system controller receives the command, the CAN controller of the main control chip parses it and determines whether it is a flashing trigger command based on the J1939 bus protocol.

[0025] If the motorcycle braking system controller fails to receive the command correctly or the command format is incorrect, the flashing process will terminate directly. The controller will remain at the Bootloader layer, continuously listening and waiting for the next valid flashing command. If the command is valid and successfully parsed, the next security authentication operation will be executed.

[0026] S4, Secure Access.

[0027] In this step, the diagnostic device sends a secure access request seed command. The motorcycle braking system controller sends random seed data to the diagnostic device. The diagnostic device performs calculations on the seed based on a preset encryption algorithm and key, generates a corresponding key, and sends it back to the controller. The controller compares the received key with the result calculated by the preset key algorithm function in the software code. If the keys do not match, subsequent flashing operations are rejected, and the process terminates. If the key is correct, security authentication is passed, and subsequent flashing data transmission is allowed.

[0028] S5, memory erase command.

[0029] In this step, the motorcycle braking system controller receives a memory erase command based on the J1939 bus protocol and initiates the erase process for the internal Flash memory. The main control chip, according to the target program partition address range specified in the command, calls the built-in Flash erase driver module. This module performs an erase operation on the target area storing the original firmware according to the Flash memory's hardware erase specifications. During the erase process, the main control chip monitors the Flash erase status in real time, obtaining the erase progress and result through the hardware status register. After the erase operation is completed, the main control chip sends a response message indicating that the erase is complete to the diagnostic device, thus completely freeing up storage space for the new program and effectively avoiding program malfunctions caused by the mixing of old and new firmware data. The controller receives the memory erase command and performs an erase operation on the program partition to be upgraded in the internal Flash memory, clearing the original firmware data and freeing up space for the new program.

[0030] S6. Create a page link.

[0031] In this step, the diagnostic device sends a TP.CM control message to establish a connection, and splits the data into packets according to the total size of the firmware to be transmitted. The instruction explicitly includes the following parameters for each packet: 1. Page number; 2. First block sequence number; 3. Valid length of a single packet; 4. Total number of data packets.

[0032] After the main control chip of the motorcycle braking system controller parses the TP.CM control message command through the CAN controller, it first verifies the validity of the command parameters. If the parameters are valid, the controller sends a response message to the diagnostic device to confirm the establishment of the page connection, and at the same time, it allocates a temporary buffer in RAM to prepare for receiving data. If the parameters are incorrect, it returns a response message indicating that the parameters are incorrect and waits for the diagnostic device to resend the sub-packet command.

[0033] S7, Transmit Data.

[0034] In this step, the diagnostic equipment sends all TP.DT data messages corresponding to a single packet in sequence according to the first sequence number: when each TP.DT message is transmitted through the CAN bus, the CAN transceiver of the motorcycle braking system controller completes the level conversion and then passes it to the main control chip. The CAN controller of the main control chip parses the message sequence number and data content in real time and writes the 8 bytes of data into the corresponding position in the RAM buffer in sequence.

[0035] After each TP.DT message is transmitted, the motorcycle braking system controller records the received block sequence number. Once all TP.DT messages in the packet have been transmitted, the diagnostic device sends a TP.CM control message, triggering the controller to verify the entire page of data. The controller uses a preset verification algorithm to perform integrity verification on the page of data in the RAM buffer, and simultaneously checks whether the total number of blocks matches the actual number of blocks received.

[0036] The page data that passes verification is temporarily stored in RAM, and the motorcycle braking system controller simultaneously updates the status message for the received page number. After receiving the successful reception response message, the diagnostic equipment automatically switches to the transmission process for the next page of data, repeating the above TP.CM control and TP.DT data transmission logic until all page data is correctly received by the controller.

[0037] If there are discontinuous block numbers or verification failures, the motorcycle braking system controller sends a request to retransmit a response message via TP.CM. The message specifies the lost block number. The diagnostic device only retransmits the corresponding TP.DT message, without needing to retransmit the entire page of data, which greatly improves transmission efficiency.

[0038] By employing a packet-splitting design based on the J1939 bus protocol TP mechanism, precise control of start / stop and retransmission during transmission is achieved using TP.CM messages. Furthermore, the 8-byte small data blocks of TP.DT messages are adapted to the frame transmission characteristics of the CAN bus, avoiding bus congestion or data loss caused by single transmission of large amounts of data. Simultaneously, the 1K-byte paging mode of page connection management is combined to efficiently utilize the RAM cache resources of the main control chip, ultimately achieving reliable and efficient transmission of firmware programs from the flashing device to the motorcycle braking system controller.

[0039] S8, End Page Link.

[0040] In this step, once all TP.DT messages for the last page of data have been transmitted, the diagnostic device sends a TP.CM end page connection message based on the J1939 bus protocol to the controller. The control bytes in this message are used to confirm that all page data of the motorcycle braking system controller has been transmitted, and the total number of bytes of the firmware program is carried in the message data field.

[0041] Upon receiving the TP.CM message, the controller immediately initiates the total data volume verification logic: it counts the cumulative total number of bytes of all received page data from its internal buffer and precisely compares this value with the total number of bytes in the diagnostic device's message. If they match, it indicates that all page data has been received completely without packet loss or data truncation. The motorcycle braking system controller then sends a transmission completion confirmation frame to the diagnostic device via the CAN bus transceiver, and the page connection process is completed normally. If the total byte count does not match, the motorcycle braking system controller sends a response message with a total length mismatch error via the TP.CM message, triggering the diagnostic device to re-initiate the transmission verification of the last page or missing data block until the total byte count matches before completing the page connection closure.

[0042] S9, Programming Verification.

[0043] In this step, after all page data transfers are completed, the diagnostic device calculates the total checksum of the program file (such as CRC checksum) and sends it to the motorcycle braking system controller via a message. The controller calculates all page data written to the internal Flash memory using a checksum algorithm and compares the result with the total checksum of the diagnostic device to verify the integrity and correctness of the written firmware data. If the checksum fails, the flashing process is terminated directly; if the checksum succeeds, the next step is executed.

[0044] S10, Download successful, reset.

[0045] In this step, when the diagnostic device receives the TP.CM response message indicating successful verification from the motorcycle brake system controller, it sends a download successful reset command message based on the J1939 bus protocol. After the CAN bus transceiver of the motorcycle brake system controller receives the command, the CAN controller of the main control chip parses and confirms the legality of the control identifier in the command message. After confirming its legality, the main control chip triggers the internal hardware reset module to execute the system hardware restart process.

[0046] S11 Enable global device active broadcasting.

[0047] In this step, after the device is reset and runs the new firmware normally, the diagnostic device receives a reset success TP.CM response message from the motorcycle braking system controller. Then, it sends an enable global device active broadcast command message based on the J1939 bus protocol to restore the controller's normal communication function. This allows the device to actively broadcast status information and sensor data in the motorcycle CAN bus network, enabling the system to return to normal communication and control logic. At this point, the entire flashing process is complete.

[0048] In summary, the complete program flashing process, through the complete link of disabling broadcasting, entering upgrade mode, security authentication, data erasure, data transmission, verification and reset, and restoring broadcasting, achieves safe and reliable online flashing of motorcycle controllers based on the J1939 bus protocol. It not only ensures the security of the upgrade process, but also improves the success rate of flashing through layered verification and fault tolerance mechanisms.

Claims

1. A motorcycle braking system controller based on the J1939 bus, characterized in that: The motorcycle braking system controller based on the J1939 bus includes a power management circuit, a main control chip, a CAN bus transceiver, a signal input circuit, and a drive control circuit. The main control chip is electrically connected to the power management circuit, signal input circuit, and drive control circuit. The main control chip integrates a CAN controller, Flash memory, and RAM. The CAN controller is configured based on the J1939 bus protocol. The Flash memory is at least 128KB and the RAM is at least 16KB. An external flashing device is connected to the CAN controller via the CAN bus transceiver interface. The CAN bus transceiver uses a high-speed CAN transceiver chip, with one end connected to the CAN controller via a hardware interface and the other end directly connected to the motorcycle's CAN bus. J1939 bus data enters the CAN controller through the CAN bus transceiver. The signal input circuit is connected to the sensors. One end of the drive control circuit is connected to the main control chip, and the other end is connected to the actuator. The power management circuit has a built-in LDO linear regulator, which converts the power supply system input voltage to 3.3V. It provides two stable outputs, 5V and 6V, to power the main control chip, CAN bus transceiver, signal input circuit, and drive control circuit.

2. A motorcycle braking system controller based on the J1939 bus according to claim 1, characterized in that: The main control chip is an Infineon XC2000 series chip.

3. A motorcycle braking system controller based on the J1939 bus according to claim 1, characterized in that: The high-speed CAN transceiver chip is model TJA1043.

4. A motorcycle braking system controller based on the J1939 bus according to claim 3, characterized in that: In the CAN bus transceiver and CAN controller circuit, the CAN_TX and CAN_RX pins of the main control chip are connected to the TXD and RXD pins of the high-speed CAN transceiver chip respectively through the first high-speed optocoupler (U2) and the second high-speed optocoupler (U3); the CANH and CANL pins of the high-speed CAN transceiver chip are connected to the motorcycle CAN bus through the common-mode inductor (L1); a terminating resistor (R1) is connected in parallel between the CANH and CANL pins of the high-speed CAN transceiver chip; and the CANH and CANL pins of the high-speed CAN transceiver chip are connected to ground by the second TVS diode (D2) and the first TVS diode (D1) respectively.

5. A motorcycle braking system controller based on the J1939 bus according to claim 1, characterized in that: The main control chip is connected to an external crystal oscillator circuit and a reset circuit. The crystal oscillator circuit effectively ensures the running sequence of the J1939 protocol, and the reset circuit can reset the system and reinitialize the system state when the J1939 communication is abnormal.

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