Power supply control circuit and PMIC chip input power abnormal jitter automatic recovery system

Abstract

The utility model discloses a power control circuit and PMIC chip input power abnormality dithering's automatic recovery system, and this system includes watchdog circuit, CPU and its peripheral circuit, PMIC and its peripheral circuit and power control circuit. Power control circuit includes: high side switch, connects between circuit power input and circuit power output, low side bleed switch, connects between circuit power output and ground, and control logic circuit, and its input electrically connected to control signal input, and its output electrically connected to common control node, and the control end of high side switch and low side bleed switch all electrically connected to common control node. The utility model can automatically cut off high side switch to power off, and turn on low side bleed switch to initiative bleed PMIC input voltage, simulate hardware power off restart, solve the problem that CPU can not start and software reset failure.

Description

Technical Field

[0001] This utility model belongs to the field of electronic circuit technology, and in particular to an automatic recovery system for abnormal jitter of power input power of a power control circuit and a PMIC chip. Background Technology

[0002] In embedded devices with extremely high reliability requirements, such as power acquisition terminals and remote communication base stations, the application of high-performance CPUs and System-on-Chip (SoC) is becoming increasingly widespread. These complex processors typically require dedicated power management integrated circuits (PMICs) to provide multiple core voltages, I / O voltages, and memory voltages with strict power-up timing requirements. Therefore, the ability of PMICs to stably start and operate under various harsh power grid environments has become a key prerequisite for ensuring the high availability of the entire embedded system, and is of significant research importance.

[0003] Currently, to improve system reliability, existing technical solutions mainly focus on the software level or conventional hardware reset level. For example, some solutions periodically query the internal register status of the PMIC after the CPU is running normally to determine if its operation is abnormal, and attempt to reset it via software instructions when an abnormality is detected. Other solutions use a hardware watchdog circuit, which determines that the system has failed when it detects that the CPU has failed to feed the watchdog within a specified time, and then outputs a reset signal to the CPU's reset pin (RESET) or the PMIC's enable pin (EN) to attempt to restart the system or PMIC.

[0004] However, the existing solutions described above have technical limitations when dealing with specific power supply anomalies. These limitations mainly focus on the hardware lock-up state of the PMIC caused by input power quality issues and the resulting concurrent monitoring failures. Utility Model Content

[0005] Purpose of the utility model: To provide a power control circuit and an automatic recovery system for abnormal jitter of PMIC chip input power, so as to solve the above-mentioned problems existing in the prior art.

[0006] Technical solution: An automatic recovery system for abnormal input power jitter in a PMIC chip, comprising:

[0007] The watchdog circuit has a reset signal output terminal and a feed signal input terminal;

[0008] The CPU and its peripheral circuits have a watchdog signal output terminal, which is electrically connected to the watchdog signal input terminal of the watchdog circuit.

[0009] The PMIC and its peripheral circuits have a PMIC power input terminal;

[0010] The power control circuit has a control signal input terminal, a circuit power input terminal, and a circuit power output terminal;

[0011] The control signal input terminal of the power control circuit is electrically connected to the reset signal output terminal of the watchdog circuit, and the circuit power output terminal of the power control circuit is electrically connected to the PMIC power input terminal of the PMIC and its peripheral circuits.

[0012] The power control circuit also includes:

[0013] The high-side switch Q1 is electrically connected between the circuit power input terminal and the circuit power output terminal;

[0014] The low-side bleeder switch Q3 is electrically connected between the circuit power output terminal and the ground terminal;

[0015] The control logic circuit has its input terminal electrically connected to the control signal input terminal and its output terminal electrically connected to the common control node.

[0016] The control terminal of the high-side switch Q1 is electrically connected to the common control node;

[0017] The control terminal of the low-side bleeder switch Q3 is also electrically connected to the common control node.

[0018] According to one aspect of this application, it also includes:

[0019] First input power;

[0020] The first step-down converter circuit has its input terminal electrically connected to the first input power supply and its output terminal electrically connected to the circuit power input terminal of the power control circuit.

[0021] The second step-down converter circuit has its input terminal electrically connected to the first input power supply and its output terminal electrically connected to the power supply terminal of the watchdog circuit.

[0022] According to one aspect of this application, the high-side switch Q1 is a PMOS transistor;

[0023] The low-side discharge switch Q3 is an NMOS transistor;

[0024] The control logic circuit includes an NPN transistor Q2.

[0025] According to one aspect of this application, the base of the NPN transistor Q2 is electrically connected to the control signal input terminal, the emitter is electrically connected to the ground terminal, and the collector is electrically connected to the common control node through the second resistor R2.

[0026] The power control circuit also includes a first resistor R1, which is electrically connected between the circuit power input terminal and the common control node.

[0027] According to one aspect of this application, it includes:

[0028] Circuit power input terminal, circuit power output terminal, control signal input terminal and ground terminal;

[0029] The high-side switch Q1 is electrically connected between the circuit power input terminal and the circuit power output terminal, and has a high-side switch control terminal;

[0030] The low-side discharge switch Q3 is electrically connected between the circuit power output terminal and the ground terminal, and has a low-side discharge switch control terminal;

[0031] A control logic circuit has an input terminal and an output terminal, wherein the input terminal is electrically connected to a control signal input terminal;

[0032] The output terminal, high-side switch control terminal, and low-side discharge switch control terminal of the control logic circuit are electrically connected to a common control node.

[0033] According to one aspect of this application, the high-side switch Q1 is a PMOS transistor;

[0034] The low-side discharge switch Q3 is an NMOS transistor;

[0035] The control logic circuit includes an NPN transistor Q2.

[0036] According to one aspect of this application, the NPN transistor Q2 has a base, a collector, and an emitter;

[0037] The base of NPN transistor Q2 is electrically connected to the control signal input terminal, and the emitter of NPN transistor Q2 is electrically connected to the ground terminal; the collector of NPN transistor Q2 is electrically connected to the common control node through the second resistor R2.

[0038] The power control circuit also includes a first resistor R1, which is electrically connected between the circuit power input terminal and the common control node.

[0039] Beneficial effects: This utility model can automatically cut off the high-side switch to disconnect the power and conduct the low-side discharge switch to actively discharge the PMIC input voltage, simulating hardware power failure and restart. It solves the problem that the PMIC enters a hardware lock state due to non-monotonic power-on of the input power, which causes the CPU to fail to start and the software reset to fail. Attached Figure Description

[0040] Figure 1 This is a topology diagram of an automatic recovery system for abnormal jitter of PMIC chip input power supply provided in an embodiment of the present invention.

[0041] Figure 2 A power control circuit diagram provided for an embodiment of this utility model. Detailed Implementation

[0042] The research revealed that mainstream PMIC chips have extremely strict requirements for the startup waveform (i.e., power-on monotonicity) of their input power supply. When the input power supply experiences non-monotonic jitter, drops, or fluctuations during power-on, the PMIC's internal state machine or logic circuitry enters an unexpected hardware lock-in state. In this state, the PMIC completely stops working, unable to supply power to the CPU, preventing the CPU from starting at all. Therefore, any software-based monitoring or reset mechanisms become completely ineffective. More critically, this lock-in state cannot usually be released by simply switching the PMIC's enable (EN) pin. The only reliable way to recover is to physically disconnect its main input power supply, completely discharge any residual charge at its input terminals to ground, and then power it on again. Existing watchdog circuits only reset the CPU or PMIC enable pin and do not implement this power-off-discharge hardware process. Furthermore, in many existing designs, the watchdog circuit used to monitor the CPU state shares the same power rail as the PMIC's input power supply (or its upstream power supply). This design has a flaw: when the input power fluctuates violently, the fluctuation can cause the PMIC to lock up, and may also cause the watchdog circuit itself to fail due to power loss. This causes the monitoring system to fail first when it is most needed to intervene, unable to generate any effective reset signal, resulting in a system crash.

[0043] like Figure 1 As shown, an automatic recovery system for abnormal input power jitter in a PMIC chip is provided, comprising: a first input power supply, a second input power supply, a power control circuit, a PMIC and its peripheral circuits, a CPU and its peripheral circuits, and a watchdog circuit. The system connections are as follows: the CPU and its peripheral circuits have a watchdog signal output terminal, which is electrically connected to the watchdog signal input terminal of the watchdog circuit. The watchdog circuit has a reset signal output terminal, which is electrically connected to the control signal input terminal of the power control circuit. The power control circuit has a circuit power input terminal (receiving power supply V2 from the second input power supply) and a circuit power output terminal (outputting power supply V3). The circuit power output terminal is electrically connected to the PMIC power input terminal of the PMIC and its peripheral circuits. The multiple power output terminals of the PMIC and its peripheral circuits are electrically connected to the power supply terminals of the CPU and its peripheral circuits, providing operating power to the CPU.

[0044] like Figure 2As shown, the power control circuit includes a high-side switch Q1, which is preferably a PMOS transistor in this embodiment. The source of the high-side switch Q1 is electrically connected to the circuit power input terminal, and the drain of the high-side switch Q1 is electrically connected to the circuit power output terminal. The power control circuit also includes a low-side discharge switch Q3, which is preferably an NMOS transistor in this embodiment. The drain (D) of the low-side discharge switch Q3 is electrically connected to the circuit power output terminal through a load resistor R4, and the source (S) of the low-side discharge switch Q3 is electrically connected to the ground terminal. The power control circuit also includes a control logic circuit, which is preferably an NPN transistor Q2 in this embodiment. The base of the NPN transistor Q2 is electrically connected to the control signal input terminal through a third resistor R3, and the emitter of the NPN transistor Q2 is electrically connected to the ground terminal. The gate (i.e., the high-side switch control terminal) of the high-side switch Q1 and the gate (G) (i.e., the low-side discharge switch control terminal) of the low-side discharge switch Q3 are electrically connected together to form a common control node. The common control node is electrically connected to the circuit power input terminal through the first resistor R1, and simultaneously electrically connected to the collector of the NPN transistor Q2 through the second resistor R2.

[0045] During normal operation, the CPU performs a normal watchdog timer (WDI), and the watchdog circuit outputs a high-level reset signal (RST). This high level turns on NPN transistor Q2, and its collector pulls the common control node low. The gate of high-side switch Q1 is pulled low and turns on, supplying power to the PMIC input through the high-side switch Q1. Simultaneously, the gate of low-side bleeder switch Q3 is pulled low and turns off, and the bleeder branch is inactive. When an abnormality occurs, such as PMIC locking due to power jitter, the CPU loses power and stops watchingdog timer (WDI). The watchdog circuit times out and outputs a low-level reset signal (RST). This low level turns off NPN transistor Q2. The common control node is pulled up to a high level at the circuit power input through the first resistor R1. This high-level state, on the one hand, pulls the gate of the high-side switch Q1 high and cuts it off, cutting off the power supply from the circuit power input terminal to the PMIC power input terminal; on the other hand, it pulls the gate of the low-side discharge switch Q3 high and turns it on, and the residual charge on the PMIC power input terminal is quickly discharged to ground through the load resistor R4 and the low-side discharge switch Q3.

[0046] When the RST low-level pulse (e.g., 200 milliseconds) ends, RST returns to high level, the circuit returns to normal operation, high-side switch Q1 is turned on again, low-side discharge switch Q3 is turned off, and the PMIC obtains a clean, monotonically rising power-on process, thus recovering from the locked state. In this embodiment, the control terminals of high-side switch Q1 and low-side discharge switch Q3 are connected to a common control node and are driven inversely by the control logic circuit, so that the power-off action of high-side switch Q1 and the discharge action of low-side discharge switch Q3 are strictly complementary and automatically coordinated. This can automatically simulate the manual power-off-discharge-re-power-on process in the event of a complete CPU failure, solving the industry problem of PMIC locking up due to abnormal input power fluctuations and the failure of the software reset mechanism.

[0047] In one exemplary embodiment, the system includes a first input power supply, such as a 12V DC power supply. It also includes a first buck converter circuit and a second buck converter circuit. The input of the first buck converter circuit (e.g., a first buck chip) is electrically connected to the first input power supply, and its output outputs a second input power supply, such as a stable 5V voltage. The output of the second input power supply is electrically connected to the circuit power input of a power control circuit. The input of the second buck converter circuit (e.g., a second buck chip) is electrically connected to the first input power supply, and its output outputs a power supply V4, such as a stable 3.3V voltage. This output is electrically connected to the power supply of a watchdog circuit.

[0048] Understandably, the power supply V4 for the watchdog circuit is obtained independently from the first input power supply through the second buck converter circuit, and power supply V4 is independent of the second input power supply that supplies power to the power control circuit. This ensures that even if the second input power supply fails due to abnormal fluctuations in the first input power supply, the watchdog circuit can still operate reliably with the stable power supply V4, thus guaranteeing that the reset signal (RST) can still be correctly triggered in the event of CPU failure.

[0049] In a preferred implementation, the power control circuit topology is as follows: The high-side switch Q1 is preferably a PMOS transistor. The low-side discharge switch Q3 is preferably an NMOS transistor. The control logic circuit preferably includes an NPN transistor Q2. The base of the NPN transistor Q2 is electrically connected to the control signal input terminal via a third resistor R3, and the emitter of the NPN transistor Q2 is electrically connected to ground. The source of the high-side switch Q1 is electrically connected to the circuit power input terminal, and the drain of the high-side switch Q1 is electrically connected to the circuit power output terminal. The drain (D) of the low-side discharge switch Q3 is electrically connected to the circuit power output terminal via a fourth resistor, and the source (S) of the low-side discharge switch Q3 is electrically connected to ground. The gates (G) of the high-side switch Q1 and the low-side discharge switch Q3 are electrically connected to the same common control node. The common control node is electrically connected to the circuit power input terminal via a first resistor R1, and the common control node is also electrically connected to the collector of the NPN transistor Q2 via a second resistor R2.

[0050] This embodiment uses a PMOS transistor as a high-side switch and an NMOS transistor as a low-side discharge switch. An inverting control logic is constructed using an NPN transistor and its peripheral resistors, which can stably respond to the RST signal and perform complementary power-off and active discharge functions.

[0051] According to one aspect of this application, a power control circuit includes a power input terminal, a power output terminal, a control signal input terminal, and a ground terminal. It also includes a high-side switch electrically connected between the power input terminal and the power output terminal, and having a high-side switch control terminal. Furthermore, it includes a low-side bleeder switch electrically connected between the power output terminal and the ground terminal, and having a low-side bleeder switch control terminal. Finally, it includes a control logic circuit having an input terminal and an output terminal, the input terminal being electrically connected to the control signal input terminal. The output terminal of the control logic circuit, the high-side switch control terminal, and the low-side bleeder switch control terminal are electrically connected to a common control node.

[0052] According to one aspect of this application, in the power control circuit, the high-side switch is preferably a PMOS transistor. The low-side discharge switch is preferably an NMOS transistor. The control logic circuit preferably includes an NPN transistor. The NPN transistor has a base, a collector, and an emitter. The base of the NPN transistor is electrically connected to the control signal input terminal, and the emitter of the NPN transistor is electrically connected to the ground terminal. The collector of the NPN transistor is electrically connected to the common control node through a second resistor. The power control circuit also includes a first resistor electrically connected between the circuit power input terminal and the common control node. To further clarify the circuit structure of this embodiment, the source of the PMOS transistor is electrically connected to the circuit power input terminal, and the drain is electrically connected to the circuit power output terminal. The gate of the NMOS transistor is electrically connected to the common control node, the source is electrically connected to the ground terminal, and the drain is electrically connected to the circuit power output terminal through a fourth resistor. The base of the NPN transistor is electrically connected to the control signal input terminal through a third resistor for current limiting.

[0053] It should be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this utility model will not describe the various possible combinations separately.

Claims

1. An automatic recovery system for abnormal input power jitter in a PMIC chip, characterized in that, include: The watchdog circuit has a reset signal output terminal and a feed signal input terminal; The CPU and its peripheral circuits have a watchdog signal output terminal, which is electrically connected to the watchdog signal input terminal of the watchdog circuit. The PMIC and its peripheral circuits have a PMIC power input terminal; The power control circuit has a control signal input terminal, a circuit power input terminal, and a circuit power output terminal; The control signal input terminal of the power control circuit is electrically connected to the reset signal output terminal of the watchdog circuit, and the circuit power output terminal of the power control circuit is electrically connected to the PMIC power input terminal of the PMIC and its peripheral circuits. The power control circuit also includes: The high-side switch Q1 is electrically connected between the circuit power input terminal and the circuit power output terminal; The low-side bleeder switch Q3 is electrically connected between the circuit power output terminal and the ground terminal; The control logic circuit has its input terminal electrically connected to the control signal input terminal and its output terminal electrically connected to the common control node. The control terminal of the high-side switch Q1 is electrically connected to the common control node; The control terminal of the low-side bleeder switch Q3 is also electrically connected to the common control node.

2. The system according to claim 1, characterized in that, Also includes: First input power; The first step-down converter circuit has its input terminal electrically connected to the first input power supply and its output terminal electrically connected to the circuit power input terminal of the power control circuit. The second step-down converter circuit has its input terminal electrically connected to the first input power supply and its output terminal electrically connected to the power supply terminal of the watchdog circuit.

3. The system according to claim 1, characterized in that: The high-side switch Q1 is a PMOS transistor; The low-side discharge switch Q3 is an NMOS transistor; The control logic circuit includes an NPN transistor Q2.

4. The system according to claim 3, characterized in that: The base of NPN transistor Q2 is electrically connected to the control signal input terminal, the emitter is electrically connected to the ground terminal, and the collector is electrically connected to the common control node through the second resistor R2. The power control circuit also includes a first resistor R1, which is electrically connected between the circuit power input terminal and the common control node.

5. A power supply control circuit, characterized in that, include: Circuit power input terminal, circuit power output terminal, control signal input terminal and ground terminal; The high-side switch Q1 is electrically connected between the circuit power input terminal and the circuit power output terminal, and has a high-side switch control terminal; The low-side discharge switch Q3 is electrically connected between the circuit power output terminal and the ground terminal, and has a low-side discharge switch control terminal; A control logic circuit has an input terminal and an output terminal, wherein the input terminal is electrically connected to a control signal input terminal; The output terminal, high-side switch control terminal, and low-side discharge switch control terminal of the control logic circuit are electrically connected to a common control node.

6. The circuit according to claim 5, characterized in that: The high-side switch Q1 is a PMOS transistor; The low-side discharge switch Q3 is an NMOS transistor; The control logic circuit includes an NPN transistor Q2.

7. The circuit according to claim 6, characterized in that: The NPN transistor Q2 has a base, a collector, and an emitter; The base of NPN transistor Q2 is electrically connected to the control signal input terminal, and the emitter of NPN transistor Q2 is electrically connected to the ground terminal; the collector of NPN transistor Q2 is electrically connected to the common control node through the second resistor R2. The power control circuit also includes a first resistor R1, which is electrically connected between the circuit power input terminal and the common control node.

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