An ultra-low dropout large power hybrid regulated power supply device

Abstract

The utility model discloses a kind of super-low voltage difference high-power hybrid regulating power supply devices, including EMI filter module, rectification filter module, flyback switching power supply module and linear adjustment module. Wherein flyback switching power supply module adopts transformer with double secondary winding;Linear adjustment module uses NMOS tube as adjustment element, its gate is driven by auxiliary power supply, drain-source electrode is connected between 12.3V and 12.0V output, realizes 0.3V super-low voltage difference adjustment;First voltage stabilizer controls switching power supply output 12.3V, second voltage stabilizer controls NMOS tube gate voltage, will finally output accurate stabilization at 12.0V. The utility model is by double independent power supply and double-stage independent control, make NMOS tube work in deep linear region, voltage difference is only 0.3V, compared with traditional 2V voltage difference scheme, reduce power consumption, simultaneously realize the output accuracy of ±0.01V and the ripple of less than 5mV, improve the whole machine efficiency.

Description

Technical Field

[0001] This utility model belongs to the field of power supply design, and in particular to a high-power hybrid adjustable power supply device with ultra-low voltage drop. Background Technology

[0002] With the rapid development of precision instruments, communication equipment, medical electronics, and other fields, increasingly stringent requirements are being placed on the output accuracy, ripple noise, and dynamic response of power supplies. Especially in applications requiring strict control of output voltage accuracy, such as precision ADC reference power supplies, high-speed digital circuit power supplies, and sensitive analog circuits, ±0.1% voltage accuracy and millivolt-level ripple have become fundamental requirements. Simultaneously, with the continuous increase in power density, how to reduce power consumption and improve efficiency while maintaining high accuracy has become a significant challenge in power supply design.

[0003] Currently, the industry commonly uses a cascaded architecture of switching power supplies and linear regulators to achieve high-precision output. A typical approach involves first converting the mains voltage to DC power slightly higher than the target voltage using a flyback or forward switching power supply, and then performing secondary regulation using a three-terminal linear regulator (such as LM7812, LM317, etc.) or a low-dropout linear regulator (LDO). The switching power supply section typically employs current-mode PWM control, achieving initial voltage regulation through a feedback loop consisting of a TL431 and an optocoupler. The linear regulator section utilizes a bandgap reference and an error amplifier to achieve high-precision voltage regulation. This architecture effectively suppresses switching ripple, achieving an output voltage accuracy of ±1% and reducing ripple to below 10mV.

[0004] However, existing cascaded architectures suffer from technical challenges such as excessive voltage drop in the linear regulator stage leading to significant power consumption, and mutual interference between the two control loops affecting dynamic response. Specifically, traditional three-terminal regulators require at least a 2V input-output voltage difference to maintain stable operation. This is because their internal regulating transistors use Darlington structures or PNP transistors, resulting in high saturation voltage drops, and require a voltage margin for the internal bias circuit. At a 50W output power, a 2V voltage difference translates to 8.3W of power loss, not only reducing overall efficiency but also creating significant heat dissipation challenges. More critically, the switching power supply and the linear regulator each have independent control loops. When the load changes abruptly, the response times of the two loops are mismatched (approximately 10ms for switching power supplies and approximately 100μs for linear regulators), causing mutual interference and resulting in overshoot or undershoot in the output voltage, thus degrading transient response performance. Utility Model Content

[0005] Purpose of the utility model: To provide a high-power hybrid adjustable power supply device with ultra-low voltage drop, so as to solve the above-mentioned problems existing in the prior art.

[0006] Technical solution: A high-power hybrid regulating power supply device with ultra-low dropout voltage, comprising:

[0007] The AC input terminal is configured to receive AC power input.

[0008] An EMI filter module, whose input terminal is electrically connected to an AC input terminal, includes a common-mode inductor L801, a first X capacitor C810, and a second X capacitor C811;

[0009] The rectifier and filter module, whose input is electrically connected to the output of the EMI filter module, includes a rectifier bridge D800 and a first filter capacitor C809;

[0010] A flyback switching power supply module, whose input terminal is electrically connected to the output terminal of a rectifier and filter module, includes:

[0011] PWM controller U801;

[0012] The T800 switching transformer has a primary winding, a first-stage winding, and a second-stage winding, wherein the first-stage winding and the second-stage winding share a center tap;

[0013] The first rectifier diode V802 has its anode electrically connected to the first end of the first primary winding, and its cathode serves as the first DC output terminal.

[0014] The second rectifier diode V803 has its anode electrically connected to the first end of the second stage winding, and its cathode serves as the auxiliary power output terminal.

[0015] The linear adjustment module includes:

[0016] The NMOS transistor Q800 has its drain electrically connected to the first DC output terminal and its source as the final output terminal.

[0017] The first reference voltage regulator circuit includes a first voltage regulator D803, configured to stabilize the voltage at the first DC output terminal at 12.3V;

[0018] The second reference voltage regulator circuit includes a second voltage regulator D802, whose cathode is electrically connected to the gate of the NMOS transistor Q800, and whose reference terminal is connected to the final output terminal through a voltage divider resistor network, configured to stabilize the voltage at the final output terminal at 12.0V.

[0019] The auxiliary power supply output is electrically connected to the gate drive circuit of the NMOS transistor Q800, providing a gate bias voltage higher than the final output voltage.

[0020] According to one aspect of this application, the winding configuration of the switching transformer T800 includes:

[0021] The primary winding is connected between pin 1 and pin 3;

[0022] The primary winding is connected between pin 4 and pins 5 and 6, with pin 4 being the center tap.

[0023] The secondary winding is connected between pin 4 and pin 7;

[0024] The primary winding is configured to provide main power output with an output current greater than 4A.

[0025] The secondary winding is configured to provide gate bias power with an output current of less than 10mA.

[0026] The center tap pin 4 is connected to the circuit ground to form a dual-path differential output structure.

[0027] According to one aspect of this application, the second reference voltage regulator circuit further includes:

[0028] The first feedback resistor R822 is connected between the gate of the NMOS transistor Q800 and the cathode of the second regulator D802.

[0029] The second feedback resistor R813 is connected between the gate of the NMOS transistor Q800 and the reference terminal of the second regulator D802.

[0030] The gate capacitor C828 is connected between the gate of the NMOS transistor Q800 and the anode of the second voltage regulator D802.

[0031] According to one aspect of this application, the gate bias power supply circuit of a flyback switching power supply module includes:

[0032] The second rectifier diode V803 has its pins 1 and 3 electrically connected to pin 7 of the switching transformer T800;

[0033] The energy storage capacitor C815 has its positive terminal electrically connected to pin 2 of the second rectifier diode V803, and its negative terminal electrically connected to the circuit ground.

[0034] The filter capacitor C816 is connected in parallel across the energy storage capacitor C815.

[0035] According to one aspect of this application, a first reference voltage regulator circuit includes: resistors R814, R815, R816, R817, R820, R821, and R823; capacitors C829, C830, C831, and C833; an optocoupler D801; and a first voltage regulator D803. One end of capacitor C829 is connected to both pin 4 of optocoupler D801 and pin 4 of PWM controller U801. The other end of capacitor C829 is grounded to pin 3 of optocoupler D801. Pin 1 of optocoupler D801 is connected in parallel with one end of resistors R814 and R815. The other ends of resistors R814 and R815 are connected to a power supply. Pin 2 is simultaneously connected to one end of resistors R821 and R820, one end of capacitor C833, and pin 2 of the first voltage regulator D803. The other end of resistor R821 is connected to one end of resistor R815. The other end of resistor R820 is connected to one end of capacitor C830. The other end of capacitor C830 is simultaneously connected to the other end of capacitor C833, one end of resistors R816, R823, and C831, and pin 1 of the first voltage regulator D803. The other end of resistor R816 is connected to the power supply. The other end of resistor R823 is simultaneously connected to pin 3 of the first voltage regulator D803 and ground. The other end of capacitor C831 is connected to one end of resistor R817. The other end of resistor R817 is connected to the power supply.

[0036] According to one aspect of this application, an EMI filtering module includes:

[0037] Fuse F800 is connected in series to the live wire input terminal of the AC input terminal;

[0038] The common mode inductor L801 has its first winding connected between the output terminal of fuse F800 and the first AC input terminal of rectifier bridge D800, and its second winding connected between the neutral input terminal of the AC input terminal and the second AC input terminal of rectifier bridge D800.

[0039] The first capacitor C810 is connected between pin 1 and pin 4 of the common mode inductor L801;

[0040] The second capacitor C811 is connected between pin 2 and pin 3 of the common mode inductor L801;

[0041] The varistor MV800 is connected in parallel with the first X capacitor C810.

[0042] According to one aspect of this application, the flyback switching power supply module further includes an output filtering circuit, comprising:

[0043] The output filter inductor L800 is connected in series between the cathode of the first rectifier diode V802 and the first DC output terminal;

[0044] The output capacitor C804 is connected between the output terminal of the output filter inductor L800 and the circuit ground.

[0045] Output capacitors C801 to C803 are connected in parallel across output capacitor C804;

[0046] The bleeder resistor R806 is connected in parallel across the output capacitor C801.

[0047] According to one aspect of this application, a protection circuit is also included, comprising:

[0048] Input overvoltage protection branch, including:

[0049] Transient voltage suppressor diode V804 is bidirectionally connected between the positive and negative terminals of the rectified DC bus.

[0050] Clamping capacitor C825 is connected in parallel across transient suppression diode V804;

[0051] Output overvoltage protection branch, including:

[0052] Zener diode V805 is connected between the gate and source of NMOS transistor Q800 to limit the gate-source voltage to no more than 18V;

[0053] Overcurrent protection branch, including:

[0054] The sensing resistor is formed by resistors R811 and R812;

[0055] When the detection voltage corresponding to the detection resistor exceeds the threshold of pin 1 of the PWM controller U801, cycle-by-cycle current limiting protection is triggered.

[0056] The short-circuit protection function is implemented through the hiccup mode integrated inside the PWM controller U801. When the overcurrent protection is triggered for 8 consecutive cycles, the hiccup mode is entered.

[0057] Beneficial effects: This utility model enables the NMOS transistor to operate in the deep linear region through dual-path independent power supply and dual-stage independent control, thereby reducing power consumption and improving output accuracy and overall efficiency. Attached Figure Description

[0058] Figure 1 The topology diagram of a high-power hybrid adjustable power supply device with ultra-low voltage drop provided by this utility model.

[0059] Figure 2 The circuit diagram of a high-power hybrid adjustable power supply device with ultra-low voltage drop provided by this utility model.

[0060] Figure 3 The output filter circuit diagram of the flyback switching power supply module provided by this utility model.

[0061] Figure 4 The second reference voltage regulator circuit diagram of the linear adjustment module provided by this utility model. Detailed Implementation

[0062] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0063] The research revealed that traditional flyback switching power supplies typically employ a single-stage voltage regulation scheme, directly stabilizing the output voltage at 12V via a PWM controller. However, this approach suffers from several technical problems: due to factors such as the leakage inductance of the flyback transformer, the voltage drop of the rectifier diodes, and the DC resistance of the output filter inductor, the output voltage of the switching power supply exhibits significant ripple and dynamic fluctuations, typically ±200mV. To achieve a stable 12V output, traditional solutions require the addition of a linear regulator at the end of the switching power supply stage, typically a three-terminal regulator such as the LM7812. Furthermore, to ensure the linear regulator operates correctly, its input voltage must be at least 2V higher than the output voltage, meaning the switching power supply needs to output a voltage of at least 14V. Under a 50W load, the output current is approximately 4.17A, and the power consumption of the linear regulator is: P = (14V-12V) × 4.17A = 8.34W. This not only reduces overall efficiency but also leads to severe heat dissipation issues.

[0064] like Figures 1 to 4As shown, a high-power hybrid regulated power supply device with ultra-low dropout voltage is proposed. From left to right, the device includes an AC input terminal, an EMI filter module, a rectifier filter module, a flyback switching power supply module, and a linear regulation module. The L and N lines of the AC input terminal are connected to a fuse F800 and the neutral input terminal, respectively. For example, the fuse F800 is model C310T-SC-2-R with a rated current of 2A, providing protection against input overcurrent. The EMI filter module includes a common-mode inductor L801 (model KL5.757.A011WX), whose two windings are connected in series in the live and neutral paths, respectively. On the input side of the common-mode inductor, a varistor MV800 (MYN12-471K) is connected between the L and N lines to provide surge protection; a first X capacitor C810 (0.1μF / 310VAC) is connected across the input terminals of the common-mode inductor L801. The second capacitor, C811 (0.1μF / 310VAC), is connected across the output terminals of the common-mode inductor L801 to filter differential-mode interference. The rectifier and filter module uses a rectifier bridge D800 to convert AC to DC. The positive terminal of the rectified power supply is connected to the first filter capacitor C809 (22μF / 400V), and the negative terminal is connected to primary ground. Capacitor C809 provides a smooth DC bus voltage for subsequent switching conversion, typically 310V. The flyback switching power supply module includes a PWM controller U801 (PN8149HNEC-T1) and a switching transformer T800. The PWM controller U801 is an 8-pin package, with the following pin functions: pin 1 (CS) connects to the current detection signal, pin 2 (GND) connects to primary ground, pin 3 (VDD) is the power supply terminal, pin 4 (COMP) connects to the compensation network, and pins 6, 7, and 8 (SW) output PWM drive signals. The switching transformer T800 uses a three-winding structure. The primary winding is connected between pins 1 and 3 of the switching transformer T800. Pin 1 is connected to the positive terminal of the DC bus, and pin 3 is connected to the primary ground. The second-stage winding is connected between pin 4 (center tap) and pins 5 and 6 of the switching transformer T800, providing the main power output. The third-stage winding is connected between pins 4 and 7 of the switching transformer T800, providing auxiliary power. The linear regulation module uses an NMOS transistor Q800 (2N7002K) as the regulating transistor. Its drain is connected to the 12.3V output of the switching power supply, and its source outputs the final 12.0V. The gate is biased and controlled by a circuit to maintain a suitable gate-source voltage, allowing the NMOS transistor to operate in the linear region. The first TL431 regulator D803 and its peripheral circuitry in the linear regulation module constitute the first-stage voltage regulation control, stabilizing the switching power supply output at 12.3V. The second TL431 regulator D802 and its peripheral circuitry constitute the second stage of voltage regulation control. By adjusting the gate voltage of the NMOS transistor, the final output is precisely stabilized at 12.0V.

[0065] According to one aspect of this application, the switching transformer T800 uses an EE28 magnetic core with a primary inductance of 1.2mH. The primary winding is wound with 120 turns of 0.25mm enameled wire and connected between pins 1 and 3. When the PWM controller U801 outputs a high level, the power switch is turned on, current flows in from pin 1, flows out from pin 3 through the primary winding, and stores energy in the magnetic core. The first primary winding is the main power output winding, wound with 8 turns using 0.8mm × 3 strands in parallel, and employs a center-tapped structure. Pin 4 is the center tap and connected to circuit ground. Pins 5 and 6 are respectively connected to the anode of the first rectifier diode V802 (US1M). The center-tapped structure can reduce the reverse voltage stress of the rectifier diode, reduce output ripple, and improve transformer utilization. The second primary winding is the auxiliary power supply winding, wound with 12 turns of 0.25mm enameled wire, and outputs approximately 18V. This winding is specifically designed to provide gate bias voltage for the NMOS transistor Q800, and is isolated from the main power circuit to avoid the impact of load changes on the gate drive.

[0066] According to one aspect of this application, a linear adjustment module includes: a first reference voltage regulator circuit and a second reference voltage regulator circuit. In the first-stage control loop of the first reference voltage regulator circuit, a voltage divider network divides the 12.3V output voltage to 6.15V, which is then fed to pin 1 of the TL431 regulator D803. When this voltage is higher than the 2.5V internal reference, the cathode current of regulator D803 increases, transmitting an error signal to the primary side via optocoupler D801 (PC817X3CSP9F). The increased current of the optocoupler's LED leads to enhanced phototransistor conduction, pulling down the COMP pin voltage of the PWM controller, reducing the duty cycle, and thus lowering the output voltage. This negative feedback loop stabilizes the first-stage output at 12.3V ± 0.1V. The second-stage control loop of the second reference voltage regulator circuit operates independently. Resistor R813 (1.24kΩ) is sampled from the final 12.0V output and directly connected to the reference terminal of the TL431 regulator D802. Since the reference voltage is exactly 2.5V when the voltage divider ratio is designed to be 12.0V, the TL431 regulator D802 operates in the linear regulation region. When the output voltage is too high, the cathode current of the TL431 regulator D802 increases, which pulls down the gate voltage of the NMOS transistor Q800 through resistor R822 (3.24kΩ), increasing its on-resistance and causing the output voltage to drop. The reverse is also true.

[0067] In this embodiment, the first-stage control loop transmits control data through a voltage regulator and an optocoupler, with a response time of approximately 1-10 ms; the second-stage control loop directly controls the NMOS transistor, with a response time of only 10-100 μs. This combination of fast and slow control strategies ensures both steady-state accuracy and excellent dynamic response.

[0068] According to one aspect of the present application, the AC voltage output by the second secondary winding (pins 4-7 of switching transformer T800) is rectified by the second rectifier diode V803 (US1M), and then charges the energy storage capacitor C815 (220μF / 25V). During steady-state operation, the voltage across C815 is stabilized at about 18V. The parallel ceramic capacitor C816 (1μF) provides high-frequency decoupling and improves the dynamic characteristics of gate driving. Optionally, a current-limiting resistor is further included, which is connected in series between the 18V power supply and the gate of the NMOS transistor, can limit the gate charging current and prevent driving overshoot; forms RC filtering with the gate capacitor C832 (1μF) to suppress high-frequency noise; provides damping during gate voltage regulation and improves loop stability.

[0069] For example, the key parameters of the NMOS transistor Q800 (2N7002K) are as follows: threshold voltage VGS(th)=2V (typical value), when the gate-source voltage VGS=10V, the on-resistance RDS(on)=0.5Ω. In this embodiment, the gate voltage is about 18V, and the source voltage is the 12V output, so VGS=18V-12V=6V, which is much higher than the threshold voltage, ensuring that the NMOS transistor is fully turned on. Further, since the drain-source voltage VDS=12.3V-12.0V=0.3V, and VGS=6V, the condition VDS<<VGS-VGS(th) is satisfied, so the NMOS transistor operates in the deep linear region (also called ohmic region or variable resistance region). In this region, the drain-source current IDS has a linear relationship with the drain-source voltage VDS: IDS = K×(VGS-VGS(th))×VDS, where K is the transconductance parameter. Verified by SPICE simulation, under the conditions of VGS=6V and IDS=4.17A, the equivalent on-resistance of the NMOS transistor is about 0.072Ω, and the power consumption is only P=I 2 ×R=4.17 2 ×0.072=1.25W. The power consumption is reduced compared with the traditional solution. The gate capacitor C832 also plays a stabilizing role. When the load changes suddenly, the instantaneous change of the output voltage is transmitted to the gate through the voltage regulator D802 and the resistor R822, and the gate capacitor C832 provides necessary energy storage, preventing the gate voltage from fluctuating drastically and ensuring the smoothness of the adjustment process.

[0070] According to one aspect of this application, current detection in the PWM controller U801 is achieved through parallel resistors R811 and R812 (equivalent to 0.025Ω). When the power switch is turned on, the primary current flows through the detection resistor, and the resulting voltage signal is sent to pin 1 of the PWM controller U801. The internal current limit of U801 is set to 1V, corresponding to a peak current Ipk = 1V / 0.025Ω = 40A (actually operating at around 1.2A). Preferably, capacitor C829 (470pF) is connected between pin 4 of the PWM controller U801 and ground, forming a dominant pole with the output impedance of the internal error amplifier, with a crossover frequency designed to be around 1kHz. This frequency is much lower than the switching frequency of 65kHz, ensuring system stability. The PWM controller U801 adopts peak current mode control, which can provide cycle-by-cycle current limiting protection and has a fast response speed; it avoids subharmonic oscillations through natural slope compensation; and it has good linear regulation and load regulation.

[0071] In one embodiment of this application, the EMI filtering module employs a two-stage structure. The first stage is a varistor MV800 (MYN12-471K) with a clamping voltage of 470V, which conducts during lightning surges to discharge overvoltage energy to ground. The second stage is an LC filter network, where the common-mode inductor L801 (5mH×2) presents high impedance to common-mode interference but is almost transparent to differential-mode signals. The first and second X capacitors C810 and C811 (0.1μF / 310VAC) are used in parallel, so that if one capacitor fails, the other can still function; this also reduces the equivalent series inductance (ESL) and improves the high-frequency filtering effect.

[0072] In another embodiment of this application, the flyback switching power supply module further includes an output filter circuit, employing a π-type structure. The output filter inductor L800 is connected in series after the first rectifier diode V802, forming a second-order low-pass filter with the output capacitor. The cutoff frequency fc = 1 / (2πsqrt(LC)) = 1 / (2πsqrt(10μH×10μF)) ≈ 16kHz, significantly lower than the switching frequency of 65kHz. Optionally, the output capacitor uses multiple capacitance values ​​connected in parallel: C804 (2.2μF / 25V electrolytic) provides main energy storage, C801 and C802 (1μF ceramic) reduce ESR, and C803 (10nF ceramic) provides ultra-high frequency decoupling. It exhibits good impedance characteristics within the 1Hz-10MHz range. In actual output ripple measurements, the switching frequency component was 50mVpp, which decreased to 5mVpp after linear adjustment; the high-frequency noise (>1MHz) was less than 2mVpp. The total ripple noise is less than 10mVpp, meeting the requirements of sensitive loads. It also includes a bleed resistor R806 (5.1kΩ), which ensures that the output capacitor discharges to a safe voltage (<42V) within 5 seconds after power-off. The discharge time constant τ=RC=5.1k×10μ=51ms, and after 5τ, the voltage drops to 0.7% of its initial value.

[0073] In one possible embodiment, the current transfer ratio (CTR) of the optocoupler D801 (PC817X3CSP9F) is 200-400%, and this embodiment is calculated as 300%. The forward voltage drop of the LED is VF = 1.2V, and the maximum forward current is IF = 50mA. The collector-emitter breakdown voltage of the phototransistor is VCEO = 35V, which meets the requirements of the primary side application. On the light-emitting side, the pull-up resistor R816 (5.05kΩ) provides bias current from the output terminal to the optocoupler LED. When the TL431 regulator D803 is off (output voltage is low), the LED current is minimum: IF_min = (12.3V-VF-2.5V) / (R816+R_TL431) ≈ 1.6mA. When the TL431 regulator D803 is fully turned on (output voltage is high), the LED current is at its maximum: IF_max = (12.3V - VF - 2.5V) / R816 = 8.3V / 5.05kΩ = 1.64mA. The frequency compensation network consists of a capacitor C830 (0.1μF) and a resistor R820 (5.05kΩ) connected in series between pins 2 and 1 of the TL431 regulator D803. The frequency compensation network introduces a zero, fz = 1 / (2πRC) = 315Hz, compensating for the internal poles of the TL431 regulator D803 and improving the phase margin. Simultaneously, capacitor C830 filters out high-frequency noise at pin 1 of the TL431 regulator D803, preventing false triggering. On the receiving side, the collector of the phototransistor is connected to the internal 3.3V reference of U801 via a pull-up resistor R815. When the light intensity increases, the transistor's on-current IC = CTR × IF = 3 × 1.64mA = 4.92mA, and the collector voltage decreases. This voltage change directly affects the PWM duty cycle. The filter capacitor C833 (100pF) and the Miller capacitance of the phototransistor work together to filter out switching noise. At the same time, excessive capacitance is avoided to prevent a slow response. The measured loop bandwidth is approximately 2kHz, and the phase margin is 45°, meeting the stability requirements. The transfer function of the entire feedback loop can be expressed as: H(s) = K_opto × K_TL431 × K_PWM / [(1+s / ωp1)(1+s / ωp2)]; where K_opto = 3 (optical coupler gain), K_TL431 = 40dB (TL431 open-loop gain), K_PWM = 10V / V (PWM modulation gain), ωp1 and ωp2 are system poles, and s is a variable used to describe the system's response to signals of different frequencies. During dynamic response testing, when the load jumped from 10% to 90%, the output voltage deviation was less than 150mV and the recovery time was less than 5ms, proving the effectiveness of the feedback loop design.

[0074] According to one aspect of this application, the input overvoltage protection employs a two-stage design. The first stage is a varistor MV800, which conducts when the input voltage exceeds 470V to dissipate surge energy. The second stage is a transient voltage suppressor diode V804 (SMAJ22CA), which bidirectionally clamps the voltage to 22V to protect the subsequent circuitry. When the DC bus voltage exceeds 22V×sqrt(2)=31V, the transient voltage suppressor diode V804 conducts, working in conjunction with the clamping capacitor C825 (0.1μF / 1kV) to absorb transient energy.

[0075] According to another aspect of this application, output overvoltage protection is achieved through a Zener diode V805. This diode has a reverse breakdown voltage of 18V and is connected between the gate and source of the NMOS transistor Q800. Under normal operation, VGS = 6V, and the Zener diode V805 is not conducting. When the gate voltage rises abnormally (such as due to D802 failure), the Zener diode V805 breaks down, clamping VGS at 18V to prevent gate oxide breakdown. Simultaneously, an excessively high VGS causes the output voltage to rise, triggering the first-stage TL431 protection to shut down the PWM output.

[0076] According to another aspect of this application, overcurrent protection is implemented through pin 1 of the PWM controller U801, which limits the current cycle by cycle. The sensing resistors R811 / / R812 = 0.025Ω. When the primary peak current reaches 40A, the voltage at pin 1 of the PWM controller U801 reaches the 1V threshold, and the PWM controller U801 immediately terminates the current cycle. If current limiting is triggered for eight consecutive cycles (usually caused by an output short circuit), the PWM controller U801 enters a hiccup mode: it stops outputting for 100ms and then attempts to restart. If the fault persists, hiccuping continues until the fault is resolved. Assuming a primary current of 1.5A during a short circuit, operating for 10% of the time, the average power consumption P_avg = 0.1×I 2 ×R = 0.1×1.5 2 ×0.025 = 5.6mW, which is much lower than the continuous mode, effectively protecting power devices.

[0077] Optionally, the output short-circuit protection has a second line of defense. When the output is short-circuited, the VDS of the NMOS transistor Q800 is 12.3V, while VGS drops to near 0V due to the action of the second regulator D802, causing the NMOS transistor Q800 to turn off and limit the short-circuit current. Even if the NMOS transistor Q800 fails and short-circuits, the first-stage 12.3V current-limiting protection remains effective.

[0078] Optionally, although the PWM controller U801 does not integrate temperature detection, passive over-temperature protection is achieved through reasonable thermal design. The thermal resistance design of the power devices is as follows: switching transistor Rth_jc = 62.5°C / W, heatsink Rth_sa = 10°C / W. Under the worst conditions (ambient temperature 50°C, power consumption 3W), the junction temperature Tj = 50 + 3 × (62.5 + 10) = 267°C, which is still lower than the maximum junction temperature of 150°C. Furthermore, the undervoltage lockout (UVLO) function is implemented internally by the PWM controller U801. It stops operating when the VDD voltage is below 10V and starts operating when it is above 16V. A 6V hysteresis prevents the power supply from repeatedly starting and stopping near the critical voltage.

[0079] In one embodiment of this application, the first-stage voltage regulation control is based on PWM modulation of a flyback converter. The control flow is as follows: the 12.3V output voltage is divided 1:1 by resistor divider networks R820 (5.05kΩ) and R821 (5.05kΩ) to obtain a 6.15V sampling voltage; the TL431 regulator D803 compares the 6.15V sampling voltage with an internal 2.5V reference. When the sampling voltage is 6.15V (corresponding to an output of 12.3V), D803 operates in the linear region with a cathode current of approximately 2mA. The error gain is approximately 40dB; the error signal is transmitted to the primary side through optocoupler D801. A 1mA change in LED current results in a 3mA change in phototransistor current (CTR=300%). This phototransistor current change causes a voltage change at pin 4 of the PWM controller U801. The internal comparator of U801 adjusts the PWM duty cycle. The PWM signal drives the power switch, controlling the transformer's energy storage and release. The duty cycle D is related to the output voltage as: Vo = Vin×D×N / (1-D), where N is the turns ratio, Vo is the output voltage, and Vin is the input voltage. The first-stage control loop bandwidth is designed to be 1kHz, with a response time of 1-10ms. The steady-state accuracy is ±0.1V, primarily limited by the TL431 reference accuracy (±1%).

[0080] The second-stage voltage regulation control is based on the variable resistance characteristics of the NMOS transistor. The control flow is as follows: Resistor R813 (1.24kΩ) samples directly from the 12.0V output terminal without voltage division; during the design, it was precisely calculated that when Vo=12.0V, the current flowing through R813 is I=(12.0-2.5) / 1.24k=7.66mA, which is exactly the optimal operating current of TL431 regulator D802; TL431 regulator D802 adjusts the cathode current according to the reference voltage. When the output is higher than 12.0V, the reference voltage is higher than 2.5V, the cathode current increases, and the gate voltage is pulled down through resistor R822 (3.24kΩ); a 1V change in gate voltage results in a change of approximately 20mΩ in the on-resistance of the NMOS transistor. Under a load current of 4.17A, the output voltage change is ΔV=4.17×0.02=83mV; due to the absence of transformer and optocoupler delay, the second-stage response time is only 10-100μs, mainly limited by the charging and discharging of the gate capacitor C832.

[0081] In this embodiment, the first-stage control loop provides coarse adjustment, stabilizing the voltage at 12.3V ± 0.1V; the second-stage control loop provides fine adjustment, precisely stabilizing the voltage at 12.0V ± 0.01V. The two control stages have a 10-fold difference in bandwidth (1kHz vs 10kHz) to avoid mutual interference. During sudden load changes, the second-stage control loop responds quickly to suppress transients; the first-stage control loop tracks slowly to maintain steady state.

[0082] In one embodiment of this application, during the startup phase (0-100ms): Upon power-up, the input capacitor C801 is charged through the startup resistor, and the VDD voltage rises at a rate of dV / dt = I / C = 0.6mA / 10μF = 60V / s. Approximately 260ms later, the 16V startup threshold is reached. The PWM controller U801 begins outputting a PWM signal, and the transformer T800 starts operating. The secondary winding (turns ratio 12:120=0.1) outputs a voltage V_aux = 310V×0.1×D = 31V×0.45 = 14V (no load). The rectifier diode V803 conducts, charging capacitor C815. The charging time constant τ = R×C = 2.49Ω×220μF = 0.55ms. After 5τ (2.75ms), the voltage of capacitor C815 reaches 99.3% of 18V. An 18V voltage is applied to the gate of the NMOS transistor Q800, charging the gate capacitor C832 over a time constant τ = 2.49Ω × 1μF = 2.49μs. The gate voltage stabilizes after approximately 12μs. At this point, the NMOS transistor Q800's VGS = 18V - 0V = 18V (output not yet established), and it is fully turned on with extremely low equivalent resistance (<50mΩ). The main power winding begins charging the output capacitor, and the output voltage gradually increases. When it reaches 12.0V, the second-stage TL431 regulator D802 begins operation, adjusting the gate voltage to an appropriate value. During the steady-state adjustment phase: In steady state, the voltages at each key node are: First-stage output (drain of NMOS transistor Q800): 12.3V ± 0.1V; Second-stage output (source of NMOS transistor Q800): 12.0V ± 0.01V; Gate voltage: 18V (from auxiliary power supply); VGS = 18V - 12V = 6V; VDS = 12.3V - 12V = 0.3V. NMOS transistor operating point analysis: Transconductance gm = 2 × K × (VGS - Vth) = 2 × 1.5 × (6 - 2) = 12S; On-resistance RDS = 1 / gm = 83mΩ (theoretical value); Actual measured RDS ≈ 72mΩ (including package resistance); Power dissipation P = I 2 ×R = 4.17 2×0.072 = 1.25W. The power consumption P_loss of the traditional solution (2V voltage difference) is 4.17×2 = 8.34W; the power consumption P_loss of this embodiment (0.3V voltage difference) is 4.17×0.3 = 1.25W; reducing power consumption and improving efficiency. During the dynamic adjustment phase: load step response (10%→90%, i.e., 0.5A→4.5A): t=0: The load current suddenly increases, and the output voltage drops instantaneously by about 50mV due to the equivalent series resistance (ESR) and equivalent series inductance (ESL); t=0-10μs: The second-stage TL431 regulator D802 detects the voltage drop, the cathode current decreases, and the gate voltage rises by about 0.2V. The on-resistance of the NMOS transistor Q800 decreases, compensating for voltage drops; t=10-100μs: the second-stage loop stabilizes, and the output voltage recovers to 12.0V±10mV; t=0.1-1ms: the first stage detects an increase in average current and increases the PWM duty cycle; t=1-10ms: the first-stage loop stabilizes, and the system enters a new steady state. Throughout the process, the maximum output voltage deviation is <100mV, and the recovery time is <10ms, far superior to traditional single-stage control. In this implementation, the NMOS transistor Q800 has a power consumption of 1.25W, a TO-236 package thermal resistance of 62.5°C / W, and a temperature rise ΔT=1.25×62.5=78°C. At an ambient temperature of 40°C, the junction temperature Tj=40+78=118°C, which is below the 150°C limit, requiring no additional heat dissipation.

[0083] In another embodiment of this application, an ultra-low dropout high-power hybrid adjustable power supply device includes a switching power supply and a MOSFET driver circuit. In the switching power supply section: AC mains power is applied to the power input port, passes through an EMI circuit for electromagnetic interference filtering, and then undergoes rectification and filtering to generate a DC voltage. A PWM-controlled switching transistor and switching transformer convert this DC voltage into the required voltage, thus forming an AC to DC conversion process. In the MOSFET driver circuit section: to reduce the output ripple and noise of the switching power supply, an adjustable power supply with an NMOS core is added to the output of the switching power supply. The output voltage is acquired by a TL431 reference voltage regulator chip and the gate voltage of the NMOS is controlled to achieve linear adjustment. Due to the inherent characteristics of NMOS, the gate voltage must be higher than the output voltage to operate normally. An additional secondary winding is drawn from the switching transformer to power the NMOS; this route powers the gate and requires virtually no output current, which is less than 10mA. The protection functions of this embodiment include short-circuit protection, overvoltage protection, overcurrent protection, overheat protection, overload protection, and leakage protection. It overcomes the shortcomings of traditional power supplies made with power frequency transformers, such as large size, heavy weight, high noise, low efficiency, and high cost.

[0084] Furthermore, the switching power supply adopts a flyback topology. The PWM control chip L6561 generates a PWM drive signal, which drives the gate of the MOSFET through a slow-on, fast-off circuit composed of resistors and diodes. After transformer coupling, it generates two outputs with center taps. The lower part of the tap is the actual power output winding, and the upper part of the tap is for biasing the NMOS transistor. The switching power supply output voltage is regulated to 12.3V by a circuit composed of a TL431 and an optocoupler and applied to the drain of the NMOS transistor. The gate voltage of the NMOS transistor is controlled by the cathode of another TL431, and the reference of this TL431 is used as the sampling terminal for the actual output voltage. The final output voltage is set to 12.00V.

[0085] This invention decomposes the traditional single-stage voltage regulation into a two-stage independent control. The first stage stabilizes the voltage at 12.3V using a flyback switching power supply, while the second stage precisely stabilizes the voltage at 12.0V using an NMOS transistor for linear adjustment, with only a 0.3V voltage difference between the two stages. Simultaneously, an independent auxiliary winding provides an 18V gate bias voltage to the NMOS transistor, ensuring it operates in the deep linear region and achieving ultra-low on-resistance. This reduces voltage drop and power consumption, while improving stability, response speed, and overall efficiency.

[0086] It should be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this utility model will not describe the various possible combinations separately.

Claims

1. A high-power hybrid adjustable power supply device with ultra-low dropout voltage, characterized in that, include: The AC input terminal is configured to receive AC power input. An EMI filter module, whose input terminal is electrically connected to an AC input terminal, includes a common-mode inductor L801, a first X capacitor C810, and a second X capacitor C811; The rectifier and filter module, whose input is electrically connected to the output of the EMI filter module, includes a rectifier bridge D800 and a first filter capacitor C809; A flyback switching power supply module, whose input terminal is electrically connected to the output terminal of a rectifier and filter module, includes: PWM controller U801; The T800 switching transformer has a primary winding, a first-stage winding, and a second-stage winding, wherein the first-stage winding and the second-stage winding share a center tap; The first rectifier diode V802 has its anode electrically connected to the first end of the first primary winding, and its cathode serves as the first DC output terminal. The second rectifier diode V803 has its anode electrically connected to the first end of the second stage winding, and its cathode serves as the auxiliary power output terminal. The linear adjustment module includes: The NMOS transistor Q800 has its drain electrically connected to the first DC output terminal and its source as the final output terminal. The first reference voltage regulator circuit includes a first voltage regulator D803, configured to stabilize the voltage at the first DC output terminal at 12.3V; The second reference voltage regulator circuit includes a second voltage regulator D802, whose cathode is electrically connected to the gate of the NMOS transistor Q800, and whose reference terminal is connected to the final output terminal through a voltage divider resistor network, configured to stabilize the voltage at the final output terminal at 12.0V. The auxiliary power supply output is electrically connected to the gate drive circuit of the NMOS transistor Q800, providing a gate bias voltage higher than the final output voltage.

2. The ultra-low differential pressure high-power hybrid adjustable power supply device according to claim 1, characterized in that: The winding configuration of the switching transformer T800 includes: The primary winding is connected between pin 1 and pin 3; The primary winding is connected between pin 4 and pins 5 and 6, with pin 4 being the center tap. The secondary winding is connected between pin 4 and pin 7; The primary winding is configured to provide main power output with an output current greater than 4A. The secondary winding is configured to provide gate bias power with an output current of less than 10mA. The center tap pin 4 is connected to the circuit ground to form a dual-path differential output structure.

3. The ultra-low differential pressure high-power hybrid adjustable power supply device according to claim 1, characterized in that: The second reference voltage regulator circuit also includes: The first feedback resistor R822 is connected between the gate of the NMOS transistor Q800 and the cathode of the second regulator D802. The second feedback resistor R813 is connected between the gate of the NMOS transistor Q800 and the reference terminal of the second regulator D802. The gate capacitor C828 is connected between the gate of the NMOS transistor Q800 and the anode of the second voltage regulator D802.

4. The ultra-low differential pressure high-power hybrid adjustable power supply device according to claim 1, characterized in that: The gate bias power supply circuit of the flyback switching power supply module includes: The second rectifier diode V803 has its pins 1 and 3 electrically connected to pin 7 of the switching transformer T800; The energy storage capacitor C815 has its positive terminal electrically connected to pin 2 of the second rectifier diode V803, and its negative terminal electrically connected to the circuit ground. The filter capacitor C816 is connected in parallel across the energy storage capacitor C815.

5. The ultra-low differential pressure high-power hybrid adjustable power supply device according to claim 4, characterized in that: The first reference voltage regulator circuit includes: resistors R814, R815, R816, R817, R820, R821, and R823; capacitors C829, C830, C831, and C833; an optocoupler D801; and a first voltage regulator D803. One end of capacitor C829 is connected to both pin 4 of optocoupler D801 and pin 4 of the PWM controller U801. The other end of capacitor C829 is grounded via pin 3 of optocoupler D801. Pin 1 of optocoupler D801 is connected in parallel with one end of resistors R814 and R815. The other ends of resistors R814 and R815 are connected to the power supply. Pin 2 of optocoupler D801 is connected in parallel with... One end of resistor R821, resistor R820, and capacitor C833 is connected to pin 2 of the first voltage regulator D803. The other end of resistor R821 is connected to one end of resistor R815. The other end of resistor R820 is connected to one end of capacitor C830. The other end of capacitor C830 is also connected to the other end of capacitor C833, one end of resistor R816, resistor R823, and capacitor C831, as well as pin 1 of the first voltage regulator D803. The other end of resistor R816 is connected to the power supply. The other end of resistor R823 is also connected to pin 3 of the first voltage regulator D803 and ground. The other end of capacitor C831 is connected to one end of resistor R817. The other end of resistor R817 is connected to the power supply.

6. The ultra-low differential pressure high-power hybrid adjustable power supply device according to claim 1, characterized in that: EMI filtering module, including: Fuse F800 is connected in series to the live wire input terminal of the AC input terminal; The common mode inductor L801 has its first winding connected between the output terminal of fuse F800 and the first AC input terminal of rectifier bridge D800, and its second winding connected between the neutral input terminal of the AC input terminal and the second AC input terminal of rectifier bridge D800. The first capacitor C810 is connected between pin 1 and pin 4 of the common mode inductor L801; The second capacitor C811 is connected between pin 2 and pin 3 of the common mode inductor L801; The varistor MV800 is connected in parallel with the first X capacitor C810.

7. The ultra-low differential pressure high-power hybrid adjustable power supply device according to claim 5, characterized in that: The flyback switching power supply module also includes an output filtering circuit, including: The output filter inductor L800 is connected in series between the cathode of the first rectifier diode V802 and the first DC output terminal; The output capacitor C804 is connected between the output terminal of the output filter inductor L800 and the circuit ground. Output capacitors C801 to C803 are connected in parallel across output capacitor C804; The bleeder resistor R806 is connected in parallel across the output capacitor C801.

8. The ultra-low differential pressure high-power hybrid adjustable power supply device according to claim 1, characterized in that: It also includes protection circuitry, including: Input overvoltage protection branch, including: Transient voltage suppressor diode V804 is bidirectionally connected between the positive and negative terminals of the rectified DC bus. Clamping capacitor C825 is connected in parallel across transient suppression diode V804; Output overvoltage protection branch, including: Zener diode V805 is connected between the gate and source of NMOS transistor Q800 to limit the gate-source voltage to no more than 18V; Overcurrent protection branch, including: The sensing resistor is formed by resistors R811 and R812; When the detection voltage corresponding to the detection resistor exceeds the threshold of pin 1 of the PWM controller U801, cycle-by-cycle current limiting protection is triggered. The short-circuit protection function is implemented through the hiccup mode integrated inside the PWM controller U801. When the overcurrent protection is triggered for 8 consecutive cycles, the hiccup mode is entered.

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