triggering unit

Abstract

The application relates to a trigger unit, which comprises a first comparison feedback circuit, a first clock gating circuit, a main latch and a slave latch assembly; the first comparison feedback circuit is used for detecting the signal jump state of an external input signal according to a first output signal output from a main latch output end, generating a corresponding first state feedback signal, making the first clock gating circuit generate a corresponding first gated clock signal according to the first state feedback signal and a reference clock signal, and controlling the main latch to update the first output signal according to the external input signal in the case that the first gated clock signal is valid; the trigger unit can accurately control the state switching time of the main latch, effectively reduces unnecessary clock rollover in the trigger and the transistor switching activity caused by the clock rollover, and thus effectively reduces the dynamic power consumption related to the clock network and the dynamic power consumption caused by the internal node rollover of the data path.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a trigger unit. Background Technology

[0002] In traditional digital circuit design, flip-flops, as basic sequential logic units, are widely used in data storage and state control. However, traditional flip-flops typically latch data by continuously responding to clock signals. Even if the input data has not changed, a sampling operation is performed as soon as a valid clock edge is received, leading to unnecessary internal node flipping and output switching. This not only increases the dynamic power consumption of the circuit but also adversely affects the overall energy efficiency of the system.

[0003] There is currently no effective solution to the problem of high dynamic power consumption of trigger units in existing technologies. Utility Model Content

[0004] Therefore, it is necessary to provide a triggering unit to address the aforementioned technical problems.

[0005] This application provides a triggering unit, which includes a first comparison feedback circuit, a first clock gating circuit, a master latch, and a slave latch assembly; wherein...

[0006] The input terminal of the master latch is used to receive external input signals; the output terminal of the master latch is connected to the first input terminal of the first comparison feedback circuit and the input terminal of the slave latch assembly, respectively.

[0007] The second input terminal of the first comparison feedback circuit is connected to the input terminal of the main latch; the output terminal of the first comparison feedback circuit is connected to the first input terminal of the first clock gating circuit.

[0008] The second input terminal of the first clock gating circuit is used to receive a reference clock signal; the output terminal of the first clock gating circuit is connected to the clock terminal of the master latch; the clock terminal of the slave latch assembly is used to receive the reference clock signal.

[0009] The first comparison feedback circuit is used to detect the signal transition state of the external input signal based on the first output signal output from the output terminal of the main latch, and generate a corresponding first state feedback signal so that the first clock gating circuit generates a corresponding first gated clock signal based on the first state feedback signal and the reference clock signal, and controls the main latch to update the first output signal based on the external input signal when the first gated clock signal is valid.

[0010] In one embodiment, each clock cycle of the reference clock signal includes a first clock phase and a second clock phase; the first clock phase refers to the time window corresponding to the current clock cycle from the first edge to the second edge; the second clock phase refers to the time window corresponding to the current clock cycle from the second edge to the first edge of the next clock cycle.

[0011] During the first clock phase, the reference clock signal is at a first level;

[0012] During the second clock phase, the reference clock signal is at the second level;

[0013] The first voltage level and the second voltage level are inverses of each other.

[0014] In one embodiment, the first state feedback signal includes a first feedback signal and a second feedback signal;

[0015] The first comparison feedback circuit is further configured to generate a first feedback signal if it detects that the external input signal and the first output signal are the same; the first feedback signal indicates that the signal transition state of the external input signal is that no signal transition has occurred; if it detects that the external input signal and the first output signal are different, it generates a second feedback signal; the second feedback signal indicates that the signal transition state of the external input signal is that a signal transition has occurred.

[0016] The logic levels of the first feedback signal and the second feedback signal are inverses of each other.

[0017] In one embodiment, the first gated clock signal includes a first gated signal and a second gated signal;

[0018] When the first feedback signal is generated during the first clock phase, the first clock gating circuit is further configured to perform level logic conversion on the first feedback signal and the first level during the first clock phase, generate a first gating signal, and control the main latch to be in a holding state to hold the first output signal that was last latched; the first gating signal is consistent with the level state of the first level.

[0019] When the first feedback signal is generated during the second clock phase, the first clock gating circuit is further configured to perform level logic conversion on the first feedback signal and the second level during the second clock phase, generate a second gating signal, and control the main latch to be in a holding state to maintain the first output signal latched last time; the level state of the second gating signal is consistent with that of the first feedback signal.

[0020] In one embodiment, the first gated clock signal includes a third gated signal and a fourth gated signal;

[0021] When the second feedback signal is generated during the first clock phase, the first clock gating circuit is further configured to perform level logic conversion on the second feedback signal and the first level during the first clock phase, generate a third gating signal, and control the main latch to be in a holding state to hold the first output signal that was last latched; the third gating signal is consistent with the level state of the first level.

[0022] When the second feedback signal is generated during the second clock phase, the first clock gating circuit is further configured to perform level logic conversion on the second feedback signal and the second level during the second clock phase, generate a fourth gating signal, control the main latch to enter a transparent state, and update the first output signal according to the latest received external input signal; the level state of the fourth gating signal is consistent with that of the second feedback signal.

[0023] In one embodiment, the slave latch assembly includes a slave latch; the clock terminal of the slave latch is used to receive the reference clock signal; the input terminal of the slave latch is connected to the output terminal of the master latch;

[0024] The latch is configured to enter a transparent state during the first clock phase of the reference clock signal, and output a corresponding second output signal according to the latest received first output signal; and to be in a hold state during the second clock phase of the reference clock signal to hold the second output signal that was last latched.

[0025] In one embodiment, the slave latch assembly includes a slave latch, a second compare feedback circuit, and a second clock gating circuit;

[0026] The input terminal of the slave latch is connected to the output terminal of the master latch; the output terminal of the slave latch is connected to the first input terminal of the second comparison feedback circuit.

[0027] The second input terminal of the second comparison feedback circuit is connected to the input terminal of the slave latch; the output terminal of the second comparison feedback circuit is connected to the first input terminal of the second clock gating circuit.

[0028] The second input terminal of the second clock gate circuit is used to receive the reference clock signal.

[0029] In one embodiment, the second comparison feedback circuit is used to detect the signal transition state of the first output signal based on the second output signal output from the latch output terminal, and generate a corresponding second state feedback signal so that the second clock gating circuit generates a corresponding second gated clock signal based on the second state feedback signal and the reference clock signal, and controls the latch to update the second output signal based on the first output signal when the second gated clock signal is valid.

[0030] In one embodiment, the second state feedback signal includes a third feedback signal and a fourth feedback signal;

[0031] The second comparison feedback circuit is further configured to generate a third feedback signal if the first output signal and the second output signal are detected to be the same; the third feedback signal indicates that the signal transition state of the first output signal is that no signal transition has occurred; and to generate a fourth feedback signal if the first output signal and the second output signal are detected to be different; the fourth feedback signal indicates that the signal transition state of the first output signal is that a signal transition has occurred.

[0032] The logic levels of the third feedback signal and the fourth feedback signal are inverses of each other.

[0033] In one embodiment, the second gated clock signal includes a fifth gated signal and a sixth gated signal;

[0034] When the third feedback signal is generated during the first clock phase, the second clock gating circuit is further configured to perform level logic conversion on the third feedback signal and the first level during the first clock phase to generate a fifth gating signal, controlling the latch to be in a holding state to hold the second output signal last latched; the fifth gating signal is consistent with the level state of the third feedback signal.

[0035] When the third feedback signal is generated during the second clock phase, the second clock gating circuit is further configured to perform level logic conversion on the third feedback signal and the second level during the second clock phase to generate a sixth gating signal, controlling the latch to be in a holding state to hold the second output signal last latched; the sixth gating signal is consistent with the level state of the second level.

[0036] In one embodiment, the second gated clock signal includes a seventh gated signal and an eighth gated signal;

[0037] When the fourth feedback signal is generated during the first clock phase, the second clock gating circuit is further configured to perform level logic conversion on the fourth feedback signal and the first level during the first clock phase, generate a seventh gating signal, control the latch to enter the transparent state, and update the second output signal according to the latest received first output signal; the level state of the seventh gating signal is consistent with that of the fourth feedback signal.

[0038] When the fourth feedback signal is generated during the second clock phase, the second clock gating circuit is further configured to perform level logic conversion on the fourth feedback signal and the second level during the second clock phase to generate an eighth gating signal, which controls the latch to be in a holding state to hold the second output signal last latched; the eighth gating signal is consistent with the level state of the second level.

[0039] In one embodiment, the first comparison feedback circuit includes an XOR logic circuit; the first clock gating circuit includes an OR gate logic circuit.

[0040] The master latch is a falling-edge triggered D-type flip-flop; the slave latch is a rising-edge triggered D-type flip-flop.

[0041] In one embodiment, the first comparison feedback circuit includes an XOR logic circuit; the first clock gating circuit includes an AND gate logic circuit.

[0042] The master latch is a rising-edge triggered D-type flip-flop; the slave latch is a falling-edge triggered D-type flip-flop.

[0043] In one embodiment, the first comparison feedback circuit includes an XOR logic circuit; the first clock gating circuit includes an OR gate logic circuit.

[0044] The second comparison feedback circuit includes an XOR logic circuit; the second clock gate circuit includes an AND gate logic circuit.

[0045] The master latch is a falling-edge triggered D-type flip-flop; the slave latch is a rising-edge triggered D-type flip-flop.

[0046] In one embodiment, the first comparison feedback circuit includes an XOR logic circuit; the first clock gating circuit includes an AND gate logic circuit.

[0047] The second comparison feedback circuit includes an XOR logic circuit; the second clock gate circuit includes an OR gate logic circuit.

[0048] The master latch is a rising-edge triggered D-type flip-flop; the slave latch is a falling-edge triggered D-type flip-flop.

[0049] In one embodiment, the triggering unit is a library unit in the standard cell library of digital circuit EDA.

[0050] The aforementioned triggering unit detects the signal transition state of the external input signal through a first comparison feedback circuit, generates a corresponding first state feedback signal, and then performs a logical conversion between the first state feedback signal and the reference clock signal based on a first clock gating circuit to generate a corresponding first gating clock signal. When the first gating clock signal is valid, the main latch is controlled to enter a transparent state. Based on this, the timing of the main latch state switching can be precisely controlled, effectively reducing unnecessary clock flips inside the trigger and the resulting transistor switching activity. This effectively reduces the dynamic power consumption related to the clock network and the dynamic power consumption caused by the flipping of nodes inside the data path, while simplifying the complexity of the circuit implementation and improving the stability and timing controllability of the triggering unit. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the overall structure of the triggering unit in one embodiment;

[0053] Figure 2 This is a schematic diagram of the waveform of the reference clock signal in one embodiment;

[0054] Figure 3 This is a schematic diagram of the overall structure of the triggering unit in the first embodiment;

[0055] Figure 4 This is a schematic diagram of the overall structure of the triggering unit in the first specific embodiment;

[0056] Figure 5 The timing waveform diagram of the triggering unit in the first specific embodiment is shown below.

[0057] Figure 6 This is a schematic diagram of the overall structure of the triggering unit in the second specific embodiment;

[0058] Figure 7 This is a timing waveform diagram of the triggering unit in the second specific embodiment;

[0059] Figure 8 This is a schematic diagram of the overall structure of the triggering unit in the second embodiment;

[0060] Figure 9 This is a schematic diagram of the overall structure of the triggering unit in the third specific embodiment;

[0061] Figure 10 This is a timing waveform diagram of the triggering unit in the third specific embodiment;

[0062] Figure 11 This is a schematic diagram of the overall structure of the triggering unit in the fourth specific embodiment;

[0063] Figure 12 The timing waveform diagram of the triggering unit in the fourth specific embodiment is shown.

[0064] Explanation of reference numerals in the attached figures:

[0065] 100. First comparison feedback circuit; 200. First clock gating circuit; 300. Master latch; 400. Slave latch assembly; 410. Slave latch; 420. Second comparison feedback circuit; 430. Second clock gating circuit. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0068] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0069] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0070] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.

[0071] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0072] In modern integrated circuit (IC) design, electronic design automation (EDA) tools and standard cell libraries form the core technological foundation for digital circuit implementation. Digital circuits are typically constructed using standard logic gates (such as AND gates, OR gates, NOT gates, XOR gates, etc.) and sequential storage elements (mainly flip-flops). Logic gates implement combinational logic functions, while flip-flops store the results of operations and form sequential logic circuit structures.

[0073] Among them, the edge-triggered D flip-flop (DFF) synchronously transmits the logic state of the data input terminal (D) to the data output terminal (Q) when triggered by a valid edge of the clock signal (rising or falling edge), and maintains the stability of the output state in subsequent clock cycles until the next valid edge arrives. Based on this characteristic, flip-flops have become the basic functional units for constructing sequential circuit modules such as registers, counters, and finite state machines.

[0074] Furthermore, the power consumption of edge-triggered flip-flops mainly includes two aspects: static power consumption and dynamic power consumption. Static power consumption is mainly caused by transistor leakage current; dynamic power consumption originates from signal switching; dynamic power consumption can be further divided into data-dependent dynamic power consumption and clock-dependent dynamic power consumption.

[0075] Data-dependent dynamic power consumption occurs when the output state of a flip-flop changes, driving subsequent combinational logic circuits to generate corresponding signal switches. Clock-dependent dynamic power consumption, on the other hand, is caused by the periodic switching of the clock signal. Specifically, even if the input data remains unchanged and the output does not change, the clock signal continues to drive the internal clock buffer and transistor circuits, resulting in redundant switching operations. In traditional designs, clock-dependent dynamic power consumption is the main source of power consumption, especially during the data retention phase, which continues to consume energy and severely restricts overall energy efficiency.

[0076] To reduce the dynamic power consumption of flip-flops in digital circuits, related technologies propose optimizing power consumption by setting a data selector module at the front end of the flip-flop. This data selector module is controlled by an external enable signal. Specifically, when the enable signal is valid, the external input data is transmitted to the flip-flop input; when the enable signal is invalid, the flip-flop output data is fed back to its input. This technology effectively suppresses unnecessary data transmission path switching by maintaining the stability of the input data, thereby reducing the dynamic power consumption caused by data flipping. However, this solution fails to block the continuous driving of the clock signal on the internal circuitry of the flip-flop, thus failing to reduce clock-dependent dynamic power consumption. Based on this, this application proposes a trigger unit designed to precisely control the timing of the master latch state switching, effectively reducing unnecessary clock flips within the flip-flop and the resulting transistor switching activity, thereby effectively reducing clock network-related dynamic power consumption and dynamic power consumption caused by internal node flipping in the data path. Simultaneously, it simplifies the complexity of circuit implementation and improves the stability and timing controllability of the trigger unit.

[0077] In one embodiment, such as Figure 1 As shown, Figure 1 This is a schematic diagram of the overall structure of the trigger unit in one embodiment; the trigger unit includes a first comparison feedback circuit 100, a first clock gating circuit 200, a master latch 300, and a slave latch assembly 400; wherein,

[0078] The input terminal of the master latch 300 is used to receive the external input signal DATA; the output terminal of the master latch 300 is connected to the first input terminal of the first comparison feedback circuit 100 and the input terminal of the slave latch assembly 400, respectively.

[0079] The second input terminal of the first comparison feedback circuit 100 is connected to the input terminal of the main latch 300; the output terminal of the first comparison feedback circuit 100 is connected to the first input terminal of the first clock gate circuit 200.

[0080] The second input terminal of the first clock gate circuit 200 is used to receive the reference clock signal CLK; the output terminal of the first clock gate circuit 200 is connected to the clock terminal of the main latch 300; the clock terminal of the latch assembly 400 is used to receive the reference clock signal CLK.

[0081] The first comparison feedback circuit 100 is used to detect the signal transition state of the external input signal DATA based on the first output signal QM output from the output terminal of the main latch 300, and generate a corresponding first state feedback signal EN1, so that the first clock gating circuit 200 generates a corresponding first gated clock signal EN_CLK1 based on the first state feedback signal EN1 and the reference clock signal CLK, and controls the main latch 300 to update the first output signal QM based on the external input signal DATA when the first gated clock signal EN_CLK1 is valid.

[0082] The latch assembly 400 includes at least a slave latch. It should be noted that in this embodiment, the trigger unit adopts a master-slave latch configuration (i.e., including a master latch and a slave latch). Based on the different level-sensitivity characteristics of the master and slave latches, reliable data transmission is achieved through complementary clock phases.

[0083] It should be noted that the level sensitivity of the master latch is synchronized with the second clock phase of the reference clock signal CLK. Specifically, it enters a transparent state during the second clock phase, capable of receiving and temporarily storing external input data; while during the first clock phase, it enters a hold state, blocking new data input and maintaining the already latched value. Similarly, the level sensitivity of the slave latch is synchronized with the first clock phase of the reference clock signal CLK. During the first clock phase, it enters a transparent state, outputting the data stored in the previous stage (master latch); while during the second clock phase, it enters a hold state, locking the output to prevent interference from the current update operation of the master latch, thus ensuring stable and reliable output.

[0084] It should be noted that the reference clock signal CLK is used to provide the basic timing cycle. Each clock cycle of the reference clock signal CLK includes a first clock phase and a second clock phase; wherein, the first clock phase refers to the time window corresponding to the current clock cycle of the reference clock signal CLK from the first edge to the second edge; the second clock phase refers to the time window corresponding to the current clock cycle of the reference clock signal CLK from the second edge to the first edge of the next clock cycle.

[0085] In this design, the first edge and the second edge are two mutually exclusive edge signals. For example, in an embodiment where the master latch is triggered by a rising edge and the slave latch by a falling edge, the first edge is a falling edge and the second edge is a rising edge; in an embodiment where the master latch is triggered by a falling edge and the slave latch by a rising edge, the first edge is a rising edge and the second edge is a falling edge. It is understood that the first clock phase and the second clock phase are sequential and mutually exclusive in time, together constituting a complete clock cycle.

[0086] The first state feedback signal EN1 is used to characterize whether the external input signal DATA has undergone a logical transition relative to the first output signal QM (i.e., the currently latched data) output by the main latch 300.

[0087] The first state feedback signal EN1 includes a first feedback signal and a second feedback signal; the logic levels of the first feedback signal and the second feedback signal are inverted; the first feedback signal is used to characterize the signal transition state of the external input signal DATA as no signal transition has occurred; the second feedback signal is used to characterize the signal transition state of the external input signal DATA as a signal transition has occurred.

[0088] In an exemplary embodiment, if the first comparison feedback circuit 100 detects that the logic value of the external input signal DATA received at the input terminal of the main latch 300 is consistent with the logic value of the first output signal QM output at the output terminal of the main latch 300, it indicates that the external input signal DATA has not undergone a signal transition. At this time, the first comparison feedback circuit 100 generates a first feedback signal and transmits it to the first clock gating circuit 200. If the first comparison feedback circuit 100 detects that the logic value of the external input signal DATA received at the input terminal of the main latch 300 is inconsistent with the logic value of the first output signal QM output at the output terminal of the main latch 300, it indicates that the external input signal DATA has undergone a signal transition. At this time, the first comparison feedback circuit 100 generates a second feedback signal and transmits it to the first clock gating circuit 200.

[0089] The first clock gate circuit 200 is used to generate a corresponding first gate clock signal EN_CLK1 based on the first state feedback signal EN1 (i.e., the first feedback signal or the second feedback signal) and the reference clock signal CLK.

[0090] The first gate clock signal EN_CLK1 is used to determine when the main latch 300 enters the transparent state (i.e., updates the first output signal QM according to the external input signal DATA), and to determine when the main latch 300 is in the hold state (i.e., keeps the current first output signal QM unchanged).

[0091] The first gate clock signal EN_CLK1 has two states: valid and invalid. In an exemplary embodiment, when the first gate clock signal EN_CLK1 is valid, it is used to control the main latch 300 to enter a transparent state, so that the main latch 300 updates the first output signal QM according to the external input signal DATA; when the first gate clock signal EN_CLK1 is invalid, it is used to control the main latch 300 to be in a holding state.

[0092] It should be noted that the validity of the first gate clock signal EN_CLK1 is not determined solely by the reference clock signal CLK, but is determined by a combination of factors, including the first state feedback signal EN1 and the level sensitivity characteristics of the main latch 300.

[0093] Understandably, based on the level-sensitive characteristics of the main latch 300 in the second clock phase, combined with the first comparison feedback circuit 100 and the first clock gating circuit 200, it can dynamically sense the signal transition state of the external input signal DATA, so that the main latch 300 enters the transparent state and updates its internal data only when the external input signal DATA has indeed changed and the first gating clock signal EN_CLK1 is valid.

[0094] Specifically, the basic condition for generating a valid first gate clock signal EN_CLK1 is met only when the external input signal DATA ≠ the first output signal QM. At this time, it is also necessary to further combine the reference clock signal CLK and the level sensitivity characteristics of the main latch 300 to generate a valid first gate clock signal EN_CLK1, so as to ensure that the main latch 300 can be accurately controlled to enter the transparent state.

[0095] When the external input signal DATA = the first output signal QM, regardless of whether the reference clock signal CLK is at a high level or a low level, and regardless of whether the current time is in the second clock stage that is sensitive to the main latch 300, the first gate clock signal EN_CLK1 remains in an invalid state to control the main latch 300 to be in a holding state, preventing unnecessary clock flips inside the main latch 300 and the resulting transistor switching activity.

[0096] It should be noted that the first comparison feedback circuit 100 and the first clock gate circuit 200 can be more tightly integrated and coupled at the transistor level and within the trigger unit to fully save redundant logic, or they can be rapidly integrated as additional circuits. No specific limitations are made here.

[0097] In this embodiment, the first comparison feedback circuit 100 detects the signal transition state of the external input signal DATA and generates a corresponding first state feedback signal EN1. Then, based on the first clock gating circuit 200, the first state feedback signal EN1 and the reference clock signal CLK are logically converted to generate a corresponding first gated clock signal EN_CLK1. When the first gated clock signal EN_CLK1 is valid, the main latch 300 is controlled to enter a transparent state. Based on this, the timing of the state switching of the main latch 300 can be precisely controlled, effectively reducing unnecessary clock flips inside the trigger and the transistor switching activities caused by them. This effectively reduces the dynamic power consumption related to the clock network and the dynamic power consumption caused by the flipping of nodes inside the data path. At the same time, it simplifies the complexity of the circuit implementation and improves the stability and timing controllability of the trigger unit.

[0098] In one embodiment, such as Figure 2 As shown, Figure 2 This is a waveform diagram of a reference clock signal in one embodiment; each clock cycle of the reference clock signal CLK includes a first clock phase and a second clock phase; the first clock phase refers to the time window corresponding to the current clock cycle from the first edge to the second edge; the second clock phase refers to the time window corresponding to the current clock cycle from the second edge to the first edge of the next clock cycle.

[0099] During the first clock phase, the reference clock signal CLK is at the first level;

[0100] During the second clock phase, the reference clock signal CLK is at the second level;

[0101] The first and second voltage levels are inverses of each other.

[0102] The first edge and the second edge are two mutually exclusive edge signals. The first clock phase and the second clock phase are sequential and mutually exclusive in time, together forming a complete clock cycle.

[0103] For example, with Figure 2 Taking the reference clock signal CLK as an example, Figure 2 The first edge of the reference clock signal CLK is a rising edge and the second edge is a falling edge; during the first clock phase, the reference clock signal CLK is at a high level (i.e., the first level), and during the second clock phase, the reference clock signal CLK is at a low level (i.e., the second level).

[0104] It should be noted that the edge polarity of the reference clock signal CLK can be flexibly configured according to the trigger type corresponding to the master-slave latch, and is not specifically limited here. For example, in other embodiments, the falling edge is used as the first edge and the rising edge is used as the second edge. Correspondingly, in the first clock phase, the reference clock signal CLK is at a low level (i.e., the first level), and in the second clock phase, the reference clock signal CLK is at a high level (i.e., the second level).

[0105] In this embodiment, each clock cycle of the reference clock signal CLK is divided into a first clock phase and a second clock phase, which lays the foundation for the contention-free data transmission of the trigger unit in the master-slave latch configuration.

[0106] In one embodiment, the first state feedback signal EN1 includes a first feedback signal and a second feedback signal;

[0107] The first comparison feedback circuit 100 is further configured to generate a first feedback signal if the external input signal DATA and the first output signal QM are detected to be the same, and to generate a second feedback signal if the external input signal DATA and the first output signal QM are detected to be different.

[0108] The first feedback signal indicates that the signal transition state of the external input signal DATA is no signal transition; the second feedback signal indicates that the signal transition state of the external input signal DATA is a signal transition.

[0109] The logic levels of the first feedback signal and the second feedback signal are opposite to each other; for example, if the first feedback signal is high, the second feedback signal is low; if the first feedback signal is low, the second feedback signal is high.

[0110] In this embodiment, based on the first comparison feedback circuit 100, the logic transition of the external input signal DATA can be accurately sensed, and a corresponding first state feedback signal EN1 can be generated and fed back to the first clock gate circuit 200, providing a key logical basis for the first clock gate circuit 200 to generate an accurate first gate clock signal EN_CLK1.

[0111] In one embodiment, the first gated clock signal EN_CLK1 includes a first gated signal and a second gated signal;

[0112] When the first feedback signal is generated in the first clock phase, the first clock gate circuit 200 is also used to perform level logic conversion on the first feedback signal and the first level in the first clock phase, generate the first gate signal, and control the main latch 300 to be in the holding state so as to hold the first output signal QM latched last time.

[0113] The first gate signal maintains the same level as the first level.

[0114] When the first feedback signal is generated in the second clock phase, the first clock gate circuit 200 is also used to perform level logic conversion on the first feedback signal and the second level in the second clock phase to generate a second gate signal, which controls the main latch 300 to be in a holding state so as to hold the first output signal QM that was latched last time.

[0115] The second gating signal maintains the same level as the first feedback signal.

[0116] The first clock gate circuit 200 has the capability of level logic conversion.

[0117] In an exemplary embodiment, when the first feedback signal is generated in the first clock phase, it indicates that the external input signal DATA currently received by the main latch 300 during the first clock phase is the same as the first output signal QM currently output by the main latch 300. At this time, since it is in the first clock phase, and the level sensitivity characteristic of the main latch 300 is synchronized with the second clock phase, it is necessary to ensure that the main latch 300 is in the holding state during the first clock phase to prevent data sampling timing from being disordered. Based on this, when the first feedback signal is generated in the first clock phase, the first clock gating circuit 200 needs to perform level logic conversion on the first feedback signal and the first level to generate a first gating signal with the same level state as the first level, and control the main latch 300 to be in the holding state to maintain the first output signal QM latched last time.

[0118] In another exemplary embodiment, when the first feedback signal is generated during the second clock phase, it indicates that the external input signal DATA currently received by the main latch 300 during the second clock phase is the same as the first output signal QM currently output by the main latch 300. At this time, the first clock gating circuit 200 performs level logic conversion between the first feedback signal and the second level to generate a second gating signal that maintains the same level state as the first feedback signal. Based on the second gating signal, the main latch 300 is controlled to remain in a holding state to maintain the last latched first output signal QM. Although the level sensitivity of the main latch 300 is synchronized with the second clock phase, the second gating signal can force the main latch 300 to remain in a holding state, thereby avoiding redundant power consumption when there is no data change. It is understood that in this embodiment (i.e., when the first feedback signal is generated during the second clock phase), regardless of the state of the reference clock signal CLK, it will not have any impact on the main latch 300, further reducing dynamic power consumption.

[0119] It should be noted that the control master latch 300 is in a holding state during the second clock phase in at least the following two situations:

[0120] Scenario 1: For the same clock cycle of the reference clock signal CLK, when the external input signal DATA received by the main latch 300 and the first output signal QM are always the same throughout the entire clock cycle, the first comparison feedback circuit 100 will always output the first feedback signal throughout the entire clock cycle (including the first clock phase and the second clock phase); while the first clock gate circuit 200 will generate the first gate signal and the second gate signal successively according to the first feedback signal and the first level, and the first feedback signal and the second level, so as to control the clock of the main latch 300 to be in a hold state throughout the entire clock cycle, reducing unnecessary state switching and clock flipping inside the main latch 300.

[0121] Scenario 2: After the main latch 300 completes the data update in the second clock phase (i.e., during the second clock phase, if the external input signal DATA is different from the first output signal QM, the first output signal QM is updated according to the external input signal DATA), the first comparison feedback circuit 100 can immediately detect that the external input signal DATA received by the main latch 300 is the same as the first output signal QM, and then outputs the first feedback signal to ensure that the first clock gating circuit 200 responds to the first feedback signal in a timely manner. Based on the first feedback signal and the second level, a second gating signal with the same level state as the first feedback signal is generated, thereby controlling the main latch 300 to immediately return to the holding state after the data update, reducing unnecessary power consumption.

[0122] In one specific embodiment, when the main latch 300 is a falling-edge triggered D-type flip-flop, the first edge of the reference clock signal CLK is a rising edge, and the second edge is a falling edge. During the first clock phase, the reference clock signal CLK is high, i.e., the first level is high. During the second clock phase, the reference clock signal CLK is low, i.e., the second level is low. In this embodiment, the first feedback signal is high. When the first feedback signal is generated during the first clock phase, the first clock gating circuit 200 performs a level logic conversion between the first feedback signal (i.e., high level) and the first level (i.e., high level) to generate a first gating signal (i.e., high level) that is consistent with the level state of the first level (i.e., high level), controlling the main latch 300 to be in a holding state to hold the first output signal QM latched last time. When the first feedback signal is generated in the second clock phase, the first clock gate circuit 200 performs level logic conversion on the first feedback signal (i.e., high level) and the second level (i.e., low level) to generate a second gate signal (i.e., high level) that is consistent with the level state of the first feedback signal (i.e., high level), and controls the main latch 300 to be in a holding state so as to hold the first output signal QM that was latched last time.

[0123] In another specific embodiment, when the main latch 300 is a rising-edge triggered D-type flip-flop, the first edge of the reference clock signal CLK is a falling edge, and the second edge is a rising edge. During the first clock phase, the reference clock signal CLK is at a low level, i.e., the first level is low. During the second clock phase, the reference clock signal CLK is at a high level, i.e., the second level is high. In this embodiment, the first feedback signal is at a low level. When the first feedback signal is generated during the first clock phase, the first clock gating circuit 200 performs a level logic conversion between the first feedback signal (i.e., low level) and the first level (i.e., low level) to generate a first gating signal (i.e., low level) that is consistent with the level state of the first level (i.e., low level), controlling the main latch 300 to be in a holding state to hold the first output signal QM latched last time. When the first feedback signal is generated in the second clock phase, the first clock gate circuit 200 performs level logic conversion on the first feedback signal (i.e., low level) and the second level (i.e., high level) to generate a second gate signal (i.e., low level) that is consistent with the level state of the first feedback signal (i.e., low level), and controls the main latch 300 to be in a holding state so as to hold the first output signal QM that was latched last time.

[0124] In this embodiment, the first clock gating circuit 200 can adaptively select to perform level logic conversion with the first level or the second level according to the generation timing of the first feedback signal (first clock stage or second clock stage), thereby generating the corresponding first gating signal or second gating signal. Based on the first gating signal or the second gating signal, it is ensured that no matter which clock stage, as long as the external input signal DATA is the same as the first output signal QM (i.e. no data update is needed or the data update has been completed), the main latch 300 can be quickly and reliably controlled in the holding state, so as to effectively reduce unnecessary dynamic power consumption.

[0125] In one embodiment, the first gated clock signal EN_CLK1 includes a third gated signal and a fourth gated signal;

[0126] When the second feedback signal is generated in the first clock phase, the first clock gate circuit 200 is also used to perform level logic conversion on the second feedback signal and the first level in the first clock phase to generate a third gate signal, which controls the main latch 300 to be in a holding state so as to hold the first output signal QM that was latched last time.

[0127] The third gating signal maintains the same level as the first level.

[0128] When the second feedback signal is generated in the second clock phase, the first clock gate circuit 200 is also used in the second clock phase to perform level logic conversion on the second feedback signal and the second level, generate the fourth gate signal, control the main latch 300 to enter the transparent state, and update the first output signal QM according to the latest received external input signal.

[0129] The fourth gating signal maintains the same level as the second feedback signal.

[0130] In an exemplary embodiment, when the second feedback signal is generated in the first clock phase, it indicates that the external input signal DATA currently received by the main latch 300 during the first clock phase is different from the first output signal QM currently output. At this time, since it is in the first clock phase, and the level sensitivity characteristic of the main latch 300 is synchronized with the second clock phase, it is necessary to ensure that the main latch 300 is in a hold state during the first clock phase to prevent data sampling timing from being disordered. Based on this, when the second feedback signal is generated in the first clock phase, the first clock gating circuit 200 needs to perform level logic conversion on the second feedback signal and the first level to generate a third gating signal with the same level state as the first level, controlling the main latch 300 to be in a hold state to maintain the first output signal QM latched last time.

[0131] In another exemplary embodiment, when the second feedback signal is generated during the second clock phase, it indicates that the external input signal DATA currently received by the main latch 300 during the second clock phase is different from the currently output first output signal QM. At this time, since the level sensitivity of the main latch 300 is synchronized with the second clock phase, it is necessary to perform level logic conversion between the second feedback signal and the second level through the first clock gating circuit 200 to generate a fourth gating signal consistent with the level state of the second feedback signal. Based on the fourth gating signal, the main latch 300 is controlled to enter a transparent state, and the first output signal QM is updated according to the latest received external input signal DATA.

[0132] In one specific embodiment, when the main latch 300 is a falling-edge triggered D-type flip-flop, the first edge of the reference clock signal CLK is a rising edge, and the second edge is a falling edge. During the first clock phase, the reference clock signal CLK is high, i.e., the first level is high. During the second clock phase, the reference clock signal CLK is low, i.e., the second level is low. In this embodiment, the second feedback signal is low. When the second feedback signal is generated during the first clock phase, the first clock gating circuit 200 performs a level logic conversion between the second feedback signal (i.e., low level) and the first level (i.e., high level) to generate a third gating signal (i.e., high level) that is consistent with the level state of the first level (i.e., high level), controlling the main latch 300 to be in a holding state to hold the first output signal QM latched last time. When the second feedback signal is generated in the second clock phase, the first clock gate circuit 200 performs level logic conversion on the second feedback signal (i.e., low level) and the second level (i.e., low level) to generate a fourth gate signal (i.e., low level) that is consistent with the level state of the second feedback signal (i.e., low level), controls the main latch 300 to enter the transparent state, and updates the first output signal QM according to the latest received external input signal DATA.

[0133] In another specific embodiment, when the main latch 300 is a rising-edge triggered D-type flip-flop, the first edge of the reference clock signal CLK is a falling edge, and the second edge is a rising edge. During the first clock phase, the reference clock signal CLK is low, i.e., the first level is low. During the second clock phase, the reference clock signal CLK is high, i.e., the second level is high. In this embodiment, the second feedback signal is high. When the second feedback signal is generated during the first clock phase, the first clock gating circuit 200 performs a level logic conversion between the second feedback signal (i.e., high level) and the first level (i.e., low level) to generate a third gating signal (i.e., low level) that is consistent with the level state of the first level (i.e., low level), controlling the main latch 300 to be in a holding state to hold the first output signal QM latched last time. When the second feedback signal is generated in the second clock phase, the first clock gate circuit 200 performs level logic conversion on the second feedback signal (i.e., high level) and the second level (i.e., high level) to generate a fourth gate signal (i.e., high level) that is consistent with the level state of the second feedback signal (i.e., high level), controls the main latch 300 to enter the transparent state, and updates the first output signal QM according to the latest received external input signal DATA.

[0134] In this embodiment, the first clock gating circuit 200 can adaptively select to perform level logic conversion with the first level or the second level according to the generation timing of the second feedback signal (first clock stage or second clock stage), thereby generating the corresponding third gating signal or fourth gating signal; based on the third gating signal, it can ensure that the main latch 300 is always in the holding state during the first clock stage, and no data update is performed even if the external input signal DATA is different from the first output signal QM; based on the fourth gating signal, it can accurately control the main latch 300 to enter the transparent state, update the first output signal QM according to the latest received external input signal DATA, and realize timely data response and latching.

[0135] In one embodiment, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the overall structure of the trigger unit in the first embodiment; the latch assembly 400 includes a slave latch 410; the clock terminal of the slave latch 410 is used to receive the reference clock signal CLK; the input terminal of the slave latch 410 is connected to the output terminal of the master latch 300;

[0136] The latch 410 is used to enter a transparent state during the first clock phase of the reference clock signal CLK, and output a corresponding second output signal Q according to the latest received first output signal QM; and to be in a holding state during the second clock phase of the reference clock signal to hold the second output signal Q that was last latched.

[0137] It should be noted that the level sensitivity of latch 410 is synchronized with the first clock phase. That is, latch 410 enters the transparent state in the first clock phase, and the second output signal Q follows the first output signal QM; while in the second clock phase, it enters the holding state and locks the output.

[0138] Specifically, for application scenarios where the latch component 400 includes the latch 410, the following provides two specific implementation methods for the trigger unit:

[0139] In the first specific embodiment, see Figure 4 The first comparison feedback circuit 100 includes an XOR logic circuit; the first clock gate circuit 200 includes an OR gate logic circuit; the master latch 300 is a falling edge triggered D flip-flop; and the slave latch 410 is a rising edge triggered D flip-flop.

[0140] by Figure 5 Taking the timing waveform diagram of the trigger unit shown as an example, for... Figure 4 The working principle of the trigger unit shown is explained in detail below:

[0141] Figure 5 In this circuit, the first edge of the reference clock signal CLK is a rising edge, and the second edge is a falling edge. During the first clock phase, the reference clock signal CLK is high, and during the second clock phase, the reference clock signal CLK is low. DATA represents the external input signal, QM represents the first output signal, EN1 represents the first state feedback signal, EN_CLK1 represents the first gate clock signal, and Q represents the second output signal.

[0142] from Figure 5 As can be seen, during cycle T0, the trigger unit is inactive (i.e., DATA=0, QM=0, Q=0). At this time, the DATA received by the main latch 300 is the same as its output QM. EN1 outputs a high level throughout cycle T0. EN_CLK1 follows CLK (high level) as high during the first clock phase of cycle T0, and follows EN1 (high level) as high during the second clock phase of cycle T0. The main latch 300 remains in a holding state throughout the entire cycle T0. During the first clock phase of cycle T0, the slave latch 410 enters a transparent state, and during the second clock phase, the slave latch 410 remains in a holding state. However, since the main latch 300 does not update data throughout cycle T0, its final output Q remains unchanged. Therefore, during cycle T0, the invalid clock toggling activity of the main latch 300 inside the trigger unit is effectively suppressed, exhibiting significant low-power characteristics.

[0143] Entering cycle T1, DATA jumps from 0 to 1 in the first clock phase and remains stable thereafter. In the first clock phase, since the DATA received by the master latch 300 (DATA=1) is different from its current output QM (QM=0), EN1 goes low. At this time, EN_CLK1 follows the change of CLK, thus EN_CLK1 is high during the first clock phase, the master latch 300 is in a hold state, and QM remains 0. Meanwhile, the slave latch 410, having no data update, maintains its output Q at 0. Then, entering the second clock phase, EN1 remains low, and EN_CLK1 follows EN1 to go low. The master latch 300 enters a transparent state, and its output QM is updated to the value of DATA (DATA=1), i.e., QM is updated to 1. After QM is updated to 1, the first comparison feedback circuit 100, i.e., the XOR logic circuit, detects that DATA (DATA=1) is the same as the updated QM (QM=1). EN1 immediately flips back to high level, causing EN_CLK1 to be pulled high, and the master latch 300 then returns to the holding state. For the slave latch 410, since it is still in the second clock phase, the slave latch 410 continues to maintain its state, and Q remains 0.

[0144] Entering cycle T2, during the first clock phase, latch 410 enters a transparent state, and its output Q is immediately updated to the value of the main latch 300's output QM (QM=1), i.e., Q is updated to 1, thus completing a full data latching and transfer, realizing the basic logic function of the trigger unit. During this clock phase, if there is no new DATA input change in the main latch 300, EN1 and EN_CLK1 corresponding to the main latch 300 remain at a high level. Then, the second clock phase begins. Figure 5 The waveform diagram shows that during the second clock phase of cycle T2, DATA experiences a brief glitch (indicated by the gray area) before stabilizing to 0. During this period, the master latch 300 first responds to this glitch input: from Figure 5As shown by the red dashed box, when DATA briefly deviates from its stable value (i.e., the period immediately following its entry into the gray area, for example, changing from 1 to 0), it becomes inconsistent with the then-current QM (QM=1). EN1 will go low, and EN_CLK1 will follow suit, causing QM to attempt to follow the unstable DATA. However, once DATA finally stabilizes at 0, because DATA (DATA=0) is still inconsistent with the previous QM (QM=1), EN1 remains low, and EN_CLK1 is also low. The main latch 300 enters a transparent state, and its output QM is finally updated to the new DATA value, i.e., 0. It should be noted that QM follows the changes in unstable DATA. This process occurs because changes in DATA affect the level of EN1, which in turn affects the level of EN_CLK1, ultimately causing a change in QM. Therefore, the change in QM has a certain delay compared to the change in DATA. Figure 5 During the period when DATA just stabilizes at 0 (as indicated by the green dashed box), QM does not change accordingly and remains at 1, resulting in a discrepancy between DATA and QM. Subsequently, because DATA (DATA=0) and QM (QM=0) are consistent, EN1 goes high again, and EN_CL1K also goes high, putting the master latch 300 into a holding state. Since the slave latch 410 remains in a holding state throughout the entire second clock phase of cycle T2, any brief fluctuations in the master latch 300 output QM during the response to DATA glitches are not transmitted to the slave latch 410 output Q, effectively filtering out input glitches.

[0145] Entering cycle T3, during the first clock phase, the DATA (DATA=0) received by the master latch 300 and its output QM (QM=0) have stabilized at the end of cycle T2. Therefore, EN1 is high, and EN_CLK1 is also high. The master latch 300 remains in the hold state, and QM remains 0. For the slave latch 410, it enters the transparent state during the first clock phase, and its output Q is updated to the current value of QM (QM=0), that is, Q is updated to 0, completing the data transfer and state update of the trigger unit within cycle T3. Subsequent operations will repeat the above implementation logic based on subsequent changes in the DATA signal, which will not be elaborated here.

[0146] In the second specific embodiment, see Figure 6 The first comparison feedback circuit 100 includes an XOR logic circuit; the first clock gate circuit 200 includes an AND gate logic circuit; the master latch 300 is a rising edge triggered D flip-flop; and the slave latch 410 is a falling edge triggered D flip-flop.

[0147] by Figure 7Taking the timing waveform diagram of the trigger unit shown as an example, for... Figure 6 The working principle of the trigger unit shown is explained in detail below:

[0148] Figure 7 In this circuit, the first edge of the reference clock signal CLK is a falling edge, and the second edge is a rising edge. During the first clock phase, the reference clock signal CLK is low, and during the second clock phase, the reference clock signal CLK is high. DATA represents the external input signal, QM represents the first output signal, EN1 represents the first state feedback signal, EN_CLK1 represents the first gate clock signal, and Q represents the second output signal.

[0149] from Figure 7 As can be seen, during cycle T0, the trigger unit is inactive (DATA=0, QM=0, Q=0). At this time, the DATA received by the main latch 300 is the same as its output QM. EN1 outputs a low level throughout cycle T0. EN_CLK1 follows CLK (low level) as low during the first clock phase of cycle T0, and follows EN1 (low level) as low during the second clock phase of cycle T0. The main latch 300 remains in a holding state throughout the entire cycle T0. During the first clock phase of cycle T0, the slave latch 410 enters a transparent state, and during the second clock phase, the slave latch 410 remains in a holding state. Since the main latch 300 does not update data throughout cycle T0, its final output Q remains unchanged. Therefore, during cycle T0, the invalid clock toggling activity of the main latch 300 inside the trigger unit is effectively suppressed, exhibiting significant low-power characteristics.

[0150] Entering cycle T1, DATA jumps from 0 to 1 in the first clock phase and remains stable thereafter. In the first clock phase, since the DATA received by the master latch is different from its current output QM (QM=0), EN1 goes high. At this time, because EN_CLK1 follows the change of CLK (low level), EN_CLK1 is low during the first clock phase, the master latch 300 is in a hold state, and QM remains 0. Meanwhile, the slave latch 410, due to no data update, maintains its output Q at 0. Then, entering the second clock phase, EN1 remains high, EN_CLK1 follows EN1 to go high, the master latch 300 enters a transparent state, and its output QM is updated to the value of DATA (DATA=1), i.e., QM is updated to 1. After QM is updated to 1, the first comparison feedback circuit 100, i.e., the XOR logic circuit, detects that DATA (DATA=1) is the same as the updated QM (QM=1). EN1 immediately flips back to low level, causing EN_CLK1 to be pulled down to low level, and the master latch 300 then returns to the holding state. For the slave latch 410, since it is still in the second clock phase, the slave latch 410 continues to maintain its state, and Q remains 0.

[0151] Entering cycle T2, during the first clock phase, latch 410 enters a transparent state, and its output Q is immediately updated to the value of the main latch output QM (QM=1), i.e., Q is updated to 1, thus completing a full data latching and transfer, realizing the basic logic function of the trigger unit. During this clock phase, if there is no new DATA input change in the main latch 300, EN1 and EN_CLK1 corresponding to the main latch 300 remain low. Then, the second clock phase begins. Figure 7 The waveform diagram shows that during the second clock phase of cycle T2, DATA experiences a brief glitch (indicated by the gray area) before stabilizing to 0. During this period, the master latch 300 first responds to this glitch input: from Figure 7As shown by the red dashed box, when DATA briefly deviates from its stable value (i.e., the period immediately following its entry into the gray area, for example, changing from 1 to 0), it becomes inconsistent with the then-current QM (QM=1). EN1 goes high, and EN_CLK1 follows suit, causing QM to attempt to follow the unstable DATA. However, once DATA finally stabilizes at 0, because DATA (DATA=0) is still inconsistent with the previous QM (QM=1), EN1 remains high, and EN_CLK1 is also high. The main latch 300 enters a transparent state, and its output QM is finally updated to the new DATA value, 0. Afterward, because DATA (DATA=0) is consistent with QM (QM=0), EN1 goes low again, and EN_CLK1 also goes low, causing the main latch 300 to enter a holding state. Since latch 410 remains in a held state throughout the entire second clock phase of cycle T2, brief fluctuations that may occur in the output QM of master latch 300 during response to DATA glitches will not be propagated to the output Q of slave latch 410, effectively filtering input glitches.

[0152] Entering cycle T3, during the first clock phase, the DATA (DATA=0) received by the master latch 300 and its output QM (QM=0) have stabilized at the end of cycle T2. Therefore, EN1 is low, and EN_CLK1 is also low. The master latch 300 remains in the hold state, and QM remains 0. For the slave latch 410, it enters the transparent state during the first clock phase, and its output Q is updated to the current value of QM (QM=0), that is, Q is updated to 0, completing the data transfer and state update of the trigger unit within cycle T3. Subsequent operations will repeat the above implementation logic based on subsequent changes in the DATA signal, which will not be elaborated here.

[0153] The aforementioned triggering unit not only possesses low power consumption characteristics but also effectively suppresses signal glitches and external disturbances, improving circuit stability and anti-interference capabilities. Furthermore, by tightly integrating the first comparison feedback circuit 100 and the first clock gate circuit 200 within the master-slave latch structure, the inherent master-slave cascading characteristics of the D-type flip-flop are utilized, avoiding the complex gate unit that is a separate external circuit in traditional solutions. This significantly simplifies the overall circuit structure. Without sacrificing functionality, only the first comparison feedback circuit 100 and the first clock gate circuit 200 need to be added to the master latch 300. Moreover, the original transistors and internal signals from the flip-flop design can be reused, achieving superior area efficiency.

[0154] Furthermore, the aforementioned triggering unit, without any external enable input, can accurately sense changes in the external input signal DATA based on the first comparison feedback circuit 100 and the first clock gating circuit 200. It only enables the corresponding first gating clock signal EN_CLK1 to act on the main latch 300 when the data actually needs to be updated. This not only reduces unnecessary clock flips within the main latch 300 and the resulting transistor switching activity, thus reducing dynamic power consumption related to the clock network and dynamic power consumption caused by node flips within the data path, but also simplifies the interface of the triggering unit itself. More importantly, it reduces the complexity of the system-level design and the difficulty of timing convergence, making the design process simpler and more efficient.

[0155] In one embodiment, such as Figure 8 As shown, Figure 8 This is a schematic diagram of the overall structure of the trigger unit in the second embodiment; the latch assembly 400 includes a latch 410, a second comparison feedback circuit 420, and a second clock gating circuit 430;

[0156] The input terminal of latch 410 is connected to the output terminal of main latch 300; the output terminal of latch 410 is connected to the first input terminal of second comparison feedback circuit 420.

[0157] The second input terminal of the second comparison feedback circuit 420 is connected to the input terminal of the latch 410; the output terminal of the second comparison feedback circuit 420 is connected to the first input terminal of the second clock gate circuit 430.

[0158] The second input of the second clock gate circuit 430 is used to receive the reference clock signal CLK.

[0159] The second comparison feedback circuit 420 is used to detect the signal transition state of the first output signal QM based on the second output signal Q output from the output terminal of the latch 410, and generate a corresponding second state feedback signal EN2, so that the second clock gating circuit 430 generates a corresponding second gated clock signal EN_CLK2 based on the second state feedback signal EN2 and the reference clock signal CLK, and controls the latch 410 to update the second output signal Q based on the first output signal QM when the second gated clock signal EN_CLK2 is valid.

[0160] The second state feedback signal EN2 is used to characterize whether a logic transition has occurred in the first output signal QM relative to the second output signal Q. The second state feedback signal EN2 includes a third feedback signal and a fourth feedback signal; the logic levels of the third and fourth feedback signals are inverted. The third feedback signal indicates that the signal transition state of the first output signal QM is no signal transition; the fourth feedback signal indicates that the signal transition state of the first output signal QM is a signal transition.

[0161] In an exemplary embodiment, if the second comparison feedback circuit 420 detects that the first output signal QM and the second output signal Q are the same, it indicates that the first output signal QM has not undergone a signal transition, and the second comparison feedback circuit 420 generates a third feedback signal; if the second comparison feedback circuit 420 detects that the first output signal QM and the second output signal Q are different, it indicates that the first output signal QM has undergone a signal transition, and the second comparison feedback circuit 420 generates a fourth feedback signal.

[0162] The second clock gating circuit 430 is used to generate a corresponding second gating clock signal EN_CLK2 based on the second state feedback signal EN2 and the reference clock signal CLK. The second gating clock signal EN_CLK2 is used to determine the timing of entering the transparent state from the latch 410 and the timing of entering the holding state from the latch 410.

[0163] The second gated clock signal EN_CLK2 includes two states: valid and invalid. In an exemplary embodiment, when the second gated clock signal EN_CLK2 is valid, it controls the slave latch 410 to enter a transparent state, so that the slave latch 410 updates the second output signal Q according to the first output signal QM; when the second gated clock signal EN_CLK2 is invalid, it controls the slave latch 410 to remain in a holding state. Based on this, unnecessary clock flips within the slave latch 410 and the resulting transistor switching activity can be effectively reduced, thereby effectively reducing the dynamic power consumption related to the clock network and the dynamic power consumption caused by node flips within the data path.

[0164] It should be noted that the validity of the second gate clock signal EN_CLK2 is not determined solely by the reference clock signal CLK, but is determined by a combination of factors, including the second state feedback signal EN2 and the level sensitivity characteristics of the latch 410.

[0165] Understandably, based on the level-sensitive characteristics of the slave latch 410 in the first clock phase, combined with the second comparison feedback circuit 420 and the second clock gating circuit 430, the signal transition state of the first output signal QM can be dynamically sensed, so that the slave latch 410 enters a transparent state and updates its internal data only when the first output signal QM has indeed changed and the second gating clock signal EN_CLK2 is valid.

[0166] Specifically, the basic condition for generating a valid second gate clock signal EN_CLK2 is met only when the first output signal QM ≠ the second output signal Q. At this time, it is also necessary to further combine the reference clock signal CLK and the level sensitivity characteristics of the slave latch 410 to generate a valid second gate clock signal EN_CLK2, so as to ensure that the slave latch 410 can be accurately controlled to enter the transparent state.

[0167] When the first output signal QM equals the second output signal Q, regardless of whether the reference clock signal CLK is high or low, and regardless of whether the current time is in the first clock phase sensitive to the latch 410 level, the second gate clock signal EN_CLK2 remains in an invalid state to control the latch 410 to remain in a holding state, preventing unnecessary clock flips inside the latch 410 and the resulting transistor switching activity.

[0168] In this embodiment, the second comparison feedback circuit 420 detects the signal transition state of the first output signal QM and generates a corresponding second state feedback signal EN2. Then, based on the second clock gating circuit 430, the second state feedback signal EN2 and the reference clock signal CLK are logically converted to generate a corresponding second gated clock signal EN_CLK2. When the second gated clock signal EN_CLK2 is valid, the latch 410 is controlled to enter a transparent state. Based on this, the state switching timing of the latch 410 can be precisely controlled, effectively reducing unnecessary clock flips inside the latch 410 and the transistor switching activities caused thereby. This effectively reduces the dynamic power consumption related to the clock network and the dynamic power consumption caused by the flipping of nodes inside the data path.

[0169] In one embodiment, the second gated clock signal EN_CLK2 includes a fifth gated signal and a sixth gated signal;

[0170] When the third feedback signal is generated in the first clock phase, the second clock gate circuit 430 is also used in the first clock phase to perform level logic conversion on the third feedback signal and the first level to generate a fifth gate signal, which controls the latch 410 to be in a holding state to hold the second output signal Q that was latched last time.

[0171] Among them, the level state of the fifth gating signal is consistent with that of the third feedback signal;

[0172] When the third feedback signal is generated in the second clock phase, the second clock gate circuit 430 is also used to perform level logic conversion on the third feedback signal and the second level in the second clock phase to generate a sixth gate signal, which controls the latch 410 to be in a holding state to hold the second output signal Q that was latched last time.

[0173] The sixth gating signal maintains the same level as the second level.

[0174] The second clock gate circuit 430 has the capability of level logic conversion.

[0175] In an exemplary embodiment, when the third feedback signal is generated during the first clock phase, it indicates that the first output signal QM currently received from latch 410 is the same as its output second output signal Q during the first clock phase. At this time, the second clock gating circuit 430 performs level logic conversion on the third feedback signal and the first level to generate a fifth gating signal consistent with the level state of the third feedback signal, controlling latch 410 to be in a holding state to hold the second output signal Q last latched. Although the level sensitivity of latch 410 is synchronized with the first clock phase, the fifth gating signal forces latch 410 to be in a holding state, thus avoiding redundant power consumption when there is no data change.

[0176] It should be noted that the control latch 410 is in a holding state during the first clock phase, including at least the following two cases:

[0177] Scenario 1: For the same clock cycle of the reference clock signal CLK, when the first output signal QM received from latch 410 and the second output signal Q output are always the same throughout the entire clock cycle, the second comparison feedback circuit 420 will always output the third feedback signal throughout the entire clock cycle (including the first clock phase and the second clock phase); while the second clock gate circuit 430 will generate the fifth gate signal and the sixth gate signal successively according to the third feedback signal and the first level, and the third feedback signal and the second level, so as to control the latch 410 to keep the clock in a holding state throughout the entire clock cycle, reducing unnecessary state switching and clock flipping inside the latch 410.

[0178] Scenario 2: After the latch 410 completes the data update in the first clock phase (i.e., if the first output signal QM is different from the second output signal Q during the first clock phase, the second output signal Q is updated according to the first output signal QM), the second comparison feedback circuit 420 can immediately detect that the first output signal QM received from the latch 410 is the same as the output second output signal Q, and then outputs the third feedback signal to ensure that the second clock gating circuit 430 responds to the third feedback signal in a timely manner. Based on the third feedback signal and the first level, a fifth gating signal with the same level state as the third feedback signal is generated to control the latch 410 to immediately return to the holding state after the data update, thereby reducing unnecessary power consumption.

[0179] In another exemplary embodiment, when the third feedback signal is generated during the second clock phase, it indicates that the first output signal QM currently received from latch 410 during the second clock phase is the same as the second output signal Q it outputs. At this time, the third feedback signal and the second level are logically converted by the second clock gating circuit 430 to generate a sixth gating signal that is consistent with the level state of the second level. Based on the sixth gating signal, latch 410 is controlled to be in a holding state to hold the second output signal Q that was last latched.

[0180] In one specific embodiment, when latch 410 is a rising-edge triggered D-type flip-flop, the first edge of the reference clock signal CLK is a rising edge, and the second edge is a falling edge. During the first clock phase, the reference clock signal CLK is high, i.e., the first level is high. During the second clock phase, the reference clock signal CLK is low, i.e., the second level is low. In this embodiment, the third feedback signal is low. When the third feedback signal is generated during the first clock phase, the second clock gating circuit 430 performs a level logic conversion between the third feedback signal (i.e., low level) and the first level (i.e., high level) to generate a fifth gating signal (i.e., low level) that is consistent with the level state of the third feedback signal (i.e., low level), controlling latch 410 to be in a holding state to hold the second output signal Q latched last time. When the third feedback signal is generated in the second clock phase, the second clock gate circuit 430 performs level logic conversion on the third feedback signal (i.e., low level) and the second level (i.e., low level) to generate a sixth gate signal (i.e., low level) that is consistent with the level state of the second level (i.e., low level), and controls the latch 410 to be in a holding state to hold the second output signal Q that was latched last time.

[0181] In another specific embodiment, when latch 410 is a falling-edge triggered D-type flip-flop, the first edge of the reference clock signal CLK is a falling edge, and the second edge is a rising edge. During the first clock phase, the reference clock signal CLK is low, i.e., the first level is low. During the second clock phase, the reference clock signal CLK is high, i.e., the second level is high. In this embodiment, the third feedback signal is high. When the third feedback signal is generated during the first clock phase, the second clock gating circuit 430 performs a level logic conversion between the third feedback signal (i.e., high level) and the first level (i.e., low level) to generate a fifth gating signal (i.e., high level) that is consistent with the level state of the third feedback signal (i.e., high level), controlling latch 410 to be in a holding state to hold the second output signal Q latched last time. When the third feedback signal is generated in the second clock phase, the second clock gate circuit 430 performs level logic conversion on the third feedback signal (i.e., high level) and the second level (i.e., high level) to generate a sixth gate signal (i.e., high level) that is consistent with the level state of the second level (i.e., high level), and controls the latch 410 to be in the holding state to hold the second output signal Q that was latched last time.

[0182] In this embodiment, the second clock gating circuit 430 can adaptively select to perform level logic conversion with the first level or the second level according to the generation timing of the third feedback signal (first clock stage or second clock stage), thereby generating the corresponding fifth gating signal or sixth gating signal. Based on the fifth gating signal or the sixth gating signal, it is ensured that no matter which clock stage, as long as the first output signal QM is the same as the second output signal Q (i.e. no data update is required or the data update has been completed), the latch 410 can be quickly and reliably controlled in the holding state to effectively reduce unnecessary dynamic power consumption.

[0183] In one embodiment, the second gated clock signal EN_CLK2 includes a seventh gated signal and an eighth gated signal;

[0184] When the fourth feedback signal is generated in the first clock phase, the second clock gate circuit 430 is also used in the first clock phase to perform level logic conversion on the fourth feedback signal and the first level to generate the seventh gate signal, control the latch 410 to enter the transparent state, and update the second output signal Q according to the latest received first output signal QM.

[0185] Among them, the level state of the seventh gating signal is consistent with that of the fourth feedback signal;

[0186] When the fourth feedback signal is generated in the second clock phase, the second clock gate circuit 430 is also used to perform level logic conversion on the fourth feedback signal and the second level in the second clock phase to generate the eighth gate signal, which controls the latch 410 to be in a holding state to hold the second output signal Q that was latched last time.

[0187] The eighth gating signal maintains the same level as the second level.

[0188] In an exemplary embodiment, when the fourth feedback signal is generated during the first clock phase, it indicates that the first output signal QM currently received from the latch 410 is different from its output second output signal Q during the first clock phase. At this time, since the level sensitivity characteristic of the latch 410 is synchronized with the first clock phase, it is necessary to perform level logic conversion on the fourth feedback signal and the first level through the second clock gating circuit 430 to generate a seventh gating signal that is consistent with the level state of the fourth feedback signal, control the latch 410 to enter the transparent state, and update the second output signal Q according to the latest received first output signal QM.

[0189] In another exemplary embodiment, when the fourth feedback signal is generated during the second clock phase, it indicates that the first output signal QM currently received from latch 410 is different from its output second output signal Q during the second clock phase. At this time, the fourth feedback signal and the second level are logically converted by the second clock gating circuit 430 to generate an eighth gating signal that is consistent with the level state of the second level. Based on the eighth gating signal, latch 410 is controlled to be in a holding state to hold the second output signal Q that was last latched.

[0190] In one specific embodiment, when latch 410 is a rising-edge triggered D-type flip-flop, the first edge of the reference clock signal CLK is a rising edge, and the second edge is a falling edge. During the first clock phase, the reference clock signal CLK is high, i.e., the first level is high. During the second clock phase, the reference clock signal CLK is low, i.e., the second level is low. In this embodiment, the fourth feedback signal is high. When the fourth feedback signal is generated during the first clock phase, the second clock gating circuit 430 performs a level logic conversion between the fourth feedback signal (i.e., high level) and the first level (i.e., high level) to generate a seventh gating signal (i.e., high level) that is consistent with the level state of the fourth feedback signal (i.e., high level), controlling latch 410 to enter a transparent state, and updating the second output signal Q according to the latest received first output signal QM. When the fourth feedback signal is generated in the second clock phase, the second clock gating circuit 430 performs level logic conversion on the fourth feedback signal (i.e., high level) and the second level (i.e., low level) to generate an eighth gating signal (i.e., low level) that is consistent with the level state of the second level (i.e., low level), and controls the latch 410 to be in a holding state to hold the second output signal Q that was latched last time.

[0191] In another specific embodiment, when latch 410 is a D-type flip-flop triggered by a falling edge, the first edge of the reference clock signal CLK is a falling edge, and the second edge is a rising edge. During the first clock phase, the reference clock signal CLK is low, i.e., the first level is low. During the second clock phase, the reference clock signal CLK is high, i.e., the second level is high. In this embodiment, the fourth feedback signal is low. When the fourth feedback signal is generated during the first clock phase, the second clock gating circuit 430 performs a level logic conversion between the fourth feedback signal (i.e., low level) and the first level (i.e., low level) to generate a seventh gating signal (i.e., low level) that is consistent with the level state of the fourth feedback signal (i.e., low level), controlling latch 410 to enter a transparent state, and updating the second output signal Q according to the latest received first output signal QM. When the fourth feedback signal is generated in the second clock phase, the second clock gate circuit 430 performs level logic conversion on the fourth feedback signal (i.e., low level) and the second level (i.e., high level) to generate an eighth gate signal (i.e., high level) that is consistent with the level state of the second level (i.e., high level), and controls the latch 410 to be in a holding state to hold the second output signal Q that was latched last time.

[0192] In this embodiment, the second clock gating circuit 430 can adaptively select to perform level logic conversion with the first level or the second level according to the generation timing of the fourth feedback signal (first clock stage or second clock stage), thereby generating the corresponding seventh gating signal or eighth gating signal. Based on the seventh gating signal, it can accurately control the latch 410 to enter the transparent state and update the second output signal Q according to the latest received first output signal QM, realizing timely data response and latching. Based on the eighth gating signal, it can ensure that the latch 410 is always in the holding state during the second clock stage, and no data update is performed even if the first output signal QM and the second output signal Q are different.

[0193] Furthermore, for application scenarios where the latch assembly 400 includes a slave latch 410, a second comparison feedback circuit 420, and a second clock gate circuit 430, the following provides two specific implementation methods for the trigger unit:

[0194] In the third specific embodiment, see Figure 9 The first comparison feedback circuit 100 includes an XOR logic circuit; the first clock gate circuit 200 includes an OR gate logic circuit; the second comparison feedback circuit 420 includes an XOR logic circuit; the second clock gate circuit 430 includes an AND gate logic circuit; the master latch 300 is a falling edge triggered D flip-flop; and the slave latch 410 is a rising edge triggered D flip-flop.

[0195] by Figure 10 Taking the timing waveform diagram of the trigger unit shown as an example, for... Figure 9 The working principle of the trigger unit shown is explained in detail below:

[0196] Figure 10 In this circuit, the first edge of the reference clock signal CLK is a rising edge, and the second edge is a falling edge. During the first clock phase, the reference clock signal CLK is high, and during the second clock phase, the reference clock signal CLK is low. DATA represents the external input signal, QM represents the first output signal, EN1 represents the first state feedback signal, EN_CLK1 represents the first gate clock signal, EN2 represents the second state feedback signal, EN_CLK2 represents the second gate clock signal, and Q represents the second output signal.

[0197] It should be noted that the working principle of the master latch 300 in this embodiment is the same as that of the master latch 300 in the first specific embodiment above, and will not be repeated here. Only the working principle of the slave latch 410 will be described in detail.

[0198] from Figure 10As can be seen, during cycle T0, the trigger unit is inactive (DATA=0, QM=0, Q=0). At this time, the QM received from latch 410 (QM=0) is the same as its output Q (Q=0), EN2 outputs a low level, and EN_CLK2 follows EN2 as low, keeping latch 410 in a holding state. Therefore, during cycle T0, invalid clock toggling activity within the trigger unit is effectively suppressed, exhibiting significant low-power characteristics.

[0199] Entering cycle T1, during the first clock phase of cycle T1, the input QM (QM=0) of latch 410 remains consistent with its output Q (Q=0). Therefore, EN2 remains low during the first clock phase, causing EN_CLK2 to remain low. Latch 410 continues to hold, and its output Q remains 0. Subsequently, during the second clock phase, since the output QM of master latch 300 has changed during the second clock phase of cycle T1, the input QM (QM=1) of latch 410 and its output Q (Q=0) are no longer consistent. This causes EN2 to go high during the second clock phase of cycle T1. However, since we are still in the second clock phase, EN_CLK2 will remain low following CLK, so latch 410 continues to hold its state, and Q remains 0.

[0200] Entering cycle T2, during the first clock phase, EN2, which had previously gone high, also goes high along with EN_CLK2, controlling latch 410 to enter a transparent state. Its output Q is immediately updated to the value of the master latch 300's output QM (QM=1), i.e., Q is updated to 1, thus completing a full data latching and transfer, realizing the basic logic function of the trigger unit. After Q is updated to 1, the second comparison feedback circuit 420, i.e., the XOR logic circuit, detects that the input QM (QM=1) of latch 410 matches the new output Q (Q=1), causing EN2 to flip back to a low level, which in turn pulls EN_CLK2 low, restoring latch 410 to its holding state. Then, during the second clock phase, since EN_CLK2 and CLK are always clamped low throughout the second clock phase, latch 410 remains in a holding state. Therefore, the brief fluctuations that may occur in the output QM of the master latch during the response to DATA glitches will not be transmitted to the output Q of the slave latch 410, effectively filtering out input glitches.

[0201] Entering cycle T3, during the first clock phase, for latch 410, its input QM (QM=0) is inconsistent with the output Q (Q=1) at the end of the previous cycle, causing EN2 to go high. EN_CLK2 also goes high following EN2, making latch 410 enter a transparent state and updating the output Q to the current value of QM (QM=0), i.e., Q is updated to 0. This completes the data transfer and state update of the trigger unit within this clock cycle. After Q is updated to 0, QM (QM=0) is consistent with the new Q (Q=0), EN2 flips back to low, and EN_CLK2 is also pulled low following EN2, restoring latch 410 to its holding state; and so on, without further explanation.

[0202] In the fourth specific embodiment, see Figure 11 The first comparison feedback circuit 100 includes an XOR logic circuit; the first clock gate circuit 200 includes an AND gate logic circuit; the second comparison feedback circuit 420 includes an XNOR logic circuit; the second clock gate circuit 430 includes an OR gate logic circuit; the master latch 300 is a rising edge triggered D-type flip-flop; and the slave latch 410 is a falling edge triggered D-type flip-flop.

[0203] by Figure 12 Taking the timing waveform diagram of the trigger unit shown as an example, for... Figure 11 The working principle of the trigger unit shown is explained in detail below:

[0204] Figure 12 In this circuit, the first edge of the reference clock signal CLK is a falling edge, and the second edge is a rising edge. During the first clock phase, the reference clock signal CLK is low, and during the second clock phase, the reference clock signal CLK is high. DATA represents the external input signal, QM represents the first output signal, EN1 represents the first state feedback signal, EN_CLK1 represents the first gate clock signal, EN2 represents the second state feedback signal, EN_CLK2 represents the second gate clock signal, and Q represents the second output signal.

[0205] It should be noted that the working principle of the master latch 300 in this embodiment is the same as that of the master latch 300 in the second specific embodiment above, and will not be repeated here. Only the working principle of the slave latch 410 will be described in detail.

[0206] from Figure 12As can be seen, during cycle T0, the trigger unit is inactive (DATA=0, QM=0, Q=0). At this time, the QM received from latch 410 (QM=0) is the same as its output Q (Q=0), EN2 outputs a high level, and EN_CLK2 follows EN2 and is also high, keeping latch 410 in a holding state. Therefore, during cycle T0, invalid clock toggling activity within the trigger unit is effectively suppressed, exhibiting significant low-power characteristics.

[0207] Entering cycle T1, during the first clock phase of cycle T1, the input QM (QM=0) of latch 410 remains consistent with its output Q (Q=0). Therefore, EN2 remains high during the first clock phase, causing EN_CLK2 to remain high, and latch 410 continues to hold, with output Q remaining 0. Subsequently, during the second clock phase, the output QM of master latch 300 changes during the second clock phase of cycle T1, causing the input QM (QM=1) of latch 410 to no longer match its output Q (Q=0). This causes EN2 to go low during the second clock phase of cycle T1. However, since we are still in the second clock phase, EN_CLK2 will remain high following CLK, so latch 410 continues to hold its state, and Q remains 0.

[0208] Entering cycle T2, during the first clock phase, EN2, which had previously gone low, also goes low along with EN_CLK2, controlling latch 410 to enter a transparent state. Its output Q is immediately updated to the value of the master latch 300's output QM (QM=1), i.e., Q is updated to 1, thus completing a full data latching and transfer, realizing the basic logic function of the trigger unit. After Q is updated to 1, the second comparison feedback circuit 420, i.e., the XOR logic circuit, detects that the input QM (QM=1) of latch 410 matches the new output Q (Q=1), causing EN2 to flip back to a high level, which in turn pulls EN_CLK2 high, restoring latch 410 to its holding state. Subsequently, during the second clock phase, since EN_CLK2 and CLK are always clamped high throughout the second clock phase, latch 410 remains in a holding state. Therefore, the brief fluctuations that may occur in the output QM of the master latch during the response to DATA glitches will not be transmitted to the output Q of the slave latch 410, effectively filtering out input glitches.

[0209] Entering cycle T3, during the first clock phase, for latch 410, its input QM (QM=0) is inconsistent with the output Q (Q=1) at the end of the previous cycle, causing EN2 to go low. EN_CLK2 also goes low following EN2, making latch 410 enter a transparent state and updating its output Q to the current value of QM (QM=0), i.e., Q is updated to 0. This completes the data transfer and state update of the trigger unit within this clock cycle. After Q is updated to 0, QM (QM=0) becomes consistent with the new Q (Q=0), EN2 flips back to high, and EN_CLK2 is also pulled high following EN2, restoring latch 410 to its holding state; and so on, without further explanation.

[0210] The aforementioned triggering unit not only possesses low power consumption characteristics but also effectively suppresses signal glitches and external disturbances, improving circuit stability and anti-interference capabilities. Furthermore, by tightly integrating the first comparison feedback circuit 100, the first clock gate circuit 200, the second comparison feedback circuit 420, and the second clock gate circuit 430 within the master-slave latch structure, the inherent master-slave cascading characteristics of the D-type flip-flop are utilized. This avoids the complex gate unit that is a separate external circuit in traditional solutions, significantly simplifying the overall circuit structure. Without sacrificing functionality, only the first comparison feedback circuit 100 and the first clock gate circuit 200 need to be added to the master latch 300, and the second comparison feedback circuit 4200 and the second clock gate circuit 430 need to be added to the slave latch 410. Moreover, the original transistors and internal signals from the flip-flop design can be reused, achieving better area efficiency.

[0211] Furthermore, the aforementioned trigger unit, without any external enable input, can accurately sense the changes in the first output signal QM based on the second comparison feedback circuit 4200 and the second clock gating circuit 430. It only enables the corresponding second gating clock signal EN_CLK2 to act on the slave latch 410 when the data actually needs to be updated. This not only reduces unnecessary clock flips inside the slave latch 410 and the resulting transistor switching activities, but also reduces the dynamic power consumption related to the clock network and the dynamic power consumption caused by the flipping of nodes inside the data path. It also simplifies the interface of the trigger unit itself. More importantly, it reduces the complexity of the system-level design and the difficulty of timing convergence, making the design process simpler and more efficient.

[0212] It should be noted that the above embodiments are only examples of ordinary D-type flip-flops. However, in other embodiments, other types of edge-triggered flip-flops may be used, including but not limited to D-type flip-flops with set / reset functions or D-type flip-flops with scan inputs. As long as the implementation logic is correct, no specific limitations are made.

[0213] It should be noted that, in the above embodiments, the specific structures of the first comparison feedback circuit 100, the first clock gate circuit 200, the second comparison feedback circuit 420, and the second clock gate circuit 430 are not limited to the forms described. In other embodiments, they can also be implemented by different CMOS circuit structures, or by combining other gate circuits under the premise of equivalent logic functions (for example, replacing the XOR logic circuit in the first comparison feedback circuit 100 with an XOR NOT logic circuit and adjusting the subsequent implementation logic accordingly).

[0214] It should be noted that the first comparison feedback circuit 100, the first clock gate circuit 200, the second comparison feedback circuit 420, and the second clock gate circuit 430 can be more tightly integrated and coupled with the internal circuitry of the transistor level and the trigger unit to fully save redundant logic, or they can be integrated quickly as additional circuits. No specific limitations are made here.

[0215] In one embodiment, the trigger unit is a library unit in the standard cell library of digital circuit EDA.

[0216] It is understood that the triggering unit described in any of the above embodiments can be used as a library unit in the standard cell library of digital circuit EDA. It can seamlessly replace the traditional D-type flip-flop in the existing digital circuit logic synthesis, automated placement and routing and other design processes without major modifications to the design methodology or toolchain. It has good engineering practicality and promotion.

[0217] In the description of this specification, references to terms such as "some embodiments," "other embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0218] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0219] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A triggering unit, characterized in that, The triggering unit includes a first comparison feedback circuit, a first clock gating circuit, a master latch, and a slave latch assembly; wherein... The input terminal of the master latch is used to receive external input signals; the output terminal of the master latch is connected to the first input terminal of the first comparison feedback circuit and the input terminal of the slave latch assembly, respectively. The second input terminal of the first comparison feedback circuit is connected to the input terminal of the main latch; the output terminal of the first comparison feedback circuit is connected to the first input terminal of the first clock gating circuit. The second input terminal of the first clock gating circuit is used to receive a reference clock signal; the output terminal of the first clock gating circuit is connected to the clock terminal of the master latch; the clock terminal of the slave latch assembly is used to receive the reference clock signal. The first comparison feedback circuit is used to detect the signal transition state of the external input signal based on the first output signal output from the output terminal of the main latch, and generate a corresponding first state feedback signal so that the first clock gating circuit generates a corresponding first gated clock signal based on the first state feedback signal and the reference clock signal, and controls the main latch to update the first output signal based on the external input signal when the first gated clock signal is valid.

2. The triggering unit according to claim 1, characterized in that, Each clock cycle of the reference clock signal includes a first clock phase and a second clock phase; the first clock phase refers to the time window corresponding to the current clock cycle from the first edge to the second edge; The second clock phase refers to the time window from the second edge of the current clock cycle to the first edge of the next clock cycle; During the first clock phase, the reference clock signal is at a first level; During the second clock phase, the reference clock signal is at the second level; The first voltage level and the second voltage level are inverses of each other.

3. The triggering unit according to claim 2, characterized in that, The first state feedback signal includes a first feedback signal and a second feedback signal; The first comparison feedback circuit is further configured to generate a first feedback signal if it detects that the external input signal and the first output signal are the same; The first feedback signal indicates that the signal transition state of the external input signal is no signal transition; if the external input signal and the first output signal are detected to be different, a second feedback signal is generated; the second feedback signal indicates that the signal transition state of the external input signal is a signal transition. The logic levels of the first feedback signal and the second feedback signal are inverses of each other.

4. The triggering unit according to claim 3, characterized in that, The first gated clock signal includes a first gated signal and a second gated signal; When the first feedback signal is generated during the first clock phase, the first clock gating circuit is further configured to perform level logic conversion on the first feedback signal and the first level during the first clock phase, generate a first gating signal, and control the main latch to be in a holding state to hold the first output signal that was last latched; the first gating signal is consistent with the level state of the first level. When the first feedback signal is generated during the second clock phase, the first clock gating circuit is further configured to perform level logic conversion on the first feedback signal and the second level during the second clock phase, generate a second gating signal, and control the main latch to be in a holding state to maintain the first output signal latched last time; the level state of the second gating signal is consistent with that of the first feedback signal.

5. The triggering unit according to claim 3, characterized in that, The first gated clock signal includes a third gated signal and a fourth gated signal; When the second feedback signal is generated during the first clock phase, the first clock gating circuit is further configured to perform level logic conversion on the second feedback signal and the first level during the first clock phase, generate a third gating signal, and control the main latch to be in a holding state to hold the first output signal that was last latched; the third gating signal is consistent with the level state of the first level. When the second feedback signal is generated during the second clock phase, the first clock gating circuit is further configured to perform level logic conversion on the second feedback signal and the second level during the second clock phase, generate a fourth gating signal, control the main latch to enter a transparent state, and update the first output signal according to the latest received external input signal; the level state of the fourth gating signal is consistent with that of the second feedback signal.

6. The triggering unit according to claim 2, characterized in that, The slave latch assembly includes a slave latch; the clock terminal of the slave latch is used to receive the reference clock signal; the input terminal of the slave latch is connected to the output terminal of the master latch; The latch is configured to enter a transparent state during the first clock phase of the reference clock signal and output a corresponding second output signal according to the latest received first output signal. The reference clock signal is held during the second clock phase to hold the second output signal that was last latched.

7. The triggering unit according to claim 2, characterized in that, The slave latch assembly includes a slave latch, a second comparison feedback circuit, and a second clock gating circuit; The input terminal of the slave latch is connected to the output terminal of the master latch; the output terminal of the slave latch is connected to the first input terminal of the second comparison feedback circuit. The second input terminal of the second comparison feedback circuit is connected to the input terminal of the slave latch; the output terminal of the second comparison feedback circuit is connected to the first input terminal of the second clock gating circuit. The second input terminal of the second clock gate circuit is used to receive the reference clock signal.

8. The triggering unit according to claim 7, characterized in that, The second comparison feedback circuit is used to detect the signal transition state of the first output signal based on the second output signal output from the output terminal of the latch, and generate a corresponding second state feedback signal so that the second clock gating circuit generates a corresponding second gated clock signal based on the second state feedback signal and the reference clock signal, and controls the latch to update the second output signal based on the first output signal when the second gated clock signal is valid.

9. The triggering unit according to claim 8, characterized in that, The second state feedback signal includes a third feedback signal and a fourth feedback signal; The second comparison feedback circuit is further configured to generate a third feedback signal if the first output signal and the second output signal are detected to be the same; the third feedback signal indicates that the signal transition state of the first output signal is that no signal transition has occurred; and to generate a fourth feedback signal if the first output signal and the second output signal are detected to be different; the fourth feedback signal indicates that the signal transition state of the first output signal is that a signal transition has occurred. The logic levels of the third feedback signal and the fourth feedback signal are inverses of each other.

10. The triggering unit according to claim 9, characterized in that, The second gated clock signal includes a fifth gated signal and a sixth gated signal; When the third feedback signal is generated during the first clock phase, the second clock gating circuit is further configured to perform level logic conversion on the third feedback signal and the first level during the first clock phase to generate a fifth gating signal, controlling the latch to be in a holding state to hold the second output signal last latched; the fifth gating signal is consistent with the level state of the third feedback signal. When the third feedback signal is generated during the second clock phase, the second clock gating circuit is further configured to perform level logic conversion on the third feedback signal and the second level during the second clock phase to generate a sixth gating signal, controlling the latch to be in a holding state to hold the second output signal last latched; the sixth gating signal is consistent with the level state of the second level.

11. The triggering unit according to claim 9, characterized in that, The second gated clock signal includes a seventh gated signal and an eighth gated signal; When the fourth feedback signal is generated during the first clock phase, the second clock gating circuit is further configured to perform level logic conversion on the fourth feedback signal and the first level during the first clock phase, generate a seventh gating signal, control the latch to enter the transparent state, and update the second output signal according to the latest received first output signal; the level state of the seventh gating signal is consistent with that of the fourth feedback signal. When the fourth feedback signal is generated during the second clock phase, the second clock gating circuit is further configured to perform level logic conversion on the fourth feedback signal and the second level during the second clock phase to generate an eighth gating signal, which controls the latch to be in a holding state to hold the second output signal last latched; the eighth gating signal is consistent with the level state of the second level.

12. The triggering unit according to claim 6, characterized in that, The first comparison feedback circuit includes an XOR logic circuit; the first clock gate circuit includes an OR gate logic circuit. The master latch is a falling-edge triggered D-type flip-flop; the slave latch is a rising-edge triggered D-type flip-flop.

13. The triggering unit according to claim 6, characterized in that, The first comparison feedback circuit includes an XOR logic circuit; the first clock gate circuit includes an AND gate logic circuit. The master latch is a rising-edge triggered D-type flip-flop; the slave latch is a falling-edge triggered D-type flip-flop.

14. The triggering unit according to claim 7, characterized in that, The first comparison feedback circuit includes an XOR logic circuit; the first clock gate circuit includes an OR gate logic circuit. The second comparison feedback circuit includes an XOR logic circuit; the second clock gate circuit includes an AND gate logic circuit. The master latch is a falling-edge triggered D-type flip-flop; the slave latch is a rising-edge triggered D-type flip-flop.

15. The triggering unit according to claim 7, characterized in that, The first comparison feedback circuit includes an XOR logic circuit; the first clock gate circuit includes an AND gate logic circuit. The second comparison feedback circuit includes an XOR logic circuit; the second clock gate circuit includes an OR gate logic circuit. The master latch is a rising-edge triggered D-type flip-flop; the slave latch is a falling-edge triggered D-type flip-flop.

16. The triggering unit according to any one of claims 1 to 15, characterized in that, The triggering unit is a library unit in the standard unit library of digital circuit EDA.

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