Anti-power-down false latching circuit and fault latching system

Abstract

The application relates to the field of automobile electronics, in particular to a power-off error prevention latching circuit and a fault latching system. The power-off error prevention latching circuit comprises: a voltage detection logic unit, which is used for receiving a power supply voltage and outputting a voltage detection signal according to the comparison result of the power supply voltage and an under-voltage threshold; and a signal selection logic unit, which is used for receiving the voltage detection signal output by the voltage detection logic unit, and is also used for receiving an original clear latching signal, outputting a clear latching signal according to the original clear latching signal and the voltage detection signal. In the case that the power supply voltage is lower than the under-voltage threshold, the signal selection logic unit provides a low-level clear latching signal to replace the original clear latching signal used for fault latching, so that the latching circuit does not perform fault latching, and the error latching caused by the unstable output of a logic chip due to insufficient power supply of the latching circuit is avoided.

Description

Technical Field

[0001] This application relates to the field of automotive electronics technology, specifically to a circuit and fault latching system for preventing power failure and accidental latching. Background Technology

[0002] In current hybrid vehicle solutions, the bus voltage is sampled using voltage divider resistors and an isolation operational amplifier, and the sampled voltage is output linearly. When the sampled voltage exceeds a threshold, overvoltage protection measures are required. Furthermore, to maintain the stability of the overvoltage fault signal, a fault latch circuit is needed.

[0003] In related technologies, when the supply voltage drops, the latching circuit, due to the requirement of the internal logic chip for the supply voltage, will fail when the voltage is lower than the undervoltage threshold, resulting in unstable output and easy false latching of fault latching signals. If the latching circuit falsely latches overvoltage fault signals when the supply voltage is undervoltage, it will cause the vehicle to falsely report an overvoltage fault, affecting normal operation. Utility Model Content

[0004] The purpose of this application is to provide a circuit and fault latching system to prevent power failure and prevent accidental latching, so as to solve the technical problem in the prior art where the latching circuit accidentally latches the overvoltage fault signal when the power supply voltage is low, causing the vehicle to falsely report an overvoltage fault.

[0005] To address the aforementioned technical problems, embodiments of this application disclose the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a power-loss-induced latching circuit, comprising:

[0007] The voltage detection logic unit is used to receive the supply voltage and output a voltage detection signal based on the comparison result between the supply voltage and the undervoltage threshold.

[0008] The signal selection logic unit receives the voltage detection signal at one input terminal and the original clear latch signal at the other input terminal, and outputs a clear latch signal based on the original clear latch signal and the voltage detection signal.

[0009] Specifically, when the supply voltage is lower than the undervoltage threshold, the clear latch signal is low; when the supply voltage is higher than or equal to the undervoltage threshold, the clear latch signal follows the original clear latch signal.

[0010] In one embodiment of this application, the voltage detection logic unit includes a comparator, a first input terminal of the comparator for receiving the supply voltage, a second input terminal of the comparator for receiving the undervoltage threshold, and an output terminal of the comparator for outputting the voltage detection signal;

[0011] When the supply voltage is higher than or equal to the undervoltage threshold, the output of the comparator is used to output a high-level voltage detection signal; when the supply voltage is lower than the undervoltage threshold, the output of the comparator is used to output a low-level voltage detection signal.

[0012] In one embodiment of this application, a voltage divider unit is further included. The input terminal of the voltage divider unit is used to connect to a first reference voltage, and the first reference voltage is divided based on the voltage divider unit to generate the undervoltage threshold.

[0013] In one embodiment of this application, a filtering unit is further included, wherein a first end of the filtering unit is connected to the power supply terminal of the comparator, and a second end of the filtering unit is grounded.

[0014] In one embodiment of this application, the voltage detection logic unit includes a switching element, which is used to connect to the power supply voltage and controllably output the voltage detection signal according to the power supply voltage;

[0015] When the supply voltage is higher than or equal to the undervoltage threshold, the switch is open and outputs a high-level voltage detection signal; when the supply voltage is lower than the undervoltage threshold, the switch is open and outputs a low-level voltage detection signal.

[0016] In one embodiment of this application, the signal selection logic unit includes:

[0017] The first diode has its cathode connected to the output terminal of the voltage detection logic unit, and its anode is used to connect to the power supply voltage through the sixth resistor.

[0018] The second diode has its cathode connected to the original clear latch signal, and its anode connected to the anode of the first diode, for outputting the clear latch signal.

[0019] Secondly, embodiments of this application provide a fault latching system, including a power-loss fault latching circuit and a latching circuit, wherein the power-loss fault latching circuit and the latching circuit are connected and the power-loss fault latching circuit is used to provide a clear latching signal to the latching circuit.

[0020] In one embodiment of this application, the latch circuit includes:

[0021] The first AND gate chip has a first input terminal for connecting to the clear latch signal via a seventh resistor, a second input terminal for connecting to the inverted signal of the first latch signal, a power supply terminal for connecting to the power supply voltage, and an output terminal for outputting a first logic signal.

[0022] The second AND gate chip has a first input terminal for receiving the first latch signal, a second input terminal for receiving an overvoltage fault signal, and an output terminal for outputting a second logic signal.

[0023] An inverter, wherein the first input terminal of the inverter is connected to the output terminal of the first AND gate chip, and the first output terminal of the inverter is used to output the first latch signal which is opposite to the first logic signal; the second input terminal of the inverter is connected to the output terminal of the second AND gate chip, and the second output terminal of the inverter is used to output the inverted signal of the first latch signal which is opposite to the second logic signal.

[0024] In one embodiment of this application, the latch circuit further includes:

[0025] The eighth resistor has a first end connected to the power supply voltage and a second end connected to the first input terminal of the first AND gate chip.

[0026] The fourth capacitor has its first terminal connected to the first input terminal of the first AND gate chip, and its second terminal grounded.

[0027] The fifth capacitor has its first terminal connected to the power supply terminal of the first AND gate chip, and its second terminal grounded.

[0028] The sixth capacitor has its first terminal connected to the power supply terminal of the inverter, and its second terminal grounded. The power supply terminal of the inverter is used to receive the power supply voltage.

[0029] In one embodiment of this application, the latching circuit further includes a step-down unit, the input terminal of which is connected to the first power supply voltage output terminal for receiving the first power supply voltage, and the step-down unit is used to output the power supply voltage according to the first power supply voltage.

[0030] This application constructs a circuit to prevent false latching due to power failure. The voltage detection logic unit monitors the relationship between the supply voltage and the undervoltage threshold in real time. When the supply voltage is lower than the undervoltage threshold, the signal selection logic unit provides a low-level clear latch signal to replace the original clear latch signal. This cancels the fault latching function of the original clear latch signal when it is high-level, forcing the latch circuit not to perform fault latching and avoiding false latching caused by unstable logic chip output due to insufficient power supply to the latch circuit. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a latch circuit connected to the original clear latch signal;

[0033] Figure 2 This is the circuit diagram of the latch circuit;

[0034] Figure 3 This is the circuit diagram of the buck unit of the latch circuit;

[0035] Figure 4 This is a logic architecture diagram of the anti-power-loss latch circuit according to an embodiment of this application;

[0036] Figure 5 This is a circuit diagram of a power-loss latch-up protection circuit according to an embodiment of this application;

[0037] Figure 6 This is a circuit diagram of another anti-power-loss latching circuit according to an embodiment of this application;

[0038] Figure 7 This is a schematic diagram of the latch circuit receiving the clear latch signal according to an embodiment of this application.

[0039] Figure 8 This is a circuit diagram of the latch circuit in an embodiment of this application receiving the clear latch signal.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1. Anti-power-loss latch circuit; 11. Voltage detection logic unit; 12. Signal selection logic unit; 2. Latch circuit; 3. Buck unit; 4. Voltage divider unit; 5. Filter unit; U1. Comparator; U2. First AND gate chip; U3. Second AND gate chip; U4. Inverter; U5. Voltage regulator; Q1. MOSFET;

[0042] R1, First resistor; R2, Second resistor; R3, Third resistor; R4, Fourth resistor; R5, Fifth resistor; R6, Sixth resistor; R7, Seventh resistor; R8, Eighth resistor; C1, First capacitor; C2, Second capacitor; C3, Third capacitor; C4, Fourth capacitor; C5, Fifth capacitor; C6, Sixth capacitor; C7, Seventh capacitor; C8, Eighth capacitor; C9, Ninth capacitor; C10, Tenth capacitor; C11, Eleventh capacitor; C12, Twelfth capacitor; D1, First diode; D2, Second diode; Vsafe, Supply voltage; nVsafe, Voltage detection signal; V1, Latch signal; V2, First reference voltage; V3, Second reference voltage; nV1, Inverted latch signal; RST1, Original clear latch signal; RST2, Clear latch signal; FAULT, Overvoltage fault signal; VREF, Undervoltage threshold; VC1, First supply voltage. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "up," "down," "left," and "right" generally refer to up, down, left, and right in the actual use or working state of the device, specifically the drawing directions in the accompanying drawings.

[0044] In this application, unless otherwise expressly specified and limited, the terms "connected," "linked," "stacked," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0045] As a preamble to this application, a latching circuit is provided, such as Figure 1 , Figure 2 As shown, the latch circuit 2 includes:

[0046] The first AND gate chip U2 has a first input terminal for connecting the original clear latch signal RST1 through the seventh resistor R7, a second input terminal for connecting the inverted latch signal nV1, a power supply terminal for connecting the power supply voltage Vsafe, and an output terminal for outputting the first logic signal.

[0047] The second AND gate chip U3 has a first input terminal for receiving the latch signal V1, a second input terminal for receiving the overvoltage fault signal FAULT, and an output terminal for outputting the second logic signal.

[0048] Inverter U4 has its first input connected to the output of the first AND gate chip U2, and its first output used to generate a latch signal V1 that is opposite to the first logic signal. The second input of inverter U4 is connected to the output of the second AND gate chip U3, and its second output used to generate an inverted latch signal nV1 that is opposite to the second logic signal.

[0049] The latch circuit 2 also includes:

[0050] The eighth resistor R8 has its first end connected to the power supply voltage Vsafe, and its second end connected to the first input terminal of the first AND gate chip U2.

[0051] The fourth capacitor C4 has its first terminal connected to the first input terminal of the first AND gate chip U2, and its second terminal grounded.

[0052] The fifth capacitor C5 has its first terminal connected to the power supply terminal of the first AND gate chip U2, and its second terminal grounded.

[0053] The sixth capacitor C6 has its first terminal connected to the power supply terminal of the inverter U4, and its second terminal grounded. The power supply terminal of the inverter U4 is used to receive the supply voltage Vsafe.

[0054] like Figure 3 As shown, the latching circuit 2 also includes a step-down unit 3. The input terminal of the step-down unit 3 is connected to the output terminal of the first power supply voltage VC1 and is used to input the first power supply voltage VC1. The step-down unit 3 is used to output the power supply voltage Vsafe according to the first power supply voltage VC1.

[0055] Step-down unit 3 includes:

[0056] Voltage regulator U5 has its input terminal connected to the output terminal of the first power supply voltage VC1 for input. The output terminal of voltage regulator U5 serves as the output terminal of step-down unit 3 for outputting the power supply voltage Vsafe. The ground terminal of voltage regulator U5 is grounded.

[0057] Several input capacitors are connected in parallel between the input terminal of the voltage regulator U5 and ground; among them, the input capacitors include the seventh capacitor C7, the eighth capacitor C8 and the ninth capacitor C9;

[0058] Several output capacitors are connected in parallel between the output terminal of voltage regulator U5 and ground. These output capacitors include the tenth capacitor C10, the eleventh capacitor C11, and the twelfth capacitor C12.

[0059] The latch circuit 2 is designed based on an RS flip-flop. The overvoltage fault signal FAULT is normal when it is high and abnormal when it is low. The original clear latch signal RST1 latches when it is high and clears the latch when it is low. The latch signal V1 is the fault latch signal output by the latch circuit 2. It is normal when it is high and abnormal when it is low. The inverted signal nV1 of the latch signal V1 is the inverted version of the latch signal V1. The truth table corresponding to the latch circuit 2 is shown in Table 1.

[0060] Table 1: Truth Table for Latch Circuit

[0061] 1 H H H L 2 H L H L 3 L H L H 4 L L H H

[0062] For the latch circuit 2, a low-voltage battery is used to provide power. The output terminal of the low-voltage battery serves as the first power supply voltage output terminal, which provides two power supplies. The first power supply voltage output terminal generates a power supply voltage Vsafe through the voltage regulator U5 to power the latch circuit 2. The second power supply voltage output terminal is connected to the system base chip (SBC chip). The output terminal of the SBC chip serves as the second power supply voltage output terminal to output the second power supply voltage to power the controller. When the output voltage of the low-voltage battery drops, the second power supply voltage can be maintained for a short time due to the built-in boost circuit of the SBC chip. However, the power supply voltage Vsafe will drop rapidly due to the lack of boost capability.

[0063] In hybrid vehicle systems, frequent sleep and wake-up cycles of client devices cause rapid voltage fluctuations in the low-voltage battery. This can result in the low-voltage battery output voltage dropping and then quickly rising again. At certain drop times, the second power supply voltage may still be able to maintain the normal operation of the controller, but the supply voltage Vsafe has dropped to a level that cannot maintain the normal operation of the first AND gate chip U2, the second AND gate chip U3, and the inverter U4. In this case, the internal CMOS structure of the first AND gate chip U2, the second AND gate chip U3, and the inverter U4 will fail, resulting in unstable output signals. Consequently, the latch signal V1 is mistakenly latched as low. Even after the supply voltage Vsafe recovers, the latch signal V1 will continue to be mistakenly latched as low. Since the controller is still operating normally, the original clear latch signal RST1 remains high, and the latch circuit 2 still cannot automatically clear the mistaken latch state, causing the mistaken latch to persist. This leads to the customer vehicle falsely reporting an overvoltage fault.

[0064] like Figures 4 to 6 As shown, this application constructs a power-loss-preventing latch circuit 1. The voltage detection logic unit 11 monitors the relationship between the power supply voltage Vsafe and the undervoltage threshold VREF in real time. When the power supply voltage Vsafe is lower than the undervoltage threshold VREF, the signal selection logic unit 12 provides a low-level clear latch signal RST2 so that the latch circuit 2 does not perform fault latching, thus avoiding false latching caused by insufficient power supply to the latch circuit 2 leading to unstable logic chip output.

[0065] This application provides a circuit for preventing accidental latching during power loss, including:

[0066] The voltage detection logic unit 11 is used to receive the supply voltage Vsafe and output a voltage detection signal nVsafe based on the comparison result between the supply voltage Vsafe and the undervoltage threshold VREF.

[0067] The signal selection logic unit 12 receives the voltage detection signal nVsafe at one input terminal and the original clear latch signal RST1 at the other input terminal. Based on the original clear latch signal RST1 and the voltage detection signal nVsafe, it outputs the clear latch signal RST2.

[0068] Specifically, when the supply voltage Vsafe is lower than the undervoltage threshold VREF, the clear latch signal RST2 is low; when the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, the clear latch signal RST2 follows the original clear latch signal RST1.

[0069] Specifically, when the supply voltage Vsafe is lower than the undervoltage threshold VREF, the voltage detection logic unit 11 outputs a low-level voltage detection signal nVsafe, triggering the anti-false latching. The signal selection logic unit 12 forcibly pulls the clear latch signal RST2 transmitted to the latch circuit 2 low, causing the latch circuit 2 to stop performing fault latching and avoid false latching caused by undervoltage.

[0070] When the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, the voltage detection logic unit 11 outputs a high-level voltage detection signal nVsafe, indicating that the power supply is normal. The signal selection logic unit 12 then makes the clear latch signal RST2 follow the original clear latch signal RST1, without affecting the normal circuit latching function. The logic truth table of this application is shown in Table 2:

[0071] Table 2: Logic Truth Table for Power-Off Accidental Latching Circuit

[0072] 1 H H H 2 L H L 3 H L L 4 L L L

[0073] In one alternative embodiment, such as Figure 5 As shown, the voltage detection logic unit 11 includes a comparator U1. The first input terminal of the comparator U1 is used to receive the supply voltage Vsafe, the second input terminal of the comparator U1 is used to receive the undervoltage threshold VREF, and the output terminal of the comparator U1 is used to output the voltage detection signal nVsafe.

[0074] When the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, the output of comparator U1 is used to output a high-level voltage detection signal nVsafe; when the supply voltage Vsafe is lower than the undervoltage threshold VREF, the output of comparator U1 is used to output a low-level voltage detection signal nVsafe.

[0075] Specifically, the positive input of comparator U1 is connected to the supply voltage Vsafe, and the negative input is connected to the undervoltage threshold VREF. When the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, comparator U1 outputs a high-level voltage detection signal nVsafe, indicating that the power supply is normal; the level of the clear latch signal RST2 sent to latch circuit 2 depends on the original clear latch signal RST1, that is, it does not affect the original latch logic.

[0076] When the supply voltage Vsafe is lower than the undervoltage threshold VREF, the comparator U1 outputs a high-level voltage detection signal nVsafe, and the drive signal selection logic section 12 outputs a low-level clear latch signal RST2, so that the latch circuit 2 does not perform fault latching and avoids false latching.

[0077] When the supply voltage Vsafe recovers to above the undervoltage threshold VREF, the voltage detection signal nVsafe output by comparator U1 returns to a high level, and the latch clear signal RST2 resumes to follow the original latch clear signal RST1.

[0078] In an optional embodiment, a voltage divider unit 4 is further included. The voltage divider unit 4 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is used to connect to the first reference voltage V2. The second end of the first resistor R1 is connected to the second input terminal of the comparator U1. The first end of the second resistor R2 is connected to the second end of the first resistor R1. The second end of the second resistor R2 is grounded. The first reference voltage V2 is divided based on the first resistor R1 and the second resistor R2 to generate an undervoltage threshold VREF.

[0079] In this application, a first resistor R1 and a second resistor R2 are connected in series. The first terminal of the first resistor R1 is connected to a first reference voltage V2, and the second terminal of the second resistor R2 is grounded. The connection point of the first resistor R1 and the second resistor R2 is connected to the second input terminal of comparator U1, which outputs an undervoltage threshold VREF. In this application, the first resistor R1 and the second resistor R2 have the same resistance value, both 10kΩ. When the first reference voltage V2 is 5V, the undervoltage threshold VREF is 2.5V. Of course, in other embodiments, the ratio of the first reference voltage V2 and the resistance values ​​of the first resistor R1 and the second resistor R2 can be arbitrarily adjusted to obtain the desired undervoltage threshold VREF.

[0080] In another embodiment, in addition to the series resistor form, the voltage divider unit 4 can also use a variable resistor instead of a fixed resistor to achieve adjustable voltage division ratio, thereby adjusting the undervoltage threshold VREF. The variable resistor is, for example, a sliding rheostat or a potentiometer. One end of the sliding rheostat is used to connect to the reference voltage V2, and the middle tap is used to output the undervoltage threshold VREF.

[0081] In an optional embodiment, the voltage detection logic unit 11 further includes a filtering unit 5. Taking the first capacitor C1 as an example, the first end of the first capacitor C1 is connected to the power supply terminal of the comparator U1, and the second end of the first capacitor C1 is grounded. The first capacitor C1 is used to filter out noise, and the power supply terminal of the comparator U1 is connected to the power supply voltage Vsafe.

[0082] In one alternative embodiment, such as Figure 6 As shown, the voltage detection logic unit 11 includes a switching element, which is used to connect to the supply voltage Vsafe and output a voltage detection signal nVsafe controllably according to the supply voltage Vsafe.

[0083] When the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, the switch is open and outputs a high-level voltage detection signal nVsafe; when the supply voltage Vsafe is lower than the undervoltage threshold VREF, the switch Q1 is turned on and outputs a low-level voltage detection signal nVsafe.

[0084] The switching devices in this application include MOSFETs, transistors, or insulated-gate bipolar transistors (IGBTs), such as... Figure 6 As shown, this application takes MOSFET Q1 as an example of a switching device. The gate of MOSFET Q1 is connected to the supply voltage Vsafe through the third resistor R3, the drain of MOSFET Q1 is grounded, the source of MOSFET Q1 is connected to the second reference voltage V3 through the fourth resistor R4, and the source of MOSFET Q1 is also used to output the voltage detection signal nVsafe.

[0085] The voltage detection logic unit 11 also includes:

[0086] The fifth resistor R5 has its first end connected to the gate of MOSFET Q1 and its second end connected to the source of MOSFET Q1.

[0087] The second capacitor C2 has its first end connected to the gate of the MOSFET Q1 and its second end connected to the drain of the MOSFET Q1.

[0088] When the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, MOSFET Q1 is turned off, and the source of MOSFET Q1 is used to output a high-level voltage detection signal nVsafe; when the supply voltage Vsafe is lower than the undervoltage threshold VREF, MOSFET Q1 is turned on, and the source of MOSFET Q1 is used to output a low-level voltage detection signal nVsafe.

[0089] In this application, the MOSFET Q1 is a PMOS transistor. The gate voltage of the MOSFET Q1 is approximately equal to the supply voltage Vsafe, and the source voltage is pulled up to the second reference voltage V3. In this application, the second reference voltage V3 is set to 5V. Of course, in other embodiments, the ratio of the second reference voltage V3 to the resistance values ​​of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 can be arbitrarily adjusted to obtain the required undervoltage threshold VREF.

[0090] When the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, the MOSFET Q1 is turned off, and the source is pulled up through the fourth resistor R4, outputting a high-level voltage detection signal nVsafe, indicating that the power supply is normal.

[0091] When the supply voltage Vsafe is less than the undervoltage threshold VREF, the MOSFET Q1 will turn on. Because its drain is grounded, the source voltage will be close to 0V, and a low-level voltage detection signal nVsafe will be output.

[0092] In one alternative embodiment, such as Figure 5 , Figure 6 As shown, the signal selection logic unit 12 includes:

[0093] The first diode D1 has its negative terminal connected to the output terminal of the voltage detection logic unit 11, and its positive terminal is used to connect to the power supply voltage Vsafe through the sixth resistor R6.

[0094] The second diode D2 has its cathode connected to the original clear latch signal RST1, and its anode connected to the anode of the first diode D1, which is used to output the clear latch signal RST2.

[0095] The third capacitor C3 has its first terminal connected to the positive terminal of the second diode D2, and its second terminal grounded.

[0096] Specifically, when the voltage detection signal nVsafe is high, the first diode D1 is cut off, and the voltage at the positive terminal of the first diode D1 is pulled up to the supply voltage Vsafe by the sixth resistor R6. When the original clear latch signal RST1 is high, both the negative and positive terminals of the second diode D2 are high, so the second diode D2 is cut off, and the output clear latch signal RST2 is high, just like the original clear latch signal RST1. When the original clear latch signal RST1 is low, the second diode D2 is turned on, and the output clear latch signal RST2 is low, just like the original clear latch signal RST1. This achieves the function that, under normal power supply conditions, the clear latch signal RST2 follows the change of the original clear latch signal RST1 without interfering with the original latch logic.

[0097] When the voltage detection signal nVsafe is low, the first diode D1 is turned on. So, regardless of whether the original clear latch signal RST1 is high or low, the output clear latch signal RST2 is low. This enables the clear latch signal RST2 to be forcibly pulled low when the power supply is undervoltage, thus disabling the fault latch function.

[0098] This application embodiment also provides a fault latching system, including a power-loss fault latching circuit 1 and a latching circuit 2, which are connected to provide a clear latching signal RST2 to the latching circuit 2.

[0099] like Figure 7 , Figure 8As shown, in the fault latching system of this application, the first AND gate chip U2 of the latching circuit 2 receives the clear latch signal RST2 provided by the latching circuit 2, instead of directly receiving the original clear latch signal RST1 as mentioned in the previous section. When the supply voltage Vsafe is lower than the undervoltage threshold VREF, the clear latch signal RST2 is forced to a low level, so that the latching circuit 2 does not perform fault latching, thus avoiding false latching caused by the unstable output of the logic chip due to insufficient power supply to the latching circuit 2.

[0100] The above provides a detailed description of a power-loss error latching circuit and fault latching system provided by this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A circuit for preventing accidental latching due to power failure, characterized in that, include: The voltage detection logic unit (11) is used to receive the supply voltage (Vsafe) and output a voltage detection signal (nVsafe) based on the comparison result of the supply voltage (Vsafe) and the undervoltage threshold (VREF); The signal selection logic unit (12) receives the voltage detection signal (nVsafe) at one input terminal and the original clear latch signal (RST1) at the other input terminal. Based on the original clear latch signal (RST1) and the voltage detection signal (nVsafe), it outputs the clear latch signal (RST2). Specifically, when the supply voltage (Vsafe) is lower than the undervoltage threshold (VREF), the clear latch signal (RST2) is low; when the supply voltage (Vsafe) is higher than or equal to the undervoltage threshold (VREF), the clear latch signal (RST2) follows the original clear latch signal (RST1).

2. The anti-power-loss latching circuit according to claim 1, characterized in that, The voltage detection logic unit (11) includes a comparator (U1), the first input terminal of the comparator (U1) is used to receive the supply voltage (Vsafe), the second input terminal of the comparator (U1) is used to receive the undervoltage threshold (VREF), and the output terminal of the comparator (U1) is used to output the voltage detection signal (nVsafe). When the supply voltage (Vsafe) is higher than or equal to the undervoltage threshold (VREF), the output of the comparator (U1) is used to output a high-level voltage detection signal (nVsafe); when the supply voltage (Vsafe) is lower than the undervoltage threshold (VREF), the output of the comparator (U1) is used to output a low-level voltage detection signal (nVsafe).

3. The anti-power-loss latching circuit according to claim 2, characterized in that, The voltage detection logic unit (11) further includes a voltage divider unit (4), the input terminal of which is used to connect to a first reference voltage (V2), and the first reference voltage (V2) is divided based on the voltage divider unit (4) to generate the undervoltage threshold (VREF).

4. The anti-power-loss latching circuit according to claim 2, characterized in that, The voltage detection logic unit (11) further includes a filter unit (5), the first end of which is connected to the power supply terminal of the comparator (U1), and the second end of which is grounded.

5. The anti-power-loss latching circuit according to claim 1, characterized in that, The voltage detection logic unit (11) includes a switch element, which is used to connect to the power supply voltage (Vsafe) and controllably output the voltage detection signal (nVsafe) according to the power supply voltage (Vsafe); When the supply voltage (Vsafe) is higher than or equal to the undervoltage threshold (VREF), the switch is open and outputs a high-level voltage detection signal (nVsafe); when the supply voltage (Vsafe) is lower than the undervoltage threshold (VREF), the switch is open and outputs a low-level voltage detection signal (nVsafe).

6. The anti-power-loss latching circuit according to claim 1, characterized in that, The signal selection logic unit (12) includes: The first diode (D1) has its cathode connected to the output terminal of the voltage detection logic unit (11), and its anode is used to connect to the supply voltage (Vsafe) through the sixth resistor (R6). The second diode (D2) has its cathode connected to the original clear latch signal (RST1), and its anode connected to the anode of the first diode (D1) to output the clear latch signal (RST2).

7. A fault latching system, characterized in that, Includes the anti-power-loss latch circuit (1) and latch circuit (2) as described in any one of claims 1-6, wherein the anti-power-loss latch circuit (1) and the latch circuit (2) are connected and are used to provide a clear latch signal (RST2) to the latch circuit (2).

8. The fault latching system according to claim 7, characterized in that, The latch circuit (2) includes: The first AND gate chip (U2) has a first input terminal for connecting to the clear latch signal (RST2) via a seventh resistor (R7), a second input terminal for connecting to the inverted signal (nV1) of the first latch signal (V1), a power supply terminal for connecting to the supply voltage (Vsafe), and an output terminal for outputting a first logic signal. The second AND gate chip (U3) has a first input terminal for receiving the first latch signal (V1), a second input terminal for receiving the overvoltage fault signal (FAULT), and an output terminal for outputting the second logic signal. An inverter (U4) is provided, with its first input connected to the output of the first AND gate chip (U2) and its first output being used to output the first latch signal (V1) which is opposite to the first logic signal. The second input of the inverter (U4) is connected to the output of the second AND gate chip (U3) and its second output being used to output the inverted signal (nV1) of the first latch signal which is opposite to the second logic signal.

9. The fault latching system according to claim 8, characterized in that, The latch circuit (2) further includes: The eighth resistor (R8) has its first terminal connected to the supply voltage (Vsafe) and its second terminal connected to the first input terminal of the first AND gate chip (U2). The fourth capacitor (C4) has its first terminal connected to the first input terminal of the first AND gate chip (U2), and its second terminal grounded. The fifth capacitor (C5) has its first terminal connected to the power supply terminal of the first AND gate chip (U2), and its second terminal grounded. The sixth capacitor (C6) has its first terminal connected to the power supply terminal of the inverter (U4) and its second terminal grounded. The power supply terminal of the inverter (U4) is used to receive the supply voltage (Vsafe).

10. The fault latching system according to claim 7, characterized in that, The latching circuit (2) further includes a step-down unit (3). The input terminal of the step-down unit (3) is connected to the output terminal of the first power supply voltage (VC1) and is used to input the first power supply voltage (VC1). The step-down unit (3) is used to output the power supply voltage (Vsafe) according to the first power supply voltage (VC1).

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