Anti-power-down false latching circuit
Patent Information
- Application Number
- CN202521826499.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-26
- Publication Date
- 2026-09-15
- Estimated Expiration
- 2035-08-26
AI Technical Summary
[0003]本申请的实施例目的在于提供一种防掉电误锁存电路，以解决现有技术中锁存电路在供电电压欠压时误锁存过压故障信号使车辆误报过压故障的技术问题
[0029]The beneficial effects of this application are as follows: This application constructs a circuit to prevent false latching due to power failure. The voltage detection logic unit monitors the relationship between the supply voltage and the undervoltage threshold in real time. The signal selection logic unit outputs a second latch signal to replace the original first latch signal. When the supply voltage is normal, the second latch signal follows the first latch signal and can correctly reflect the fault state under normal operating conditions. When the supply voltage is lower than the undervoltage threshold, the signal selection logic unit forces the output of the second latch signal to be high to cover the first latch signal, which may be falsely changed to a low level due to the failure of the logic chip. This avoids false latching caused by the unstable output of the logic chip due to insufficient power supply to the latch circuit.
Smart Images
Figure CN224760217U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of automotive electronics technology, specifically to a circuit for preventing accidental latching during power loss. Background Technology
[0002] In current hybrid vehicle solutions, the bus voltage is sampled using voltage divider resistors and isolation operational amplifiers, and the sampled voltage is output linearly. When the sampled voltage exceeds a threshold, overvoltage protection measures are required. Simultaneously, to maintain the stability of the overvoltage fault signal, a fault latch circuit is needed. However, in related technologies, the latch circuit, due to the internal logic chip's requirements on the supply voltage, experiences logic failure when the voltage falls below the undervoltage threshold, resulting in unstable output and potentially leading to false latching of the fault latch signal. If the latch circuit falsely latches the overvoltage fault signal when the supply voltage is undervoltage, the vehicle will falsely report an overvoltage fault, affecting normal operation. Utility Model Content
[0003] The purpose of this application is to provide a circuit to prevent false latching during power failure, so as to solve the technical problem in the prior art where the latching circuit falsely latches overvoltage fault signals when the supply voltage is low, causing the vehicle to falsely report an overvoltage fault.
[0004] To address the aforementioned technical problems, embodiments of this application disclose the following technical solutions:
[0005] In a first aspect, embodiments of this application provide a power-loss-induced latching circuit, comprising:
[0006] The voltage detection logic unit is used to receive the supply voltage and output a voltage detection signal based on the comparison result between the supply voltage and the undervoltage threshold.
[0007] The signal selection logic unit receives the voltage detection signal at one input terminal and the first latch signal at the other input terminal. The signal selection logic unit is used to output a second latch signal based on the first latch signal and the voltage detection signal.
[0008] Specifically, when the supply voltage is lower than the undervoltage threshold, the second latch signal is high; when the supply voltage is higher than or equal to the undervoltage threshold, the second latch signal follows the first latch signal.
[0009] In one embodiment of this application, the voltage detection logic unit includes a switching element, which is used to connect to the power supply voltage and controllably output the voltage detection signal according to the power supply voltage;
[0010] When the supply voltage is higher than or equal to the undervoltage threshold, the switch is turned on and outputs a low-level voltage detection signal; when the supply voltage is lower than the undervoltage threshold, the switch is turned off and outputs a high-level voltage detection signal.
[0011] In one embodiment of this application, the switching device is one of a MOSFET, a transistor, and an IGBT.
[0012] In one embodiment of this application, the voltage detection logic unit includes a comparator, a first input terminal of the comparator for receiving the supply voltage, a second input terminal of the comparator for connecting the undervoltage threshold, and an output terminal of the comparator for outputting the voltage detection signal.
[0013] When the supply voltage is higher than or equal to the undervoltage threshold, the output of the comparator is used to output a low-level voltage detection signal; when the supply voltage is lower than the undervoltage threshold, the output of the comparator is used to output a high-level voltage detection signal.
[0014] In one embodiment of this application, the voltage detection logic unit further includes a filtering unit, the first end of which is connected to the second input terminal of the comparator, and the second end of which is grounded.
[0015] In one embodiment of this application, the signal selection logic unit includes:
[0016] The first diode has its anode connected to the voltage detection logic unit for receiving the voltage detection signal, and its cathode connected to the fourth resistor. The first diode is used to output the second latch signal.
[0017] The second diode has its anode connected to the latching circuit to receive the first latching signal, and its cathode connected to the cathode of the first diode.
[0018] In one embodiment of this application, a sampling unit is further included. The first end of the sampling unit is connected to the output end of the signal selection logic unit and is used to receive the second latch signal. The output end of the sampling unit is used to output a sampling signal according to the second latch signal.
[0019] In one embodiment of this application, the latch circuit includes:
[0020] The first AND gate chip has a first input terminal connected to a sixth resistor for receiving a clear latch signal through the sixth resistor. The second input terminal of the first AND gate chip is used to receive the inverted signal of the first latch signal. The power supply terminal of the first AND gate chip is used to receive the supply voltage. The first AND gate chip is used to output a first logic signal.
[0021] The second AND gate chip has a first input terminal for receiving the first latch signal, a second input terminal for receiving an overvoltage fault signal, and an output second logic signal.
[0022] An inverter, wherein the first input terminal of the inverter is connected to the output terminal of the first AND gate chip, and the first output terminal of the inverter is used to output the first latch signal which is opposite to the first logic signal; the second input terminal of the inverter is connected to the output terminal of the second AND gate chip, and the second output terminal of the inverter is used to output the inverted signal of the first latch signal which is opposite to the second logic signal.
[0023] In one embodiment of this application, the latch circuit further includes:
[0024] The seventh resistor has a first end connected to the power supply voltage and a second end connected to the first input terminal of the first AND gate chip.
[0025] The fourth capacitor has its first terminal connected to the first input terminal of the first AND gate chip, and its second terminal grounded.
[0026] The fifth capacitor has its first terminal connected to the power supply terminal of the first AND gate chip, and its second terminal grounded.
[0027] The sixth capacitor has its first terminal connected to the power supply terminal of the inverter, and its second terminal grounded. The power supply terminal of the inverter is used to receive the power supply voltage.
[0028] In one embodiment of this application, the latching circuit further includes a step-down unit, the input terminal of which is used to connect to a second power supply voltage, and the output terminal of which is used to output the power supply voltage.
[0029] The beneficial effects of this application are as follows: This application constructs a circuit to prevent false latching due to power failure. The voltage detection logic unit monitors the relationship between the supply voltage and the undervoltage threshold in real time. The signal selection logic unit outputs a second latch signal to replace the original first latch signal. When the supply voltage is normal, the second latch signal follows the first latch signal and can correctly reflect the fault state under normal operating conditions. When the supply voltage is lower than the undervoltage threshold, the signal selection logic unit forces the output of the second latch signal to be high to cover the first latch signal, which may be falsely changed to a low level due to the failure of the logic chip. This avoids false latching caused by the unstable output of the logic chip due to insufficient power supply to the latch circuit. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 This is a circuit diagram of a latching circuit;
[0032] Figure 2 This is the circuit diagram of the buck unit of the latch circuit;
[0033] Figure 3 This is a logical architecture diagram of an embodiment of this application;
[0034] Figure 4 This is a circuit diagram of a power-loss latch-up protection circuit according to an embodiment of this application;
[0035] Figure 5 This is a circuit diagram of another anti-power-loss latching circuit according to an embodiment of this application.
[0036] Explanation of reference numerals in the attached figures:
[0037] 1. Voltage detection logic unit; 2. Signal selection logic unit; 3. Sampling unit; 4. Buck unit; 5. Filtering unit; Q1, MOSFET; U1, Comparator; U2, First AND gate chip; U3, Second AND gate chip; U4, Inverter; U5, Regulator; Vsafe, Supply voltage; nVsafe, Voltage detection signal; V1, First latch signal; nV1, Inverted signal of the first latch signal; V2, Second latch signal; V3, Sampling signal; RST, Clear latch signal; FAULT, Overvoltage fault signal; VREF, Undervoltage threshold; VC1 1. First power supply voltage; VC2. Second power supply voltage; R1. First resistor; R2. Second resistor; R3. Third resistor; R4. Fourth resistor; R5. Fifth resistor; R6. Sixth resistor; R7. Seventh resistor; C1. First capacitor; C2. Second capacitor; C3. Third capacitor; C4. Fourth capacitor; C5. Fifth capacitor; C6. Sixth capacitor; C7. Seventh capacitor; C8. Eighth capacitor; C9. Ninth capacitor; C10. Tenth capacitor; C11. Eleventh capacitor; C12. Twelfth capacitor; D1. First diode; D2. Second diode. Detailed Implementation
[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "up," "down," "left," and "right" generally refer to up, down, left, and right in the actual use or working state of the device, specifically the drawing directions in the accompanying drawings.
[0039] In this application, unless otherwise expressly specified and limited, the terms "connected," "linked," "stacked," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0040] As a preamble to this application, a latching circuit is provided, such as Figure 1 As shown, the latch circuit includes:
[0041] The first AND gate chip U2 has its first input terminal connected to the sixth resistor R6, which is used to access the clear latch signal RST through the sixth resistor R6. The clear latch signal RST is output by the controller. The second input terminal of the first AND gate chip U2 is used to access the inverted signal nV1 of the first latch signal. The power supply terminal of the first AND gate chip U2 is used to access the supply voltage Vsafe. The first AND gate chip U2 is used to output the first logic signal.
[0042] The second AND gate chip U3 has a first input terminal for receiving the first latch signal V1, a second input terminal for receiving the overvoltage fault signal FAULT, and a second logic signal for outputting the second AND gate chip U3.
[0043] Inverter U4 has its first input connected to the output of the first AND gate chip U2, and its first output used to output a first latch signal V1 that is opposite to the first logic signal. The second input of inverter U4 is connected to the output of the second AND gate chip U3, and its second output used to output an inverted signal nV1 that is opposite to the second logic signal of the first latch signal.
[0044] The seventh resistor R7 has its first end connected to the power supply voltage output terminal, which is used to connect the power supply voltage Vsafe. The second end of the seventh resistor R7 is connected to the first input terminal of the first AND gate chip U2.
[0045] The fourth capacitor C4 has its first terminal connected to the first input terminal of the first AND gate chip U2, and its second terminal grounded.
[0046] The fifth capacitor C5 has its first terminal connected to the power supply terminal of the first AND gate chip U2, and its second terminal grounded.
[0047] The sixth capacitor C6 has its first terminal connected to the power supply terminal of the inverter U4, and its second terminal grounded. The power supply terminal of the inverter U4 is connected to the power supply voltage output terminal to receive the power supply voltage Vsafe.
[0048] like Figure 2 As shown, the latching circuit also includes a step-down unit 4. The input terminal of the step-down unit 4 is connected to the second power supply voltage output terminal and is used to connect to the second power supply voltage VC2. The output terminal of the step-down unit 4 is the power supply voltage output terminal and is used to output the power supply voltage Vsafe.
[0049] Step-down unit 4 includes:
[0050] Voltage regulator U5 has its input terminal connected to the second power supply voltage output terminal for inputting the second power supply voltage VC2. The output terminal of voltage regulator U5 is the output terminal of buck unit 4 for outputting the power supply voltage Vsafe. The ground terminal of voltage regulator U5 is grounded.
[0051] Several input capacitors are connected in parallel between the input terminal of the voltage regulator U5 and ground; among them, the input capacitors include the seventh capacitor C7, the eighth capacitor C8 and the ninth capacitor C9;
[0052] Several output capacitors are connected in parallel between the output terminal of voltage regulator U5 and ground. These output capacitors include the tenth capacitor C10, the eleventh capacitor C11, and the twelfth capacitor C12.
[0053] This latch circuit is designed based on an RS flip-flop. The overvoltage fault signal FAULT is normal when it is high and abnormal when it is low. The clear latch signal RST is latched when it is high and cleared when it is low. The first latch signal V1 is the fault latch signal output by this latch circuit. It is normal when it is high and abnormal when it is low. The inverted signal nV1 of the first latch signal is the inverted fault latch signal. The truth table of the latch circuit is shown in Table 1.
[0054] 1 H H H L 2 H L H L 3 L H L H 4 L L H H
[0055] Table 1
[0056] For this latching circuit, a low-voltage battery is used for power supply. The output terminal of the low-voltage battery serves as the second power supply voltage output terminal, which provides two power supplies. The first power supply voltage Vsafe is generated by the voltage regulator U5 to power the latching circuit. The second power supply voltage is connected to the output terminal of the system base chip (SBC chip) and serves as the first power supply voltage output terminal, outputting the first power supply voltage VC1 to power the controller. When the output voltage of the low-voltage battery drops, the first power supply voltage VC1 can be maintained for a short time due to the built-in boost circuit of the SBC chip. However, the power supply voltage Vsafe will drop rapidly due to the lack of boost capability.
[0057] In hybrid vehicle systems, frequent sleep and wake-up cycles of client devices cause rapid voltage fluctuations in the low-voltage battery. This can result in the low-voltage battery output voltage dropping and then quickly rising again. At specific drop times, the first power supply voltage VC1 can still maintain the normal operation of the controller, but the supply voltage Vsafe has dropped to a level that cannot maintain the normal operation of the first AND gate chip U2, the second AND gate chip U3, and the inverter U4. In this case, the internal CMOS structure of the first AND gate chip U2, the second AND gate chip U3, and the inverter U4 will fail, resulting in unstable output signals. Consequently, the first latch signal V1 is mistakenly latched as low. Even after the supply voltage Vsafe recovers, the first latch signal V1 will continue to be mistakenly latched as low. Since the controller is still operating normally, the clear latch signal RST remains high, and the latch circuit still cannot automatically clear the mistaken latch state, causing the mistaken latch to persist. This leads to the customer vehicle falsely reporting an overvoltage fault.
[0058] This application constructs a circuit to prevent false latching due to power failure. The voltage detection logic unit monitors the relationship between the supply voltage and the undervoltage threshold in real time. When the supply voltage is lower than the undervoltage threshold, the signal selection logic unit forces the output of a high-level second latch signal, thus avoiding false latching caused by unstable logic chip output due to insufficient power supply to the latch circuit.
[0059] like Figures 3 to 5 As shown, this application embodiment provides a power-loss error prevention latching circuit, including:
[0060] Voltage detection logic unit 1 is connected to the power supply voltage output terminal, used to receive the power supply voltage Vsafe, and output a voltage detection signal nVsafe based on the comparison result between the power supply voltage Vsafe and the undervoltage threshold VREF;
[0061] The signal selection logic unit 2 has one input terminal connected to the voltage detection logic unit 1 to receive the voltage detection signal nVsafe, and the other input terminal connected to the latch circuit to receive the first latch signal V1. The signal selection logic unit 2 outputs the second latch signal V2 according to the first latch signal V1 and the voltage detection signal nVsafe.
[0062] Specifically, when the supply voltage Vsafe is lower than the undervoltage threshold VREF, the second latch signal V2 is high; when the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, the second latch signal V2 follows the first latch signal V1.
[0063] Specifically, when the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, the voltage detection logic unit 1 outputs a low-level voltage detection signal nVsafe, indicating that the power supply is normal. The signal selection logic unit 2 makes the second latch signal V2 follow the first latch signal V1, so that the second latch signal V2 can respond normally to the overvoltage fault.
[0064] When the supply voltage Vsafe is lower than the undervoltage threshold VREF, the voltage detection logic unit 1 outputs a high-level voltage detection signal nVsafe, triggering the anti-false latch. The signal selection logic unit 2 forces the output of a high-level second latch signal V2, overwriting the original first latch signal V1, to avoid false latching caused by undervoltage. The logic truth table of this application is shown in Table 2:
[0065] 1 H H H 2 L H L 3 H L H 4 L L H
[0066] Table 2
[0067] In one optional embodiment, the voltage detection logic unit 1 includes a switching element for receiving the supply voltage Vsafe and outputting a voltage detection signal nVsafe controllably according to the supply voltage Vsafe.
[0068] When the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, the switch is turned on and outputs a low-level voltage detection signal nVsafe; when the supply voltage Vsafe is lower than the undervoltage threshold VREF, the switch is turned off and outputs a high-level voltage detection signal nVsafe.
[0069] The switching devices in this application include MOSFETs, transistors, or insulated-gate bipolar transistors (IGBTs), such as... Figure 4 As shown, this application takes MOSFET Q1 as an example of a switching device. The gate of MOSFET Q1 is connected to the power supply voltage output terminal through the first resistor R1 and is connected to the power supply voltage Vsafe. The source of MOSFET Q1 is grounded. The drain of MOSFET Q1 is connected to the first power supply voltage output terminal through the second resistor R2 and is used to connect to the first power supply voltage VC1 through the second resistor R2. The drain of MOSFET Q1 is also used to output the voltage detection signal nVsafe.
[0070] When the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, MOSFET Q1 is turned on, and the drain of MOSFET Q1 is used to output a low-level voltage detection signal nVsafe; when the supply voltage Vsafe is lower than the undervoltage threshold VREF, MOSFET Q1 is turned off, and the drain of MOSFET Q1 is used to output a high-level voltage detection signal nVsafe.
[0071] Specifically, the gate of MOSFET Q1 is connected to the supply voltage Vsafe through the first resistor R1 and grounded through the third resistor R3, forming a voltage divider network. Since the controller's power supply, i.e., the first power supply voltage VC1, will not drop quickly due to the boost circuit, the drain of MOSFET Q1 is connected to the first power supply voltage VC1 through the second resistor R2 and pulled up by the first power supply voltage VC1. The drain voltage is the output voltage detection signal nVsafe.
[0072] When the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, the gate-source voltage of MOSFET Q1 can reach the turn-on voltage of MOSFET Q1. At this time, MOSFET Q1 is turned on, and the drain voltage output is low, indicating that the power supply is normal.
[0073] When the supply voltage Vsafe drops below the undervoltage threshold VREF, MOSFET Q1 enters the cutoff state, the voltage detection signal nVsafe jumps from low level to high level, and the drive signal selection logic unit 2 sets the second latch signal V2 to high level to avoid false latching.
[0074] When the supply voltage Vsafe recovers to above the undervoltage threshold VREF, the MOSFET Q1 is turned on again, the voltage detection signal nVsafe returns to a low level, and the second latch signal V2 resumes to follow the first latch signal V1.
[0075] In an optional embodiment, the voltage detection logic unit 1 further includes:
[0076] The third resistor R3 has its first end connected to the gate of MOSFET Q1 and its second end connected to the source of MOSFET Q1.
[0077] The first capacitor C1 has its first end connected to the gate of the MOSFET Q1, and its second end connected to the source of the MOSFET Q1.
[0078] Specifically, the third resistor R3 is used to form a voltage divider with the first resistor R1, and the first capacitor C1 is used to filter out gate noise.
[0079] In one alternative embodiment, such as Figure 5 As shown, the voltage detection logic unit 1 includes a comparator U1. The first input terminal of the comparator U1 is connected to the power supply voltage output terminal to receive the power supply voltage Vsafe. The second input terminal of the comparator U1 is used to connect the undervoltage threshold VREF. The output terminal of the comparator U1 is used to output the voltage detection signal nVsafe.
[0080] When the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, the output of comparator U1 is used to output a low-level voltage detection signal nVsafe; when the supply voltage Vsafe is lower than the undervoltage threshold VREF, the output of comparator U1 is used to output a high-level voltage detection signal nVsafe.
[0081] Specifically, the positive input of comparator U1 is connected to the supply voltage Vsafe, and the negative input is connected to a preset undervoltage threshold VREF. When the supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, comparator U1 outputs a low-level voltage detection signal nVsafe, indicating that the power supply is normal.
[0082] When the supply voltage Vsafe is lower than the undervoltage threshold VREF, the comparator U1 outputs a high-level voltage detection signal nVsafe, and the drive signal selection logic section 2 sets the second latch signal V2 to a high level to avoid false latching.
[0083] When the supply voltage Vsafe recovers to above the undervoltage threshold VREF, the voltage detection signal nVsafe output by comparator U1 returns to a low level, and the second latch signal V resumes to follow the first latch signal V1.
[0084] In an optional embodiment, the voltage detection logic unit 1 further includes a filtering unit 5. Taking the second capacitor C2 as an example, the first end of the second capacitor C2 is connected to the second input terminal of the comparator U1, the second end of the second capacitor C2 is grounded, and the second input terminal of the comparator U1 is a positive input terminal connected to the first power supply voltage output terminal.
[0085] Specifically, comparator U1 is powered by the first power supply voltage VC1 provided by the first power supply voltage output terminal, and the second capacitor C2 is used to filter out noise from the power supply terminal.
[0086] In one optional embodiment, the signal selection logic unit 2 includes:
[0087] The first diode D1, the positive terminal of the first diode D1 is connected to the voltage detection logic section 1, and is used to receive the voltage detection signal nVsafe. The negative terminal of the first diode D1 is connected to the fourth resistor R4 and is used to output the second latch signal V2.
[0088] The positive terminal of the second diode D2 is connected to the latching circuit to receive the first latching signal V1, and the negative terminal of the second diode D2 is connected to the negative terminal of the first diode D1.
[0089] Specifically, this application uses a diode OR gate structure to construct the signal selection logic unit 2. When the power supply is normal, that is, when the power supply voltage Vsafe is higher than or equal to the undervoltage threshold VREF, the voltage detection signal nVsafe is low level, the first latch signal V1 is transmitted to the output terminal of the signal selection logic unit 2 through the second diode D2, and the second latch signal V2 is equal to the first latch signal V1.
[0090] When the supply voltage Vsafe is lower than the undervoltage threshold VREF, the voltage detection signal nVsafe is high. The voltage detection signal nVsafe is transmitted to the output of the signal selection logic unit 2 through the first diode D1. Regardless of whether the first latch signal V1 is low or high, the second latch signal V2 will always remain high to prevent false latching.
[0091] In a preferred embodiment, a sampling unit 3 is further included. The sampling unit 3 of this application includes:
[0092] The fifth resistor R5 has its first end connected to the output of the signal selection logic section 2 to receive the second latch signal V2, and its second end is used to output the sampling signal V3.
[0093] The third capacitor C3 has its first terminal connected to the second terminal of the fifth resistor R5, and its second terminal grounded.
[0094] Specifically, in this application, a sampling unit is constructed using an RC structure to smoothly sample the second latched signal V2 to obtain a sampled signal V3. The obtained sampled signal V3 is used for monitoring and reference of subsequent external devices.
[0095] The above provides a detailed description of a power-loss error-prevention latching circuit provided by this application. Specific examples have been used to illustrate the principle and implementation of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A circuit for preventing accidental latching due to power failure, characterized in that, include: The voltage detection logic unit (1) is used to receive the supply voltage (Vsafe) and output a voltage detection signal (nVsafe) based on the comparison result between the supply voltage (Vsafe) and the undervoltage threshold (VREF); The signal selection logic unit (2) receives the voltage detection signal (nVsafe) at one input terminal and the first latch signal (V1) at the other input terminal. The signal selection logic unit (2) is used to output a second latch signal (V2) based on the first latch signal (V1) and the voltage detection signal (nVsafe). Specifically, when the supply voltage (Vsafe) is lower than the undervoltage threshold (VREF), the second latch signal (V2) is high; when the supply voltage (Vsafe) is higher than or equal to the undervoltage threshold (VREF), the second latch signal (V2) follows the first latch signal (V1).
2. The anti-power-loss latching circuit according to claim 1, characterized in that, The voltage detection logic unit (1) includes a switch element, which is used to connect to the power supply voltage (Vsafe) and controllably output the voltage detection signal (nVsafe) according to the power supply voltage (Vsafe); When the supply voltage (Vsafe) is higher than or equal to the undervoltage threshold (VREF), the switch is turned on and outputs a low-level voltage detection signal (nVsafe); when the supply voltage (Vsafe) is lower than the undervoltage threshold (VREF), the switch is turned off and outputs a high-level voltage detection signal (nVsafe).
3. The anti-power-loss latching circuit according to claim 2, characterized in that, The switching device is one of a MOSFET, a transistor, or an IGBT.
4. The anti-power-loss latching circuit according to claim 1, characterized in that, The voltage detection logic unit (1) includes a comparator (U1), the first input terminal of the comparator (U1) is used to receive the supply voltage (Vsafe), the second input terminal of the comparator (U1) is used to connect the undervoltage threshold (VREF), and the output terminal of the comparator (U1) is used to output the voltage detection signal (nVsafe). When the supply voltage (Vsafe) is higher than or equal to the undervoltage threshold (VREF), the output of the comparator (U1) is used to output a low-level voltage detection signal (nVsafe); when the supply voltage (Vsafe) is lower than the undervoltage threshold (VREF), the output of the comparator (U1) is used to output a high-level voltage detection signal (nVsafe).
5. The anti-power-loss latching circuit according to claim 4, characterized in that, The voltage detection logic unit (1) further includes a filtering unit (5), the first end of which is connected to the second input terminal of the comparator (U1), and the second end of which is grounded.
6. The anti-power-loss latching circuit according to claim 1, characterized in that, The signal selection logic unit (2) includes: The first diode (D1) is connected to the voltage detection logic unit (1) to receive the voltage detection signal (nVsafe). The negative terminal of the first diode (D1) is connected to the fourth resistor. The first diode (D1) is used to output the second latch signal (V2). The second diode (D2) has its anode connected to the latching circuit to receive the first latching signal (V1), and its cathode connected to the cathode of the first diode (D1).
7. The anti-power-loss latching circuit according to claim 1, characterized in that, It also includes a sampling unit (3), the first end of which is connected to the output of the signal selection logic unit (2) for receiving the second latch signal (V2), and the output of the sampling unit (3) for outputting a sampling signal (V3) according to the second latch signal (V2).
8. The anti-power-loss latching circuit according to claim 1, characterized in that, The latching circuit includes: The first AND gate chip (U2) has its first input terminal connected to the sixth resistor (R6) for receiving the clear latch signal (RST) through the sixth resistor (R6). The second input terminal of the first AND gate chip (U2) is used to receive the inverted signal (nV1) of the first latch signal. The power supply terminal of the first AND gate chip (U2) is used to receive the supply voltage (Vsafe). The first AND gate chip (U2) is used to output the first logic signal. The second AND gate chip (U3) has a first input terminal for receiving the first latch signal (V1), a second input terminal for receiving the overvoltage fault signal (FAULT), and an output second logic signal. An inverter (U4) is provided, wherein the first input terminal of the inverter (U4) is connected to the output terminal of the first AND gate chip (U2), and the first output terminal of the inverter (U4) is used to output the first latch signal (V1) which is opposite to the first logic signal; the second input terminal of the inverter (U4) is connected to the output terminal of the second AND gate chip (U3), and the second output terminal of the inverter (U4) is used to output the inverted signal of the first latch signal (V1) which is opposite to the second logic signal.
9. The anti-power-loss latching circuit according to claim 8, characterized in that, The latching circuit also includes: The seventh resistor (R7) has its first end connected to the power supply voltage (Vsafe), and its second end connected to the first input terminal of the first AND gate chip (U2). The fourth capacitor (C4) has its first terminal connected to the first input terminal of the first AND gate chip (U2), and its second terminal grounded. The fifth capacitor (C5) has its first terminal connected to the power supply terminal of the first AND gate chip (U2), and its second terminal grounded. The sixth capacitor (C6) has its first terminal connected to the power supply terminal of the inverter (U4) and its second terminal grounded. The power supply terminal of the inverter (U4) is used to receive the supply voltage (Vsafe).
10. The anti-power-loss latching circuit according to claim 1, characterized in that, The latching circuit also includes a step-down unit (4), the input terminal of which is used to connect to the second power supply voltage (VC2), and the output terminal of which is used to output the power supply voltage (Vsafe).