A buffer driving circuit, combinational logic circuit and integrated circuit

Abstract

The application provides a buffer driving circuit, a combination logic circuit and an integrated circuit, and is applied to the technical field of integrated circuits.The buffer driving circuit comprises a pull-up circuit, a pull-down circuit and a driving circuit.The connection point of the pull-up circuit and the pull-down circuit receives a low-level input signal or a high-level input signal.The pull-up circuit outputs a pull-up signal in response to the high-level input signal.The pull-down circuit outputs a pull-down signal in response to the low-level input signal.The driving circuit outputs a first driving level in response to the pull-up signal, or outputs a second driving level in response to the pull-down signal.The pull-up circuit in the circuit comprises a first capacitive adjustment circuit with adjustable capacitance value.The pull-down circuit comprises a second capacitive adjustment circuit with adjustable capacitance value.The capacitance values of the first capacitive adjustment circuit and the second capacitive adjustment circuit can be adjusted according to the timing requirements of the integrated circuit, so as to adjust the delay duration of the driving signal output by the buffer driving circuit, and meet the requirements for the delay duration in different scenarios.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a buffer driver circuit, a combinational logic circuit, and an integrated circuit. Background Technology

[0002] As integrated circuits become increasingly larger, the length of the interconnects between different logic units also increases. This leads to the interconnect delay accounting for a larger proportion of the overall circuit delay, even becoming a key factor limiting circuit performance. To meet the timing requirements of integrated circuits, when signals need to drive large loads, the signal driving capability can be improved by connecting buffer drivers in series in the interconnects, thus adjusting the timing characteristics of the timing path and meeting the timing requirements.

[0003] In practical applications, integrated circuits consist of numerous logic units, and the lengths of the connection lines between these logic units vary, resulting in different timing adjustment requirements. Existing technologies simply achieve timing adjustment by connecting different numbers of buffer drivers in series. This not only results in unsatisfactory timing adjustment but also occupies a large amount of layout space in the integrated circuit, increasing the difficulty of integrated circuit design and potentially even increasing the overall cost of the integrated circuit. Utility Model Content

[0004] In view of this, this application aims to provide a buffer drive circuit, combinational logic circuit, and integrated circuit to solve the problems of poor timing adjustment effect, increased design difficulty due to buffer drive circuit, and increased overall cost of integrated circuit in the prior art.

[0005] In a first aspect, this application provides a buffer drive circuit, comprising: a pull-up circuit, a pull-down circuit, and a drive circuit, wherein, The pull-up input terminal of the pull-up circuit is connected to the pull-down input terminal of the pull-down circuit, and the resulting connection point serves as the signal input terminal of the buffer drive circuit. The signal input terminal is used to receive low-level input signals or high-level input signals. The pull-up output terminal of the pull-up circuit and the pull-down output terminal of the pull-down circuit are respectively connected to the driving circuit; The pull-up circuit outputs a pull-up signal in response to the high-level input signal; The pull-down circuit outputs a pull-down signal in response to the low-level input signal; The driving circuit outputs a first driving level in response to the pull-up signal, or outputs a second driving level in response to the pull-down signal; The pull-up circuit includes a first capacitive adjustment circuit with an adjustable capacitance value, the capacitance value of which is related to the duration required for the pull-up circuit to output the pull-up signal. The pull-down circuit includes a second capacitive adjustment circuit with an adjustable capacitance value, the capacitance value of which is related to the duration required for the pull-down circuit to output the pull-down signal.

[0006] In one alternative implementation, the pull-up circuit charges the first capacitive regulation circuit in response to the low-level input signal. The pull-down circuit charges the second capacitive adjustment circuit in response to the high-level input signal.

[0007] In one optional embodiment, the first capacitive adjustment circuit and the second capacitive adjustment circuit are capacitive adjustment circuits with identical structures, and the capacitive adjustment circuit includes at least one adjustable capacitor.

[0008] In one optional embodiment, the capacitive adjustment circuit includes at least two adjustable capacitors, wherein, The adjustable capacitors are connected in parallel to form a parallel branch; One end of the parallel branch serves as the first terminal of the capacitive regulation circuit, and the other end of the parallel branch serves as the second terminal of the capacitive regulation circuit.

[0009] In one optional embodiment, the pull-up circuit further includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor, wherein, The source of the first PMOS transistor is used to receive the operating voltage of the buffer drive circuit. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor and the first terminal of the first capacitive adjustment circuit. The drain of the second PMOS transistor is grounded. The second terminal of the first capacitive adjustment circuit is connected to the source of the first NMOS transistor and the drain of the second NMOS transistor, respectively, and the source of the second NMOS transistor is grounded. The gate of the second PMOS transistor serves as the pull-up output terminal of the pull-up circuit, and is connected to the source of the first NMOS transistor, the gate of the second NMOS transistor, and the drain of the third PMOS transistor, respectively. The source of the third PMOS transistor is used to receive the operating voltage. The gates of the first PMOS transistor, the first NMOS transistor, and the third PMOS transistor are connected together, and the resulting connection point serves as the pull-up input terminal of the pull-up circuit.

[0010] In one optional embodiment, the pull-down circuit further includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor, wherein, The gates of the third NMOS transistor, the fifth NMOS transistor, and the fifth PMOS transistor are connected, and the resulting connection point serves as the pull-down input terminal of the pull-down circuit. The drain of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, the gate of the fourth PMOS transistor, and the drain of the fifth PMOS transistor, respectively, and the source of the third NMOS transistor is grounded. The drain of the fourth NMOS transistor is used to receive the operating voltage of the buffer drive circuit. The source of the fourth NMOS transistor is connected to the second terminal of the second capacitive adjustment circuit and the drain of the fifth NMOS transistor. The gate of the fourth NMOS transistor also serves as the pull-down output terminal of the pull-down circuit. The source of the fifth NMOS transistor is grounded; The source of the fourth PMOS transistor is used to receive the operating voltage, and the drain of the fourth PMOS transistor is connected to the first terminal of the second capacitive adjustment circuit and the source of the fifth PMOS transistor, respectively.

[0011] In one optional embodiment, the driving circuit includes: a sixth PMOS transistor and a sixth NMOS transistor, wherein, The source of the sixth PMOS transistor is used to receive the operating voltage of the buffer drive circuit, the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor, and the gate of the sixth PMOS transistor serves as the first input terminal of the drive circuit. The source of the sixth NMOS transistor is grounded, and the gate of the sixth NMOS transistor serves as the second input terminal of the driving circuit. The connection point between the sixth PMOS transistor and the sixth NMOS transistor serves as the output terminal of the driving circuit.

[0012] Secondly, this application provides a combinational logic circuit, including: an input circuit and a buffer drive circuit as described in any embodiment of the first aspect of this application, wherein... The input circuit is connected to the buffer drive circuit; The input circuit is used to perform preset processing on the input signal and then output it to the buffer drive circuit.

[0013] In one alternative implementation, the input circuit includes: an arithmetic operation circuit, a logic operation circuit, or a timing circuit.

[0014] Thirdly, this application provides an integrated circuit including at least one buffer drive circuit as described in any embodiment of the first aspect of this application.

[0015] Based on the above, the buffer drive circuit provided in this application includes a pull-up circuit, a pull-down circuit, and a drive circuit. The connection point between the pull-up circuit and the pull-down circuit serves as the signal input terminal of the buffer drive circuit, receiving a low-level input signal or a high-level input signal. The pull-up circuit and the pull-down circuit are respectively connected to the drive circuit. The pull-up circuit outputs a pull-up signal in response to a high-level input signal, and the pull-down circuit outputs a pull-down signal in response to a low-level input signal. The drive circuit outputs a first drive level in response to the pull-up signal, or outputs a second drive level in response to the pull-down signal. In the buffer drive circuit provided in this application, the pull-up circuit includes a first capacitive adjustment circuit with an adjustable capacitance value, and the capacitance value of the first capacitive adjustment circuit is related to the output voltage of the pull-up circuit. The pull-down circuit includes a second capacitive adjustment circuit with an adjustable capacitance value. The capacitance value of the second capacitive adjustment circuit is related to the duration required for the pull-down signal output by the pull-down circuit. With this configuration, the capacitance values ​​of the first and second capacitive adjustment circuits can be adjusted according to the timing requirements of the integrated circuit, thereby adjusting the duration required for the pull-up signal output by the pull-up circuit and the duration required for the pull-down signal output by the pull-down circuit. This adjusts the delay duration of the drive signal output by the buffer drive circuit, providing a more flexible timing adjustment scheme to meet the delay duration requirements in different scenarios. Furthermore, it can effectively reduce the number of buffer drive circuits, helping to reduce the design difficulty and overall cost of integrated circuits. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a structural block diagram of a buffer drive circuit provided in an embodiment of the present invention.

[0018] Figure 2 This is a circuit topology diagram of a buffer drive circuit provided in an embodiment of this utility model.

[0019] Figure 3 This is a circuit topology diagram of another buffer drive circuit provided in an embodiment of this utility model.

[0020] Figure 4 This is a structural block diagram of a combinational logic circuit provided in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The efficient operation of core computing circuits in high-speed digital signal processing, artificial intelligence, and high-performance computing relies heavily on robust hardware support. Large-scale computing power requires a large number of computing chips, leading to a continuous expansion in the scale of integrated circuits. The length of the interconnects between different logic units within integrated circuits is also constantly increasing, causing the latency of these interconnects to account for a growing proportion of the overall circuit latency, even becoming a key factor limiting circuit performance. To meet the timing requirements of integrated circuits, when signals need to drive large loads, the signal driving capability can be improved by connecting buffer drivers in series in the interconnects, thus adjusting the timing characteristics of the timing path and meeting the timing requirements. However, existing technologies that simply connect different numbers of buffer drivers in series to achieve timing adjustment not only produce unsatisfactory timing adjustment results but also occupy a significant amount of layout space in the integrated circuit, increasing the complexity of integrated circuit design and potentially even increasing the overall cost.

[0023] To address the aforementioned issues, this application provides a buffer drive circuit, including a first capacitive adjustment circuit and a second capacitive adjustment circuit with adjustable capacitance values. The capacitance values ​​of the first and second capacitive adjustment circuits can be adjusted according to the timing requirements of the integrated circuit, thereby adjusting the delay duration of the output drive signal of the buffer drive circuit. This provides a more flexible timing adjustment scheme, meeting the delay duration requirements in different scenarios. Furthermore, it effectively reduces the number of buffer drive circuits required, helping to reduce the design difficulty and overall cost of the integrated circuit.

[0024] Based on the above, see Figure 1 The buffer drive circuit provided in this application embodiment includes: a pull-up circuit 10, a pull-down circuit 20, and a drive circuit 30.

[0025] Combination Figure 1 As shown, the pull-up circuit 10 has a pull-up input terminal and a pull-up output terminal, and the pull-down circuit 20 has a pull-down input terminal and a pull-down output terminal. The pull-up input terminal of the pull-up circuit 10 is connected to the pull-down input terminal of the pull-down circuit 20, and the resulting connection point serves as the signal input terminal of the buffer drive circuit, receiving low-level input signals or high-level input signals. In practical applications, the low-level input signals and high-level input signals are provided by the pre-stage circuit of the buffer drive circuit. This application does not limit the specific source of the low-level input signals and high-level input signals.

[0026] The driving circuit 30 has a first input terminal, a second input terminal, and a driving output terminal. The pull-up output terminal of the pull-up circuit 10 and the pull-down output terminal of the pull-down circuit 20 are respectively connected to the driving circuit 30. Specifically, the pull-up output terminal is connected to the first input terminal of the driving circuit 30, and the pull-down output terminal is connected to the second input terminal of the driving circuit 30. The driving output terminal of the driving circuit 30 serves as the output terminal of the buffer driving circuit and is connected to the subsequent circuit.

[0027] When the input signal is a high-level input signal, the pull-up circuit 10 outputs a pull-up signal in response to the high-level input signal. When the input signal is a low-level input signal, the pull-down circuit 20 outputs a pull-down signal in response to the low-level input signal.

[0028] Referring to the foregoing content and Figure 1 As can be seen from the connections between the circuits shown, the drive circuit 30 can only receive the output signal of either the pull-up circuit 10 or the pull-down circuit 20 at any given time. Based on this, the drive circuit 30 outputs a first drive level in response to the pull-up signal provided by the pull-up circuit 10, or outputs a second drive level in response to the pull-down signal provided by the pull-down circuit 20. It is understood that both the first and second drive levels are used to drive the subsequent circuits connected to the buffer drive circuit. The specific driving method is related to the specific function of the subsequent circuit, and will not be detailed here.

[0029] More importantly, in the buffer drive circuit provided in this embodiment, the pull-up circuit 10 is provided with a first capacitive adjustment circuit whose capacitance value is adjustable. Figure 1 (Not shown in the figure), the capacitance value of the first capacitive adjustment circuit is related to the duration required for the pull-up circuit 10 to output the pull-up signal, that is, it is related to the duration required to establish the pull-up signal. By adjusting the capacitance value of the first capacitive adjustment circuit, the duration of the pull-up signal output by the pull-up circuit 10 can be adjusted, thereby adjusting the duration required for the drive circuit 30 to output the first drive level. Correspondingly, the pull-down circuit 20 is provided with a second capacitive adjustment circuit with an adjustable capacitance value ( Figure 1 (Not shown in the diagram), the capacitance value of the second capacitive adjustment circuit is related to the duration required for the pull-down circuit 20 to output the pull-down signal, that is, the duration required to establish the pull-down signal. By adjusting the capacitance value of the second capacitive adjustment circuit, the duration of the pull-down signal output by the pull-down circuit 20 can also be adjusted, thereby adjusting the duration required for the drive circuit 30 to output the second drive level. It can be understood that adjusting the duration required for the drive circuit 30 to output the drive level is equivalent to adjusting the interval between the buffer drive circuit receiving the input signal and outputting the drive level. This interval is the delay time of the buffer drive circuit when transmitting the signal. Therefore, by adjusting the capacitance values ​​of the first and second capacitive adjustment circuits, the delay time of the buffer drive circuit can be adjusted.

[0030] Furthermore, in one optional embodiment, the pull-up circuit 10 charges the first capacitive adjustment circuit in response to a low-level input signal, preparing for the pull-up circuit 10 to respond to a high-level input signal and output a first drive level. Correspondingly, the pull-down circuit 20 charges the second capacitive adjustment circuit in response to a high-level input signal, preparing for the pull-down circuit 20 to respond to a low-level input signal and output a second drive level. The specific configurations of the pull-up circuit 10 and the pull-down circuit 20 will be detailed later and will not be described here.

[0031] In summary, the buffer drive circuit provided in this application includes a pull-up circuit comprising a first capacitive adjustment circuit with adjustable capacitance, the capacitance of which is related to the duration required for the pull-up circuit to output the pull-up signal. The pull-down circuit includes a second capacitive adjustment circuit with adjustable capacitance, the capacitance of which is related to the duration required for the pull-down circuit to output the pull-down signal. This configuration allows for adjustment of the capacitance values ​​of the first and second capacitive adjustment circuits according to the timing requirements of the integrated circuit, thereby adjusting the duration required for the pull-up circuit to output the pull-up signal and the duration required for the pull-down circuit to output the pull-down signal. This, in turn, adjusts the delay duration of the drive signal output by the buffer drive circuit, providing a more flexible timing adjustment scheme to meet the delay duration requirements in different scenarios. Furthermore, it effectively reduces the number of buffer drive circuits required, helping to reduce the design difficulty and overall cost of the integrated circuit.

[0032] Based on the above core idea, this application further provides another buffer driving circuit, the circuit topology of which can be found in [reference needed]. Figure 2 As shown.

[0033] Combination Figure 2 As shown, the pull-up circuit 10 includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1, a second NMOS transistor N2, and a first capacitive adjustment circuit 110.

[0034] The source of the first PMOS transistor P1 is used to receive the operating voltage V of the buffer drive circuit. DD The drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2 and the first terminal of the first capacitive adjustment circuit 110, respectively. The drain of the second PMOS transistor P2 is grounded (i.e., V). SS The second terminal of the first capacitive adjustment circuit 110 is connected to the source of the first NMOS transistor N1 and the drain of the second NMOS transistor N2, respectively. The source of the second NMOS transistor N2 is grounded (i.e., V). SSThe gate of the second PMOS transistor P2 serves as the pull-up output of the pull-up circuit 10, connected to the first input of the subsequent drive circuit 30, and is also connected to the source of the first NMOS transistor N1, the gate of the second NMOS transistor N2, and the drain of the third PMOS transistor P3. The source of the third PMOS transistor P3 is used to receive the operating voltage V. DD The gates of the first PMOS transistor P1, the first NMOS transistor N1, and the third PMOS transistor P3 are connected, and the resulting connection point serves as the pull-up input terminal of the pull-up circuit 10, used to receive low-level input signals or high-level input signals.

[0035] Accordingly, the pull-down circuit 20 includes: a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a second capacitive adjustment circuit 210.

[0036] The gates of the third NMOS transistor N3, the fifth NMOS transistor N5, and the fifth PMOS transistor P5 are connected together, and the resulting connection point serves as the pull-down input of the pull-down circuit 20, used to receive low-level or high-level input signals. The drain of the third NMOS transistor N3 is connected to the gates of the fourth NMOS transistor N4, the fourth PMOS transistor P4, and the fifth PMOS transistor P5, respectively. The source of the third NMOS transistor N3 is grounded (i.e., V). SS The drain of the fourth NMOS transistor N4 is used to receive the operating voltage V of the buffer drive circuit. DD The source of the fourth NMOS transistor N4 is connected to the second terminal of the second capacitive adjustment circuit 210 and the drain of the fifth NMOS transistor N5, respectively. The gate of the fourth NMOS transistor N4 also serves as the pull-down output terminal of the pull-down circuit 20, and is connected to the second input terminal of the subsequent drive circuit 30. The source of the fifth NMOS transistor N5 is grounded (i.e., V). SS The source of the fourth PMOS transistor P4 is used to receive the operating voltage V. DD The drain of the fourth PMOS transistor P4 is connected to the first terminal of the second capacitive adjustment circuit 210 and the source of the fifth PMOS transistor P5, respectively.

[0037] Furthermore, the driving circuit 30 includes a sixth PMOS transistor P6 and a sixth NMOS transistor N6, combined with Figure 2 As shown, the source of the sixth PMOS transistor P6 is used to receive the operating voltage V of the buffer drive circuit. DD The drain of the sixth PMOS transistor P6 is connected to the drain of the sixth NMOS transistor N6, and the gate of the sixth PMOS transistor P6 serves as the first input terminal of the drive circuit 30; the source of the sixth NMOS transistor N6 is grounded (i.e., V). SSThe gate of the sixth NMOS transistor N6 serves as the second input terminal of the driving circuit 30; the connection point between the sixth PMOS transistor P6 and the sixth NMOS transistor N6 serves as the output terminal Vo of the driving circuit 30, which is used to connect to the subsequent circuit.

[0038] The following is an introduction Figure 2 The working process of the buffer drive circuit shown is as follows: 1) The input signal is a high-level input signal: Pull-up circuit 10 is in the bootstrap phase, and pull-down circuit 20 is in the charging phase.

[0039] Combination Figure 2 As shown, when the input signal is a high-level input signal, the fifth NMOS transistor N5 and the third NMOS transistor N3 are turned on, and the fifth PMOS transistor P5 is turned off. Since the third NMOS transistor N3 is turned on, the gates of the sixth NMOS transistor N6, the fourth NMOS transistor N4, and the fourth PMOS transistor P4 are at a high level. The sixth NMOS transistor N6 and the fourth NMOS transistor N4 are turned off, and the fourth PMOS transistor P4 is turned on. Both the fourth PMOS transistor P4 and the fifth NMOS transistor N5 are turned on. The second capacitive adjustment circuit 210 is connected to the operating voltage VDD and ground VDD. SS A closed loop is formed, the second capacitive regulation circuit 210 is charged, and the pull-down circuit 20 is in the charging stage.

[0040] Furthermore, when the input signal is a high-level input signal, the first PMOS transistor P1 and the third PMOS transistor P3 are turned off, and the first NMOS transistor N1 is turned on. The second terminal of the first capacitive adjustment circuit 110 transmits data through the first NMOS transistor N1 to the gate of the second PMOS transistor P2 and the gate of the sixth PMOS transistor P6 in the drive circuit 20. Both the second PMOS transistor P2 and the sixth PMOS transistor P6 are turned on, and the ground point (i.e., V) is connected. SS The ground potential of the first capacitive adjustment circuit 110 is transmitted through the second PMOS transistor P2 to the first terminal of the first capacitive adjustment circuit 110, and the potential of the second terminal of the first capacitive adjustment circuit 110 is reduced to -V. DD The voltage is transmitted through the first NMOS transistor N1 to the gate of the sixth PMOS transistor P6, which provides a negative voltage (i.e., a pull-up signal) to the drive circuit 30, thus completing the bootstrap phase of the pull-up circuit 10.

[0041] During the bootstrap phase, to prevent the substrates of the relevant power devices from being forward biased by the source and drain due to the low level, the substrates of the second NMOS transistor N2 and the first NMOS transistor N1 in the voltage propagation path need to be connected to a low potential. Therefore, the substrate of the second NMOS transistor N2 is connected to the drain, and the substrate of the first NMOS transistor N1 is connected to the source.

[0042] The conduction states of each power device in the buffer drive circuit when the input signal is a high-level input signal can be seen in Table 1: Table 1 In this context, ON indicates that the corresponding power device is turned on, and OFF indicates that the corresponding power device is turned off.

[0043] 2) The input signal is a low-level input signal: Pull-up circuit 10 is in the charging phase, and pull-down circuit 20 is in the bootstrap phase.

[0044] Combination Figure 2 As shown, when the input signal is a low-level input signal, the first PMOS transistor P1 and the third PMOS transistor P3 in the pull-up circuit 10 are turned on, and the first NMOS transistor N1 is turned off. Since the third PMOS transistor P3 is turned on, the gates of the sixth PMOS transistor P6, the second PMOS transistor P2, and the second NMOS transistor N2 are at a high level. The sixth PMOS transistor P6 and the second PMOS transistor P2 are turned off, and the second NMOS transistor N2 is turned on. Both the second NMOS transistor N2 and the first PMOS transistor P1 are turned on, and the first capacitive adjustment circuit 110 is charged to prepare for the bootstrap stage.

[0045] Furthermore, when the input signal is a low-level input signal, the fifth NMOS transistor N5 and the third NMOS transistor N3 in the pull-down circuit 20 are turned off, and the fifth PMOS transistor P5 is turned on. The high voltage at the first terminal of the second capacitive adjustment circuit 210 is transmitted through the fifth PMOS transistor P5 to the gate of the fourth NMOS transistor N4 and the second input terminal of the drive circuit 30, i.e., the gate of the sixth NMOS transistor N6. Both the fourth NMOS transistor N4 and the sixth NMOS transistor N6 are turned on, and the operating voltage V DD The voltage at the first terminal of the second capacitive regulation circuit 210 is raised to 2V by the fourth NMOS transistor N4, which reaches the second terminal of the second capacitive regulation circuit 210. DD The signal is transmitted to the gate of the sixth NMOS transistor N6 through the fifth PMOS transistor P5, thus outputting a pull-down signal, completing the bootstrap phase of the pull-down circuit 20.

[0046] During the bootstrap phase, to prevent the substrate and source / drain from being forward biased due to a high level, the substrates of the PMOS transistors in the voltage propagation path, namely the fourth PMOS transistor P4 and the fifth PMOS transistor P5, need to be connected to a high potential. Therefore, the substrate of the fourth PMOS transistor P4 is connected to the drain, and the substrate of the fifth PMOS transistor P5 is connected to the source.

[0047] The conduction states of each power device in the buffer drive circuit when the input signal is a low-level input signal can be seen in Table 2: Table 2 In this context, ON indicates that the corresponding power device is turned on, and OFF indicates that the corresponding power device is turned off.

[0048] based on Figure 2 The circuit topology shown allows adjustment of the capacitance values ​​of the first and second capacitive adjustment circuits, thereby changing the duration of establishing pull-up and pull-down signals. This adjusts the delay time of the buffer drive circuit when transmitting input signals, meeting application requirements in different scenarios. Furthermore, since the delay time can be adjusted using a single buffer drive circuit, the number of buffer drive circuits can be reduced in scenarios requiring longer delay time adjustments, helping to lower the overall cost of the integrated circuit.

[0049] Furthermore, based on the foregoing embodiments, this application provides another buffer drive circuit, which offers optional implementations of a first capacitive adjustment circuit and a second capacitive adjustment circuit.

[0050] See Figure 3 As shown, the first capacitive adjustment circuit 110 and the second capacitive adjustment circuit 210 are capacitive adjustment circuits with identical structures, each including at least one adjustable capacitor (shown as adjustable capacitors C1-Cn in the figure, where n≥1). As an optional implementation, when the capacitive adjustment circuit includes at least two adjustable capacitors, each adjustable capacitor is as follows... Figure 3 The parallel connection shown creates a corresponding parallel branch. One end of this parallel branch serves as the first terminal of the capacitive adjustment circuit, and the other end serves as the second terminal. In practical applications, the number of adjustable capacitors can be set according to actual adjustment requirements, which will not be detailed here.

[0051] This application also provides a combinational logic circuit, see [link to relevant documentation] Figure 4 As shown, it includes input circuit 40 and buffer drive circuit provided in any of the foregoing embodiments (to... Figure 1 The illustrated embodiment is shown.

[0052] The input circuit 40 is connected to the input terminals of the pull-up circuit 10 and the pull-down circuit 20 in the buffer drive circuit, respectively. The input circuit 40 preprocesses the input signal and outputs it to the buffer drive circuit.

[0053] In practical applications, the input circuit 40 can be selected from various options. It can be an arithmetic operation circuit, such as an adder circuit, a multiplier circuit, a divider circuit, etc. It can also be a logic operation circuit, such as an AND gate circuit, an OR gate circuit, an AND-OR-NOT gate circuit, etc. It can also be a sequential circuit. Of course, it can also be other input circuits that can be used in conjunction with the buffer drive circuit. They will not be described in detail here. As long as they do not exceed the core idea of ​​this application, they also fall within the scope of protection of this application.

[0054] The aforementioned types of input circuits can be widely used in integrated circuits, especially in large-scale computing systems such as machine learning and artificial intelligence. Therefore, cascading input circuits can lead to large loads or long delays. Connecting the input circuit to a buffer drive circuit allows the input circuit to send its computational results to the buffer drive circuit. The buffer drive circuit can drive long lines and large loads, and by tuning the adjustable capacitors in the pull-up and pull-down circuits, the circuit's delay time can be controlled, thus making the system's timing controllable. This reduces the difficulty of delay tuning in large-scale computing circuits and enables precise control of delay time under heavy loads.

[0055] This application also provides an integrated circuit including at least one buffer drive circuit as provided in any of the foregoing embodiments.

[0056] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0057] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0058] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0059] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A buffer drive circuit, characterized by comprising: include: Pull-up circuit, pull-down circuit, and driver circuit, among which, The pull-up input terminal of the pull-up circuit is connected to the pull-down input terminal of the pull-down circuit, and the resulting connection point serves as the signal input terminal of the buffer drive circuit. The signal input terminal is used to receive low-level input signals or high-level input signals. The pull-up output terminal of the pull-up circuit and the pull-down output terminal of the pull-down circuit are respectively connected to the driving circuit; The pull-up circuit outputs a pull-up signal in response to the high-level input signal; The pull-down circuit outputs a pull-down signal in response to the low-level input signal; The driving circuit outputs a first driving level in response to the pull-up signal, or outputs a second driving level in response to the pull-down signal; The pull-up circuit includes a first capacitive adjustment circuit with an adjustable capacitance value, the capacitance value of which is related to the duration required for the pull-up circuit to output the pull-up signal. The pull-down circuit includes a second capacitive adjustment circuit with an adjustable capacitance value, the capacitance value of which is related to the duration required for the pull-down circuit to output the pull-down signal.

2. The buffer driving circuit according to claim 1, wherein The pull-up circuit responds to the low-level input signal and charges the first capacitive adjustment circuit. The pull-down circuit charges the second capacitive adjustment circuit in response to the high-level input signal.

3. The buffer drive circuit according to claim 1, characterized in that, The first capacitive adjustment circuit and the second capacitive adjustment circuit are capacitive adjustment circuits with the same structure, and the capacitive adjustment circuit includes at least one adjustable capacitor.

4. The buffer drive circuit according to claim 3, characterized in that, The capacitive adjustment circuit includes at least two adjustable capacitors, wherein, The adjustable capacitors are connected in parallel to form a parallel branch; One end of the parallel branch serves as the first terminal of the capacitive regulation circuit, and the other end of the parallel branch serves as the second terminal of the capacitive regulation circuit.

5. The buffer drive circuit according to claim 1, characterized in that, The pull-up circuit further includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor, wherein, The source of the first PMOS transistor is used to receive the operating voltage of the buffer drive circuit. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor and the first terminal of the first capacitive adjustment circuit. The drain of the second PMOS transistor is grounded. The second terminal of the first capacitive adjustment circuit is connected to the source of the first NMOS transistor and the drain of the second NMOS transistor, respectively, and the source of the second NMOS transistor is grounded. The gate of the second PMOS transistor serves as the pull-up output terminal of the pull-up circuit, and is connected to the source of the first NMOS transistor, the gate of the second NMOS transistor, and the drain of the third PMOS transistor, respectively. The source of the third PMOS transistor is used to receive the operating voltage. The gates of the first PMOS transistor, the first NMOS transistor, and the third PMOS transistor are connected together, and the resulting connection point serves as the pull-up input terminal of the pull-up circuit.

6. The buffer drive circuit according to claim 1, characterized in that, The pull-down circuit further includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor, wherein, The gates of the third NMOS transistor, the fifth NMOS transistor, and the fifth PMOS transistor are connected, and the resulting connection point serves as the pull-down input terminal of the pull-down circuit. The drain of the third NMOS transistor is connected to the gate of the fourth NMOS transistor, the gate of the fourth PMOS transistor, and the drain of the fifth PMOS transistor, respectively, and the source of the third NMOS transistor is grounded. The drain of the fourth NMOS transistor is used to receive the operating voltage of the buffer drive circuit. The source of the fourth NMOS transistor is connected to the second terminal of the second capacitive adjustment circuit and the drain of the fifth NMOS transistor. The gate of the fourth NMOS transistor also serves as the pull-down output terminal of the pull-down circuit. The source of the fifth NMOS transistor is grounded; The source of the fourth PMOS transistor is used to receive the operating voltage, and the drain of the fourth PMOS transistor is connected to the first terminal of the second capacitive adjustment circuit and the source of the fifth PMOS transistor, respectively.

7. The buffer drive circuit according to claim 1, characterized in that, The driving circuit includes a sixth PMOS transistor and a sixth NMOS transistor, wherein... The source of the sixth PMOS transistor is used to receive the operating voltage of the buffer drive circuit, the drain of the sixth PMOS transistor is connected to the drain of the sixth NMOS transistor, and the gate of the sixth PMOS transistor serves as the first input terminal of the drive circuit. The source of the sixth NMOS transistor is grounded, and the gate of the sixth NMOS transistor serves as the second input terminal of the driving circuit. The connection point between the sixth PMOS transistor and the sixth NMOS transistor serves as the output terminal of the driving circuit.

8. A combinational logic circuit, characterized in that, include: The input circuit and the buffer drive circuit as described in any one of claims 1 to 7, wherein, The input circuit is connected to the buffer drive circuit; The input circuit is used to perform preset processing on the input signal and then output it to the buffer drive circuit.

9. The combinational logic circuit according to claim 8, characterized in that, The input circuit includes: arithmetic operation circuit, logic operation circuit, or sequential circuit.

10. An integrated circuit, characterized in that, It includes at least one buffer drive circuit as described in any one of claims 1 to 7.

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