Communication system

Abstract

The application provides a communication system, which comprises a host computer, at least one slave computer connected with the host computer through a two-wire bus, the host computer sends a level carrier signal to the slave computer, the slave computer converts and processes the level carrier signal to obtain a first level signal, and enables a second analysis module in the slave computer based on the first level signal, the host computer sends a power line carrier signal to the slave computer, and the slave computer sends a response signal of the power line carrier signal to the host computer based on the enabled second analysis module, so that the host computer queries data of the slave computer. The application realizes high-speed data transmission under the premise of ensuring low power consumption through the cooperative work of the host computer and the slave computer.

Description

Technical Field

[0001] This application relates to the field of carrier communication technology, specifically to a communication system. Background Technology

[0002] Currently, there are two main implementation methods for two-bus communication technology: The first uses a traditional voltage / current loop communication mechanism, where downlink signals are transmitted via voltage levels (high and medium voltage), while uplink signals rely on the slave device generating a large instantaneous current on the bus to achieve data transmission. This method has a significant transmission rate bottleneck, reaching a maximum of only 19200bps, which is insufficient to meet the large data transmission requirements of modern industrial scenarios. Furthermore, the current loop communication method has stringent requirements for signal detection accuracy and is easily affected by changes in line impedance. The second method uses power line carrier communication technology. Although high-speed transmission of 1M-12Mbps can be achieved through Time Division Multiple Access (TDMA) or Carrier Sense Multiple Access with Collision Avoidance (CSMA / CA) modes, its modulation and demodulation processes consume significant power, failing to meet low-power requirements.

[0003] Traditional two-bus technology faces challenges in scenarios requiring long-distance, multi-node networking, such as fire alarms and building automation. These challenges include response delays due to low-speed transmission and excessive power consumption in carrier communication schemes. Particularly in systems requiring simultaneous device status queries and real-time data transmission, existing technologies struggle to achieve a balance between communication speed, node capacity, and power consumption control. Utility Model Content

[0004] This application provides a communication system that enables high-speed data transmission while ensuring low power consumption, effectively solving the technical problem that transmission rate and power consumption cannot be simultaneously achieved in traditional two-bus technology.

[0005] This application provides a communication system.

[0006] The communication system includes: a host and at least one slave device that is communicatively connected to the host via a dual bus;

[0007] The host is used to send a level carrier signal to the slave.

[0008] The slave device is used to convert the level carrier signal to obtain a first level signal, and enable the second parsing module in the slave device based on the first level signal;

[0009] The host is also used to send power line carrier signals to the slave.

[0010] The slave device is further configured to send a response signal of the power line carrier signal to the host device based on the enabled second parsing module, so that the host device can query the data of the slave device.

[0011] In summary, the communication system provided in this application achieves high-speed carrier communication through the collaborative work of the master and slave devices, combined with a parsing module and a serial port module. Simultaneously, it utilizes level signal conversion and address verification mechanisms to reduce power consumption, achieving high-speed data transmission while ensuring low power consumption. This effectively solves the technical challenge of the trade-off between transmission rate and power consumption in traditional two-bus technology. Specifically, the master device includes a first serial port module and a first parsing module, while the slave device includes a second serial port module and a second parsing module. The master device sends a level carrier signal to the slave device through the first serial port module. After the slave device parses the level signal to confirm address matching, it activates the second parsing module. The master device then sends a power line carrier signal through the first parsing module for data querying. The slave device replies with a power line carrier signal through the activated parsing module. This application achieves dual optimization of power consumption and speed in the two-bus communication system. The use of level signals during the address confirmation phase reduces unnecessary energy consumption, and the carrier communication activated by the slave device ensures data transmission efficiency. This dynamic power management mode enables the system to maintain low static power consumption while possessing the ability to initiate high-speed communication on demand, effectively solving the problem of the trade-off between speed and power consumption in traditional technologies. Attached Figure Description

[0012] The present application will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for explaining some embodiments of the present application. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0013] Figure 1 This is a schematic diagram of a communication system provided for an embodiment of this application.

[0014] Figure 2 This is yet another schematic diagram of a communication system provided for an embodiment of this application.

[0015] Figure 3 This is a schematic diagram illustrating an application scenario of the communication system provided in an embodiment of this application.

[0016] Figure 4 A schematic diagram of the structure of a DC power bus circuit provided for an embodiment of this application.

[0017] Figure 5 This is a schematic diagram of the receiving circuit module provided in an embodiment of this application.

[0018] Figure 6 A timing diagram provided for an embodiment of this application.

[0019] Figure 7 This is a schematic diagram illustrating another application scenario of the communication system provided in the embodiments of this application. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0021] In the description of this application, the terms "first," "second," and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms "multiple" and similar words indicate two or more unless otherwise expressly defined. Embodiments of this application can be combined with each other.

[0022] This application provides a communication system, which includes, but is not limited to, the following embodiments and combinations thereof.

[0023] In one embodiment, Figure 1 A schematic diagram of a communication system provided for an embodiment of this application; as shown Figure 1 As shown, the communication system 100 includes: a host 101 and at least one slave 102 that is communicatively connected to the host via a dual bus 103;

[0024] The host 101 is used to send level carrier signals to the slave.

[0025] Slave device 102 is used to convert and process the level carrier signal to obtain a first level signal, and enable the second parsing module in slave device 102 based on the first level signal.

[0026] The host 101 is also used to send power line carrier signals to the slave 102.

[0027] Slave 102 is also used to send a response signal of power line carrier signal to host based on the enabled second parsing module, so that host 101 can query data from slave.

[0028] Level carrier refers to a communication method that uses a DC power bus to generate two distinguishable voltage states. Specifically, this can be achieved by using a DC power bus circuit to generate a high-level carrier signal and a medium-level carrier signal. This feature enables low-power addressing during the device selection phase, avoiding the continuous operation of high-power modules.

[0029] Power line carrier (PLC) is a communication method that transmits high-frequency modulated signals over power lines. Specifically, it can be implemented using a PLC modem to generate signals in the 1MHz-12MHz frequency band. This feature provides a high-speed channel during data transmission, ensuring the rapid transmission of large amounts of data.

[0030] This application combines the advantages of two technologies. It introduces the high-speed advantage of carrier technology in the data transmission stage and optimizes energy efficiency through dynamic channel switching. Thus, this application effectively solves the challenge of balancing speed and power consumption in two-bus systems. This method is particularly suitable for industrial IoT scenarios that require both periodic data acquisition and bursty large-scale data transmission.

[0031] In one embodiment, such as Figure 1 As shown, the host 101 includes a first chip; the first chip includes a first parsing module and a first serial port module; the slave 102 includes a second chip; the second chip includes a second parsing module and a second serial port module.

[0032] The host 101 is used to generate a level carrier signal based on the selection frame sent by the first serial port module and send the level carrier signal to the slave 102.

[0033] Slave device 102 is used to receive level carrier signals; convert the level carrier signals to obtain a first level signal; parse the first level signal through the second serial port module to obtain a selection frame; determine whether the first address information in the selection frame is the same as its own second address information; if the first address information and the second address information are the same, enable the second parsing module.

[0034] The host 101 is also used to send data request frames for power line carrier signals based on the first parsing module.

[0035] Slave 102 is also used to receive data request frames based on the enabled second parsing module, generate data reply frames in response to power line carrier signals based on the data request frames, and send the data reply frames to the data reply frames via power line carrier signals, so that the master can complete the data query of the slave based on the data reply frames.

[0036] The parsing module can be a hardware unit with protocol parsing capabilities, specifically implemented using a dedicated integrated circuit, for processing the modulation and demodulation of power line carrier signals. The serial port module can be a communication interface that performs level signal conversion, responsible for the mutual conversion between level signals and digital signals. The two-wire bus can be a two-wire line that simultaneously carries power supply and data communication, specifically implemented using twisted-pair or coaxial cable, alternating between level signals and carrier signals through time-division multiplexing. For example, the parsing module could be a power line communication (PLC) parsing module.

[0037] Specifically, during the initial communication phase, the master unit converts the digital signal into high and medium level signals via a serial port module, which are then transmitted to all slave units via a two-wire bus. Upon receiving the level signals, the slave units revert to digital signals via the serial port module for address comparison. When a slave unit confirms an address match, it activates the parsing module, which is currently in sleep mode. The master unit then switches to carrier communication mode and sends a power line carrier signal containing a query command via the parsing module. The activated slave unit parses the carrier signal, generates an acknowledgment signal, and returns it to the master unit via carrier communication. This phased communication mechanism allows non-target slave units to keep their parsing modules in sleep mode most of the time, significantly reducing overall system power consumption.

[0038] As an example, a selection frame can be a selection frame, and a data request frame can be a request frame. Both the first and second chips can be System-on-Chips (SOC) chips, and both the first and second parsing modules can be called PLC parsing modules. Similarly, both the first and second serial port modules can be called serial port processing modules. For instance, if the PLC carrier parsing function of all slave devices is disabled, the master SOC sends a slave module selection frame through the serial port processing module's sending unit to generate a power level carrier. After receiving the level carrier signal, all slave RX receiving modules convert it into a high or low level recognized by the system and send it to the slave's serial port processing module. The slave SOC's serial port processing module receives the data, performs frame parsing, and checks if the slave address field in the slave module selection frame matches its own slave address field. If they match, the slave's PLC parsing module is enabled. Otherwise, the slave's PLC protocol module function is not enabled. The master PLC parsing module sends a PLC carrier data request frame to the bus. The slave device with the newly enabled PLC protocol module function receives the frame, performs protocol parsing, and sends a data reply frame to the bus. The host PLC parsing module will receive the data response frame and complete the data query for the slave device.

[0039] This application employs a collaborative mechanism that uses low-power level signals during the address confirmation phase and high-speed carrier signals during the data phase. While maintaining the low-power characteristics of traditional two-bus systems, it elevates the effective data transmission rate to the level of carrier communication. Simultaneously, non-target slave devices immediately enter a low-power state after address confirmation, avoiding the continuous power consumption problem of all nodes in PLC carrier communication. Thus, this application achieves dual optimization of power consumption and speed in the two-bus communication system. The use of level signals during the address confirmation phase reduces unnecessary power consumption, while carrier communication after the target device is activated ensures efficient data transmission. This dynamic power management mode enables the system to maintain low static power consumption while possessing the ability to initiate high-speed communication on demand, effectively solving the problem of the trade-off between speed and power consumption in traditional technologies, and providing a feasible technical solution for large-scale device networking.

[0040] In one embodiment, Figure 2 Another schematic diagram of a communication system provided for embodiments of this application; as shown Figure 2 As shown, the host 101 also includes a transmission processing module, a DC power bus circuit, and an AC-DC power supply circuit; the transmission processing module is connected to the DC power bus circuit and the first serial port module respectively; the AC-DC power supply circuit is connected to the DC power bus circuit; and the DC power bus circuit is connected to the two-wire bus.

[0041] An AC-DC power supply circuit is used to output a DC power signal.

[0042] The DC power bus circuit is used to receive the second-level signal from the transmit pin provided by the transmit processing module based on the selection frame; and to generate a level carrier signal based on the DC power signal and the second-level signal.

[0043] The transmission processing module can be a circuit that converts the digital signal output from the first serial port module into a level signal. Specifically, it can be implemented using logic gate circuits or level conversion chips. Its function is to convert the logic signal corresponding to the selection frame into a high-level or low-level signal that can drive the DC power bus circuit. The DC power bus circuit can be a circuit that superimposes the DC power signal with the level signal of the transmission pin to generate a carrier signal. Specifically, it can be implemented using a structure where switching devices are connected in parallel with the power path, for example, by controlling the on / off state of the power path using transistors or MOSFETs. Its function is to combine the static DC power supply with the dynamic level signal to form carrier signals with different amplitudes. The AC-DC power supply circuit can be a module that converts external AC power into DC power. Specifically, it can be implemented using a combination circuit of a rectifier bridge and filter capacitors. Its function is to provide a stable DC power supply foundation for the system.

[0044] Specifically, when the master needs to send a selection frame to the slave, the first serial port module converts the data into a digital signal and transmits it to the transmission processing module. The transmission processing module generates a corresponding second-level signal based on the high or low level of the digital signal, for example, a high level of 5V and a low level of 0V. After receiving the second-level signal, the DC power bus circuit modulates the DC power signal output from the AC-DC power supply circuit. For example, when the second-level signal is high, the switching device in the DC power bus circuit is turned on, causing the bus voltage to rise to a preset high-level carrier amplitude; when the second-level signal is low, the switching device switches to another on state, causing the bus voltage to drop to a medium-level carrier amplitude. In this way, the DC power signal and the dynamic level signal are superimposed to form a carrier waveform that can transmit data, while maintaining the DC power supply capability on the bus.

[0045] As an example, Figure 3A schematic diagram illustrating an application scenario of the communication system provided in an embodiment of this application; such as Figure 2 and Figure 3 As shown, the transmission processing module can be a TX transmission processing module; the DC power bus circuit can be a DC-DC power bus circuit; the AC-DC power supply circuit can also be called an AC-DC power supply. The AC-DC power supply uses a flyback switching power supply, outputting approximately 30V DC power to power the host's DC-DC power bus circuit. The DC-DC bus power supply converts the high voltage output from the AC-DC power supply into the bus voltage, energizing the bus. The DC-DC bus power supply output is controlled by the TX transmission processing module and can output two voltage levels to the bus: high and low. The TX transmission processing module receives signals from the SOC's serial port transmission pins and can control the power level type of the DC-DC bus power supply output.

[0046] This application integrates DC power supply and carrier signal generation functions through a DC power bus circuit. While maintaining low-power DC power supply, it directly modulates the carrier amplitude using a level signal, avoiding the power consumption problem of traditional current loops and simplifying the complex modulation circuits required for power line carriers. Thus, this application can simultaneously achieve high-speed data communication and low-power power supply on a single two-bus architecture. The DC power bus circuit generates carrier signals by dynamically switching power paths, eliminating the need for an additional independent carrier modulation module and reducing hardware complexity. The collaborative operation of the transmission processing module and the DC power bus circuit allows level signals to be directly converted into carrier amplitude variations, improving signal conversion efficiency and significantly increasing communication speed while remaining compatible with traditional two-bus power supply architectures.

[0047] In one embodiment, Figure 4 A schematic diagram of the DC power bus circuit provided for an embodiment of this application; as shown. Figure 4 As shown, the DC power bus circuit includes a first module and a second module; the second level signal includes a high level signal and a low level signal; the level carrier signal includes a high level carrier signal and a medium level carrier signal;

[0048] The first module is used to be in the conducting state when the second level signal is a high level signal, and to convert the DC power supply signal to obtain a high level carrier signal.

[0049] The second module is used to be in the conducting state when the second level signal is a low level signal, and to convert the DC power supply signal to obtain a medium level carrier signal.

[0050] The first module can be a circuit unit capable of conducting and converting a DC power supply signal based on a high-level signal. Specifically, it can be implemented using a circuit including a MOSFET and voltage divider resistors. Its function is to convert the logic state corresponding to the high-level signal into a high-level carrier signal with a defined voltage characteristic. The second module can be a circuit unit capable of conducting and converting a DC power supply signal based on a low-level signal. Specifically, it can be implemented using a circuit including a transistor and current-limiting resistors. Its function is to convert the logic state corresponding to the low-level signal into a medium-level carrier signal with intermediate voltage characteristics. The high-level carrier signal can be a carrier signal with a voltage amplitude higher than a preset threshold, specifically defined by adjusting the resistance ratio of the voltage divider resistors, used to transmit a logic "1" state on the bus. The medium-level carrier signal can be a carrier signal with a voltage amplitude between high and low levels, specifically defined by adjusting the resistance value of the current-limiting resistors, used to transmit a logic "0" state on the bus. The first and second modules can be determined according to actual conditions and are not limited here. As an example, the first module can be a DC-DC power supply module 1; the second module can be a DC-DC power supply module 2.

[0051] Specifically, when the transmitting processing module outputs a high-level signal, the MOSFET in the first module is turned on, and the DC power supply signal is converted into a high-level carrier signal through a voltage divider resistor network and transmitted to the slave device via a two-wire bus. When the transmitting processing module outputs a low-level signal, the transistor in the second module is turned on, and the DC power supply signal is converted into a medium-level carrier signal through a current-limiting resistor. By processing different level signals with two independent modules, signal distortion caused by high-low level switching in traditional single circuits is avoided. Furthermore, the voltage divider and current-limiting structures ensure the stability of the level signals. For example, the voltage divider resistor network in the first module can convert 24V DC power supply into a 12V high-level carrier signal, while the current-limiting resistor in the second module can convert 24V DC power supply into a 6V medium-level carrier signal, thus forming two distinguishable communication levels.

[0052] As an example, such as Figure 4 As shown, the first module is a DC-DC power supply module 1; the second module is a DC-DC power supply module 2. The host's DC-DC bus power supply module includes a DC-DC power supply module 1, which is used to convert the AC-DC power supply output level to a high level; and a DC-DC power supply module 2, which is used to convert the AC-DC power supply output level to a medium level.

[0053] This application processes high and low level signals separately through independent modules, significantly reducing interference during signal conversion. Furthermore, existing power line carrier technology requires complex modulation circuits to achieve high-speed communication, while this solution directly generates two level carrier signals through voltage divider and current limiting structures, simplifying circuit design while maintaining communication speed. Thus, this application solves the communication reliability problem caused by signal distortion in traditional two-bus systems, while avoiding the high power consumption drawback of power line carrier technology. By processing different level signals in modules, rapid switching and stable output of high and low level carrier signals are achieved, enabling accurate identification of logic states between the master and slave devices, thereby improving communication speed and reducing bit error rate.

[0054] In one embodiment, such as Figure 2 As shown, the slave device 102 also includes a receiving circuit module. One end of the receiving circuit module is connected to the first bus in the two-bus 103, and the other end is connected to the second serial port module. The level carrier signal includes a high-level carrier signal and a medium-level carrier signal. The first level signal includes a first level sub-signal and a second level sub-signal.

[0055] The receiving circuit module is used to receive high-level carrier signals and medium-level carrier signals; and to convert the high-level carrier signals and medium-level carrier signals to obtain a first level sub-signal and a second level sub-signal.

[0056] The receiving circuit module can be a circuit module used to convert the level carrier signal on the bus into a serial port recognizable level signal. Specifically, it can be implemented by a combination of voltage divider resistors and comparators. The amplitude range of the input signal is adjusted by voltage division, and then the logic level signal is output by comparator.

[0057] The high-level carrier signal and the medium-level carrier signal can be two modulated signals with different voltage amplitudes sent by the host through the bus. Specifically, they can be carrier signals with different voltage values ​​generated by the DC power supply bus circuit, used to distinguish logic states.

[0058] The first level sub-signal and the second level sub-signal can be two logic level signals output after processing by the receiving circuit. Specifically, they can be high-level or low-level signals output by the comparator, which are used by the serial port module to parse into data frames.

[0059] Specifically, the receiving circuit module uses a first resistor and a second resistor to divide the high-level and medium-level carrier signals on the bus, adjusting the carrier signal with the higher amplitude to within the comparator's input range. The comparator compares the divided signal with a reference voltage; when the input voltage is higher than the reference voltage, it outputs a high level as the first level sub-signal; otherwise, it outputs a low level as the second level sub-signal. A third resistor limits the comparator's output current, ensuring stable signal transmission to the second serial port module. Through this circuit structure, the slave device can accurately identify the different level carrier signals sent by the master and convert them into serial port-resolvable logic signals, thereby completing address matching and data exchange.

[0060] As an example, the receiving circuit module can be an RX receiving circuit module; the high-level carrier signal can be a 24V voltage level; and the medium-level carrier signal can be a 12V voltage level. The RX receiving circuit module is used to convert the 24V level on the bus to 3.3V and the 12V level to 0V, and output them to the serial port receiving module of the SOC.

[0061] This application directly converts level signals using a resistor divider and comparator, eliminating the need for current changes, thus reducing power consumption and improving signal resolution speed. Furthermore, compared to the complex modulation and demodulation circuits in power line carrier technology, this solution employs a simpler and lower-cost combination of voltage divider and comparator. In this way, this application achieves efficient conversion and resolution of slave-to-master level carrier signals, improving communication speed while retaining the low-power characteristics of the two-bus interface. The synergistic effect of the voltage divider circuit and comparator avoids the delay issues associated with traditional current detection, simplifies the signal processing flow, reduces the bit error rate, and enhances system reliability.

[0062] In one embodiment, Figure 5 A schematic diagram of the receiving circuit module provided in the embodiments of this application; as shown. Figure 5 As shown, the receiving circuit module includes a first resistor R1, a second resistor R2, a third resistor R3, and a comparator; one end of the first resistor R1 is connected to the first bus, and the other end is connected to one end of the second resistor R2 and the first end of the comparator; the other end of the second resistor R2 is connected to ground and the second end of the comparator; the third end of the comparator is connected to the second serial port module and one end of the third resistor R3; the other end of the third resistor is connected to the second serial port module.

[0063] The first resistor R1 and the second resistor R2 are used to divide the high-level carrier signal and the medium-level carrier signal and then input them to the comparator.

[0064] The comparator compares the divided voltage with a reference voltage, outputs a second level sub-signal, and outputs a first level sub-signal through a third resistor; the reference voltage is determined based on a high-level carrier signal and a medium-level carrier signal.

[0065] Among them, the first resistor R1 and the second resistor R2 can be voltage divider resistors connected in series between the bus and the ground terminal. Specifically, they can be implemented using metal film resistors with different resistance values. By dividing the voltage, the high-level carrier signal and the medium-level carrier signal on the bus are converted into a voltage range suitable for the comparator input.

[0066] A comparator can be a voltage comparator device with differential input terminals. Specifically, it can be implemented using an operational amplifier or a dedicated voltage comparator chip. It is used to compare the voltage after voltage division with a reference voltage and output a high or low level signal.

[0067] The third resistor R3 can be a current-limiting resistor connected between the comparator output and the second serial port module. Specifically, it can be implemented using a carbon film resistor to limit the output current and match the input level requirements of the serial port module.

[0068] The reference voltage can be a reference voltage value used to determine the signal level after voltage division. Specifically, it can be generated by a voltage divider network or a voltage regulator circuit, and its value is dynamically adjusted according to the voltage range of the high-level carrier signal and the medium-level carrier signal.

[0069] Specifically, when a high-level or medium-level carrier signal is transmitted to the receiving circuit module via the first bus, the first and second resistors perform voltage division on the bus signal, converting the high-voltage signal into a low-voltage signal recognizable by the comparator. The divided voltage is input to the first terminal of the comparator and compared with the reference voltage connected to the second terminal. If the divided voltage is higher than the reference voltage, the comparator outputs a high-level second-level sub-signal; if the divided voltage is lower than the reference voltage, it outputs a low-level second-level sub-signal. Simultaneously, the third resistor transmits the level signal output by the comparator to the second serial port module, forming a first-level sub-signal, thus completing the parsing and conversion of the level signal.

[0070] As an example, such as Figure 5As shown, the receiving circuit module consists of resistors R1, R2, a comparator, and resistor R3. R1 and R2 are used to divide the bus voltage and output the resulting voltage to the input side of the comparator. For example, choosing 18V as the dividing line, the comparator outputs a low level when the voltage exceeds 3V (open-drain output) and a low level when the voltage is below 3V. For example, if R2 has a resistance of 3kΩ and R1 has a resistance of 15kΩ, the output of the series voltage divider will be exactly 3V. That is, from 18V to 24V, the comparator outputs a low level (open-drain output), and from 12V to 18V, the comparator outputs a low level. Through the pull-up of R3, the open-drain output will be high. This converts the 24V and 12V level carrier signals into 3.3V and 0V TTL levels that the MCU serial port can recognize. The comparator output is connected to the RX pin of the MCU's serial port processing module. The timing of this level can be combined with... Figure 6 To understand, Figure 6 A timing diagram provided for an embodiment of this application.

[0071] This application converts bus signals into stable digital levels through a combination of voltage divider resistors and comparators. Simultaneously, the dynamic adjustment of the reference voltage adapts to signal amplitude variations under different operating conditions, significantly improving the accuracy of signal analysis and anti-interference capability. Thus, this application can accurately distinguish between high-level and medium-level carrier signals, avoiding bit error problems caused by signal attenuation or noise, ensuring reliable communication between the master and slave devices. Furthermore, it achieves low-power signal analysis through hardware circuitry, meeting the dual requirements of high speed and low power consumption in a two-bus system.

[0072] In one embodiment, the selection frame includes a first address field and a check field, wherein the first address information is located in the first address field; the check field is used to verify whether the data in the first address field is correct.

[0073] The first address field can be a data area for storing the target slave identification code, which can be implemented using a binary encoding format, such as using 8-bit or 16-bit data lengths to represent different slave addresses. The check field can be an additional information area for verifying the integrity of the address field data, which can be implemented using parity check or cyclic redundancy check algorithms. For example, the sender calculates the checksum of the address field data and appends it to the frame structure, and the receiver compares the results by recalculating the checksum.

[0074] Specifically, when the host sends a selection frame, it writes the target slave's address information into the first address field and generates a corresponding checksum based on the address field data, filling it into the checksum field. Upon receiving the selection frame, the slave first extracts the checksum from the checksum field and performs integrity verification on the first address field data. If the verification result is correct, it continues with address matching; if the verification fails, it discards the current frame to avoid erroneous responses. The introduction of the checksum field effectively identifies address information errors caused by interference during transmission, preventing the slave from mistakenly triggering the parsing module.

[0075] As an example, the selection frame contains an address field and a check field. The address field contains the slave device's address, which can be either the slave device's unique identifier or a broadcast address. The check field is used to verify whether the address field data is normal. If the slave device detects that the address field matches its own unique identifier or is a broadcast address, it will activate its power line parsing module.

[0076] This application solves the problem of erroneous operation caused by signal distortion by adding an independent check field to the frame structure and using a dual verification mechanism to ensure the accuracy of address information. Thus, this application can accurately identify the target slave address in complex electromagnetic environments, reduce the probability of communication failure due to transmission errors, and improve the system's anti-interference capability. The introduction of the check field ensures that the slave device only starts the parsing module when the address is correct and the data is complete, avoiding unnecessary power consumption and further optimizing system energy efficiency.

[0077] In one embodiment, such as Figure 2 As shown, the host 101 also includes a first filter circuit; a first capacitor is provided on the first bus of the dual bus 103; a second capacitor is provided on the second bus of the dual bus 103; the first filter circuit is connected to the first capacitor and the second capacitor respectively.

[0078] The first filtering circuit is used to filter out signals in the non-carrier frequency band of the data request frame to obtain the filtered data request frame.

[0079] The first and second capacitors are used to isolate the DC signal in the filtered data request frame to obtain the first communication signal on the two buses for communication with the slave of the enabled second parsing module.

[0080] The first filter circuit can be a circuit module used to filter out non-carrier frequency band interference. Specifically, it can be implemented using a bandpass filter or a low-pass filter. Its function is to eliminate the influence of high-frequency noise or low-frequency interference on the carrier signal, thereby improving the stability of signal transmission. The first capacitor and the second capacitor can be capacitive components used to isolate DC components. Specifically, they can be implemented using ceramic capacitors or electrolytic capacitors. Their function is to block the superposition interference of DC power supply signals on carrier communication signals, ensuring the pure transmission of carrier signals on the bus.

[0081] Specifically, when the host sends a data request frame, the first filtering circuit first performs frequency band filtering on the data request frame containing the power line carrier signal, filtering out spurious signals outside the carrier frequency band, such as high-frequency noise or low-frequency ripple, thereby retaining the valid carrier signal. Subsequently, the first capacitor and the second capacitor are connected in series on the first bus and the second bus, respectively. Through the DC blocking characteristics of the capacitors, the DC component in the filtered data request frame is isolated, allowing only the AC carrier signal to be transmitted through the bus. Thus, the first communication signal formed on the two buses contains only the valid carrier component, avoiding interference from DC levels to the slave parsing module and ensuring that the slave can accurately receive and parse the data request frame.

[0082] As an example, combined Figure 3 To understand this, the first filtering circuit can be an LC filtering circuit, used to condition the signals from the isolation DC capacitor and the SOC power line analysis module, filter out signals in the non-carrier frequency band, and provide signal reliability protection.

[0083] This application, through the synergistic effect of filtering circuits and capacitors, effectively suppresses DC interference and external noise while preserving the high-speed transmission characteristics of the carrier wave, significantly improving the anti-interference capability and reliability of the communication signal. Thus, this application achieves precise filtering and DC isolation of the carrier signal, solving the communication quality degradation problem caused by signal interference in traditional two-bus systems, while avoiding the high power consumption drawbacks of power line carrier technology, maintaining the system's low power consumption characteristics while ensuring high-speed communication.

[0084] In one embodiment, such as Figure 2 As shown, the slave device 102 also includes a second filter circuit; a third capacitor is provided on the first bus; a fourth capacitor is provided on the second bus; and the second filter circuit is connected to the third capacitor and the fourth capacitor respectively.

[0085] The second filtering circuit is used to filter out signals in the non-carrier frequency band in the data response frame to obtain the filtered data response frame.

[0086] The first capacitor and the second capacitor are used to isolate the DC signal in the filtered data reply frame to obtain the second communication signal on the second bus 103 for communication with the host 101.

[0087] The second filtering circuit can be a circuit module used to filter out non-carrier frequency band interference signals. Specifically, it can be implemented using a bandpass filter or a low-pass filter. Its function is to eliminate the interference of high-frequency noise or low-frequency interference on the carrier signal and ensure the integrity of the carrier signal in the data reply frame. The third and fourth capacitors can be capacitor elements respectively set on the first bus and the second bus. Specifically, they can be implemented using electrolytic capacitors or ceramic capacitors. Their function is to isolate the DC component, allow the AC carrier signal to pass through, and at the same time provide a stable DC power supply path for the slave device.

[0088] Specifically, when the slave device generates a data reply frame and prepares to send it to the master device, the second filtering circuit first performs frequency band filtering on the data reply frame signal, for example, by using a filter with a cutoff frequency equal to the carrier frequency band to filter out non-carrier frequency band interference in the signal. The filtered data reply frame is DC isolated by the third and fourth capacitors, allowing the AC component of the carrier signal to couple onto the two-wire bus, while the DC power signal is blocked to avoid affecting the transmission quality of the communication signal. At the same time, the first and second capacitors further isolate the DC signal on the master side, ensuring that the second communication signal on the two-wire bus contains only the AC component of the carrier frequency band, thereby completing reliable data transmission from the slave device to the master device.

[0089] As an example, combined Figure 3 To understand this, both the first and second capacitors can be isolation DC capacitors; the second filter circuit can be an LC filter circuit, which has the same function as the host's power line filter circuit, filtering out signals in the non-carrier frequency band and providing signal reliability protection.

[0090] This application achieves high-quality carrier signal transmission while maintaining low power consumption through a second filter circuit and capacitor isolation structure. This avoids the speed limitations of traditional two-bus systems and solves the problem of excessive power consumption in power line carrier technology. Thus, this application can effectively filter out non-carrier frequency interference in slave response signals, ensuring the purity of the carrier signal. Simultaneously, by isolating DC components through capacitors, it maintains the coexistence and non-interference of power supply and communication signals on the two-bus system, thereby improving communication speed and stability and meeting the needs of high-speed transmission of large amounts of data.

[0091] In one embodiment, the data request frame includes a second address field, which includes an end identifier; the end identifier is used to determine whether there are consecutive data request frames following the data request frame.

[0092] The second address field can be a component of the frame structure used to carry address information. Specifically, it can be implemented using a fixed-length data field. For example, specific bytes can be reserved in the frame structure to store address information, thereby ensuring that the receiving end can accurately identify the target device.

[0093] The end marker can be a flag bit used to mark the end of a frame or the state of consecutive frames. Specifically, it can be implemented using binary bits or a specific encoding sequence. For example, a bit can be set at the end of the second address field. When the bit is at a preset value, it indicates that there are consecutive data request frames after the current frame, thereby realizing dynamic control of the frame sequence.

[0094] Specifically, when the host sends a data request frame, the end marker set in the second address field is embedded into the carrier signal using a specific encoding method. When the slave receives the data request frame, it parses the end marker in the second address field to determine whether the current frame is the end of a continuous frame sequence. If the end marker indicates that there are subsequent frames, the slave maintains the receiving state and prepares to process the next frame of data; if the end marker indicates that the current frame is the last frame, the slave completes data reception and enters the response processing flow. This mechanism allows the continuity of frames during data transmission to be dynamically adjusted according to actual needs, without relying on a fixed-length frame structure.

[0095] In some specific implementations, the end marker can be a single-bit flag, such as setting the last bit of the second address field to 0 or 1, where 0 indicates no subsequent frames and 1 indicates the presence of consecutive data request frames. Alternatively, the end marker can be implemented using a specific character sequence, such as adding two consecutive bytes of a specific hexadecimal code to the end of the second address field. When the receiving end detects this code pattern, it triggers preparation for receiving consecutive frames.

[0096] As an example, a data request frame can be a power line carrier data request frame, containing at least an address field, a read / write identifier, and an end identifier. If there are consecutive power line carrier data request frames following the current one, the end identifier is set to 0. If there are no subsequent power line carrier data request frames, the end identifier is set to 1. Upon receiving a power line carrier data request frame, the slave device will shut down its PLC carrier module, regardless of whether the address field is its own, a non-single-device SN code, or a broadcast address. The master device's carrier module will remain on and will not shut down its PLC carrier module.

[0097] This application enables the frame sequence continuity to be adjusted in real time according to the data volume by setting a dynamic end marker in the second address field. This avoids the inefficiency of the traditional fixed frame structure and overcomes the power consumption burden caused by continuous frame scheduling in carrier communication. Thus, this application achieves dynamic frame sequence control, improving data transmission efficiency while maintaining low power consumption. The introduction of the end marker allows the master and slave to flexibly adjust the frame transmission rhythm according to the actual data volume, reducing invalid waiting time. Therefore, while retaining the low power consumption advantages of the traditional two-bus system, it significantly improves communication speed and resource utilization.

[0098] In one embodiment, such as Figure 2 As shown, the host 101 also includes a first DC power supply circuit; the first DC power supply circuit is connected to the AC-DC power supply circuit.

[0099] The first DC power supply circuit is used to convert the DC power signal into a voltage signal to power the first chip.

[0100] The first DC power supply circuit can be a module that performs secondary processing on the DC power signal output from the AC-DC power supply circuit. Specifically, it can be implemented using a voltage conversion chip or a voltage regulator circuit, adjusting the voltage amplitude to match the power supply requirements of the main control chip. This circuit optimizes power conversion efficiency, reducing energy loss and maintaining system stability.

[0101] Specifically, the DC power signal output by the AC-DC power supply circuit may experience voltage fluctuations or mismatch with the rated voltage of the main control chip. The first DC power supply circuit filters, reduces, or regulates the input signal through its internal voltage conversion unit to generate a voltage signal that meets the operating requirements of the first chip. For example, when the AC-DC power supply circuit outputs a 24V DC voltage, the first DC power supply circuit can convert it to a stable 3.3V or 5V voltage, thereby providing a continuous and precise power supply to the main control chip. This process, through a two-stage power processing structure, ensures power quality while avoiding the overload risk of a single power module.

[0102] As an example, the first DC power supply circuit can be a DC-DC power supply circuit, which can also be called a DC-DC system power supply or a DC-DC power supply host power supply. The DC-DC system power supply converts the large voltage output from the AC-DC power supply to a smaller voltage, providing power to the host module of the SOC, power line filter circuit, TX transmission processing module.

[0103] This application achieves secondary optimization of the power signal by adding a first DC power supply circuit, which solves the voltage adaptation problem and reduces the probability of system failure caused by power instability. Thus, this application can provide a stable and matched power supply voltage to the main control chip, effectively improving the overall system reliability. At the same time, by optimizing the power conversion path, it reduces energy waste and supports high-speed communication functions while maintaining low power consumption.

[0104] In one embodiment, such as Figure 2 As shown, slave device 102 also includes a second DC power supply circuit; the second DC power supply circuit is connected to the two-wire bus.

[0105] The second DC power supply circuit is used to convert the power signal on the two buses to obtain the power signal on the slave device 102, so as to power the second chip.

[0106] The second DC power supply circuit can be determined based on actual conditions and is not limited here. As an example, the second DC power supply circuit can be a DC-DC power supply circuit. This DC-DC power supply circuit can also be called a DC-DC power slave module, or simply a DC-DC power slave module. The DC-DC power slave module is directly connected to the bus and its function is to convert the power supply on the bus into slave power, which is then used to power the SOC chip, power line filter circuit, RX receiver circuit module, and other modules.

[0107] This application optimizes the power signal by adding a second DC power supply circuit, solving the voltage matching problem and reducing the probability of system failures caused by power instability. Thus, this application can provide a stable and matched power supply voltage to the main control chip, effectively improving the overall system reliability. At the same time, by optimizing the power conversion path, it reduces energy waste and supports high-speed communication functions while maintaining low power consumption.

[0108] As an example, Figure 7 ,like Figure 3 and Figure 7 As shown, Figure 7This is a schematic diagram illustrating another application scenario of the communication system provided in the embodiments of this application. The communication system can be a two-bus communication system, consisting of a master unit, slave units, and two buses. The master unit includes a SOC chip, a PLC filtering circuit, a TX transmission processing module, an AC-DC power supply module, a DC-DC system power supply, a DC-DC power bus circuit, and an isolation DC capacitor. The slave unit includes a SOC chip, a DC-DC slave power supply, a PLC filtering circuit, an RX receiving circuit module, and an isolation DC capacitor. Communication between the master and slave units includes two methods: based on a high-bandwidth, high-frequency signal carrier from the PLC and based on a low-bandwidth, low-frequency signal carrier from a level. The slave module to be communicated is selected through the level carrier. The high-bandwidth, high-frequency signal carrier from the PLC is used to achieve large data communication. When a single device requests data, at most two devices can communicate using the PLC simultaneously. The communication process includes: First, the PLC carrier parsing function of all slave units is turned off. Second, the master SOC sends a slave module selection frame to the TX transmission processing module through the serial port processing module's sending unit to control the DC-DC bus power supply to output a power level carrier. Third, after receiving the level carrier signal, all slave RX receiving modules convert it into a high or low level recognized by the system and send it to the slave's serial port processing module. Fourth, after receiving the data, the slave's SOC serial port processing module performs frame parsing and checks whether the slave address field in the slave module selection frame matches its own slave address field. If they match, the slave's PLC parsing module is enabled. Otherwise, the slave's PLC protocol module function is not enabled. Fifth, the master PLC parsing module sends a PLC carrier data request frame to the bus. The slave that just enabled its PLC protocol module function receives the frame, performs protocol parsing, and sends a data reply frame to the bus. The master PLC parsing module receives the data reply frame and completes the data query for that slave. If the slave finds that it is the last slave request frame in the data request frame, it will send its data reply frame and then disable its PLC parsing module. Sixth, the master continues to send the serial port slave module selection frame and PLC carrier data request frame to the bus in the polling order of the slaves. Complete one round of data interaction between slave devices.

[0109] Specifically, the master and slave SOC chips include a serial port processing module and a PLC parsing module. The PLC uses fixed-slot scheduling TDMA mode and CSMA / CA mode for carrier transmission. During transmission, after passing through the PLC rate circuit, the carrier signal is superimposed on the two buses through two capacitors isolating the two buses. The carrier signal on the two buses, after passing through this isolation DC capacitor, will pass through the PLC filtering circuit and then reach the PLC parsing module of the SOC to obtain the communication signal on the bus, realizing the PLC carrier communication. The master carrier module will always be on and will not be turned off. The slave's carrier function will be turned on or off depending on the selection.

[0110] For the host computer, the AC-DC power supply uses a flyback switching power supply, outputting approximately 30V DC power to power the host's DC-DC system power supply and DC-DC bus power supply module. The DC-DC system power supply converts the high voltage output from the AC-DC power supply to a lower voltage, powering the host components including the SOC, PLC filter circuit, and TX transmission processing module. The DC-DC bus power supply converts the high voltage output from the AC-DC power supply into the bus voltage, energizing the bus. The DC-DC bus power supply output is controlled by the TX transmission processing module, allowing it to output two voltage levels to the bus: high and low. The TX transmission processing module receives signals from the SOC's serial port transmit pins and controls the DC-DC bus power supply output voltage level. The PLC filter circuit primarily conditions the signals from the isolation DC capacitor and the SOC's PLC parsing module, filtering out non-carrier frequency signals and providing signal reliability protection. The process of converting the TTL level of the serial port processing module to a level carrier can be achieved by the host's DC-DC bus power supply module, which includes DC-DC power supply module 1, used to convert the AC-DC power supply output level to a high level; and DC-DC power supply module 2, used to convert the AC-DC power supply output level to a medium level.

[0111] When the TX pin of the host MCU's serial port processing module is not transmitting a signal or is transmitting a 1 signal, it is at a high level, enabling DC-DC power supply module 1. The high-level output of DC-DC power supply module 1 is output to the bus via a diode. The high-level TX pin outputs a low-level signal through a NAND gate, disabling DC-DC power supply module 2. When the TX pin transmits a 0 signal, it is at a low level, disabling DC-DC power supply module 1. The low-level signal is changed to a high-level signal through a NOT gate, controlling DC-DC power supply module 2. This module outputs a low-level signal, which is output to the bus via a diode. The baud rate of the high and low levels on the bus is the same as the baud rate on the TX pin of the serial port processing module.

[0112] For the slave device, the DC-DC power supply module is directly connected to the bus. Its function is to convert the power supply on the bus into the slave system power supply. The converted power supply is used to power the SOC chip, PLC filter circuit, RX receiver circuit module, and other modules. The PLC filter circuit has the same function as the host PLC filter circuit. The RX receiver circuit module is used to convert the level changes on the bus into level changes that the system recognizes, and outputs them to the SOC's serial port receiver module. The bus high level is converted to the system-recognized high level, and the bus mid level is converted to the system-recognized low level. The PLC parsing module is a high-power module that uses the PLC's high-bandwidth, high-frequency signal carrier to achieve large data communication. The serial port module is a low-power module that communicates via level carrier. The high and mid levels of the bus are converted to TTL levels. The conversion process is completed by the slave receiver processing circuit. The principle is that this circuit consists of R1, R2, a comparator, and R3. R1 and R2 are used to divide the bus level and output the voltage Vs to the input side of the comparator. The middle level V2 between the bus high level V0 and the mid level V1 is selected as the dividing line. The comparator has a comparison voltage threshold Vl. When the level of Vs is greater than Vl, the comparator outputs an open-drain output; when the level of Vs is less than Vl, the comparator outputs a TTL low level. By subtracting R1 and R2, the output level of V2 is equal to Vl. Between the levels of V0 and V2, the comparator outputs an open-drain output, and through the pull-up resistor R3, it outputs a TTL high level. Between the levels of V2 and V1, the comparator outputs a TTL low level. This achieves demodulation of the power supply voltage level to the RX pin of the slave MCU serial port processing module.

[0113] The selection frame contains an address field and a check field. The address field contains the slave device's address, which can be either the slave device's unique identifier or a broadcast address. The check field is used to verify whether the address field data is normal. If the slave device detects that the address field matches its own unique identifier or is a broadcast address, it will activate its PLC parsing module. The PLC carrier data request frame contains at least an address field, a read / write flag, and an end flag. If there are consecutive PLC carrier data request frames following the current PLC carrier data request frame, the end flag is set to 0. If there are no subsequent PLC carrier data request frames, the end flag is set to 1. After receiving a PLC carrier data request frame, the slave device will shut down its PLC carrier module, regardless of whether the address field is its own, a non-single-device SN code, or a broadcast address.

[0114] Communication between the master and slave devices includes two methods: high-bandwidth, high-frequency signal carrier based on the PLC, and low-bandwidth, low-frequency signal carrier based on level signals. The PLC parsing module is a high-power module, while the serial port module is a low-power module. Level carrier signals are used to select the slave module to communicate with. The high-bandwidth, high-frequency signal carrier of the PLC enables large data communication, allowing more devices to be driven with the same power. Because in a group, only two devices communicate with the PLC simultaneously (except for broadcast addresses).

[0115] The communication system provided in the embodiments of this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A communication system, characterized in that, The communication system includes: a host and at least one slave device that is communicatively connected to the host via a dual bus; The host is used to send a level carrier signal to the slave. The slave device is used to convert the level carrier signal to obtain a first level signal, and enable the second parsing module in the slave device based on the first level signal; The host is also used to send power line carrier signals to the slave. The slave device is also configured to send a response signal of the power line carrier signal to the host device based on the enabled second parsing module, so that the host device can complete the data query of the slave device.

2. The communication system according to claim 1, characterized in that, The host includes a first chip; the first chip includes a first parsing module and a first serial port module; the slave includes a second chip; the second chip includes a second parsing module and a second serial port module. The host is also used to generate the level carrier signal based on the selection frame sent by the first serial port module; The slave device is further configured to parse the first level signal through the second serial port module to enable the second parsing module; The host is also used to send a data request frame of a power line carrier signal based on the first parsing module; The slave device is further configured to receive the data request frame based on the enabled second parsing module, generate a data response frame according to the data request frame, and send the data response frame to the data response frame via the power line carrier signal, so that the master device can complete the data query of the slave device based on the data response frame.

3. The communication system according to claim 2, characterized in that, The host also includes: AC-DC power supply circuit for outputting DC power signals; A transmission processing module for transmitting a second-level signal of the transmission pin provided by the selection frame; A DC power bus circuit for generating the level carrier signal based on the DC power signal and the second level signal.

4. The communication system according to claim 3, characterized in that, The second level signal includes a high-level signal and a low-level signal; the level carrier signal includes a high-level carrier signal and a medium-level carrier signal; the DC power bus circuit includes: A first module is used to be in an on state when the second level signal is the high level signal, to convert the DC power supply signal to obtain the high level carrier signal; The second module is used to be in a conducting state when the second level signal is the low level signal, and to perform conversion processing on the DC power supply signal to obtain the medium level carrier signal.

5. The communication system according to claim 2, characterized in that, The level carrier signal includes a high-level carrier signal and a medium-level carrier signal; the first level signal includes a first level sub-signal and a second level sub-signal; the slave device further includes: A receiving circuit module is used to receive the high-level carrier signal and the medium-level carrier signal, and to convert the high-level carrier signal and the medium-level carrier signal to obtain the first level sub-signal and the second level sub-signal; one end of the receiving circuit module is connected to the first bus in the two buses, and the other end is connected to the second serial port module.

6. The communication system according to claim 5, characterized in that, The receiving circuit module includes: A first resistor and a second resistor are used to divide the high-level carrier signal and the medium-level carrier signal into voltages; A comparator is used to compare the voltage after voltage division with a reference voltage to output the second level sub-signal and the first level sub-signal through a third resistor; the reference voltage is determined based on the high-level carrier signal and the medium-level carrier signal; Wherein, one end of the first resistor is connected to the first bus, and the other end is connected to one end of the second resistor and the first end of the comparator; the other end of the second resistor is connected to ground and the second end of the comparator; the third end of the comparator is connected to the second serial port module and one end of the third resistor; the other end of the third resistor is connected to the second serial port module.

7. The communication system according to claim 2, characterized in that, The host also includes: A first filtering circuit is used to filter out signals in the non-carrier frequency band of the data request frame to obtain the filtered data request frame. The first and second capacitors are used to isolate the DC signal in the filtered data request frame to obtain the first communication signal on the two buses for communication with the slave of the enabled second parsing module. The first capacitor is connected to the first filter circuit and the first bus of the two buses respectively; the second capacitor is connected to the first filter circuit and the second bus of the two buses respectively.

8. The communication system according to claim 7, characterized in that, The slave device also includes: A second filtering circuit is used to filter out signals in the non-carrier frequency band of the data response frame to obtain the filtered data response frame. The third and fourth capacitors are used to isolate the DC signal in the filtered data response frame to obtain the second communication signal on the two buses for communication with the host. The third capacitor is connected to the second filter circuit and the first bus, respectively; the fourth capacitor is connected to the second filter circuit and the second bus, respectively.

9. The communication system according to claim 3, characterized in that, The host also includes: A first DC power supply circuit is used to convert the DC power signal into a voltage signal to power the first chip; the first DC power supply circuit is connected to the AC-DC power supply circuit.

10. The communication system according to any one of claims 1-9, characterized in that, The slave device also includes: A second DC power supply circuit is used to convert the power signals on the two buses to obtain the power signals on the slave device; the second DC power supply circuit is connected to the two buses.

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